2 * linux/arch/arm/mach-omap/clock.c
4 * Copyright (C) 2004 Nokia corporation
5 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 #include <linux/module.h>
12 #include <linux/kernel.h>
13 #include <linux/list.h>
14 #include <linux/errno.h>
15 #include <linux/err.h>
17 #include <asm/semaphore.h>
18 #include <asm/hardware/clock.h>
19 #include <asm/arch/board.h>
20 #include <asm/arch/usb.h>
24 static LIST_HEAD(clocks);
25 static DECLARE_MUTEX(clocks_sem);
26 static DEFINE_SPINLOCK(clockfw_lock);
27 static void propagate_rate(struct clk * clk);
28 /* External clock (MCLK & BCLK) functions */
29 static int set_ext_clk_rate(struct clk * clk, unsigned long rate);
30 static long round_ext_clk_rate(struct clk * clk, unsigned long rate);
31 static void init_ext_clk(struct clk * clk);
32 /* MPU virtual clock functions */
33 static int select_table_rate(struct clk * clk, unsigned long rate);
34 static long round_to_table_rate(struct clk * clk, unsigned long rate);
35 void clk_setdpll(__u16, __u16);
37 struct mpu_rate rate_table[] = {
38 /* MPU MHz, xtal MHz, dpll1 MHz, CKCTL, DPLL_CTL
39 * armdiv, dspdiv, dspmmu, tcdiv, perdiv, lcddiv
41 #if defined(CONFIG_OMAP_ARM_216MHZ)
42 { 216000000, 12000000, 216000000, 0x050d, 0x2910 }, /* 1/1/2/2/2/8 */
44 #if defined(CONFIG_OMAP_ARM_195MHZ)
45 { 195000000, 13000000, 195000000, 0x050e, 0x2790 }, /* 1/1/2/2/4/8 */
47 #if defined(CONFIG_OMAP_ARM_192MHZ)
48 { 192000000, 19200000, 192000000, 0x050f, 0x2510 }, /* 1/1/2/2/8/8 */
49 { 192000000, 12000000, 192000000, 0x050f, 0x2810 }, /* 1/1/2/2/8/8 */
50 { 96000000, 12000000, 192000000, 0x055f, 0x2810 }, /* 2/2/2/2/8/8 */
51 { 48000000, 12000000, 192000000, 0x0ccf, 0x2810 }, /* 4/4/4/4/8/8 */
52 { 24000000, 12000000, 192000000, 0x0fff, 0x2810 }, /* 8/8/8/8/8/8 */
54 #if defined(CONFIG_OMAP_ARM_182MHZ)
55 { 182000000, 13000000, 182000000, 0x050e, 0x2710 }, /* 1/1/2/2/4/8 */
57 #if defined(CONFIG_OMAP_ARM_168MHZ)
58 { 168000000, 12000000, 168000000, 0x010f, 0x2710 }, /* 1/1/1/2/8/8 */
60 #if defined(CONFIG_OMAP_ARM_150MHZ)
61 { 150000000, 12000000, 150000000, 0x150a, 0x2cb0 }, /* 0/0/1/1/2/2 */
63 #if defined(CONFIG_OMAP_ARM_120MHZ)
64 { 120000000, 12000000, 120000000, 0x010a, 0x2510 }, /* 1/1/1/2/4/4 */
66 #if defined(CONFIG_OMAP_ARM_96MHZ)
67 { 96000000, 12000000, 96000000, 0x0005, 0x2410 }, /* 1/1/1/1/2/2 */
69 #if defined(CONFIG_OMAP_ARM_60MHZ)
70 { 60000000, 12000000, 60000000, 0x0005, 0x2290 }, /* 1/1/1/1/2/2 */
72 #if defined(CONFIG_OMAP_ARM_30MHZ)
73 { 30000000, 12000000, 60000000, 0x0555, 0x2290 }, /* 2/2/2/2/2/2 */
79 static void ckctl_recalc(struct clk * clk)
83 /* Calculate divisor encoded as 2-bit exponent */
84 dsor = 1 << (3 & (omap_readw(ARM_CKCTL) >> clk->rate_offset));
85 if (unlikely(clk->rate == clk->parent->rate / dsor))
86 return; /* No change, quick exit */
87 clk->rate = clk->parent->rate / dsor;
89 if (unlikely(clk->flags & RATE_PROPAGATES))
94 static void followparent_recalc(struct clk * clk)
96 clk->rate = clk->parent->rate;
100 static void watchdog_recalc(struct clk * clk)
102 clk->rate = clk->parent->rate / 14;
106 static struct clk ck_ref = {
109 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
113 static struct clk ck_dpll1 = {
116 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
117 RATE_PROPAGATES | ALWAYS_ENABLED,
120 static struct clk ck_dpll1out = {
121 .name = "ck_dpll1out",
123 .flags = CLOCK_IN_OMAP16XX,
124 .enable_reg = ARM_IDLECT2,
125 .enable_bit = EN_CKOUT_ARM,
126 .recalc = &followparent_recalc,
129 static struct clk arm_ck = {
132 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
133 RATE_CKCTL | RATE_PROPAGATES | ALWAYS_ENABLED,
134 .rate_offset = CKCTL_ARMDIV_OFFSET,
135 .recalc = &ckctl_recalc,
138 static struct clk armper_ck = {
141 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
143 .enable_reg = ARM_IDLECT2,
144 .enable_bit = EN_PERCK,
145 .rate_offset = CKCTL_PERDIV_OFFSET,
146 .recalc = &ckctl_recalc,
149 static struct clk arm_gpio_ck = {
150 .name = "arm_gpio_ck",
152 .flags = CLOCK_IN_OMAP1510,
153 .enable_reg = ARM_IDLECT2,
154 .enable_bit = EN_GPIOCK,
155 .recalc = &followparent_recalc,
158 static struct clk armxor_ck = {
161 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
162 .enable_reg = ARM_IDLECT2,
163 .enable_bit = EN_XORPCK,
164 .recalc = &followparent_recalc,
167 static struct clk armtim_ck = {
170 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
171 .enable_reg = ARM_IDLECT2,
172 .enable_bit = EN_TIMCK,
173 .recalc = &followparent_recalc,
176 static struct clk armwdt_ck = {
179 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
180 .enable_reg = ARM_IDLECT2,
181 .enable_bit = EN_WDTCK,
182 .recalc = &watchdog_recalc,
185 static struct clk arminth_ck16xx = {
186 .name = "arminth_ck",
188 .flags = CLOCK_IN_OMAP16XX,
189 .recalc = &followparent_recalc,
190 /* Note: On 16xx the frequency can be divided by 2 by programming
191 * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1
193 * 1510 version is in TC clocks.
197 static struct clk dsp_ck = {
200 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
202 .enable_reg = ARM_CKCTL,
203 .enable_bit = EN_DSPCK,
204 .rate_offset = CKCTL_DSPDIV_OFFSET,
205 .recalc = &ckctl_recalc,
208 static struct clk dspmmu_ck = {
211 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
212 RATE_CKCTL | ALWAYS_ENABLED,
213 .rate_offset = CKCTL_DSPMMUDIV_OFFSET,
214 .recalc = &ckctl_recalc,
217 static struct clk tc_ck = {
220 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP730 |
221 RATE_CKCTL | RATE_PROPAGATES | ALWAYS_ENABLED,
222 .rate_offset = CKCTL_TCDIV_OFFSET,
223 .recalc = &ckctl_recalc,
226 static struct clk arminth_ck1510 = {
227 .name = "arminth_ck",
229 .flags = CLOCK_IN_OMAP1510,
230 .recalc = &followparent_recalc,
231 /* Note: On 1510 the frequency follows TC_CK
233 * 16xx version is in MPU clocks.
237 static struct clk tipb_ck = {
240 .flags = CLOCK_IN_OMAP1510,
241 .recalc = &followparent_recalc,
244 static struct clk l3_ocpi_ck = {
245 .name = "l3_ocpi_ck",
247 .flags = CLOCK_IN_OMAP16XX,
248 .enable_reg = ARM_IDLECT3,
249 .enable_bit = EN_OCPI_CK,
250 .recalc = &followparent_recalc,
253 static struct clk tc1_ck = {
256 .flags = CLOCK_IN_OMAP16XX,
257 .enable_reg = ARM_IDLECT3,
258 .enable_bit = EN_TC1_CK,
259 .recalc = &followparent_recalc,
262 static struct clk tc2_ck = {
265 .flags = CLOCK_IN_OMAP16XX,
266 .enable_reg = ARM_IDLECT3,
267 .enable_bit = EN_TC2_CK,
268 .recalc = &followparent_recalc,
271 static struct clk dma_ck = {
274 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
275 .recalc = &followparent_recalc,
278 static struct clk dma_lcdfree_ck = {
279 .name = "dma_lcdfree_ck",
281 .flags = CLOCK_IN_OMAP16XX,
282 .recalc = &followparent_recalc,
285 static struct clk api_ck = {
288 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
289 .enable_reg = ARM_IDLECT2,
290 .enable_bit = EN_APICK,
291 .recalc = &followparent_recalc,
294 static struct clk lb_ck = {
297 .flags = CLOCK_IN_OMAP1510,
298 .enable_reg = ARM_IDLECT2,
299 .enable_bit = EN_LBCK,
300 .recalc = &followparent_recalc,
303 static struct clk rhea1_ck = {
306 .flags = CLOCK_IN_OMAP16XX,
307 .recalc = &followparent_recalc,
310 static struct clk rhea2_ck = {
313 .flags = CLOCK_IN_OMAP16XX,
314 .recalc = &followparent_recalc,
317 static struct clk lcd_ck = {
320 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP730 |
322 .enable_reg = ARM_IDLECT2,
323 .enable_bit = EN_LCDCK,
324 .rate_offset = CKCTL_LCDDIV_OFFSET,
325 .recalc = &ckctl_recalc,
328 static struct clk uart1_ck = {
330 /* Direct from ULPD, no parent */
332 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
333 RATE_FIXED | ENABLE_REG_32BIT,
334 .enable_reg = MOD_CONF_CTRL_0,
337 * The "enable bit" actually chooses between 48MHz and 12MHz.
341 static struct clk uart2_ck = {
343 /* Direct from ULPD, no parent */
345 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
346 RATE_FIXED | ENABLE_REG_32BIT,
347 .enable_reg = MOD_CONF_CTRL_0,
349 /* (for both 1510 and 16xx)
350 * The "enable bit" actually chooses between 48MHz and 12MHz/32kHz.
354 static struct clk uart3_ck = {
356 /* Direct from ULPD, no parent */
358 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
359 RATE_FIXED | ENABLE_REG_32BIT,
360 .enable_reg = MOD_CONF_CTRL_0,
363 * The "enable bit" actually chooses between 48MHz and 12MHz.
367 static struct clk usb_clko = { /* 6 MHz output on W4_USB_CLKO */
369 /* Direct from ULPD, no parent */
371 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
372 RATE_FIXED | ENABLE_REG_32BIT,
373 .enable_reg = ULPD_CLOCK_CTRL,
374 .enable_bit = USB_MCLK_EN_BIT,
377 static struct clk usb_hhc_ck1510 = {
378 .name = "usb_hhc_ck",
379 /* Direct from ULPD, no parent */
380 .rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */
381 .flags = CLOCK_IN_OMAP1510 |
382 RATE_FIXED | ENABLE_REG_32BIT,
383 .enable_reg = MOD_CONF_CTRL_0,
384 .enable_bit = USB_HOST_HHC_UHOST_EN,
387 static struct clk usb_hhc_ck16xx = {
388 .name = "usb_hhc_ck",
389 /* Direct from ULPD, no parent */
391 /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */
392 .flags = CLOCK_IN_OMAP16XX |
393 RATE_FIXED | ENABLE_REG_32BIT,
394 .enable_reg = OTG_BASE + 0x08 /* OTG_SYSCON_2 */,
395 .enable_bit = 8 /* UHOST_EN */,
398 static struct clk mclk_1510 = {
400 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
402 .flags = CLOCK_IN_OMAP1510 | RATE_FIXED,
405 static struct clk mclk_16xx = {
407 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
408 .flags = CLOCK_IN_OMAP16XX,
409 .enable_reg = COM_CLK_DIV_CTRL_SEL,
410 .enable_bit = COM_ULPD_PLL_CLK_REQ,
411 .set_rate = &set_ext_clk_rate,
412 .round_rate = &round_ext_clk_rate,
413 .init = &init_ext_clk,
416 static struct clk bclk_1510 = {
418 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
420 .flags = CLOCK_IN_OMAP1510 | RATE_FIXED,
423 static struct clk bclk_16xx = {
425 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
426 .flags = CLOCK_IN_OMAP16XX,
427 .enable_reg = SWD_CLK_DIV_CTRL_SEL,
428 .enable_bit = SWD_ULPD_PLL_CLK_REQ,
429 .set_rate = &set_ext_clk_rate,
430 .round_rate = &round_ext_clk_rate,
431 .init = &init_ext_clk,
434 static struct clk mmc1_ck = {
436 /* Functional clock is direct from ULPD, interface clock is ARMPER */
437 .parent = &armper_ck,
439 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
440 RATE_FIXED | ENABLE_REG_32BIT,
441 .enable_reg = MOD_CONF_CTRL_0,
445 static struct clk mmc2_ck = {
447 /* Functional clock is direct from ULPD, interface clock is ARMPER */
448 .parent = &armper_ck,
450 .flags = CLOCK_IN_OMAP16XX |
451 RATE_FIXED | ENABLE_REG_32BIT,
452 .enable_reg = MOD_CONF_CTRL_0,
456 static struct clk virtual_ck_mpu = {
458 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
459 VIRTUAL_CLOCK | ALWAYS_ENABLED,
460 .parent = &arm_ck, /* Is smarter alias for */
461 .recalc = &followparent_recalc,
462 .set_rate = &select_table_rate,
463 .round_rate = &round_to_table_rate,
467 static struct clk * onchip_clks[] = {
468 /* non-ULPD clocks */
479 &arminth_ck1510, &arminth_ck16xx,
501 &usb_hhc_ck1510, &usb_hhc_ck16xx,
502 &mclk_1510, &mclk_16xx,
503 &bclk_1510, &bclk_16xx,
510 struct clk *clk_get(struct device *dev, const char *id)
512 struct clk *p, *clk = ERR_PTR(-ENOENT);
515 list_for_each_entry(p, &clocks, node) {
516 if (strcmp(id, p->name) == 0 && try_module_get(p->owner)) {
525 EXPORT_SYMBOL(clk_get);
528 void clk_put(struct clk *clk)
530 if (clk && !IS_ERR(clk))
531 module_put(clk->owner);
533 EXPORT_SYMBOL(clk_put);
536 int __clk_enable(struct clk *clk)
541 if (clk->flags & ALWAYS_ENABLED)
544 if (unlikely(clk->enable_reg == 0)) {
545 printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
550 if (clk->flags & ENABLE_REG_32BIT) {
551 regval32 = omap_readl(clk->enable_reg);
552 regval32 |= (1 << clk->enable_bit);
553 omap_writel(regval32, clk->enable_reg);
555 regval16 = omap_readw(clk->enable_reg);
556 regval16 |= (1 << clk->enable_bit);
557 omap_writew(regval16, clk->enable_reg);
564 void __clk_disable(struct clk *clk)
569 if (clk->enable_reg == 0)
572 if (clk->flags & ENABLE_REG_32BIT) {
573 regval32 = omap_readl(clk->enable_reg);
574 regval32 &= ~(1 << clk->enable_bit);
575 omap_writel(regval32, clk->enable_reg);
577 regval16 = omap_readw(clk->enable_reg);
578 regval16 &= ~(1 << clk->enable_bit);
579 omap_writew(regval16, clk->enable_reg);
584 void __clk_unuse(struct clk *clk)
586 if (clk->usecount > 0 && !(--clk->usecount)) {
588 if (likely(clk->parent))
589 __clk_unuse(clk->parent);
594 int __clk_use(struct clk *clk)
597 if (clk->usecount++ == 0) {
598 if (likely(clk->parent))
599 ret = __clk_use(clk->parent);
601 if (unlikely(ret != 0)) {
606 ret = __clk_enable(clk);
608 if (unlikely(ret != 0) && clk->parent) {
609 __clk_unuse(clk->parent);
618 int clk_enable(struct clk *clk)
623 spin_lock_irqsave(&clockfw_lock, flags);
624 ret = __clk_enable(clk);
625 spin_unlock_irqrestore(&clockfw_lock, flags);
628 EXPORT_SYMBOL(clk_enable);
631 void clk_disable(struct clk *clk)
635 spin_lock_irqsave(&clockfw_lock, flags);
637 spin_unlock_irqrestore(&clockfw_lock, flags);
639 EXPORT_SYMBOL(clk_disable);
642 int clk_use(struct clk *clk)
647 spin_lock_irqsave(&clockfw_lock, flags);
648 ret = __clk_use(clk);
649 spin_unlock_irqrestore(&clockfw_lock, flags);
652 EXPORT_SYMBOL(clk_use);
655 void clk_unuse(struct clk *clk)
659 spin_lock_irqsave(&clockfw_lock, flags);
661 spin_unlock_irqrestore(&clockfw_lock, flags);
663 EXPORT_SYMBOL(clk_unuse);
666 int clk_get_usecount(struct clk *clk)
668 return clk->usecount;
670 EXPORT_SYMBOL(clk_get_usecount);
673 unsigned long clk_get_rate(struct clk *clk)
677 EXPORT_SYMBOL(clk_get_rate);
680 static __u16 verify_ckctl_value(__u16 newval)
682 /* This function checks for following limitations set
683 * by the hardware (all conditions must be true):
684 * DSPMMU_CK == DSP_CK or DSPMMU_CK == DSP_CK/2
689 * In addition following rules are enforced:
693 * However, maximum frequencies are not checked for!
702 per_exp = (newval >> CKCTL_PERDIV_OFFSET) & 3;
703 lcd_exp = (newval >> CKCTL_LCDDIV_OFFSET) & 3;
704 arm_exp = (newval >> CKCTL_ARMDIV_OFFSET) & 3;
705 dsp_exp = (newval >> CKCTL_DSPDIV_OFFSET) & 3;
706 tc_exp = (newval >> CKCTL_TCDIV_OFFSET) & 3;
707 dspmmu_exp = (newval >> CKCTL_DSPMMUDIV_OFFSET) & 3;
709 if (dspmmu_exp < dsp_exp)
710 dspmmu_exp = dsp_exp;
711 if (dspmmu_exp > dsp_exp+1)
712 dspmmu_exp = dsp_exp+1;
713 if (tc_exp < arm_exp)
715 if (tc_exp < dspmmu_exp)
717 if (tc_exp > lcd_exp)
719 if (tc_exp > per_exp)
723 newval |= per_exp << CKCTL_PERDIV_OFFSET;
724 newval |= lcd_exp << CKCTL_LCDDIV_OFFSET;
725 newval |= arm_exp << CKCTL_ARMDIV_OFFSET;
726 newval |= dsp_exp << CKCTL_DSPDIV_OFFSET;
727 newval |= tc_exp << CKCTL_TCDIV_OFFSET;
728 newval |= dspmmu_exp << CKCTL_DSPMMUDIV_OFFSET;
734 static int calc_dsor_exp(struct clk *clk, unsigned long rate)
736 /* Note: If target frequency is too low, this function will return 4,
737 * which is invalid value. Caller must check for this value and act
740 * Note: This function does not check for following limitations set
741 * by the hardware (all conditions must be true):
742 * DSPMMU_CK == DSP_CK or DSPMMU_CK == DSP_CK/2
747 unsigned long realrate;
751 if (unlikely(!(clk->flags & RATE_CKCTL)))
754 parent = clk->parent;
755 if (unlikely(parent == 0))
758 realrate = parent->rate;
759 for (dsor_exp=0; dsor_exp<4; dsor_exp++) {
760 if (realrate <= rate)
769 long clk_round_rate(struct clk *clk, unsigned long rate)
773 if (clk->flags & RATE_FIXED)
776 if (clk->flags & RATE_CKCTL) {
777 dsor_exp = calc_dsor_exp(clk, rate);
782 return clk->parent->rate / (1 << dsor_exp);
785 if(clk->round_rate != 0)
786 return clk->round_rate(clk, rate);
790 EXPORT_SYMBOL(clk_round_rate);
793 static void propagate_rate(struct clk * clk)
797 for (clkp = onchip_clks; clkp < onchip_clks+ARRAY_SIZE(onchip_clks); clkp++) {
798 if (likely((*clkp)->parent != clk)) continue;
799 if (likely((*clkp)->recalc))
800 (*clkp)->recalc(*clkp);
805 static int select_table_rate(struct clk * clk, unsigned long rate)
807 /* Find the highest supported frequency <= rate and switch to it */
808 struct mpu_rate * ptr;
810 if (clk != &virtual_ck_mpu)
813 for (ptr = rate_table; ptr->rate; ptr++) {
814 if (ptr->xtal != ck_ref.rate)
817 /* DPLL1 cannot be reprogrammed without risking system crash */
818 if (likely(ck_dpll1.rate!=0) && ptr->pll_rate != ck_dpll1.rate)
821 /* Can check only after xtal frequency check */
822 if (ptr->rate <= rate)
829 if (unlikely(ck_dpll1.rate == 0)) {
830 omap_writew(ptr->dpllctl_val, DPLL_CTL);
831 ck_dpll1.rate = ptr->pll_rate;
833 omap_writew(ptr->ckctl_val, ARM_CKCTL);
834 propagate_rate(&ck_dpll1);
839 static long round_to_table_rate(struct clk * clk, unsigned long rate)
841 /* Find the highest supported frequency <= rate */
842 struct mpu_rate * ptr;
845 if (clk != &virtual_ck_mpu)
848 highest_rate = -EINVAL;
850 for (ptr = rate_table; ptr->rate; ptr++) {
851 if (ptr->xtal != ck_ref.rate)
854 highest_rate = ptr->rate;
856 /* Can check only after xtal frequency check */
857 if (ptr->rate <= rate)
865 int clk_set_rate(struct clk *clk, unsigned long rate)
872 if (clk->flags & RATE_CKCTL) {
873 dsor_exp = calc_dsor_exp(clk, rate);
879 spin_lock_irqsave(&clockfw_lock, flags);
880 regval = omap_readw(ARM_CKCTL);
881 regval &= ~(3 << clk->rate_offset);
882 regval |= dsor_exp << clk->rate_offset;
883 regval = verify_ckctl_value(regval);
884 omap_writew(regval, ARM_CKCTL);
885 clk->rate = clk->parent->rate / (1 << dsor_exp);
886 spin_unlock_irqrestore(&clockfw_lock, flags);
888 } else if(clk->set_rate != 0) {
889 spin_lock_irqsave(&clockfw_lock, flags);
890 ret = clk->set_rate(clk, rate);
891 spin_unlock_irqrestore(&clockfw_lock, flags);
894 if (unlikely(ret == 0 && (clk->flags & RATE_PROPAGATES)))
899 EXPORT_SYMBOL(clk_set_rate);
902 static unsigned calc_ext_dsor(unsigned long rate)
906 /* MCLK and BCLK divisor selection is not linear:
907 * freq = 96MHz / dsor
909 * RATIO_SEL range: dsor <-> RATIO_SEL
910 * 0..6: (RATIO_SEL+2) <-> (dsor-2)
911 * 6..48: (8+(RATIO_SEL-6)*2) <-> ((dsor-8)/2+6)
912 * Minimum dsor is 2 and maximum is 96. Odd divisors starting from 9
915 for (dsor = 2; dsor < 96; ++dsor) {
916 if ((dsor & 1) && dsor > 8)
918 if (rate >= 96000000 / dsor)
925 static int set_ext_clk_rate(struct clk * clk, unsigned long rate)
930 dsor = calc_ext_dsor(rate);
931 clk->rate = 96000000 / dsor;
933 ratio_bits = ((dsor - 8) / 2 + 6) << 2;
935 ratio_bits = (dsor - 2) << 2;
937 ratio_bits |= omap_readw(clk->enable_reg) & ~0xfd;
938 omap_writew(ratio_bits, clk->enable_reg);
944 static long round_ext_clk_rate(struct clk * clk, unsigned long rate)
946 return 96000000 / calc_ext_dsor(rate);
950 static void init_ext_clk(struct clk * clk)
955 /* Determine current rate and ensure clock is based on 96MHz APLL */
956 ratio_bits = omap_readw(clk->enable_reg) & ~1;
957 omap_writew(ratio_bits, clk->enable_reg);
959 ratio_bits = (ratio_bits & 0xfc) >> 2;
961 dsor = (ratio_bits - 6) * 2 + 8;
963 dsor = ratio_bits + 2;
965 clk-> rate = 96000000 / dsor;
969 int clk_register(struct clk *clk)
972 list_add(&clk->node, &clocks);
978 EXPORT_SYMBOL(clk_register);
980 void clk_unregister(struct clk *clk)
983 list_del(&clk->node);
986 EXPORT_SYMBOL(clk_unregister);
990 int __init clk_init(void)
993 const struct omap_clock_config *info;
994 int crystal_type = 0; /* Default 12 MHz */
996 for (clkp = onchip_clks; clkp < onchip_clks+ARRAY_SIZE(onchip_clks); clkp++) {
997 if (((*clkp)->flags &CLOCK_IN_OMAP1510) && cpu_is_omap1510()) {
1002 if (((*clkp)->flags &CLOCK_IN_OMAP16XX) && cpu_is_omap16xx()) {
1003 clk_register(*clkp);
1007 if (((*clkp)->flags &CLOCK_IN_OMAP730) && cpu_is_omap730()) {
1008 clk_register(*clkp);
1013 info = omap_get_config(OMAP_TAG_CLOCK, struct omap_clock_config);
1015 if (!cpu_is_omap1510())
1016 crystal_type = info->system_clock_type;
1019 #if defined(CONFIG_ARCH_OMAP730)
1020 ck_ref.rate = 13000000;
1021 #elif defined(CONFIG_ARCH_OMAP16XX)
1022 if (crystal_type == 2)
1023 ck_ref.rate = 19200000;
1026 /* We want to be in syncronous scalable mode */
1027 omap_writew(0x1000, ARM_SYSST);
1029 /* Find the highest supported frequency and enable it */
1030 if (select_table_rate(&virtual_ck_mpu, ~0)) {
1031 printk(KERN_ERR "System frequencies not set. Check your config.\n");
1032 /* Guess sane values (60MHz) */
1033 omap_writew(0x2290, DPLL_CTL);
1034 omap_writew(0x1005, ARM_CKCTL);
1035 ck_dpll1.rate = 60000000;
1036 propagate_rate(&ck_dpll1);
1037 printk(KERN_INFO "Clocking rate (xtal/DPLL1/MPU): %ld/%ld/%ld\n",
1038 ck_ref.rate, ck_dpll1.rate, arm_ck.rate);
1041 /* Cache rates for clocks connected to ck_ref (not dpll1) */
1042 propagate_rate(&ck_ref);
1044 #ifdef CONFIG_MACH_OMAP_PERSEUS2
1045 /* Select slicer output as OMAP input clock */
1046 omap_writew(omap_readw(OMAP730_PCC_UPLD_CTRL) & ~0x1, OMAP730_PCC_UPLD_CTRL);
1049 /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */
1050 omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL);
1052 /* Put DSP/MPUI into reset until needed */
1053 omap_writew(0, ARM_RSTCT1);
1054 omap_writew(1, ARM_RSTCT2);
1055 omap_writew(0x400, ARM_IDLECT1);
1058 * According to OMAP5910 Erratum SYS_DMA_1, bit DMACK_REQ (bit 8)
1059 * of the ARM_IDLECT2 register must be set to zero. The power-on
1060 * default value of this bit is one.
1062 omap_writew(0x0000, ARM_IDLECT2); /* Turn LCD clock off also */
1065 * Only enable those clocks we will need, let the drivers
1066 * enable other clocks as necessary
1068 clk_use(&armper_ck);
1069 clk_use(&armxor_ck);
1070 clk_use(&armtim_ck);
1072 if (cpu_is_omap1510())
1073 clk_enable(&arm_gpio_ck);