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   1 /*
   2  *  linux/drivers/ide/pci/pdc202xx_old.c        Version 0.36    Sept 11, 2002
   3  *
   4  *  Copyright (C) 1998-2002             Andre Hedrick <andre@linux-ide.org>
   5  *
   6  *  Promise Ultra33 cards with BIOS v1.20 through 1.28 will need this
   7  *  compiled into the kernel if you have more than one card installed.
   8  *  Note that BIOS v1.29 is reported to fix the problem.  Since this is
   9  *  safe chipset tuning, including this support is harmless
  10  *
  11  *  Promise Ultra66 cards with BIOS v1.11 this
  12  *  compiled into the kernel if you have more than one card installed.
  13  *
  14  *  Promise Ultra100 cards.
  15  *
  16  *  The latest chipset code will support the following ::
  17  *  Three Ultra33 controllers and 12 drives.
  18  *  8 are UDMA supported and 4 are limited to DMA mode 2 multi-word.
  19  *  The 8/4 ratio is a BIOS code limit by promise.
  20  *
  21  *  UNLESS you enable "CONFIG_PDC202XX_BURST"
  22  *
  23  */
  24
  25 /*
  26  *  Portions Copyright (C) 1999 Promise Technology, Inc.
  27  *  Author: Frank Tiernan (frankt@promise.com)
  28  *  Released under terms of General Public License
  29  */
  30
  31 #include <linux/types.h>
  32 #include <linux/module.h>
  33 #include <linux/kernel.h>
  34 #include <linux/delay.h>
  35 #include <linux/timer.h>
  36 #include <linux/mm.h>
  37 #include <linux/ioport.h>
  38 #include <linux/blkdev.h>
  39 #include <linux/hdreg.h>
  40 #include <linux/interrupt.h>
  41 #include <linux/pci.h>
  42 #include <linux/init.h>
  43 #include <linux/ide.h>
  44
  45 #include <asm/io.h>
  46 #include <asm/irq.h>
  47
  48 #define PDC202_DEBUG_CABLE              0
  49 #define PDC202XX_DEBUG_DRIVE_INFO       0
  50
  51 static const char *pdc_quirk_drives[] = {
  52         "QUANTUM FIREBALLlct08 08",
  53         "QUANTUM FIREBALLP KA6.4",
  54         "QUANTUM FIREBALLP KA9.1",
  55         "QUANTUM FIREBALLP LM20.4",
  56         "QUANTUM FIREBALLP KX13.6",
  57         "QUANTUM FIREBALLP KX20.5",
  58         "QUANTUM FIREBALLP KX27.3",
  59         "QUANTUM FIREBALLP LM20.5",
  60         NULL
  61 };
  62
  63 /* A Register */
  64 #define SYNC_ERRDY_EN   0xC0
  65
  66 #define SYNC_IN         0x80    /* control bit, different for master vs. slave drives */
  67 #define ERRDY_EN        0x40    /* control bit, different for master vs. slave drives */
  68 #define IORDY_EN        0x20    /* PIO: IOREADY */
  69 #define PREFETCH_EN     0x10    /* PIO: PREFETCH */
  70
  71 #define PA3             0x08    /* PIO"A" timing */
  72 #define PA2             0x04    /* PIO"A" timing */
  73 #define PA1             0x02    /* PIO"A" timing */
  74 #define PA0             0x01    /* PIO"A" timing */
  75
  76 /* B Register */
  77
  78 #define MB2             0x80    /* DMA"B" timing */
  79 #define MB1             0x40    /* DMA"B" timing */
  80 #define MB0             0x20    /* DMA"B" timing */
  81
  82 #define PB4             0x10    /* PIO_FORCE 1:0 */
  83
  84 #define PB3             0x08    /* PIO"B" timing */     /* PIO flow Control mode */
  85 #define PB2             0x04    /* PIO"B" timing */     /* PIO 4 */
  86 #define PB1             0x02    /* PIO"B" timing */     /* PIO 3 half */
  87 #define PB0             0x01    /* PIO"B" timing */     /* PIO 3 other half */
  88
  89 /* C Register */
  90 #define IORDYp_NO_SPEED 0x4F
  91 #define SPEED_DIS       0x0F
  92
  93 #define DMARQp          0x80
  94 #define IORDYp          0x40
  95 #define DMAR_EN         0x20
  96 #define DMAW_EN         0x10
  97
  98 #define MC3             0x08    /* DMA"C" timing */
  99 #define MC2             0x04    /* DMA"C" timing */
 100 #define MC1             0x02    /* DMA"C" timing */
 101 #define MC0             0x01    /* DMA"C" timing */
 102
 103 static u8 pdc202xx_ratemask (ide_drive_t *drive)
 104 {
 105         u8 mode;
 106
 107         switch(HWIF(drive)->pci_dev->device) {
 108                 case PCI_DEVICE_ID_PROMISE_20267:
 109                 case PCI_DEVICE_ID_PROMISE_20265:
 110                         mode = 3;
 111                         break;
 112                 case PCI_DEVICE_ID_PROMISE_20263:
 113                 case PCI_DEVICE_ID_PROMISE_20262:
 114                         mode = 2;
 115                         break;
 116                 case PCI_DEVICE_ID_PROMISE_20246:
 117                         return 1;
 118                 default:
 119                         return 0;
 120         }
 121         if (!eighty_ninty_three(drive))
 122                 mode = min(mode, (u8)1);
 123         return mode;
 124 }
 125
 126 static int pdc202xx_tune_chipset (ide_drive_t *drive, u8 xferspeed)
 127 {
 128         ide_hwif_t *hwif        = HWIF(drive);
 129         struct pci_dev *dev     = hwif->pci_dev;
 130         u8 drive_pci            = 0x60 + (drive->dn << 2);
 131         u8 speed        = ide_rate_filter(pdc202xx_ratemask(drive), xferspeed);
 132
 133         u32                     drive_conf;
 134         u8                      AP, BP, CP, DP;
 135         u8                      TA = 0, TB = 0, TC = 0;
 136
 137         if (drive->media != ide_disk &&
 138                 drive->media != ide_cdrom && speed < XFER_SW_DMA_0)
 139                 return -1;
 140
 141         pci_read_config_dword(dev, drive_pci, &drive_conf);
 142         pci_read_config_byte(dev, (drive_pci), &AP);
 143         pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
 144         pci_read_config_byte(dev, (drive_pci)|0x02, &CP);
 145         pci_read_config_byte(dev, (drive_pci)|0x03, &DP);
 146
 147         if (speed < XFER_SW_DMA_0) {
 148                 if ((AP & 0x0F) || (BP & 0x07)) {
 149                         /* clear PIO modes of lower 8421 bits of A Register */
 150                         pci_write_config_byte(dev, (drive_pci), AP &~0x0F);
 151                         pci_read_config_byte(dev, (drive_pci), &AP);
 152
 153                         /* clear PIO modes of lower 421 bits of B Register */
 154                         pci_write_config_byte(dev, (drive_pci)|0x01, BP &~0x07);
 155                         pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
 156
 157                         pci_read_config_byte(dev, (drive_pci), &AP);
 158                         pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
 159                 }
 160         } else {
 161                 if ((BP & 0xF0) && (CP & 0x0F)) {
 162                         /* clear DMA modes of upper 842 bits of B Register */
 163                         /* clear PIO forced mode upper 1 bit of B Register */
 164                         pci_write_config_byte(dev, (drive_pci)|0x01, BP &~0xF0);
 165                         pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
 166
 167                         /* clear DMA modes of lower 8421 bits of C Register */
 168                         pci_write_config_byte(dev, (drive_pci)|0x02, CP &~0x0F);
 169                         pci_read_config_byte(dev, (drive_pci)|0x02, &CP);
 170                 }
 171         }
 172
 173         pci_read_config_byte(dev, (drive_pci), &AP);
 174         pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
 175         pci_read_config_byte(dev, (drive_pci)|0x02, &CP);
 176
 177         switch(speed) {
 178                 case XFER_UDMA_6:       speed = XFER_UDMA_5;
 179                 case XFER_UDMA_5:
 180                 case XFER_UDMA_4:       TB = 0x20; TC = 0x01; break;
 181                 case XFER_UDMA_2:       TB = 0x20; TC = 0x01; break;
 182                 case XFER_UDMA_3:
 183                 case XFER_UDMA_1:       TB = 0x40; TC = 0x02; break;
 184                 case XFER_UDMA_0:
 185                 case XFER_MW_DMA_2:     TB = 0x60; TC = 0x03; break;
 186                 case XFER_MW_DMA_1:     TB = 0x60; TC = 0x04; break;
 187                 case XFER_MW_DMA_0:
 188                 case XFER_SW_DMA_2:     TB = 0x60; TC = 0x05; break;
 189                 case XFER_SW_DMA_1:     TB = 0x80; TC = 0x06; break;
 190                 case XFER_SW_DMA_0:     TB = 0xC0; TC = 0x0B; break;
 191                 case XFER_PIO_4:        TA = 0x01; TB = 0x04; break;
 192                 case XFER_PIO_3:        TA = 0x02; TB = 0x06; break;
 193                 case XFER_PIO_2:        TA = 0x03; TB = 0x08; break;
 194                 case XFER_PIO_1:        TA = 0x05; TB = 0x0C; break;
 195                 case XFER_PIO_0:
 196                 default:                TA = 0x09; TB = 0x13; break;
 197         }
 198
 199         if (speed < XFER_SW_DMA_0) {
 200                 pci_write_config_byte(dev, (drive_pci), AP|TA);
 201                 pci_write_config_byte(dev, (drive_pci)|0x01, BP|TB);
 202         } else {
 203                 pci_write_config_byte(dev, (drive_pci)|0x01, BP|TB);
 204                 pci_write_config_byte(dev, (drive_pci)|0x02, CP|TC);
 205         }
 206
 207 #if PDC202XX_DEBUG_DRIVE_INFO
 208         printk(KERN_DEBUG "%s: %s drive%d 0x%08x ",
 209                 drive->name, ide_xfer_verbose(speed),
 210                 drive->dn, drive_conf);
 211                 pci_read_config_dword(dev, drive_pci, &drive_conf);
 212         printk("0x%08x\n", drive_conf);
 213 #endif /* PDC202XX_DEBUG_DRIVE_INFO */
 214
 215         return (ide_config_drive_speed(drive, speed));
 216 }
 217
 218
 219 /*   0    1    2    3    4    5    6   7   8
 220  * 960, 480, 390, 300, 240, 180, 120, 90, 60
 221  *           180, 150, 120,  90,  60
 222  * DMA_Speed
 223  * 180, 120,  90,  90,  90,  60,  30
 224  *  11,   5,   4,   3,   2,   1,   0
 225  */
 226 static void config_chipset_for_pio (ide_drive_t *drive, u8 pio)
 227 {
 228         u8 speed = 0;
 229
 230         if (pio == 5) pio = 4;
 231         speed = XFER_PIO_0 + ide_get_best_pio_mode(drive, 255, pio, NULL);
 232
 233         pdc202xx_tune_chipset(drive, speed);
 234 }
 235
 236 static u8 pdc202xx_old_cable_detect (ide_hwif_t *hwif)
 237 {
 238         u16 CIS = 0, mask = (hwif->channel) ? (1<<11) : (1<<10);
 239         pci_read_config_word(hwif->pci_dev, 0x50, &CIS);
 240         return (CIS & mask) ? 1 : 0;
 241 }
 242
 243 /*
 244  * Set the control register to use the 66MHz system
 245  * clock for UDMA 3/4/5 mode operation when necessary.
 246  *
 247  * It may also be possible to leave the 66MHz clock on
 248  * and readjust the timing parameters.
 249  */
 250 static void pdc_old_enable_66MHz_clock(ide_hwif_t *hwif)
 251 {
 252         unsigned long clock_reg = hwif->dma_master + 0x11;
 253         u8 clock = hwif->INB(clock_reg);
 254
 255         hwif->OUTB(clock | (hwif->channel ? 0x08 : 0x02), clock_reg);
 256 }
 257
 258 static void pdc_old_disable_66MHz_clock(ide_hwif_t *hwif)
 259 {
 260         unsigned long clock_reg = hwif->dma_master + 0x11;
 261         u8 clock = hwif->INB(clock_reg);
 262
 263         hwif->OUTB(clock & ~(hwif->channel ? 0x08 : 0x02), clock_reg);
 264 }
 265
 266 static int config_chipset_for_dma (ide_drive_t *drive)
 267 {
 268         struct hd_driveid *id   = drive->id;
 269         ide_hwif_t *hwif        = HWIF(drive);
 270         struct pci_dev *dev     = hwif->pci_dev;
 271         u32 drive_conf          = 0;
 272         u8 drive_pci            = 0x60 + (drive->dn << 2);
 273         u8 test1 = 0, test2 = 0, speed = -1;
 274         u8 AP = 0, cable = 0;
 275
 276         u8 ultra_66             = ((id->dma_ultra & 0x0010) ||
 277                                    (id->dma_ultra & 0x0008)) ? 1 : 0;
 278
 279         if (dev->device != PCI_DEVICE_ID_PROMISE_20246)
 280                 cable = pdc202xx_old_cable_detect(hwif);
 281         else
 282                 ultra_66 = 0;
 283
 284         if (ultra_66 && cable) {
 285                 printk(KERN_WARNING "Warning: %s channel requires an 80-pin cable for operation.\n", hwif->channel ? "Secondary":"Primary");
 286                 printk(KERN_WARNING "%s reduced to Ultra33 mode.\n", drive->name);
 287         }
 288
 289         if (dev->device != PCI_DEVICE_ID_PROMISE_20246)
 290                 pdc_old_disable_66MHz_clock(drive->hwif);
 291
 292         drive_pci = 0x60 + (drive->dn << 2);
 293         pci_read_config_dword(dev, drive_pci, &drive_conf);
 294         if ((drive_conf != 0x004ff304) && (drive_conf != 0x004ff3c4))
 295                 goto chipset_is_set;
 296
 297         pci_read_config_byte(dev, drive_pci, &test1);
 298         if (!(test1 & SYNC_ERRDY_EN)) {
 299                 if (drive->select.b.unit & 0x01) {
 300                         pci_read_config_byte(dev, drive_pci - 4, &test2);
 301                         if ((test2 & SYNC_ERRDY_EN) &&
 302                             !(test1 & SYNC_ERRDY_EN)) {
 303                                 pci_write_config_byte(dev, drive_pci,
 304                                         test1|SYNC_ERRDY_EN);
 305                         }
 306                 } else {
 307                         pci_write_config_byte(dev, drive_pci,
 308                                 test1|SYNC_ERRDY_EN);
 309                 }
 310         }
 311
 312 chipset_is_set:
 313
 314         pci_read_config_byte(dev, (drive_pci), &AP);
 315         if (id->capability & 4) /* IORDY_EN */
 316                 pci_write_config_byte(dev, (drive_pci), AP|IORDY_EN);
 317         pci_read_config_byte(dev, (drive_pci), &AP);
 318         if (drive->media == ide_disk)   /* PREFETCH_EN */
 319                 pci_write_config_byte(dev, (drive_pci), AP|PREFETCH_EN);
 320
 321         speed = ide_dma_speed(drive, pdc202xx_ratemask(drive));
 322
 323         if (!(speed)) {
 324                 /* restore original pci-config space */
 325                 pci_write_config_dword(dev, drive_pci, drive_conf);
 326                 return 0;
 327         }
 328
 329         (void) hwif->speedproc(drive, speed);
 330         return ide_dma_enable(drive);
 331 }
 332
 333 static int pdc202xx_config_drive_xfer_rate (ide_drive_t *drive)
 334 {
 335         ide_hwif_t *hwif        = HWIF(drive);
 336         struct hd_driveid *id   = drive->id;
 337
 338         drive->init_speed = 0;
 339
 340         if (id && (id->capability & 1) && drive->autodma) {
 341
 342                 if (ide_use_dma(drive)) {
 343                         if (config_chipset_for_dma(drive))
 344                                 return hwif->ide_dma_on(drive);
 345                 }
 346
 347                 goto fast_ata_pio;
 348
 349         } else if ((id->capability & 8) || (id->field_valid & 2)) {
 350 fast_ata_pio:
 351                 hwif->tuneproc(drive, 5);
 352                 return hwif->ide_dma_off_quietly(drive);
 353         }
 354         /* IORDY not supported */
 355         return 0;
 356 }
 357
 358 static int pdc202xx_quirkproc (ide_drive_t *drive)
 359 {
 360         const char **list, *model = drive->id->model;
 361
 362         for (list = pdc_quirk_drives; *list != NULL; list++)
 363                 if (strstr(model, *list) != NULL)
 364                         return 2;
 365         return 0;
 366 }
 367
 368 static void pdc202xx_old_ide_dma_start(ide_drive_t *drive)
 369 {
 370         if (drive->current_speed > XFER_UDMA_2)
 371                 pdc_old_enable_66MHz_clock(drive->hwif);
 372         if (drive->media != ide_disk || drive->addressing == 1) {
 373                 struct request *rq      = HWGROUP(drive)->rq;
 374                 ide_hwif_t *hwif        = HWIF(drive);
 375                 unsigned long high_16   = hwif->dma_master;
 376                 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
 377                 u32 word_count  = 0;
 378                 u8 clock = hwif->INB(high_16 + 0x11);
 379
 380                 hwif->OUTB(clock|(hwif->channel ? 0x08 : 0x02), high_16+0x11);
 381                 word_count = (rq->nr_sectors << 8);
 382                 word_count = (rq_data_dir(rq) == READ) ?
 383                                         word_count | 0x05000000 :
 384                                         word_count | 0x06000000;
 385                 hwif->OUTL(word_count, atapi_reg);
 386         }
 387         ide_dma_start(drive);
 388 }
 389
 390 static int pdc202xx_old_ide_dma_end(ide_drive_t *drive)
 391 {
 392         if (drive->media != ide_disk || drive->addressing == 1) {
 393                 ide_hwif_t *hwif        = HWIF(drive);
 394                 unsigned long high_16   = hwif->dma_master;
 395                 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
 396                 u8 clock                = 0;
 397
 398                 hwif->OUTL(0, atapi_reg); /* zero out extra */
 399                 clock = hwif->INB(high_16 + 0x11);
 400                 hwif->OUTB(clock & ~(hwif->channel ? 0x08:0x02), high_16+0x11);
 401         }
 402         if (drive->current_speed > XFER_UDMA_2)
 403                 pdc_old_disable_66MHz_clock(drive->hwif);
 404         return __ide_dma_end(drive);
 405 }
 406
 407 static int pdc202xx_old_ide_dma_test_irq(ide_drive_t *drive)
 408 {
 409         ide_hwif_t *hwif        = HWIF(drive);
 410         unsigned long high_16   = hwif->dma_master;
 411         u8 dma_stat             = hwif->INB(hwif->dma_status);
 412         u8 sc1d                 = hwif->INB((high_16 + 0x001d));
 413
 414         if (hwif->channel) {
 415                 /* bit7: Error, bit6: Interrupting, bit5: FIFO Full, bit4: FIFO Empty */
 416                 if ((sc1d & 0x50) == 0x50)
 417                         goto somebody_else;
 418                 else if ((sc1d & 0x40) == 0x40)
 419                         return (dma_stat & 4) == 4;
 420         } else {
 421                 /* bit3: Error, bit2: Interrupting, bit1: FIFO Full, bit0: FIFO Empty */
 422                 if ((sc1d & 0x05) == 0x05)
 423                         goto somebody_else;
 424                 else if ((sc1d & 0x04) == 0x04)
 425                         return (dma_stat & 4) == 4;
 426         }
 427 somebody_else:
 428         return (dma_stat & 4) == 4;     /* return 1 if INTR asserted */
 429 }
 430
 431 static int pdc202xx_ide_dma_lostirq(ide_drive_t *drive)
 432 {
 433         if (HWIF(drive)->resetproc != NULL)
 434                 HWIF(drive)->resetproc(drive);
 435         return __ide_dma_lostirq(drive);
 436 }
 437
 438 static int pdc202xx_ide_dma_timeout(ide_drive_t *drive)
 439 {
 440         if (HWIF(drive)->resetproc != NULL)
 441                 HWIF(drive)->resetproc(drive);
 442         return __ide_dma_timeout(drive);
 443 }
 444
 445 static void pdc202xx_reset_host (ide_hwif_t *hwif)
 446 {
 447         unsigned long high_16   = hwif->dma_master;
 448         u8 udma_speed_flag      = hwif->INB(high_16|0x001f);
 449
 450         hwif->OUTB((udma_speed_flag | 0x10), (high_16|0x001f));
 451         mdelay(100);
 452         hwif->OUTB((udma_speed_flag & ~0x10), (high_16|0x001f));
 453         mdelay(2000);   /* 2 seconds ?! */
 454
 455         printk(KERN_WARNING "PDC202XX: %s channel reset.\n",
 456                 hwif->channel ? "Secondary" : "Primary");
 457 }
 458
 459 static void pdc202xx_reset (ide_drive_t *drive)
 460 {
 461         ide_hwif_t *hwif        = HWIF(drive);
 462         ide_hwif_t *mate        = hwif->mate;
 463
 464         pdc202xx_reset_host(hwif);
 465         pdc202xx_reset_host(mate);
 466         hwif->tuneproc(drive, 5);
 467 }
 468
 469 static unsigned int __devinit init_chipset_pdc202xx(struct pci_dev *dev,
 470                                                         const char *name)
 471 {
 472         /* This doesn't appear needed */
 473         if (dev->resource[PCI_ROM_RESOURCE].start) {
 474                 pci_write_config_dword(dev, PCI_ROM_ADDRESS,
 475                         dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
 476                 printk(KERN_INFO "%s: ROM enabled at 0x%08lx\n", name,
 477                         (unsigned long)dev->resource[PCI_ROM_RESOURCE].start);
 478         }
 479
 480         return dev->irq;
 481 }
 482
 483 static void __devinit init_hwif_pdc202xx(ide_hwif_t *hwif)
 484 {
 485         struct pci_dev *dev = hwif->pci_dev;
 486
 487         /* PDC20265 has problems with large LBA48 requests */
 488         if ((dev->device == PCI_DEVICE_ID_PROMISE_20267) ||
 489             (dev->device == PCI_DEVICE_ID_PROMISE_20265))
 490                 hwif->rqsize = 256;
 491
 492         hwif->autodma = 0;
 493         hwif->tuneproc  = &config_chipset_for_pio;
 494         hwif->quirkproc = &pdc202xx_quirkproc;
 495
 496         if (hwif->pci_dev->device != PCI_DEVICE_ID_PROMISE_20246)
 497                 hwif->resetproc = &pdc202xx_reset;
 498
 499         hwif->speedproc = &pdc202xx_tune_chipset;
 500
 501         hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
 502
 503         hwif->ultra_mask = 0x3f;
 504         hwif->mwdma_mask = 0x07;
 505         hwif->swdma_mask = 0x07;
 506         hwif->atapi_dma = 1;
 507
 508         hwif->err_stops_fifo = 1;
 509
 510         hwif->ide_dma_check = &pdc202xx_config_drive_xfer_rate;
 511         hwif->ide_dma_lostirq = &pdc202xx_ide_dma_lostirq;
 512         hwif->ide_dma_timeout = &pdc202xx_ide_dma_timeout;
 513
 514         if (hwif->pci_dev->device != PCI_DEVICE_ID_PROMISE_20246) {
 515                 if (!(hwif->udma_four))
 516                         hwif->udma_four = (pdc202xx_old_cable_detect(hwif)) ? 0 : 1;
 517                 hwif->dma_start = &pdc202xx_old_ide_dma_start;
 518                 hwif->ide_dma_end = &pdc202xx_old_ide_dma_end;
 519         }
 520         hwif->ide_dma_test_irq = &pdc202xx_old_ide_dma_test_irq;
 521
 522         if (!noautodma)
 523                 hwif->autodma = 1;
 524         hwif->drives[0].autodma = hwif->drives[1].autodma = hwif->autodma;
 525 #if PDC202_DEBUG_CABLE
 526         printk(KERN_DEBUG "%s: %s-pin cable\n",
 527                 hwif->name, hwif->udma_four ? "80" : "40");
 528 #endif /* PDC202_DEBUG_CABLE */
 529 }
 530
 531 static void __devinit init_dma_pdc202xx(ide_hwif_t *hwif, unsigned long dmabase)
 532 {
 533         u8 udma_speed_flag = 0, primary_mode = 0, secondary_mode = 0;
 534
 535         if (hwif->channel) {
 536                 ide_setup_dma(hwif, dmabase, 8);
 537                 return;
 538         }
 539
 540         udma_speed_flag = hwif->INB((dmabase|0x1f));
 541         primary_mode    = hwif->INB((dmabase|0x1a));
 542         secondary_mode  = hwif->INB((dmabase|0x1b));
 543         printk(KERN_INFO "%s: (U)DMA Burst Bit %sABLED " \
 544                 "Primary %s Mode " \
 545                 "Secondary %s Mode.\n", hwif->cds->name,
 546                 (udma_speed_flag & 1) ? "EN" : "DIS",
 547                 (primary_mode & 1) ? "MASTER" : "PCI",
 548                 (secondary_mode & 1) ? "MASTER" : "PCI" );
 549
 550 #ifdef CONFIG_PDC202XX_BURST
 551         if (!(udma_speed_flag & 1)) {
 552                 printk(KERN_INFO "%s: FORCING BURST BIT 0x%02x->0x%02x ",
 553                         hwif->cds->name, udma_speed_flag,
 554                         (udma_speed_flag|1));
 555                 hwif->OUTB(udma_speed_flag|1,(dmabase|0x1f));
 556                 printk("%sACTIVE\n",
 557                         (hwif->INB(dmabase|0x1f)&1) ? "":"IN");
 558         }
 559 #endif /* CONFIG_PDC202XX_BURST */
 560 #ifdef CONFIG_PDC202XX_MASTER
 561         if (!(primary_mode & 1)) {
 562                 printk(KERN_INFO "%s: FORCING PRIMARY MODE BIT "
 563                         "0x%02x -> 0x%02x ", hwif->cds->name,
 564                         primary_mode, (primary_mode|1));
 565                 hwif->OUTB(primary_mode|1, (dmabase|0x1a));
 566                 printk("%s\n",
 567                         (hwif->INB((dmabase|0x1a)) & 1) ? "MASTER" : "PCI");
 568         }
 569
 570         if (!(secondary_mode & 1)) {
 571                 printk(KERN_INFO "%s: FORCING SECONDARY MODE BIT "
 572                         "0x%02x -> 0x%02x ", hwif->cds->name,
 573                         secondary_mode, (secondary_mode|1));
 574                 hwif->OUTB(secondary_mode|1, (dmabase|0x1b));
 575                 printk("%s\n",
 576                         (hwif->INB((dmabase|0x1b)) & 1) ? "MASTER" : "PCI");
 577         }
 578 #endif /* CONFIG_PDC202XX_MASTER */
 579
 580         ide_setup_dma(hwif, dmabase, 8);
 581 }
 582
 583 static int __devinit init_setup_pdc202ata4(struct pci_dev *dev,
 584                                            ide_pci_device_t *d)
 585 {
 586         if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) {
 587                 u8 irq = 0, irq2 = 0;
 588                 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
 589                 /* 0xbc */
 590                 pci_read_config_byte(dev, (PCI_INTERRUPT_LINE)|0x80, &irq2);
 591                 if (irq != irq2) {
 592                         pci_write_config_byte(dev,
 593                                 (PCI_INTERRUPT_LINE)|0x80, irq);     /* 0xbc */
 594                         printk(KERN_INFO "%s: pci-config space interrupt "
 595                                 "mirror fixed.\n", d->name);
 596                 }
 597         }
 598         return ide_setup_pci_device(dev, d);
 599 }
 600
 601 static int __devinit init_setup_pdc20265(struct pci_dev *dev,
 602                                          ide_pci_device_t *d)
 603 {
 604         if ((dev->bus->self) &&
 605             (dev->bus->self->vendor == PCI_VENDOR_ID_INTEL) &&
 606             ((dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960) ||
 607              (dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960RM))) {
 608                 printk(KERN_INFO "ide: Skipping Promise PDC20265 "
 609                         "attached to I2O RAID controller.\n");
 610                 return -ENODEV;
 611         }
 612         return ide_setup_pci_device(dev, d);
 613 }
 614
 615 static int __devinit init_setup_pdc202xx(struct pci_dev *dev,
 616                                          ide_pci_device_t *d)
 617 {
 618         return ide_setup_pci_device(dev, d);
 619 }
 620
 621 static ide_pci_device_t pdc202xx_chipsets[] __devinitdata = {
 622         {       /* 0 */
 623                 .name           = "PDC20246",
 624                 .init_setup     = init_setup_pdc202ata4,
 625                 .init_chipset   = init_chipset_pdc202xx,
 626                 .init_hwif      = init_hwif_pdc202xx,
 627                 .init_dma       = init_dma_pdc202xx,
 628                 .channels       = 2,
 629                 .autodma        = AUTODMA,
 630                 .bootable       = OFF_BOARD,
 631                 .extra          = 16,
 632         },{     /* 1 */
 633                 .name           = "PDC20262",
 634                 .init_setup     = init_setup_pdc202ata4,
 635                 .init_chipset   = init_chipset_pdc202xx,
 636                 .init_hwif      = init_hwif_pdc202xx,
 637                 .init_dma       = init_dma_pdc202xx,
 638                 .channels       = 2,
 639                 .autodma        = AUTODMA,
 640                 .bootable       = OFF_BOARD,
 641                 .extra          = 48,
 642         },{     /* 2 */
 643                 .name           = "PDC20263",
 644                 .init_setup     = init_setup_pdc202ata4,
 645                 .init_chipset   = init_chipset_pdc202xx,
 646                 .init_hwif      = init_hwif_pdc202xx,
 647                 .init_dma       = init_dma_pdc202xx,
 648                 .channels       = 2,
 649                 .autodma        = AUTODMA,
 650                 .bootable       = OFF_BOARD,
 651                 .extra          = 48,
 652         },{     /* 3 */
 653                 .name           = "PDC20265",
 654                 .init_setup     = init_setup_pdc20265,
 655                 .init_chipset   = init_chipset_pdc202xx,
 656                 .init_hwif      = init_hwif_pdc202xx,
 657                 .init_dma       = init_dma_pdc202xx,
 658                 .channels       = 2,
 659                 .autodma        = AUTODMA,
 660                 .bootable       = OFF_BOARD,
 661                 .extra          = 48,
 662         },{     /* 4 */
 663                 .name           = "PDC20267",
 664                 .init_setup     = init_setup_pdc202xx,
 665                 .init_chipset   = init_chipset_pdc202xx,
 666                 .init_hwif      = init_hwif_pdc202xx,
 667                 .init_dma       = init_dma_pdc202xx,
 668                 .channels       = 2,
 669                 .autodma        = AUTODMA,
 670                 .bootable       = OFF_BOARD,
 671                 .extra          = 48,
 672         }
 673 };
 674
 675 /**
 676  *      pdc202xx_init_one       -       called when a PDC202xx is found
 677  *      @dev: the pdc202xx device
 678  *      @id: the matching pci id
 679  *
 680  *      Called when the PCI registration layer (or the IDE initialization)
 681  *      finds a device matching our IDE device tables.
 682  */
 683
 684 static int __devinit pdc202xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 685 {
 686         ide_pci_device_t *d = &pdc202xx_chipsets[id->driver_data];
 687
 688         return d->init_setup(dev, d);
 689 }
 690
 691 static struct pci_device_id pdc202xx_pci_tbl[] = {
 692         { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20246, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
 693         { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20262, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
 694         { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20263, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
 695         { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20265, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
 696         { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20267, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
 697         { 0, },
 698 };
 699 MODULE_DEVICE_TABLE(pci, pdc202xx_pci_tbl);
 700
 701 static struct pci_driver driver = {
 702         .name           = "Promise_Old_IDE",
 703         .id_table       = pdc202xx_pci_tbl,
 704         .probe          = pdc202xx_init_one,
 705 };
 706
 707 static int __init pdc202xx_ide_init(void)
 708 {
 709         return ide_pci_register_driver(&driver);
 710 }
 711
 712 module_init(pdc202xx_ide_init);
 713
 714 MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
 715 MODULE_DESCRIPTION("PCI driver module for older Promise IDE");
 716 MODULE_LICENSE("GPL");