Merge git://git.infradead.org/battery-2.6
[linux-2.6] / arch / arm / mach-omap1 / clock.c
1 //kernel/linux-omap-fsample/arch/arm/mach-omap1/clock.c#2 - edit change 3808 (text)
2 /*
3  *  linux/arch/arm/mach-omap1/clock.c
4  *
5  *  Copyright (C) 2004 - 2005 Nokia corporation
6  *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
7  *
8  *  Modified to use omap shared clock framework by
9  *  Tony Lindgren <tony@atomide.com>
10  *
11  * This program is free software; you can redistribute it and/or modify
12  * it under the terms of the GNU General Public License version 2 as
13  * published by the Free Software Foundation.
14  */
15 #include <linux/module.h>
16 #include <linux/kernel.h>
17 #include <linux/list.h>
18 #include <linux/errno.h>
19 #include <linux/err.h>
20 #include <linux/clk.h>
21
22 #include <asm/io.h>
23 #include <asm/mach-types.h>
24
25 #include <asm/arch/cpu.h>
26 #include <asm/arch/usb.h>
27 #include <asm/arch/clock.h>
28 #include <asm/arch/sram.h>
29
30 #include "clock.h"
31
32 __u32 arm_idlect1_mask;
33
34 /*-------------------------------------------------------------------------
35  * Omap1 specific clock functions
36  *-------------------------------------------------------------------------*/
37
38 static void omap1_watchdog_recalc(struct clk * clk)
39 {
40         clk->rate = clk->parent->rate / 14;
41 }
42
43 static void omap1_uart_recalc(struct clk * clk)
44 {
45         unsigned int val = omap_readl(clk->enable_reg);
46         if (val & clk->enable_bit)
47                 clk->rate = 48000000;
48         else
49                 clk->rate = 12000000;
50 }
51
52 static void omap1_sossi_recalc(struct clk *clk)
53 {
54         u32 div = omap_readl(MOD_CONF_CTRL_1);
55
56         div = (div >> 17) & 0x7;
57         div++;
58         clk->rate = clk->parent->rate / div;
59 }
60
61 static int omap1_clk_enable_dsp_domain(struct clk *clk)
62 {
63         int retval;
64
65         retval = omap1_clk_enable(&api_ck.clk);
66         if (!retval) {
67                 retval = omap1_clk_enable_generic(clk);
68                 omap1_clk_disable(&api_ck.clk);
69         }
70
71         return retval;
72 }
73
74 static void omap1_clk_disable_dsp_domain(struct clk *clk)
75 {
76         if (omap1_clk_enable(&api_ck.clk) == 0) {
77                 omap1_clk_disable_generic(clk);
78                 omap1_clk_disable(&api_ck.clk);
79         }
80 }
81
82 static int omap1_clk_enable_uart_functional(struct clk *clk)
83 {
84         int ret;
85         struct uart_clk *uclk;
86
87         ret = omap1_clk_enable_generic(clk);
88         if (ret == 0) {
89                 /* Set smart idle acknowledgement mode */
90                 uclk = (struct uart_clk *)clk;
91                 omap_writeb((omap_readb(uclk->sysc_addr) & ~0x10) | 8,
92                             uclk->sysc_addr);
93         }
94
95         return ret;
96 }
97
98 static void omap1_clk_disable_uart_functional(struct clk *clk)
99 {
100         struct uart_clk *uclk;
101
102         /* Set force idle acknowledgement mode */
103         uclk = (struct uart_clk *)clk;
104         omap_writeb((omap_readb(uclk->sysc_addr) & ~0x18), uclk->sysc_addr);
105
106         omap1_clk_disable_generic(clk);
107 }
108
109 static void omap1_clk_allow_idle(struct clk *clk)
110 {
111         struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk;
112
113         if (!(clk->flags & CLOCK_IDLE_CONTROL))
114                 return;
115
116         if (iclk->no_idle_count > 0 && !(--iclk->no_idle_count))
117                 arm_idlect1_mask |= 1 << iclk->idlect_shift;
118 }
119
120 static void omap1_clk_deny_idle(struct clk *clk)
121 {
122         struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk;
123
124         if (!(clk->flags & CLOCK_IDLE_CONTROL))
125                 return;
126
127         if (iclk->no_idle_count++ == 0)
128                 arm_idlect1_mask &= ~(1 << iclk->idlect_shift);
129 }
130
131 static __u16 verify_ckctl_value(__u16 newval)
132 {
133         /* This function checks for following limitations set
134          * by the hardware (all conditions must be true):
135          * DSPMMU_CK == DSP_CK  or  DSPMMU_CK == DSP_CK/2
136          * ARM_CK >= TC_CK
137          * DSP_CK >= TC_CK
138          * DSPMMU_CK >= TC_CK
139          *
140          * In addition following rules are enforced:
141          * LCD_CK <= TC_CK
142          * ARMPER_CK <= TC_CK
143          *
144          * However, maximum frequencies are not checked for!
145          */
146         __u8 per_exp;
147         __u8 lcd_exp;
148         __u8 arm_exp;
149         __u8 dsp_exp;
150         __u8 tc_exp;
151         __u8 dspmmu_exp;
152
153         per_exp = (newval >> CKCTL_PERDIV_OFFSET) & 3;
154         lcd_exp = (newval >> CKCTL_LCDDIV_OFFSET) & 3;
155         arm_exp = (newval >> CKCTL_ARMDIV_OFFSET) & 3;
156         dsp_exp = (newval >> CKCTL_DSPDIV_OFFSET) & 3;
157         tc_exp = (newval >> CKCTL_TCDIV_OFFSET) & 3;
158         dspmmu_exp = (newval >> CKCTL_DSPMMUDIV_OFFSET) & 3;
159
160         if (dspmmu_exp < dsp_exp)
161                 dspmmu_exp = dsp_exp;
162         if (dspmmu_exp > dsp_exp+1)
163                 dspmmu_exp = dsp_exp+1;
164         if (tc_exp < arm_exp)
165                 tc_exp = arm_exp;
166         if (tc_exp < dspmmu_exp)
167                 tc_exp = dspmmu_exp;
168         if (tc_exp > lcd_exp)
169                 lcd_exp = tc_exp;
170         if (tc_exp > per_exp)
171                 per_exp = tc_exp;
172
173         newval &= 0xf000;
174         newval |= per_exp << CKCTL_PERDIV_OFFSET;
175         newval |= lcd_exp << CKCTL_LCDDIV_OFFSET;
176         newval |= arm_exp << CKCTL_ARMDIV_OFFSET;
177         newval |= dsp_exp << CKCTL_DSPDIV_OFFSET;
178         newval |= tc_exp << CKCTL_TCDIV_OFFSET;
179         newval |= dspmmu_exp << CKCTL_DSPMMUDIV_OFFSET;
180
181         return newval;
182 }
183
184 static int calc_dsor_exp(struct clk *clk, unsigned long rate)
185 {
186         /* Note: If target frequency is too low, this function will return 4,
187          * which is invalid value. Caller must check for this value and act
188          * accordingly.
189          *
190          * Note: This function does not check for following limitations set
191          * by the hardware (all conditions must be true):
192          * DSPMMU_CK == DSP_CK  or  DSPMMU_CK == DSP_CK/2
193          * ARM_CK >= TC_CK
194          * DSP_CK >= TC_CK
195          * DSPMMU_CK >= TC_CK
196          */
197         unsigned long realrate;
198         struct clk * parent;
199         unsigned  dsor_exp;
200
201         if (unlikely(!(clk->flags & RATE_CKCTL)))
202                 return -EINVAL;
203
204         parent = clk->parent;
205         if (unlikely(parent == 0))
206                 return -EIO;
207
208         realrate = parent->rate;
209         for (dsor_exp=0; dsor_exp<4; dsor_exp++) {
210                 if (realrate <= rate)
211                         break;
212
213                 realrate /= 2;
214         }
215
216         return dsor_exp;
217 }
218
219 static void omap1_ckctl_recalc(struct clk * clk)
220 {
221         int dsor;
222
223         /* Calculate divisor encoded as 2-bit exponent */
224         dsor = 1 << (3 & (omap_readw(ARM_CKCTL) >> clk->rate_offset));
225
226         if (unlikely(clk->rate == clk->parent->rate / dsor))
227                 return; /* No change, quick exit */
228         clk->rate = clk->parent->rate / dsor;
229
230         if (unlikely(clk->flags & RATE_PROPAGATES))
231                 propagate_rate(clk);
232 }
233
234 static void omap1_ckctl_recalc_dsp_domain(struct clk * clk)
235 {
236         int dsor;
237
238         /* Calculate divisor encoded as 2-bit exponent
239          *
240          * The clock control bits are in DSP domain,
241          * so api_ck is needed for access.
242          * Note that DSP_CKCTL virt addr = phys addr, so
243          * we must use __raw_readw() instead of omap_readw().
244          */
245         omap1_clk_enable(&api_ck.clk);
246         dsor = 1 << (3 & (__raw_readw(DSP_CKCTL) >> clk->rate_offset));
247         omap1_clk_disable(&api_ck.clk);
248
249         if (unlikely(clk->rate == clk->parent->rate / dsor))
250                 return; /* No change, quick exit */
251         clk->rate = clk->parent->rate / dsor;
252
253         if (unlikely(clk->flags & RATE_PROPAGATES))
254                 propagate_rate(clk);
255 }
256
257 /* MPU virtual clock functions */
258 static int omap1_select_table_rate(struct clk * clk, unsigned long rate)
259 {
260         /* Find the highest supported frequency <= rate and switch to it */
261         struct mpu_rate * ptr;
262
263         if (clk != &virtual_ck_mpu)
264                 return -EINVAL;
265
266         for (ptr = rate_table; ptr->rate; ptr++) {
267                 if (ptr->xtal != ck_ref.rate)
268                         continue;
269
270                 /* DPLL1 cannot be reprogrammed without risking system crash */
271                 if (likely(ck_dpll1.rate!=0) && ptr->pll_rate != ck_dpll1.rate)
272                         continue;
273
274                 /* Can check only after xtal frequency check */
275                 if (ptr->rate <= rate)
276                         break;
277         }
278
279         if (!ptr->rate)
280                 return -EINVAL;
281
282         /*
283          * In most cases we should not need to reprogram DPLL.
284          * Reprogramming the DPLL is tricky, it must be done from SRAM.
285          * (on 730, bit 13 must always be 1)
286          */
287         if (cpu_is_omap730())
288                 omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val | 0x2000);
289         else
290                 omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val);
291
292         ck_dpll1.rate = ptr->pll_rate;
293         propagate_rate(&ck_dpll1);
294         return 0;
295 }
296
297 static int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate)
298 {
299         int  ret = -EINVAL;
300         int  dsor_exp;
301         __u16  regval;
302
303         if (clk->flags & RATE_CKCTL) {
304                 dsor_exp = calc_dsor_exp(clk, rate);
305                 if (dsor_exp > 3)
306                         dsor_exp = -EINVAL;
307                 if (dsor_exp < 0)
308                         return dsor_exp;
309
310                 regval = __raw_readw(DSP_CKCTL);
311                 regval &= ~(3 << clk->rate_offset);
312                 regval |= dsor_exp << clk->rate_offset;
313                 __raw_writew(regval, DSP_CKCTL);
314                 clk->rate = clk->parent->rate / (1 << dsor_exp);
315                 ret = 0;
316         }
317
318         if (unlikely(ret == 0 && (clk->flags & RATE_PROPAGATES)))
319                 propagate_rate(clk);
320
321         return ret;
322 }
323
324 static long omap1_round_to_table_rate(struct clk * clk, unsigned long rate)
325 {
326         /* Find the highest supported frequency <= rate */
327         struct mpu_rate * ptr;
328         long  highest_rate;
329
330         if (clk != &virtual_ck_mpu)
331                 return -EINVAL;
332
333         highest_rate = -EINVAL;
334
335         for (ptr = rate_table; ptr->rate; ptr++) {
336                 if (ptr->xtal != ck_ref.rate)
337                         continue;
338
339                 highest_rate = ptr->rate;
340
341                 /* Can check only after xtal frequency check */
342                 if (ptr->rate <= rate)
343                         break;
344         }
345
346         return highest_rate;
347 }
348
349 static unsigned calc_ext_dsor(unsigned long rate)
350 {
351         unsigned dsor;
352
353         /* MCLK and BCLK divisor selection is not linear:
354          * freq = 96MHz / dsor
355          *
356          * RATIO_SEL range: dsor <-> RATIO_SEL
357          * 0..6: (RATIO_SEL+2) <-> (dsor-2)
358          * 6..48:  (8+(RATIO_SEL-6)*2) <-> ((dsor-8)/2+6)
359          * Minimum dsor is 2 and maximum is 96. Odd divisors starting from 9
360          * can not be used.
361          */
362         for (dsor = 2; dsor < 96; ++dsor) {
363                 if ((dsor & 1) && dsor > 8)
364                         continue;
365                 if (rate >= 96000000 / dsor)
366                         break;
367         }
368         return dsor;
369 }
370
371 /* Only needed on 1510 */
372 static int omap1_set_uart_rate(struct clk * clk, unsigned long rate)
373 {
374         unsigned int val;
375
376         val = omap_readl(clk->enable_reg);
377         if (rate == 12000000)
378                 val &= ~(1 << clk->enable_bit);
379         else if (rate == 48000000)
380                 val |= (1 << clk->enable_bit);
381         else
382                 return -EINVAL;
383         omap_writel(val, clk->enable_reg);
384         clk->rate = rate;
385
386         return 0;
387 }
388
389 /* External clock (MCLK & BCLK) functions */
390 static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate)
391 {
392         unsigned dsor;
393         __u16 ratio_bits;
394
395         dsor = calc_ext_dsor(rate);
396         clk->rate = 96000000 / dsor;
397         if (dsor > 8)
398                 ratio_bits = ((dsor - 8) / 2 + 6) << 2;
399         else
400                 ratio_bits = (dsor - 2) << 2;
401
402         ratio_bits |= omap_readw(clk->enable_reg) & ~0xfd;
403         omap_writew(ratio_bits, clk->enable_reg);
404
405         return 0;
406 }
407
408 static int omap1_set_sossi_rate(struct clk *clk, unsigned long rate)
409 {
410         u32 l;
411         int div;
412         unsigned long p_rate;
413
414         p_rate = clk->parent->rate;
415         /* Round towards slower frequency */
416         div = (p_rate + rate - 1) / rate;
417         div--;
418         if (div < 0 || div > 7)
419                 return -EINVAL;
420
421         l = omap_readl(MOD_CONF_CTRL_1);
422         l &= ~(7 << 17);
423         l |= div << 17;
424         omap_writel(l, MOD_CONF_CTRL_1);
425
426         clk->rate = p_rate / (div + 1);
427         if (unlikely(clk->flags & RATE_PROPAGATES))
428                 propagate_rate(clk);
429
430         return 0;
431 }
432
433 static long omap1_round_ext_clk_rate(struct clk * clk, unsigned long rate)
434 {
435         return 96000000 / calc_ext_dsor(rate);
436 }
437
438 static void omap1_init_ext_clk(struct clk * clk)
439 {
440         unsigned dsor;
441         __u16 ratio_bits;
442
443         /* Determine current rate and ensure clock is based on 96MHz APLL */
444         ratio_bits = omap_readw(clk->enable_reg) & ~1;
445         omap_writew(ratio_bits, clk->enable_reg);
446
447         ratio_bits = (ratio_bits & 0xfc) >> 2;
448         if (ratio_bits > 6)
449                 dsor = (ratio_bits - 6) * 2 + 8;
450         else
451                 dsor = ratio_bits + 2;
452
453         clk-> rate = 96000000 / dsor;
454 }
455
456 static int omap1_clk_enable(struct clk *clk)
457 {
458         int ret = 0;
459         if (clk->usecount++ == 0) {
460                 if (likely(clk->parent)) {
461                         ret = omap1_clk_enable(clk->parent);
462
463                         if (unlikely(ret != 0)) {
464                                 clk->usecount--;
465                                 return ret;
466                         }
467
468                         if (clk->flags & CLOCK_NO_IDLE_PARENT)
469                                 omap1_clk_deny_idle(clk->parent);
470                 }
471
472                 ret = clk->enable(clk);
473
474                 if (unlikely(ret != 0) && clk->parent) {
475                         omap1_clk_disable(clk->parent);
476                         clk->usecount--;
477                 }
478         }
479
480         return ret;
481 }
482
483 static void omap1_clk_disable(struct clk *clk)
484 {
485         if (clk->usecount > 0 && !(--clk->usecount)) {
486                 clk->disable(clk);
487                 if (likely(clk->parent)) {
488                         omap1_clk_disable(clk->parent);
489                         if (clk->flags & CLOCK_NO_IDLE_PARENT)
490                                 omap1_clk_allow_idle(clk->parent);
491                 }
492         }
493 }
494
495 static int omap1_clk_enable_generic(struct clk *clk)
496 {
497         __u16 regval16;
498         __u32 regval32;
499
500         if (clk->flags & ALWAYS_ENABLED)
501                 return 0;
502
503         if (unlikely(clk->enable_reg == 0)) {
504                 printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
505                        clk->name);
506                 return -EINVAL;
507         }
508
509         if (clk->flags & ENABLE_REG_32BIT) {
510                 if (clk->flags & VIRTUAL_IO_ADDRESS) {
511                         regval32 = __raw_readl(clk->enable_reg);
512                         regval32 |= (1 << clk->enable_bit);
513                         __raw_writel(regval32, clk->enable_reg);
514                 } else {
515                         regval32 = omap_readl(clk->enable_reg);
516                         regval32 |= (1 << clk->enable_bit);
517                         omap_writel(regval32, clk->enable_reg);
518                 }
519         } else {
520                 if (clk->flags & VIRTUAL_IO_ADDRESS) {
521                         regval16 = __raw_readw(clk->enable_reg);
522                         regval16 |= (1 << clk->enable_bit);
523                         __raw_writew(regval16, clk->enable_reg);
524                 } else {
525                         regval16 = omap_readw(clk->enable_reg);
526                         regval16 |= (1 << clk->enable_bit);
527                         omap_writew(regval16, clk->enable_reg);
528                 }
529         }
530
531         return 0;
532 }
533
534 static void omap1_clk_disable_generic(struct clk *clk)
535 {
536         __u16 regval16;
537         __u32 regval32;
538
539         if (clk->enable_reg == 0)
540                 return;
541
542         if (clk->flags & ENABLE_REG_32BIT) {
543                 if (clk->flags & VIRTUAL_IO_ADDRESS) {
544                         regval32 = __raw_readl(clk->enable_reg);
545                         regval32 &= ~(1 << clk->enable_bit);
546                         __raw_writel(regval32, clk->enable_reg);
547                 } else {
548                         regval32 = omap_readl(clk->enable_reg);
549                         regval32 &= ~(1 << clk->enable_bit);
550                         omap_writel(regval32, clk->enable_reg);
551                 }
552         } else {
553                 if (clk->flags & VIRTUAL_IO_ADDRESS) {
554                         regval16 = __raw_readw(clk->enable_reg);
555                         regval16 &= ~(1 << clk->enable_bit);
556                         __raw_writew(regval16, clk->enable_reg);
557                 } else {
558                         regval16 = omap_readw(clk->enable_reg);
559                         regval16 &= ~(1 << clk->enable_bit);
560                         omap_writew(regval16, clk->enable_reg);
561                 }
562         }
563 }
564
565 static long omap1_clk_round_rate(struct clk *clk, unsigned long rate)
566 {
567         int dsor_exp;
568
569         if (clk->flags & RATE_FIXED)
570                 return clk->rate;
571
572         if (clk->flags & RATE_CKCTL) {
573                 dsor_exp = calc_dsor_exp(clk, rate);
574                 if (dsor_exp < 0)
575                         return dsor_exp;
576                 if (dsor_exp > 3)
577                         dsor_exp = 3;
578                 return clk->parent->rate / (1 << dsor_exp);
579         }
580
581         if(clk->round_rate != 0)
582                 return clk->round_rate(clk, rate);
583
584         return clk->rate;
585 }
586
587 static int omap1_clk_set_rate(struct clk *clk, unsigned long rate)
588 {
589         int  ret = -EINVAL;
590         int  dsor_exp;
591         __u16  regval;
592
593         if (clk->set_rate)
594                 ret = clk->set_rate(clk, rate);
595         else if (clk->flags & RATE_CKCTL) {
596                 dsor_exp = calc_dsor_exp(clk, rate);
597                 if (dsor_exp > 3)
598                         dsor_exp = -EINVAL;
599                 if (dsor_exp < 0)
600                         return dsor_exp;
601
602                 regval = omap_readw(ARM_CKCTL);
603                 regval &= ~(3 << clk->rate_offset);
604                 regval |= dsor_exp << clk->rate_offset;
605                 regval = verify_ckctl_value(regval);
606                 omap_writew(regval, ARM_CKCTL);
607                 clk->rate = clk->parent->rate / (1 << dsor_exp);
608                 ret = 0;
609         }
610
611         if (unlikely(ret == 0 && (clk->flags & RATE_PROPAGATES)))
612                 propagate_rate(clk);
613
614         return ret;
615 }
616
617 /*-------------------------------------------------------------------------
618  * Omap1 clock reset and init functions
619  *-------------------------------------------------------------------------*/
620
621 #ifdef CONFIG_OMAP_RESET_CLOCKS
622
623 static void __init omap1_clk_disable_unused(struct clk *clk)
624 {
625         __u32 regval32;
626
627         /* Clocks in the DSP domain need api_ck. Just assume bootloader
628          * has not enabled any DSP clocks */
629         if ((u32)clk->enable_reg == DSP_IDLECT2) {
630                 printk(KERN_INFO "Skipping reset check for DSP domain "
631                        "clock \"%s\"\n", clk->name);
632                 return;
633         }
634
635         /* Is the clock already disabled? */
636         if (clk->flags & ENABLE_REG_32BIT) {
637                 if (clk->flags & VIRTUAL_IO_ADDRESS)
638                         regval32 = __raw_readl(clk->enable_reg);
639                         else
640                                 regval32 = omap_readl(clk->enable_reg);
641         } else {
642                 if (clk->flags & VIRTUAL_IO_ADDRESS)
643                         regval32 = __raw_readw(clk->enable_reg);
644                 else
645                         regval32 = omap_readw(clk->enable_reg);
646         }
647
648         if ((regval32 & (1 << clk->enable_bit)) == 0)
649                 return;
650
651         /* FIXME: This clock seems to be necessary but no-one
652          * has asked for its activation. */
653         if (clk == &tc2_ck              // FIX: pm.c (SRAM), CCP, Camera
654             || clk == &ck_dpll1out.clk  // FIX: SoSSI, SSR
655             || clk == &arm_gpio_ck      // FIX: GPIO code for 1510
656                 ) {
657                 printk(KERN_INFO "FIXME: Clock \"%s\" seems unused\n",
658                        clk->name);
659                 return;
660         }
661
662         printk(KERN_INFO "Disabling unused clock \"%s\"... ", clk->name);
663         clk->disable(clk);
664         printk(" done\n");
665 }
666
667 #else
668 #define omap1_clk_disable_unused        NULL
669 #endif
670
671 static struct clk_functions omap1_clk_functions = {
672         .clk_enable             = omap1_clk_enable,
673         .clk_disable            = omap1_clk_disable,
674         .clk_round_rate         = omap1_clk_round_rate,
675         .clk_set_rate           = omap1_clk_set_rate,
676         .clk_disable_unused     = omap1_clk_disable_unused,
677 };
678
679 int __init omap1_clk_init(void)
680 {
681         struct clk ** clkp;
682         const struct omap_clock_config *info;
683         int crystal_type = 0; /* Default 12 MHz */
684         u32 reg;
685
686 #ifdef CONFIG_DEBUG_LL
687         /* Resets some clocks that may be left on from bootloader,
688          * but leaves serial clocks on.
689          */
690         omap_writel(0x3 << 29, MOD_CONF_CTRL_0);
691 #endif
692
693         /* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */
694         reg = omap_readw(SOFT_REQ_REG) & (1 << 4);
695         omap_writew(reg, SOFT_REQ_REG);
696         if (!cpu_is_omap15xx())
697                 omap_writew(0, SOFT_REQ_REG2);
698
699         clk_init(&omap1_clk_functions);
700
701         /* By default all idlect1 clocks are allowed to idle */
702         arm_idlect1_mask = ~0;
703
704         for (clkp = onchip_clks; clkp < onchip_clks+ARRAY_SIZE(onchip_clks); clkp++) {
705                 if (((*clkp)->flags &CLOCK_IN_OMAP1510) && cpu_is_omap1510()) {
706                         clk_register(*clkp);
707                         continue;
708                 }
709
710                 if (((*clkp)->flags &CLOCK_IN_OMAP16XX) && cpu_is_omap16xx()) {
711                         clk_register(*clkp);
712                         continue;
713                 }
714
715                 if (((*clkp)->flags &CLOCK_IN_OMAP730) && cpu_is_omap730()) {
716                         clk_register(*clkp);
717                         continue;
718                 }
719
720                 if (((*clkp)->flags &CLOCK_IN_OMAP310) && cpu_is_omap310()) {
721                         clk_register(*clkp);
722                         continue;
723                 }
724         }
725
726         info = omap_get_config(OMAP_TAG_CLOCK, struct omap_clock_config);
727         if (info != NULL) {
728                 if (!cpu_is_omap15xx())
729                         crystal_type = info->system_clock_type;
730         }
731
732 #if defined(CONFIG_ARCH_OMAP730)
733         ck_ref.rate = 13000000;
734 #elif defined(CONFIG_ARCH_OMAP16XX)
735         if (crystal_type == 2)
736                 ck_ref.rate = 19200000;
737 #endif
738
739         printk("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: 0x%04x\n",
740                omap_readw(ARM_SYSST), omap_readw(DPLL_CTL),
741                omap_readw(ARM_CKCTL));
742
743         /* We want to be in syncronous scalable mode */
744         omap_writew(0x1000, ARM_SYSST);
745
746 #ifdef CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER
747         /* Use values set by bootloader. Determine PLL rate and recalculate
748          * dependent clocks as if kernel had changed PLL or divisors.
749          */
750         {
751                 unsigned pll_ctl_val = omap_readw(DPLL_CTL);
752
753                 ck_dpll1.rate = ck_ref.rate; /* Base xtal rate */
754                 if (pll_ctl_val & 0x10) {
755                         /* PLL enabled, apply multiplier and divisor */
756                         if (pll_ctl_val & 0xf80)
757                                 ck_dpll1.rate *= (pll_ctl_val & 0xf80) >> 7;
758                         ck_dpll1.rate /= ((pll_ctl_val & 0x60) >> 5) + 1;
759                 } else {
760                         /* PLL disabled, apply bypass divisor */
761                         switch (pll_ctl_val & 0xc) {
762                         case 0:
763                                 break;
764                         case 0x4:
765                                 ck_dpll1.rate /= 2;
766                                 break;
767                         default:
768                                 ck_dpll1.rate /= 4;
769                                 break;
770                         }
771                 }
772         }
773         propagate_rate(&ck_dpll1);
774 #else
775         /* Find the highest supported frequency and enable it */
776         if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) {
777                 printk(KERN_ERR "System frequencies not set. Check your config.\n");
778                 /* Guess sane values (60MHz) */
779                 omap_writew(0x2290, DPLL_CTL);
780                 omap_writew(cpu_is_omap730() ? 0x3005 : 0x1005, ARM_CKCTL);
781                 ck_dpll1.rate = 60000000;
782                 propagate_rate(&ck_dpll1);
783         }
784 #endif
785         /* Cache rates for clocks connected to ck_ref (not dpll1) */
786         propagate_rate(&ck_ref);
787         printk(KERN_INFO "Clocking rate (xtal/DPLL1/MPU): "
788                 "%ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n",
789                ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10,
790                ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10,
791                arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);
792
793 #if defined(CONFIG_MACH_OMAP_PERSEUS2) || defined(CONFIG_MACH_OMAP_FSAMPLE)
794         /* Select slicer output as OMAP input clock */
795         omap_writew(omap_readw(OMAP730_PCC_UPLD_CTRL) & ~0x1, OMAP730_PCC_UPLD_CTRL);
796 #endif
797
798         /* Amstrad Delta wants BCLK high when inactive */
799         if (machine_is_ams_delta())
800                 omap_writel(omap_readl(ULPD_CLOCK_CTRL) |
801                                 (1 << SDW_MCLK_INV_BIT),
802                                 ULPD_CLOCK_CTRL);
803
804         /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */
805         /* (on 730, bit 13 must not be cleared) */
806         if (cpu_is_omap730())
807                 omap_writew(omap_readw(ARM_CKCTL) & 0x2fff, ARM_CKCTL);
808         else
809                 omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL);
810
811         /* Put DSP/MPUI into reset until needed */
812         omap_writew(0, ARM_RSTCT1);
813         omap_writew(1, ARM_RSTCT2);
814         omap_writew(0x400, ARM_IDLECT1);
815
816         /*
817          * According to OMAP5910 Erratum SYS_DMA_1, bit DMACK_REQ (bit 8)
818          * of the ARM_IDLECT2 register must be set to zero. The power-on
819          * default value of this bit is one.
820          */
821         omap_writew(0x0000, ARM_IDLECT2);       /* Turn LCD clock off also */
822
823         /*
824          * Only enable those clocks we will need, let the drivers
825          * enable other clocks as necessary
826          */
827         clk_enable(&armper_ck.clk);
828         clk_enable(&armxor_ck.clk);
829         clk_enable(&armtim_ck.clk); /* This should be done by timer code */
830
831         if (cpu_is_omap15xx())
832                 clk_enable(&arm_gpio_ck);
833
834         return 0;
835 }
836