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   1 /*
   2  *  arch/m68k/q40/config.c
   3  *
   4  *  Copyright (C) 1999 Richard Zidlicky
   5  *
   6  * originally based on:
   7  *
   8  *  linux/bvme/config.c
   9  *
  10  * This file is subject to the terms and conditions of the GNU General Public
  11  * License.  See the file README.legal in the main directory of this archive
  12  * for more details.
  13  */
  14
  15 #include <linux/types.h>
  16 #include <linux/kernel.h>
  17 #include <linux/mm.h>
  18 #include <linux/tty.h>
  19 #include <linux/console.h>
  20 #include <linux/linkage.h>
  21 #include <linux/init.h>
  22 #include <linux/major.h>
  23 #include <linux/serial_reg.h>
  24 #include <linux/rtc.h>
  25 #include <linux/vt_kern.h>
  26
  27 #include <asm/io.h>
  28 #include <asm/rtc.h>
  29 #include <asm/bootinfo.h>
  30 #include <asm/system.h>
  31 #include <asm/pgtable.h>
  32 #include <asm/setup.h>
  33 #include <asm/irq.h>
  34 #include <asm/traps.h>
  35 #include <asm/machdep.h>
  36 #include <asm/q40_master.h>
  37
  38 extern irqreturn_t q40_process_int(int level, struct pt_regs *regs);
  39 extern void q40_init_IRQ(void);
  40 static void q40_get_model(char *model);
  41 static int  q40_get_hardware_list(char *buffer);
  42 extern void q40_sched_init(irq_handler_t handler);
  43
  44 extern unsigned long q40_gettimeoffset(void);
  45 extern int q40_hwclk(int, struct rtc_time *);
  46 extern unsigned int q40_get_ss(void);
  47 extern int q40_set_clock_mmss(unsigned long);
  48 static int q40_get_rtc_pll(struct rtc_pll_info *pll);
  49 static int q40_set_rtc_pll(struct rtc_pll_info *pll);
  50 extern void q40_reset(void);
  51 void q40_halt(void);
  52 extern void q40_waitbut(void);
  53 void q40_set_vectors(void);
  54
  55 extern void q40_mksound(unsigned int /*freq*/, unsigned int /*ticks*/);
  56
  57 static void q40_mem_console_write(struct console *co, const char *b,
  58                                   unsigned int count);
  59
  60 extern int ql_ticks;
  61
  62 static struct console q40_console_driver = {
  63         .name   = "debug",
  64         .write  = q40_mem_console_write,
  65         .flags  = CON_PRINTBUFFER,
  66         .index  = -1,
  67 };
  68
  69
  70 /* early debugging function:*/
  71 extern char *q40_mem_cptr; /*=(char *)0xff020000;*/
  72 static int _cpleft;
  73
  74 static void q40_mem_console_write(struct console *co, const char *s,
  75                                   unsigned int count)
  76 {
  77         const char *p = s;
  78
  79         if (count < _cpleft) {
  80                 while (count-- > 0) {
  81                         *q40_mem_cptr = *p++;
  82                         q40_mem_cptr += 4;
  83                         _cpleft--;
  84                 }
  85         }
  86 }
  87
  88 static int __init q40_debug_setup(char *arg)
  89 {
  90         /* useful for early debugging stages - writes kernel messages into SRAM */
  91         if (MACH_IS_Q40 && !strncmp(arg, "mem", 3)) {
  92                 /*printk("using NVRAM debug, q40_mem_cptr=%p\n",q40_mem_cptr);*/
  93                 _cpleft = 2000 - ((long)q40_mem_cptr-0xff020000) / 4;
  94                 register_console(&q40_console_driver);
  95         }
  96         return 0;
  97 }
  98
  99 early_param("debug", q40_debug_setup);
 100
 101 #if 0
 102 void printq40(char *str)
 103 {
 104         int l = strlen(str);
 105         char *p = q40_mem_cptr;
 106
 107         while (l-- > 0 && _cpleft-- > 0) {
 108                 *p = *str++;
 109                 p += 4;
 110         }
 111         q40_mem_cptr = p;
 112 }
 113 #endif
 114
 115 static int halted;
 116
 117 #ifdef CONFIG_HEARTBEAT
 118 static void q40_heartbeat(int on)
 119 {
 120         if (halted)
 121                 return;
 122
 123         if (on)
 124                 Q40_LED_ON();
 125         else
 126                 Q40_LED_OFF();
 127 }
 128 #endif
 129
 130 void q40_reset(void)
 131 {
 132         halted = 1;
 133         printk("\n\n*******************************************\n"
 134                 "Called q40_reset : press the RESET button!! \n"
 135                 "*******************************************\n");
 136         Q40_LED_ON();
 137         while (1)
 138                 ;
 139 }
 140 void q40_halt(void)
 141 {
 142         halted = 1;
 143         printk("\n\n*******************\n"
 144                    "  Called q40_halt\n"
 145                    "*******************\n");
 146         Q40_LED_ON();
 147         while (1)
 148                 ;
 149 }
 150
 151 static void q40_get_model(char *model)
 152 {
 153         sprintf(model, "Q40");
 154 }
 155
 156 /* No hardware options on Q40? */
 157
 158 static int q40_get_hardware_list(char *buffer)
 159 {
 160         *buffer = '\0';
 161         return 0;
 162 }
 163
 164 static unsigned int serports[] =
 165 {
 166         0x3f8,0x2f8,0x3e8,0x2e8,0
 167 };
 168 void q40_disable_irqs(void)
 169 {
 170         unsigned i, j;
 171
 172         j = 0;
 173         while ((i = serports[j++]))
 174                 outb(0, i + UART_IER);
 175         master_outb(0, EXT_ENABLE_REG);
 176         master_outb(0, KEY_IRQ_ENABLE_REG);
 177 }
 178
 179 void __init config_q40(void)
 180 {
 181         mach_sched_init = q40_sched_init;
 182
 183         mach_init_IRQ = q40_init_IRQ;
 184         mach_gettimeoffset = q40_gettimeoffset;
 185         mach_hwclk = q40_hwclk;
 186         mach_get_ss = q40_get_ss;
 187         mach_get_rtc_pll = q40_get_rtc_pll;
 188         mach_set_rtc_pll = q40_set_rtc_pll;
 189         mach_set_clock_mmss = q40_set_clock_mmss;
 190
 191         mach_reset = q40_reset;
 192         mach_get_model = q40_get_model;
 193         mach_get_hardware_list = q40_get_hardware_list;
 194
 195 #if defined(CONFIG_INPUT_M68K_BEEP) || defined(CONFIG_INPUT_M68K_BEEP_MODULE)
 196         mach_beep = q40_mksound;
 197 #endif
 198 #ifdef CONFIG_HEARTBEAT
 199         mach_heartbeat = q40_heartbeat;
 200 #endif
 201         mach_halt = q40_halt;
 202
 203         /* disable a few things that SMSQ might have left enabled */
 204         q40_disable_irqs();
 205
 206         /* no DMA at all, but ide-scsi requires it.. make sure
 207          * all physical RAM fits into the boundary - otherwise
 208          * allocator may play costly and useless tricks */
 209         mach_max_dma_address = 1024*1024*1024;
 210 }
 211
 212
 213 int q40_parse_bootinfo(const struct bi_record *rec)
 214 {
 215         return 1;
 216 }
 217
 218
 219 static inline unsigned char bcd2bin(unsigned char b)
 220 {
 221         return (b >> 4) * 10 + (b & 15);
 222 }
 223
 224 static inline unsigned char bin2bcd(unsigned char b)
 225 {
 226         return (b / 10) * 16 + (b % 10);
 227 }
 228
 229
 230 unsigned long q40_gettimeoffset(void)
 231 {
 232         return 5000 * (ql_ticks != 0);
 233 }
 234
 235
 236 /*
 237  * Looks like op is non-zero for setting the clock, and zero for
 238  * reading the clock.
 239  *
 240  *  struct hwclk_time {
 241  *         unsigned        sec;       0..59
 242  *         unsigned        min;       0..59
 243  *         unsigned        hour;      0..23
 244  *         unsigned        day;       1..31
 245  *         unsigned        mon;       0..11
 246  *         unsigned        year;      00...
 247  *         int             wday;      0..6, 0 is Sunday, -1 means unknown/don't set
 248  * };
 249  */
 250
 251 int q40_hwclk(int op, struct rtc_time *t)
 252 {
 253         if (op) {
 254                 /* Write.... */
 255                 Q40_RTC_CTRL |= Q40_RTC_WRITE;
 256
 257                 Q40_RTC_SECS = bin2bcd(t->tm_sec);
 258                 Q40_RTC_MINS = bin2bcd(t->tm_min);
 259                 Q40_RTC_HOUR = bin2bcd(t->tm_hour);
 260                 Q40_RTC_DATE = bin2bcd(t->tm_mday);
 261                 Q40_RTC_MNTH = bin2bcd(t->tm_mon + 1);
 262                 Q40_RTC_YEAR = bin2bcd(t->tm_year%100);
 263                 if (t->tm_wday >= 0)
 264                         Q40_RTC_DOW = bin2bcd(t->tm_wday+1);
 265
 266                 Q40_RTC_CTRL &= ~(Q40_RTC_WRITE);
 267         } else {
 268                 /* Read....  */
 269                 Q40_RTC_CTRL |= Q40_RTC_READ;
 270
 271                 t->tm_year = bcd2bin (Q40_RTC_YEAR);
 272                 t->tm_mon  = bcd2bin (Q40_RTC_MNTH)-1;
 273                 t->tm_mday = bcd2bin (Q40_RTC_DATE);
 274                 t->tm_hour = bcd2bin (Q40_RTC_HOUR);
 275                 t->tm_min  = bcd2bin (Q40_RTC_MINS);
 276                 t->tm_sec  = bcd2bin (Q40_RTC_SECS);
 277
 278                 Q40_RTC_CTRL &= ~(Q40_RTC_READ);
 279
 280                 if (t->tm_year < 70)
 281                         t->tm_year += 100;
 282                 t->tm_wday = bcd2bin(Q40_RTC_DOW)-1;
 283         }
 284
 285         return 0;
 286 }
 287
 288 unsigned int q40_get_ss(void)
 289 {
 290         return bcd2bin(Q40_RTC_SECS);
 291 }
 292
 293 /*
 294  * Set the minutes and seconds from seconds value 'nowtime'.  Fail if
 295  * clock is out by > 30 minutes.  Logic lifted from atari code.
 296  */
 297
 298 int q40_set_clock_mmss(unsigned long nowtime)
 299 {
 300         int retval = 0;
 301         short real_seconds = nowtime % 60, real_minutes = (nowtime / 60) % 60;
 302
 303         int rtc_minutes;
 304
 305         rtc_minutes = bcd2bin(Q40_RTC_MINS);
 306
 307         if ((rtc_minutes < real_minutes ?
 308              real_minutes - rtc_minutes :
 309              rtc_minutes - real_minutes) < 30) {
 310                 Q40_RTC_CTRL |= Q40_RTC_WRITE;
 311                 Q40_RTC_MINS = bin2bcd(real_minutes);
 312                 Q40_RTC_SECS = bin2bcd(real_seconds);
 313                 Q40_RTC_CTRL &= ~(Q40_RTC_WRITE);
 314         } else
 315                 retval = -1;
 316
 317         return retval;
 318 }
 319
 320
 321 /* get and set PLL calibration of RTC clock */
 322 #define Q40_RTC_PLL_MASK ((1<<5)-1)
 323 #define Q40_RTC_PLL_SIGN (1<<5)
 324
 325 static int q40_get_rtc_pll(struct rtc_pll_info *pll)
 326 {
 327         int tmp = Q40_RTC_CTRL;
 328
 329         pll->pll_value = tmp & Q40_RTC_PLL_MASK;
 330         if (tmp & Q40_RTC_PLL_SIGN)
 331                 pll->pll_value = -pll->pll_value;
 332         pll->pll_max = 31;
 333         pll->pll_min = -31;
 334         pll->pll_posmult = 512;
 335         pll->pll_negmult = 256;
 336         pll->pll_clock = 125829120;
 337
 338         return 0;
 339 }
 340
 341 static int q40_set_rtc_pll(struct rtc_pll_info *pll)
 342 {
 343         if (!pll->pll_ctrl) {
 344                 /* the docs are a bit unclear so I am doublesetting */
 345                 /* RTC_WRITE here ... */
 346                 int tmp = (pll->pll_value & 31) | (pll->pll_value<0 ? 32 : 0) |
 347                           Q40_RTC_WRITE;
 348                 Q40_RTC_CTRL |= Q40_RTC_WRITE;
 349                 Q40_RTC_CTRL = tmp;
 350                 Q40_RTC_CTRL &= ~(Q40_RTC_WRITE);
 351                 return 0;
 352         } else
 353                 return -EINVAL;
 354 }