1 /* Linker script for the FPGA implementation of the V850E2 NA85E2C cpu core
2 (CONFIG_V850E2_FPGA85E2C). */
6 RESET : ORIGIN = 0, LENGTH = 0x10
7 /* Interrupt vectors. */
8 INTV : ORIGIN = 0x10, LENGTH = 0x470
9 /* The `window' in RAM were we're allowed to load stuff. */
10 RAM_LOW : ORIGIN = 0x480, LENGTH = 0x0005FB80
11 /* Some more ram above the window were we can put bss &c. */
12 RAM_HIGH : ORIGIN = 0x00060000, LENGTH = 0x000A0000
13 /* This is the area visible from the outside world (we can use
14 this only for uninitialized data). */
15 VISIBLE : ORIGIN = 0x00200000, LENGTH = 0x00060000
22 *(.intv.reset) /* Reset vector */
26 __r0_ram = . ; /* Must be near address 0. */
32 RAMK_INIT_CONTENTS_NO_END
36 /* Where the interrupt vectors are initially loaded. */
37 __intv_load_start = . ;
40 *(.intv.common) /* Vectors common to all v850e proc. */
41 *(.intv.mach) /* Machine-specific int. vectors. */
46 /* This is here so that when we free init memory the
47 load-time copy of the interrupt vectors and any empty
48 space at the end of the `RAM_LOW' area is freed too. */
60 _memcons_output_end = . ;