2 * arch/powerpc/platforms/83xx/mpc832x_rdb.c
4 * Copyright (C) Freescale Semiconductor, Inc. 2007. All rights reserved.
7 * MPC832x RDB board specific routines.
8 * This file is based on mpc832x_mds.c and mpc8313_rdb.c
9 * Author: Michael Barkowski <michael.barkowski@freescale.com>
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
17 #include <linux/pci.h>
18 #include <linux/spi/spi.h>
20 #include <asm/of_platform.h>
25 #include <asm/qe_ic.h>
26 #include <sysdev/fsl_soc.h>
32 #define DBG(fmt...) udbg_printf(fmt)
37 static void mpc83xx_spi_activate_cs(u8 cs, u8 polarity)
39 pr_debug("%s %d %d\n", __func__, cs, polarity);
40 par_io_data_set(3, 13, polarity);
43 static void mpc83xx_spi_deactivate_cs(u8 cs, u8 polarity)
45 pr_debug("%s %d %d\n", __func__, cs, polarity);
46 par_io_data_set(3, 13, !polarity);
49 static struct spi_board_info mpc832x_spi_boardinfo = {
52 .max_speed_hz = 50000000,
54 * XXX: This is spidev (spi in userspace) stub, should
55 * be replaced by "mmc_spi" when mmc_spi will hit mainline.
60 static int __init mpc832x_spi_init(void)
62 if (!machine_is(mpc832x_rdb))
65 par_io_config_pin(3, 0, 3, 0, 1, 0); /* SPI1 MOSI, I/O */
66 par_io_config_pin(3, 1, 3, 0, 1, 0); /* SPI1 MISO, I/O */
67 par_io_config_pin(3, 2, 3, 0, 1, 0); /* SPI1 CLK, I/O */
68 par_io_config_pin(3, 3, 2, 0, 1, 0); /* SPI1 SEL, I */
70 par_io_config_pin(3, 13, 1, 0, 0, 0); /* !SD_CS, O */
71 par_io_config_pin(3, 14, 2, 0, 0, 0); /* SD_INSERT, I */
72 par_io_config_pin(3, 15, 2, 0, 0, 0); /* SD_PROTECT,I */
74 return fsl_spi_init(&mpc832x_spi_boardinfo, 1,
75 mpc83xx_spi_activate_cs,
76 mpc83xx_spi_deactivate_cs);
79 device_initcall(mpc832x_spi_init);
81 /* ************************************************************************
83 * Setup the architecture
86 static void __init mpc832x_rdb_setup_arch(void)
88 #if defined(CONFIG_PCI) || defined(CONFIG_QUICC_ENGINE)
89 struct device_node *np;
93 ppc_md.progress("mpc832x_rdb_setup_arch()", 0);
96 for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;)
97 mpc83xx_add_bridge(np);
100 #ifdef CONFIG_QUICC_ENGINE
103 if ((np = of_find_node_by_name(np, "par_io")) != NULL) {
107 for (np = NULL; (np = of_find_node_by_name(np, "ucc")) != NULL;)
108 par_io_of_config(np);
110 #endif /* CONFIG_QUICC_ENGINE */
113 static struct of_device_id mpc832x_ids[] = {
115 { .compatible = "soc", },
120 static int __init mpc832x_declare_of_platform_devices(void)
122 if (!machine_is(mpc832x_rdb))
125 /* Publish the QE devices */
126 of_platform_bus_probe(NULL, mpc832x_ids, NULL);
130 device_initcall(mpc832x_declare_of_platform_devices);
132 void __init mpc832x_rdb_init_IRQ(void)
135 struct device_node *np;
137 np = of_find_node_by_type(NULL, "ipic");
143 /* Initialize the default interrupt mapping priorities,
144 * in case the boot rom changed something on us.
146 ipic_set_default_priority();
149 #ifdef CONFIG_QUICC_ENGINE
150 np = of_find_node_by_type(NULL, "qeic");
156 #endif /* CONFIG_QUICC_ENGINE */
160 * Called very early, MMU is off, device-tree isn't unflattened
162 static int __init mpc832x_rdb_probe(void)
164 unsigned long root = of_get_flat_dt_root();
166 return of_flat_dt_is_compatible(root, "MPC832xRDB");
169 define_machine(mpc832x_rdb) {
170 .name = "MPC832x RDB",
171 .probe = mpc832x_rdb_probe,
172 .setup_arch = mpc832x_rdb_setup_arch,
173 .init_IRQ = mpc832x_rdb_init_IRQ,
174 .get_irq = ipic_get_irq,
175 .restart = mpc83xx_restart,
176 .time_init = mpc83xx_time_init,
177 .calibrate_decr = generic_calibrate_decr,
178 .progress = udbg_progress,