1 #include <linux/init.h>
2 #include <linux/module.h>
3 #include <linux/cpufreq.h>
4 #include <hwregs/reg_map.h>
5 #include <asm/arch/hwregs/reg_rdwr.h>
6 #include <asm/arch/hwregs/config_defs.h>
7 #include <asm/arch/hwregs/bif_core_defs.h>
10 cris_sdram_freq_notifier(struct notifier_block *nb, unsigned long val,
13 static struct notifier_block cris_sdram_freq_notifier_block = {
14 .notifier_call = cris_sdram_freq_notifier
17 static struct cpufreq_frequency_table cris_freq_table[] = {
20 {0, CPUFREQ_TABLE_END},
23 static unsigned int cris_freq_get_cpu_frequency(unsigned int cpu)
25 reg_config_rw_clk_ctrl clk_ctrl;
26 clk_ctrl = REG_RD(config, regi_config, rw_clk_ctrl);
27 return clk_ctrl.pll ? 200000 : 6000;
30 static void cris_freq_set_cpu_state(unsigned int state)
33 struct cpufreq_freqs freqs;
34 reg_config_rw_clk_ctrl clk_ctrl;
35 clk_ctrl = REG_RD(config, regi_config, rw_clk_ctrl);
37 for_each_possible_cpu(i) {
38 freqs.old = cris_freq_get_cpu_frequency(i);
39 freqs.new = cris_freq_table[state].frequency;
43 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
47 /* Even though we may be SMP they will share the same clock
48 * so all settings are made on CPU0. */
49 if (cris_freq_table[state].frequency == 200000)
53 REG_WR(config, regi_config, rw_clk_ctrl, clk_ctrl);
57 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
60 static int cris_freq_verify(struct cpufreq_policy *policy)
62 return cpufreq_frequency_table_verify(policy, &cris_freq_table[0]);
65 static int cris_freq_target(struct cpufreq_policy *policy,
66 unsigned int target_freq, unsigned int relation)
68 unsigned int newstate = 0;
70 if (cpufreq_frequency_table_target
71 (policy, cris_freq_table, target_freq, relation, &newstate))
74 cris_freq_set_cpu_state(newstate);
79 static int cris_freq_cpu_init(struct cpufreq_policy *policy)
83 /* cpuinfo and default policy values */
84 policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
85 policy->cpuinfo.transition_latency = 1000000; /* 1ms */
86 policy->cur = cris_freq_get_cpu_frequency(0);
88 result = cpufreq_frequency_table_cpuinfo(policy, cris_freq_table);
92 cpufreq_frequency_table_get_attr(cris_freq_table, policy->cpu);
97 static int cris_freq_cpu_exit(struct cpufreq_policy *policy)
99 cpufreq_frequency_table_put_attr(policy->cpu);
103 static struct freq_attr *cris_freq_attr[] = {
104 &cpufreq_freq_attr_scaling_available_freqs,
108 static struct cpufreq_driver cris_freq_driver = {
109 .get = cris_freq_get_cpu_frequency,
110 .verify = cris_freq_verify,
111 .target = cris_freq_target,
112 .init = cris_freq_cpu_init,
113 .exit = cris_freq_cpu_exit,
115 .owner = THIS_MODULE,
116 .attr = cris_freq_attr,
119 static int __init cris_freq_init(void)
122 ret = cpufreq_register_driver(&cris_freq_driver);
123 cpufreq_register_notifier(&cris_sdram_freq_notifier_block,
124 CPUFREQ_TRANSITION_NOTIFIER);
129 cris_sdram_freq_notifier(struct notifier_block *nb, unsigned long val,
133 struct cpufreq_freqs *freqs = data;
134 if (val == CPUFREQ_PRECHANGE) {
135 reg_bif_core_rw_sdram_timing timing =
136 REG_RD(bif_core, regi_bif_core, rw_sdram_timing);
137 timing.cpd = (freqs->new == 200000 ? 0 : 1);
139 if (freqs->new == 200000)
140 for (i = 0; i < 50000; i++) ;
141 REG_WR(bif_core, regi_bif_core, rw_sdram_timing, timing);
146 module_init(cris_freq_init);