git.oblomov.eu Git - linux-2.6/blob - arch/powerpc/platforms/86xx/mpc86xx_hpcn.c

   1 /*
   2  * MPC86xx HPCN board specific routines
   3  *
   4  * Recode: ZHANG WEI <wei.zhang@freescale.com>
   5  * Initial author: Xianghua Xiao <x.xiao@freescale.com>
   6  *
   7  * Copyright 2006 Freescale Semiconductor Inc.
   8  *
   9  * This program is free software; you can redistribute  it and/or modify it
  10  * under  the terms of  the GNU General  Public License as published by the
  11  * Free Software Foundation;  either version 2 of the  License, or (at your
  12  * option) any later version.
  13  */
  14
  15 #include <linux/stddef.h>
  16 #include <linux/kernel.h>
  17 #include <linux/pci.h>
  18 #include <linux/kdev_t.h>
  19 #include <linux/delay.h>
  20 #include <linux/seq_file.h>
  21 #include <linux/root_dev.h>
  22
  23 #include <asm/system.h>
  24 #include <asm/time.h>
  25 #include <asm/machdep.h>
  26 #include <asm/pci-bridge.h>
  27 #include <asm/mpc86xx.h>
  28 #include <asm/prom.h>
  29 #include <mm/mmu_decl.h>
  30 #include <asm/udbg.h>
  31 #include <asm/i8259.h>
  32
  33 #include <asm/mpic.h>
  34
  35 #include <sysdev/fsl_soc.h>
  36
  37 #include "mpc86xx.h"
  38 #include "mpc8641_hpcn.h"
  39
  40 #ifndef CONFIG_PCI
  41 unsigned long isa_io_base = 0;
  42 unsigned long isa_mem_base = 0;
  43 unsigned long pci_dram_offset = 0;
  44 #endif
  45
  46
  47 /*
  48  * Internal interrupts are all Level Sensitive, and Positive Polarity
  49  */
  50
  51 static u_char mpc86xx_hpcn_openpic_initsenses[] __initdata = {
  52         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  0: Reserved */
  53         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  1: MCM */
  54         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  2: DDR DRAM */
  55         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  3: LBIU */
  56         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  4: DMA 0 */
  57         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  5: DMA 1 */
  58         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  6: DMA 2 */
  59         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  7: DMA 3 */
  60         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  8: PCIE1 */
  61         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  9: PCIE2 */
  62         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 10: Reserved */
  63         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 11: Reserved */
  64         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 12: DUART2 */
  65         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 13: TSEC 1 Transmit */
  66         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 14: TSEC 1 Receive */
  67         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 15: TSEC 3 transmit */
  68         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 16: TSEC 3 receive */
  69         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 17: TSEC 3 error */
  70         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 18: TSEC 1 Receive/Transmit Error */
  71         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 19: TSEC 2 Transmit */
  72         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 20: TSEC 2 Receive */
  73         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 21: TSEC 4 transmit */
  74         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 22: TSEC 4 receive */
  75         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 23: TSEC 4 error */
  76         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 24: TSEC 2 Receive/Transmit Error */
  77         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 25: Unused */
  78         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 26: DUART1 */
  79         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 27: I2C */
  80         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 28: Performance Monitor */
  81         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 29: Unused */
  82         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 30: Unused */
  83         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 31: Unused */
  84         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 32: SRIO error/write-port unit */
  85         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 33: SRIO outbound doorbell */
  86         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 34: SRIO inbound doorbell */
  87         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 35: Unused */
  88         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 36: Unused */
  89         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 37: SRIO outbound message unit 1 */
  90         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 38: SRIO inbound message unit 1 */
  91         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 39: SRIO outbound message unit 2 */
  92         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 40: SRIO inbound message unit 2 */
  93         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 41: Unused */
  94         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 42: Unused */
  95         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 43: Unused */
  96         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 44: Unused */
  97         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 45: Unused */
  98         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 46: Unused */
  99         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 47: Unused */
 100         0x0,                                            /* External  0: */
 101         0x0,                                            /* External  1: */
 102         0x0,                                            /* External  2: */
 103         0x0,                                            /* External  3: */
 104         0x0,                                            /* External  4: */
 105         0x0,                                            /* External  5: */
 106         0x0,                                            /* External  6: */
 107         0x0,                                            /* External  7: */
 108         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* External  8: Pixis FPGA */
 109         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* External  9: ULI 8259 INTR Cascade */
 110         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* External 10: Quad ETH PHY */
 111         0x0,                                            /* External 11: */
 112         0x0,
 113         0x0,
 114         0x0,
 115         0x0,
 116 };
 117
 118
 119 void __init
 120 mpc86xx_hpcn_init_irq(void)
 121 {
 122         struct mpic *mpic1;
 123         phys_addr_t openpic_paddr;
 124
 125         /* Determine the Physical Address of the OpenPIC regs */
 126         openpic_paddr = get_immrbase() + MPC86xx_OPENPIC_OFFSET;
 127
 128         /* Alloc mpic structure and per isu has 16 INT entries. */
 129         mpic1 = mpic_alloc(openpic_paddr,
 130                         MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
 131                         16, MPC86xx_OPENPIC_IRQ_OFFSET, 0, 250,
 132                         mpc86xx_hpcn_openpic_initsenses,
 133                         sizeof(mpc86xx_hpcn_openpic_initsenses),
 134                         " MPIC     ");
 135         BUG_ON(mpic1 == NULL);
 136
 137         /* 48 Internal Interrupts */
 138         mpic_assign_isu(mpic1, 0, openpic_paddr + 0x10200);
 139         mpic_assign_isu(mpic1, 1, openpic_paddr + 0x10400);
 140         mpic_assign_isu(mpic1, 2, openpic_paddr + 0x10600);
 141
 142         /* 16 External interrupts */
 143         mpic_assign_isu(mpic1, 3, openpic_paddr + 0x10000);
 144
 145         mpic_init(mpic1);
 146
 147 #ifdef CONFIG_PCI
 148         mpic_setup_cascade(MPC86xx_IRQ_EXT9, i8259_irq_cascade, NULL);
 149         i8259_init(0, I8259_OFFSET);
 150 #endif
 151 }
 152
 153
 154
 155 #ifdef CONFIG_PCI
 156 /*
 157  * interrupt routing
 158  */
 159
 160 int
 161 mpc86xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
 162 {
 163         static char pci_irq_table[][4] = {
 164                 /*
 165                  *      PCI IDSEL/INTPIN->INTLINE
 166                  *       A      B      C      D
 167                  */
 168                 {PIRQA, PIRQB, PIRQC, PIRQD},   /* IDSEL 17 -- PCI Slot 1 */
 169                 {PIRQB, PIRQC, PIRQD, PIRQA},   /* IDSEL 18 -- PCI Slot 2 */
 170                 {0, 0, 0, 0},                   /* IDSEL 19 */
 171                 {0, 0, 0, 0},                   /* IDSEL 20 */
 172                 {0, 0, 0, 0},                   /* IDSEL 21 */
 173                 {0, 0, 0, 0},                   /* IDSEL 22 */
 174                 {0, 0, 0, 0},                   /* IDSEL 23 */
 175                 {0, 0, 0, 0},                   /* IDSEL 24 */
 176                 {0, 0, 0, 0},                   /* IDSEL 25 */
 177                 {PIRQD, PIRQA, PIRQB, PIRQC},   /* IDSEL 26 -- PCI Bridge*/
 178                 {PIRQC, 0, 0, 0},               /* IDSEL 27 -- LAN */
 179                 {PIRQE, PIRQF, PIRQH, PIRQ7},   /* IDSEL 28 -- USB 1.1 */
 180                 {PIRQE, PIRQF, PIRQG, 0},       /* IDSEL 29 -- Audio & Modem */
 181                 {PIRQH, 0, 0, 0},               /* IDSEL 30 -- LPC & PMU*/
 182                 {PIRQD, 0, 0, 0},               /* IDSEL 31 -- ATA */
 183         };
 184
 185         const long min_idsel = 17, max_idsel = 31, irqs_per_slot = 4;
 186         return PCI_IRQ_TABLE_LOOKUP + I8259_OFFSET;
 187 }
 188
 189 static void __devinit quirk_ali1575(struct pci_dev *dev)
 190 {
 191         unsigned short temp;
 192
 193         /*
 194          * ALI1575 interrupts route table setup:
 195          *
 196          * IRQ pin   IRQ#
 197          * PIRQA ---- 3
 198          * PIRQB ---- 4
 199          * PIRQC ---- 5
 200          * PIRQD ---- 6
 201          * PIRQE ---- 9
 202          * PIRQF ---- 10
 203          * PIRQG ---- 11
 204          * PIRQH ---- 12
 205          *
 206          * interrupts for PCI slot0 -- PIRQA / PIRQB / PIRQC / PIRQD
 207          *                PCI slot1 -- PIRQB / PIRQC / PIRQD / PIRQA
 208          */
 209         pci_write_config_dword(dev, 0x48, 0xb9317542);
 210
 211         /* USB 1.1 OHCI controller 1, interrupt: PIRQE */
 212         pci_write_config_byte(dev, 0x86, 0x0c);
 213
 214         /* USB 1.1 OHCI controller 2, interrupt: PIRQF */
 215         pci_write_config_byte(dev, 0x87, 0x0d);
 216
 217         /* USB 1.1 OHCI controller 3, interrupt: PIRQH */
 218         pci_write_config_byte(dev, 0x88, 0x0f);
 219
 220         /* USB 2.0 controller, interrupt: PIRQ7 */
 221         pci_write_config_byte(dev, 0x74, 0x06);
 222
 223         /* Audio controller, interrupt: PIRQE */
 224         pci_write_config_byte(dev, 0x8a, 0x0c);
 225
 226         /* Modem controller, interrupt: PIRQF */
 227         pci_write_config_byte(dev, 0x8b, 0x0d);
 228
 229         /* HD audio controller, interrupt: PIRQG */
 230         pci_write_config_byte(dev, 0x8c, 0x0e);
 231
 232         /* Serial ATA interrupt: PIRQD */
 233         pci_write_config_byte(dev, 0x8d, 0x0b);
 234
 235         /* SMB interrupt: PIRQH */
 236         pci_write_config_byte(dev, 0x8e, 0x0f);
 237
 238         /* PMU ACPI SCI interrupt: PIRQH */
 239         pci_write_config_byte(dev, 0x8f, 0x0f);
 240
 241         /* Primary PATA IDE IRQ: 14
 242          * Secondary PATA IDE IRQ: 15
 243          */
 244         pci_write_config_byte(dev, 0x44, 0x3d);
 245         pci_write_config_byte(dev, 0x75, 0x0f);
 246
 247         /* Set IRQ14 and IRQ15 to legacy IRQs */
 248         pci_read_config_word(dev, 0x46, &temp);
 249         temp |= 0xc000;
 250         pci_write_config_word(dev, 0x46, temp);
 251
 252         /* Set i8259 interrupt trigger
 253          * IRQ 3:  Level
 254          * IRQ 4:  Level
 255          * IRQ 5:  Level
 256          * IRQ 6:  Level
 257          * IRQ 7:  Level
 258          * IRQ 9:  Level
 259          * IRQ 10: Level
 260          * IRQ 11: Level
 261          * IRQ 12: Level
 262          * IRQ 14: Edge
 263          * IRQ 15: Edge
 264          */
 265         outb(0xfa, 0x4d0);
 266         outb(0x1e, 0x4d1);
 267 }
 268
 269 static void __devinit quirk_uli5288(struct pci_dev *dev)
 270 {
 271         unsigned char c;
 272
 273         pci_read_config_byte(dev,0x83,&c);
 274         c |= 0x80;
 275         pci_write_config_byte(dev, 0x83, c);
 276
 277         pci_write_config_byte(dev, 0x09, 0x01);
 278         pci_write_config_byte(dev, 0x0a, 0x06);
 279
 280         pci_read_config_byte(dev,0x83,&c);
 281         c &= 0x7f;
 282         pci_write_config_byte(dev, 0x83, c);
 283
 284         pci_read_config_byte(dev,0x84,&c);
 285         c |= 0x01;
 286         pci_write_config_byte(dev, 0x84, c);
 287 }
 288
 289 static void __devinit quirk_uli5229(struct pci_dev *dev)
 290 {
 291         unsigned short temp;
 292         pci_write_config_word(dev, 0x04, 0x0405);
 293         pci_read_config_word(dev, 0x4a, &temp);
 294         temp |= 0x1000;
 295         pci_write_config_word(dev, 0x4a, temp);
 296 }
 297
 298 static void __devinit early_uli5249(struct pci_dev *dev)
 299 {
 300         unsigned char temp;
 301         pci_write_config_word(dev, 0x04, 0x0007);
 302         pci_read_config_byte(dev, 0x7c, &temp);
 303         pci_write_config_byte(dev, 0x7c, 0x80);
 304         pci_write_config_byte(dev, 0x09, 0x01);
 305         pci_write_config_byte(dev, 0x7c, temp);
 306         dev->class |= 0x1;
 307 }
 308
 309 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x1575, quirk_ali1575);
 310 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5288, quirk_uli5288);
 311 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5229, quirk_uli5229);
 312 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AL, 0x5249, early_uli5249);
 313 #endif /* CONFIG_PCI */
 314
 315
 316 static void __init
 317 mpc86xx_hpcn_setup_arch(void)
 318 {
 319         struct device_node *np;
 320
 321         if (ppc_md.progress)
 322                 ppc_md.progress("mpc86xx_hpcn_setup_arch()", 0);
 323
 324         np = of_find_node_by_type(NULL, "cpu");
 325         if (np != 0) {
 326                 unsigned int *fp;
 327
 328                 fp = (int *)get_property(np, "clock-frequency", NULL);
 329                 if (fp != 0)
 330                         loops_per_jiffy = *fp / HZ;
 331                 else
 332                         loops_per_jiffy = 50000000 / HZ;
 333                 of_node_put(np);
 334         }
 335
 336 #ifdef CONFIG_PCI
 337         for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;)
 338                 add_bridge(np);
 339
 340         ppc_md.pci_swizzle = common_swizzle;
 341         ppc_md.pci_map_irq = mpc86xx_map_irq;
 342         ppc_md.pci_exclude_device = mpc86xx_exclude_device;
 343 #endif
 344
 345         printk("MPC86xx HPCN board from Freescale Semiconductor\n");
 346
 347 #ifdef  CONFIG_ROOT_NFS
 348         ROOT_DEV = Root_NFS;
 349 #else
 350         ROOT_DEV = Root_HDA1;
 351 #endif
 352
 353 #ifdef CONFIG_SMP
 354         mpc86xx_smp_init();
 355 #endif
 356 }
 357
 358
 359 void
 360 mpc86xx_hpcn_show_cpuinfo(struct seq_file *m)
 361 {
 362         struct device_node *root;
 363         uint memsize = total_memory;
 364         const char *model = "";
 365         uint svid = mfspr(SPRN_SVR);
 366
 367         seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
 368
 369         root = of_find_node_by_path("/");
 370         if (root)
 371                 model = get_property(root, "model", NULL);
 372         seq_printf(m, "Machine\t\t: %s\n", model);
 373         of_node_put(root);
 374
 375         seq_printf(m, "SVR\t\t: 0x%x\n", svid);
 376         seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
 377 }
 378
 379
 380 /*
 381  * Called very early, device-tree isn't unflattened
 382  */
 383 static int __init mpc86xx_hpcn_probe(void)
 384 {
 385         unsigned long root = of_get_flat_dt_root();
 386
 387         if (of_flat_dt_is_compatible(root, "mpc86xx"))
 388                 return 1;       /* Looks good */
 389
 390         return 0;
 391 }
 392
 393
 394 void
 395 mpc86xx_restart(char *cmd)
 396 {
 397         void __iomem *rstcr;
 398
 399         rstcr = ioremap(get_immrbase() + MPC86XX_RSTCR_OFFSET, 0x100);
 400
 401         local_irq_disable();
 402
 403         /* Assert reset request to Reset Control Register */
 404         out_be32(rstcr, 0x2);
 405
 406         /* not reached */
 407 }
 408
 409
 410 long __init
 411 mpc86xx_time_init(void)
 412 {
 413         unsigned int temp;
 414
 415         /* Set the time base to zero */
 416         mtspr(SPRN_TBWL, 0);
 417         mtspr(SPRN_TBWU, 0);
 418
 419         temp = mfspr(SPRN_HID0);
 420         temp |= HID0_TBEN;
 421         mtspr(SPRN_HID0, temp);
 422         asm volatile("isync");
 423
 424         return 0;
 425 }
 426
 427
 428 define_machine(mpc86xx_hpcn) {
 429         .name                   = "MPC86xx HPCN",
 430         .probe                  = mpc86xx_hpcn_probe,
 431         .setup_arch             = mpc86xx_hpcn_setup_arch,
 432         .init_IRQ               = mpc86xx_hpcn_init_irq,
 433         .show_cpuinfo           = mpc86xx_hpcn_show_cpuinfo,
 434         .get_irq                = mpic_get_irq,
 435         .restart                = mpc86xx_restart,
 436         .time_init              = mpc86xx_time_init,
 437         .calibrate_decr         = generic_calibrate_decr,
 438         .progress               = udbg_progress,
 439 };