git.oblomov.eu Git - linux-2.6/blob - drivers/video/nvidia/nvidia.c

   1 /*
   2  * linux/drivers/video/nvidia/nvidia.c - nVidia fb driver
   3  *
   4  * Copyright 2004 Antonino Daplas <adaplas@pol.net>
   5  *
   6  * This file is subject to the terms and conditions of the GNU General Public
   7  * License.  See the file COPYING in the main directory of this archive
   8  * for more details.
   9  *
  10  */
  11
  12 #include <linux/module.h>
  13 #include <linux/kernel.h>
  14 #include <linux/errno.h>
  15 #include <linux/string.h>
  16 #include <linux/mm.h>
  17 #include <linux/tty.h>
  18 #include <linux/slab.h>
  19 #include <linux/delay.h>
  20 #include <linux/fb.h>
  21 #include <linux/init.h>
  22 #include <linux/pci.h>
  23 #include <linux/console.h>
  24 #include <linux/backlight.h>
  25 #ifdef CONFIG_MTRR
  26 #include <asm/mtrr.h>
  27 #endif
  28 #ifdef CONFIG_PPC_OF
  29 #include <asm/prom.h>
  30 #include <asm/pci-bridge.h>
  31 #endif
  32
  33 #include "nv_local.h"
  34 #include "nv_type.h"
  35 #include "nv_proto.h"
  36 #include "nv_dma.h"
  37
  38 #ifndef CONFIG_PCI              /* sanity check */
  39 #error This driver requires PCI support.
  40 #endif
  41
  42 #undef CONFIG_FB_NVIDIA_DEBUG
  43 #ifdef CONFIG_FB_NVIDIA_DEBUG
  44 #define NVTRACE          printk
  45 #else
  46 #define NVTRACE          if (0) printk
  47 #endif
  48
  49 #define NVTRACE_ENTER(...)  NVTRACE("%s START\n", __FUNCTION__)
  50 #define NVTRACE_LEAVE(...)  NVTRACE("%s END\n", __FUNCTION__)
  51
  52 #ifdef CONFIG_FB_NVIDIA_DEBUG
  53 #define assert(expr) \
  54         if (!(expr)) { \
  55         printk( "Assertion failed! %s,%s,%s,line=%d\n",\
  56         #expr,__FILE__,__FUNCTION__,__LINE__); \
  57         BUG(); \
  58         }
  59 #else
  60 #define assert(expr)
  61 #endif
  62
  63 #define PFX "nvidiafb: "
  64
  65 /* HW cursor parameters */
  66 #define MAX_CURS                32
  67
  68 static struct pci_device_id nvidiafb_pci_tbl[] = {
  69         {PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
  70          PCI_BASE_CLASS_DISPLAY << 16, 0xff0000, 0},
  71         { 0, }
  72 };
  73 MODULE_DEVICE_TABLE(pci, nvidiafb_pci_tbl);
  74
  75 /* command line data, set in nvidiafb_setup() */
  76 static int flatpanel __devinitdata = -1;        /* Autodetect later */
  77 static int fpdither __devinitdata = -1;
  78 static int forceCRTC __devinitdata = -1;
  79 static int hwcur __devinitdata = 0;
  80 static int noaccel __devinitdata = 0;
  81 static int noscale __devinitdata = 0;
  82 static int paneltweak __devinitdata = 0;
  83 static int vram __devinitdata = 0;
  84 static int bpp __devinitdata = 8;
  85 #ifdef CONFIG_MTRR
  86 static int nomtrr __devinitdata = 0;
  87 #endif
  88
  89 static char *mode_option __devinitdata = NULL;
  90
  91 static struct fb_fix_screeninfo __devinitdata nvidiafb_fix = {
  92         .type = FB_TYPE_PACKED_PIXELS,
  93         .xpanstep = 8,
  94         .ypanstep = 1,
  95 };
  96
  97 static struct fb_var_screeninfo __devinitdata nvidiafb_default_var = {
  98         .xres = 640,
  99         .yres = 480,
 100         .xres_virtual = 640,
 101         .yres_virtual = 480,
 102         .bits_per_pixel = 8,
 103         .red = {0, 8, 0},
 104         .green = {0, 8, 0},
 105         .blue = {0, 8, 0},
 106         .transp = {0, 0, 0},
 107         .activate = FB_ACTIVATE_NOW,
 108         .height = -1,
 109         .width = -1,
 110         .pixclock = 39721,
 111         .left_margin = 40,
 112         .right_margin = 24,
 113         .upper_margin = 32,
 114         .lower_margin = 11,
 115         .hsync_len = 96,
 116         .vsync_len = 2,
 117         .vmode = FB_VMODE_NONINTERLACED
 118 };
 119
 120 static void nvidiafb_load_cursor_image(struct nvidia_par *par, u8 * data8,
 121                                        u16 bg, u16 fg, u32 w, u32 h)
 122 {
 123         u32 *data = (u32 *) data8;
 124         int i, j, k = 0;
 125         u32 b, tmp;
 126
 127         w = (w + 1) & ~1;
 128
 129         for (i = 0; i < h; i++) {
 130                 b = *data++;
 131                 reverse_order(&b);
 132
 133                 for (j = 0; j < w / 2; j++) {
 134                         tmp = 0;
 135 #if defined (__BIG_ENDIAN)
 136                         tmp = (b & (1 << 31)) ? fg << 16 : bg << 16;
 137                         b <<= 1;
 138                         tmp |= (b & (1 << 31)) ? fg : bg;
 139                         b <<= 1;
 140 #else
 141                         tmp = (b & 1) ? fg : bg;
 142                         b >>= 1;
 143                         tmp |= (b & 1) ? fg << 16 : bg << 16;
 144                         b >>= 1;
 145 #endif
 146                         NV_WR32(&par->CURSOR[k++], 0, tmp);
 147                 }
 148                 k += (MAX_CURS - w) / 2;
 149         }
 150 }
 151
 152 static void nvidia_write_clut(struct nvidia_par *par,
 153                               u8 regnum, u8 red, u8 green, u8 blue)
 154 {
 155         NVWriteDacMask(par, 0xff);
 156         NVWriteDacWriteAddr(par, regnum);
 157         NVWriteDacData(par, red);
 158         NVWriteDacData(par, green);
 159         NVWriteDacData(par, blue);
 160 }
 161
 162 static void nvidia_read_clut(struct nvidia_par *par,
 163                              u8 regnum, u8 * red, u8 * green, u8 * blue)
 164 {
 165         NVWriteDacMask(par, 0xff);
 166         NVWriteDacReadAddr(par, regnum);
 167         *red = NVReadDacData(par);
 168         *green = NVReadDacData(par);
 169         *blue = NVReadDacData(par);
 170 }
 171
 172 static int nvidia_panel_tweak(struct nvidia_par *par,
 173                               struct _riva_hw_state *state)
 174 {
 175         int tweak = 0;
 176
 177    if (par->paneltweak) {
 178            tweak = par->paneltweak;
 179    } else {
 180            /* begin flat panel hacks */
 181            /* This is unfortunate, but some chips need this register
 182               tweaked or else you get artifacts where adjacent pixels are
 183               swapped.  There are no hard rules for what to set here so all
 184               we can do is experiment and apply hacks. */
 185
 186            if(((par->Chipset & 0xffff) == 0x0328) && (state->bpp == 32)) {
 187                    /* At least one NV34 laptop needs this workaround. */
 188                    tweak = -1;
 189            }
 190
 191            if((par->Chipset & 0xfff0) == 0x0310) {
 192                    tweak = 1;
 193            }
 194            /* end flat panel hacks */
 195    }
 196
 197    return tweak;
 198 }
 199
 200 static void nvidia_vga_protect(struct nvidia_par *par, int on)
 201 {
 202         unsigned char tmp;
 203
 204         if (on) {
 205                 /*
 206                  * Turn off screen and disable sequencer.
 207                  */
 208                 tmp = NVReadSeq(par, 0x01);
 209
 210                 NVWriteSeq(par, 0x00, 0x01);            /* Synchronous Reset */
 211                 NVWriteSeq(par, 0x01, tmp | 0x20);      /* disable the display */
 212         } else {
 213                 /*
 214                  * Reenable sequencer, then turn on screen.
 215                  */
 216
 217                 tmp = NVReadSeq(par, 0x01);
 218
 219                 NVWriteSeq(par, 0x01, tmp & ~0x20);     /* reenable display */
 220                 NVWriteSeq(par, 0x00, 0x03);            /* End Reset */
 221         }
 222 }
 223
 224 static void nvidia_save_vga(struct nvidia_par *par,
 225                             struct _riva_hw_state *state)
 226 {
 227         int i;
 228
 229         NVTRACE_ENTER();
 230         NVLockUnlock(par, 0);
 231
 232         NVUnloadStateExt(par, state);
 233
 234         state->misc_output = NVReadMiscOut(par);
 235
 236         for (i = 0; i < NUM_CRT_REGS; i++)
 237                 state->crtc[i] = NVReadCrtc(par, i);
 238
 239         for (i = 0; i < NUM_ATC_REGS; i++)
 240                 state->attr[i] = NVReadAttr(par, i);
 241
 242         for (i = 0; i < NUM_GRC_REGS; i++)
 243                 state->gra[i] = NVReadGr(par, i);
 244
 245         for (i = 0; i < NUM_SEQ_REGS; i++)
 246                 state->seq[i] = NVReadSeq(par, i);
 247         NVTRACE_LEAVE();
 248 }
 249
 250 #undef DUMP_REG
 251
 252 static void nvidia_write_regs(struct nvidia_par *par,
 253                               struct _riva_hw_state *state)
 254 {
 255         int i;
 256
 257         NVTRACE_ENTER();
 258
 259         NVLoadStateExt(par, state);
 260
 261         NVWriteMiscOut(par, state->misc_output);
 262
 263         for (i = 1; i < NUM_SEQ_REGS; i++) {
 264 #ifdef DUMP_REG
 265                 printk(" SEQ[%02x] = %08x\n", i, state->seq[i]);
 266 #endif
 267                 NVWriteSeq(par, i, state->seq[i]);
 268         }
 269
 270         /* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 of CRTC[17] */
 271         NVWriteCrtc(par, 0x11, state->crtc[0x11] & ~0x80);
 272
 273         for (i = 0; i < NUM_CRT_REGS; i++) {
 274                 switch (i) {
 275                 case 0x19:
 276                 case 0x20 ... 0x40:
 277                         break;
 278                 default:
 279 #ifdef DUMP_REG
 280                         printk("CRTC[%02x] = %08x\n", i, state->crtc[i]);
 281 #endif
 282                         NVWriteCrtc(par, i, state->crtc[i]);
 283                 }
 284         }
 285
 286         for (i = 0; i < NUM_GRC_REGS; i++) {
 287 #ifdef DUMP_REG
 288                 printk(" GRA[%02x] = %08x\n", i, state->gra[i]);
 289 #endif
 290                 NVWriteGr(par, i, state->gra[i]);
 291         }
 292
 293         for (i = 0; i < NUM_ATC_REGS; i++) {
 294 #ifdef DUMP_REG
 295                 printk("ATTR[%02x] = %08x\n", i, state->attr[i]);
 296 #endif
 297                 NVWriteAttr(par, i, state->attr[i]);
 298         }
 299
 300         NVTRACE_LEAVE();
 301 }
 302
 303 static int nvidia_calc_regs(struct fb_info *info)
 304 {
 305         struct nvidia_par *par = info->par;
 306         struct _riva_hw_state *state = &par->ModeReg;
 307         int i, depth = fb_get_color_depth(&info->var, &info->fix);
 308         int h_display = info->var.xres / 8 - 1;
 309         int h_start = (info->var.xres + info->var.right_margin) / 8 - 1;
 310         int h_end = (info->var.xres + info->var.right_margin +
 311                      info->var.hsync_len) / 8 - 1;
 312         int h_total = (info->var.xres + info->var.right_margin +
 313                        info->var.hsync_len + info->var.left_margin) / 8 - 5;
 314         int h_blank_s = h_display;
 315         int h_blank_e = h_total + 4;
 316         int v_display = info->var.yres - 1;
 317         int v_start = info->var.yres + info->var.lower_margin - 1;
 318         int v_end = (info->var.yres + info->var.lower_margin +
 319                      info->var.vsync_len) - 1;
 320         int v_total = (info->var.yres + info->var.lower_margin +
 321                        info->var.vsync_len + info->var.upper_margin) - 2;
 322         int v_blank_s = v_display;
 323         int v_blank_e = v_total + 1;
 324
 325         /*
 326          * Set all CRTC values.
 327          */
 328
 329         if (info->var.vmode & FB_VMODE_INTERLACED)
 330                 v_total |= 1;
 331
 332         if (par->FlatPanel == 1) {
 333                 v_start = v_total - 3;
 334                 v_end = v_total - 2;
 335                 v_blank_s = v_start;
 336                 h_start = h_total - 5;
 337                 h_end = h_total - 2;
 338                 h_blank_e = h_total + 4;
 339         }
 340
 341         state->crtc[0x0] = Set8Bits(h_total);
 342         state->crtc[0x1] = Set8Bits(h_display);
 343         state->crtc[0x2] = Set8Bits(h_blank_s);
 344         state->crtc[0x3] = SetBitField(h_blank_e, 4: 0, 4:0)
 345                 | SetBit(7);
 346         state->crtc[0x4] = Set8Bits(h_start);
 347         state->crtc[0x5] = SetBitField(h_blank_e, 5: 5, 7:7)
 348                 | SetBitField(h_end, 4: 0, 4:0);
 349         state->crtc[0x6] = SetBitField(v_total, 7: 0, 7:0);
 350         state->crtc[0x7] = SetBitField(v_total, 8: 8, 0:0)
 351                 | SetBitField(v_display, 8: 8, 1:1)
 352                 | SetBitField(v_start, 8: 8, 2:2)
 353                 | SetBitField(v_blank_s, 8: 8, 3:3)
 354                 | SetBit(4)
 355                 | SetBitField(v_total, 9: 9, 5:5)
 356                 | SetBitField(v_display, 9: 9, 6:6)
 357                 | SetBitField(v_start, 9: 9, 7:7);
 358         state->crtc[0x9] = SetBitField(v_blank_s, 9: 9, 5:5)
 359                 | SetBit(6)
 360                 | ((info->var.vmode & FB_VMODE_DOUBLE) ? 0x80 : 0x00);
 361         state->crtc[0x10] = Set8Bits(v_start);
 362         state->crtc[0x11] = SetBitField(v_end, 3: 0, 3:0) | SetBit(5);
 363         state->crtc[0x12] = Set8Bits(v_display);
 364         state->crtc[0x13] = ((info->var.xres_virtual / 8) *
 365                              (info->var.bits_per_pixel / 8));
 366         state->crtc[0x15] = Set8Bits(v_blank_s);
 367         state->crtc[0x16] = Set8Bits(v_blank_e);
 368
 369         state->attr[0x10] = 0x01;
 370
 371         if (par->Television)
 372                 state->attr[0x11] = 0x00;
 373
 374         state->screen = SetBitField(h_blank_e, 6: 6, 4:4)
 375                 | SetBitField(v_blank_s, 10: 10, 3:3)
 376                 | SetBitField(v_start, 10: 10, 2:2)
 377                 | SetBitField(v_display, 10: 10, 1:1)
 378                 | SetBitField(v_total, 10: 10, 0:0);
 379
 380         state->horiz = SetBitField(h_total, 8: 8, 0:0)
 381                 | SetBitField(h_display, 8: 8, 1:1)
 382                 | SetBitField(h_blank_s, 8: 8, 2:2)
 383                 | SetBitField(h_start, 8: 8, 3:3);
 384
 385         state->extra = SetBitField(v_total, 11: 11, 0:0)
 386                 | SetBitField(v_display, 11: 11, 2:2)
 387                 | SetBitField(v_start, 11: 11, 4:4)
 388                 | SetBitField(v_blank_s, 11: 11, 6:6);
 389
 390         if (info->var.vmode & FB_VMODE_INTERLACED) {
 391                 h_total = (h_total >> 1) & ~1;
 392                 state->interlace = Set8Bits(h_total);
 393                 state->horiz |= SetBitField(h_total, 8: 8, 4:4);
 394         } else {
 395                 state->interlace = 0xff;        /* interlace off */
 396         }
 397
 398         /*
 399          * Calculate the extended registers.
 400          */
 401
 402         if (depth < 24)
 403                 i = depth;
 404         else
 405                 i = 32;
 406
 407         if (par->Architecture >= NV_ARCH_10)
 408                 par->CURSOR = (volatile u32 __iomem *)(info->screen_base +
 409                                                        par->CursorStart);
 410
 411         if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
 412                 state->misc_output &= ~0x40;
 413         else
 414                 state->misc_output |= 0x40;
 415         if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
 416                 state->misc_output &= ~0x80;
 417         else
 418                 state->misc_output |= 0x80;
 419
 420         NVCalcStateExt(par, state, i, info->var.xres_virtual,
 421                        info->var.xres, info->var.yres_virtual,
 422                        1000000000 / info->var.pixclock, info->var.vmode);
 423
 424         state->scale = NV_RD32(par->PRAMDAC, 0x00000848) & 0xfff000ff;
 425         if (par->FlatPanel == 1) {
 426                 state->pixel |= (1 << 7);
 427
 428                 if (!par->fpScaler || (par->fpWidth <= info->var.xres)
 429                     || (par->fpHeight <= info->var.yres)) {
 430                         state->scale |= (1 << 8);
 431                 }
 432
 433                 if (!par->crtcSync_read) {
 434                         state->crtcSync = NV_RD32(par->PRAMDAC, 0x0828);
 435                         par->crtcSync_read = 1;
 436                 }
 437
 438                 par->PanelTweak = nvidia_panel_tweak(par, state);
 439         }
 440
 441         state->vpll = state->pll;
 442         state->vpll2 = state->pll;
 443         state->vpllB = state->pllB;
 444         state->vpll2B = state->pllB;
 445
 446         VGA_WR08(par->PCIO, 0x03D4, 0x1C);
 447         state->fifo = VGA_RD08(par->PCIO, 0x03D5) & ~(1<<5);
 448
 449         if (par->CRTCnumber) {
 450                 state->head = NV_RD32(par->PCRTC0, 0x00000860) & ~0x00001000;
 451                 state->head2 = NV_RD32(par->PCRTC0, 0x00002860) | 0x00001000;
 452                 state->crtcOwner = 3;
 453                 state->pllsel |= 0x20000800;
 454                 state->vpll = NV_RD32(par->PRAMDAC0, 0x00000508);
 455                 if (par->twoStagePLL)
 456                         state->vpllB = NV_RD32(par->PRAMDAC0, 0x00000578);
 457         } else if (par->twoHeads) {
 458                 state->head = NV_RD32(par->PCRTC0, 0x00000860) | 0x00001000;
 459                 state->head2 = NV_RD32(par->PCRTC0, 0x00002860) & ~0x00001000;
 460                 state->crtcOwner = 0;
 461                 state->vpll2 = NV_RD32(par->PRAMDAC0, 0x0520);
 462                 if (par->twoStagePLL)
 463                         state->vpll2B = NV_RD32(par->PRAMDAC0, 0x057C);
 464         }
 465
 466         state->cursorConfig = 0x00000100;
 467
 468         if (info->var.vmode & FB_VMODE_DOUBLE)
 469                 state->cursorConfig |= (1 << 4);
 470
 471         if (par->alphaCursor) {
 472                 if ((par->Chipset & 0x0ff0) != 0x0110)
 473                         state->cursorConfig |= 0x04011000;
 474                 else
 475                         state->cursorConfig |= 0x14011000;
 476                 state->general |= (1 << 29);
 477         } else
 478                 state->cursorConfig |= 0x02000000;
 479
 480         if (par->twoHeads) {
 481                 if ((par->Chipset & 0x0ff0) == 0x0110) {
 482                         state->dither = NV_RD32(par->PRAMDAC, 0x0528) &
 483                             ~0x00010000;
 484                         if (par->FPDither)
 485                                 state->dither |= 0x00010000;
 486                 } else {
 487                         state->dither = NV_RD32(par->PRAMDAC, 0x083C) & ~1;
 488                         if (par->FPDither)
 489                                 state->dither |= 1;
 490                 }
 491         }
 492
 493         state->timingH = 0;
 494         state->timingV = 0;
 495         state->displayV = info->var.xres;
 496
 497         return 0;
 498 }
 499
 500 static void nvidia_init_vga(struct fb_info *info)
 501 {
 502         struct nvidia_par *par = info->par;
 503         struct _riva_hw_state *state = &par->ModeReg;
 504         int i;
 505
 506         for (i = 0; i < 0x10; i++)
 507                 state->attr[i] = i;
 508         state->attr[0x10] = 0x41;
 509         state->attr[0x11] = 0xff;
 510         state->attr[0x12] = 0x0f;
 511         state->attr[0x13] = 0x00;
 512         state->attr[0x14] = 0x00;
 513
 514         memset(state->crtc, 0x00, NUM_CRT_REGS);
 515         state->crtc[0x0a] = 0x20;
 516         state->crtc[0x17] = 0xe3;
 517         state->crtc[0x18] = 0xff;
 518         state->crtc[0x28] = 0x40;
 519
 520         memset(state->gra, 0x00, NUM_GRC_REGS);
 521         state->gra[0x05] = 0x40;
 522         state->gra[0x06] = 0x05;
 523         state->gra[0x07] = 0x0f;
 524         state->gra[0x08] = 0xff;
 525
 526         state->seq[0x00] = 0x03;
 527         state->seq[0x01] = 0x01;
 528         state->seq[0x02] = 0x0f;
 529         state->seq[0x03] = 0x00;
 530         state->seq[0x04] = 0x0e;
 531
 532         state->misc_output = 0xeb;
 533 }
 534
 535 static int nvidiafb_cursor(struct fb_info *info, struct fb_cursor *cursor)
 536 {
 537         struct nvidia_par *par = info->par;
 538         u8 data[MAX_CURS * MAX_CURS / 8];
 539         int i, set = cursor->set;
 540         u16 fg, bg;
 541
 542         if (cursor->image.width > MAX_CURS || cursor->image.height > MAX_CURS)
 543                 return -ENXIO;
 544
 545         NVShowHideCursor(par, 0);
 546
 547         if (par->cursor_reset) {
 548                 set = FB_CUR_SETALL;
 549                 par->cursor_reset = 0;
 550         }
 551
 552         if (set & FB_CUR_SETSIZE)
 553                 memset_io(par->CURSOR, 0, MAX_CURS * MAX_CURS * 2);
 554
 555         if (set & FB_CUR_SETPOS) {
 556                 u32 xx, yy, temp;
 557
 558                 yy = cursor->image.dy - info->var.yoffset;
 559                 xx = cursor->image.dx - info->var.xoffset;
 560                 temp = xx & 0xFFFF;
 561                 temp |= yy << 16;
 562
 563                 NV_WR32(par->PRAMDAC, 0x0000300, temp);
 564         }
 565
 566         if (set & (FB_CUR_SETSHAPE | FB_CUR_SETCMAP | FB_CUR_SETIMAGE)) {
 567                 u32 bg_idx = cursor->image.bg_color;
 568                 u32 fg_idx = cursor->image.fg_color;
 569                 u32 s_pitch = (cursor->image.width + 7) >> 3;
 570                 u32 d_pitch = MAX_CURS / 8;
 571                 u8 *dat = (u8 *) cursor->image.data;
 572                 u8 *msk = (u8 *) cursor->mask;
 573                 u8 *src;
 574
 575                 src = kmalloc(s_pitch * cursor->image.height, GFP_ATOMIC);
 576
 577                 if (src) {
 578                         switch (cursor->rop) {
 579                         case ROP_XOR:
 580                                 for (i = 0; i < s_pitch * cursor->image.height; i++)
 581                                         src[i] = dat[i] ^ msk[i];
 582                                 break;
 583                         case ROP_COPY:
 584                         default:
 585                                 for (i = 0; i < s_pitch * cursor->image.height; i++)
 586                                         src[i] = dat[i] & msk[i];
 587                                 break;
 588                         }
 589
 590                         fb_pad_aligned_buffer(data, d_pitch, src, s_pitch,
 591                                                 cursor->image.height);
 592
 593                         bg = ((info->cmap.red[bg_idx] & 0xf8) << 7) |
 594                             ((info->cmap.green[bg_idx] & 0xf8) << 2) |
 595                             ((info->cmap.blue[bg_idx] & 0xf8) >> 3) | 1 << 15;
 596
 597                         fg = ((info->cmap.red[fg_idx] & 0xf8) << 7) |
 598                             ((info->cmap.green[fg_idx] & 0xf8) << 2) |
 599                             ((info->cmap.blue[fg_idx] & 0xf8) >> 3) | 1 << 15;
 600
 601                         NVLockUnlock(par, 0);
 602
 603                         nvidiafb_load_cursor_image(par, data, bg, fg,
 604                                                    cursor->image.width,
 605                                                    cursor->image.height);
 606                         kfree(src);
 607                 }
 608         }
 609
 610         if (cursor->enable)
 611                 NVShowHideCursor(par, 1);
 612
 613         return 0;
 614 }
 615
 616 static int nvidiafb_set_par(struct fb_info *info)
 617 {
 618         struct nvidia_par *par = info->par;
 619
 620         NVTRACE_ENTER();
 621
 622         NVLockUnlock(par, 1);
 623         if (!par->FlatPanel || !par->twoHeads)
 624                 par->FPDither = 0;
 625
 626         if (par->FPDither < 0) {
 627                 if ((par->Chipset & 0x0ff0) == 0x0110)
 628                         par->FPDither = !!(NV_RD32(par->PRAMDAC, 0x0528)
 629                                            & 0x00010000);
 630                 else
 631                         par->FPDither = !!(NV_RD32(par->PRAMDAC, 0x083C) & 1);
 632                 printk(KERN_INFO PFX "Flat panel dithering %s\n",
 633                        par->FPDither ? "enabled" : "disabled");
 634         }
 635
 636         info->fix.visual = (info->var.bits_per_pixel == 8) ?
 637             FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
 638
 639         nvidia_init_vga(info);
 640         nvidia_calc_regs(info);
 641
 642         NVLockUnlock(par, 0);
 643         if (par->twoHeads) {
 644                 VGA_WR08(par->PCIO, 0x03D4, 0x44);
 645                 VGA_WR08(par->PCIO, 0x03D5, par->ModeReg.crtcOwner);
 646                 NVLockUnlock(par, 0);
 647         }
 648
 649         nvidia_vga_protect(par, 1);
 650
 651         nvidia_write_regs(par, &par->ModeReg);
 652         NVSetStartAddress(par, 0);
 653
 654 #if defined (__BIG_ENDIAN)
 655         /* turn on LFB swapping */
 656         {
 657                 unsigned char tmp;
 658
 659                 VGA_WR08(par->PCIO, 0x3d4, 0x46);
 660                 tmp = VGA_RD08(par->PCIO, 0x3d5);
 661                 tmp |= (1 << 7);
 662                 VGA_WR08(par->PCIO, 0x3d5, tmp);
 663     }
 664 #endif
 665
 666         info->fix.line_length = (info->var.xres_virtual *
 667                                  info->var.bits_per_pixel) >> 3;
 668         if (info->var.accel_flags) {
 669                 info->fbops->fb_imageblit = nvidiafb_imageblit;
 670                 info->fbops->fb_fillrect = nvidiafb_fillrect;
 671                 info->fbops->fb_copyarea = nvidiafb_copyarea;
 672                 info->fbops->fb_sync = nvidiafb_sync;
 673                 info->pixmap.scan_align = 4;
 674                 info->flags &= ~FBINFO_HWACCEL_DISABLED;
 675                 NVResetGraphics(info);
 676         } else {
 677                 info->fbops->fb_imageblit = cfb_imageblit;
 678                 info->fbops->fb_fillrect = cfb_fillrect;
 679                 info->fbops->fb_copyarea = cfb_copyarea;
 680                 info->fbops->fb_sync = NULL;
 681                 info->pixmap.scan_align = 1;
 682                 info->flags |= FBINFO_HWACCEL_DISABLED;
 683         }
 684
 685         par->cursor_reset = 1;
 686
 687         nvidia_vga_protect(par, 0);
 688
 689         NVTRACE_LEAVE();
 690         return 0;
 691 }
 692
 693 static int nvidiafb_setcolreg(unsigned regno, unsigned red, unsigned green,
 694                               unsigned blue, unsigned transp,
 695                               struct fb_info *info)
 696 {
 697         struct nvidia_par *par = info->par;
 698         int i;
 699
 700         NVTRACE_ENTER();
 701         if (regno >= (1 << info->var.green.length))
 702                 return -EINVAL;
 703
 704         if (info->var.grayscale) {
 705                 /* gray = 0.30*R + 0.59*G + 0.11*B */
 706                 red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
 707         }
 708
 709         if (regno < 16 && info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
 710                 ((u32 *) info->pseudo_palette)[regno] =
 711                     (regno << info->var.red.offset) |
 712                     (regno << info->var.green.offset) |
 713                     (regno << info->var.blue.offset);
 714         }
 715
 716         switch (info->var.bits_per_pixel) {
 717         case 8:
 718                 /* "transparent" stuff is completely ignored. */
 719                 nvidia_write_clut(par, regno, red >> 8, green >> 8, blue >> 8);
 720                 break;
 721         case 16:
 722                 if (info->var.green.length == 5) {
 723                         for (i = 0; i < 8; i++) {
 724                                 nvidia_write_clut(par, regno * 8 + i, red >> 8,
 725                                                   green >> 8, blue >> 8);
 726                         }
 727                 } else {
 728                         u8 r, g, b;
 729
 730                         if (regno < 32) {
 731                                 for (i = 0; i < 8; i++) {
 732                                         nvidia_write_clut(par, regno * 8 + i,
 733                                                           red >> 8, green >> 8,
 734                                                           blue >> 8);
 735                                 }
 736                         }
 737
 738                         nvidia_read_clut(par, regno * 4, &r, &g, &b);
 739
 740                         for (i = 0; i < 4; i++)
 741                                 nvidia_write_clut(par, regno * 4 + i, r,
 742                                                   green >> 8, b);
 743                 }
 744                 break;
 745         case 32:
 746                 nvidia_write_clut(par, regno, red >> 8, green >> 8, blue >> 8);
 747                 break;
 748         default:
 749                 /* do nothing */
 750                 break;
 751         }
 752
 753         NVTRACE_LEAVE();
 754         return 0;
 755 }
 756
 757 static int nvidiafb_check_var(struct fb_var_screeninfo *var,
 758                               struct fb_info *info)
 759 {
 760         struct nvidia_par *par = info->par;
 761         int memlen, vramlen, mode_valid = 0;
 762         int pitch, err = 0;
 763
 764         NVTRACE_ENTER();
 765
 766         var->transp.offset = 0;
 767         var->transp.length = 0;
 768
 769         var->xres &= ~7;
 770
 771         if (var->bits_per_pixel <= 8)
 772                 var->bits_per_pixel = 8;
 773         else if (var->bits_per_pixel <= 16)
 774                 var->bits_per_pixel = 16;
 775         else
 776                 var->bits_per_pixel = 32;
 777
 778         switch (var->bits_per_pixel) {
 779         case 8:
 780                 var->red.offset = 0;
 781                 var->red.length = 8;
 782                 var->green.offset = 0;
 783                 var->green.length = 8;
 784                 var->blue.offset = 0;
 785                 var->blue.length = 8;
 786                 var->transp.offset = 0;
 787                 var->transp.length = 0;
 788                 break;
 789         case 16:
 790                 var->green.length = (var->green.length < 6) ? 5 : 6;
 791                 var->red.length = 5;
 792                 var->blue.length = 5;
 793                 var->transp.length = 6 - var->green.length;
 794                 var->blue.offset = 0;
 795                 var->green.offset = 5;
 796                 var->red.offset = 5 + var->green.length;
 797                 var->transp.offset = (5 + var->red.offset) & 15;
 798                 break;
 799         case 32:                /* RGBA 8888 */
 800                 var->red.offset = 16;
 801                 var->red.length = 8;
 802                 var->green.offset = 8;
 803                 var->green.length = 8;
 804                 var->blue.offset = 0;
 805                 var->blue.length = 8;
 806                 var->transp.length = 8;
 807                 var->transp.offset = 24;
 808                 break;
 809         }
 810
 811         var->red.msb_right = 0;
 812         var->green.msb_right = 0;
 813         var->blue.msb_right = 0;
 814         var->transp.msb_right = 0;
 815
 816         if (!info->monspecs.hfmax || !info->monspecs.vfmax ||
 817             !info->monspecs.dclkmax || !fb_validate_mode(var, info))
 818                 mode_valid = 1;
 819
 820         /* calculate modeline if supported by monitor */
 821         if (!mode_valid && info->monspecs.gtf) {
 822                 if (!fb_get_mode(FB_MAXTIMINGS, 0, var, info))
 823                         mode_valid = 1;
 824         }
 825
 826         if (!mode_valid) {
 827                 struct fb_videomode *mode;
 828
 829                 mode = fb_find_best_mode(var, &info->modelist);
 830                 if (mode) {
 831                         fb_videomode_to_var(var, mode);
 832                         mode_valid = 1;
 833                 }
 834         }
 835
 836         if (!mode_valid && info->monspecs.modedb_len)
 837                 return -EINVAL;
 838
 839         if (par->fpWidth && par->fpHeight && (par->fpWidth < var->xres ||
 840                                               par->fpHeight < var->yres))
 841                 return -EINVAL;
 842
 843         if (var->yres_virtual < var->yres)
 844                 var->yres_virtual = var->yres;
 845
 846         if (var->xres_virtual < var->xres)
 847                 var->xres_virtual = var->xres;
 848
 849         var->xres_virtual = (var->xres_virtual + 63) & ~63;
 850
 851         vramlen = info->screen_size;
 852         pitch = ((var->xres_virtual * var->bits_per_pixel) + 7) / 8;
 853         memlen = pitch * var->yres_virtual;
 854
 855         if (memlen > vramlen) {
 856                 var->yres_virtual = vramlen / pitch;
 857
 858                 if (var->yres_virtual < var->yres) {
 859                         var->yres_virtual = var->yres;
 860                         var->xres_virtual = vramlen / var->yres_virtual;
 861                         var->xres_virtual /= var->bits_per_pixel / 8;
 862                         var->xres_virtual &= ~63;
 863                         pitch = (var->xres_virtual *
 864                                  var->bits_per_pixel + 7) / 8;
 865                         memlen = pitch * var->yres;
 866
 867                         if (var->xres_virtual < var->xres) {
 868                                 printk("nvidiafb: required video memory, "
 869                                        "%d bytes, for %dx%d-%d (virtual) "
 870                                        "is out of range\n",
 871                                        memlen, var->xres_virtual,
 872                                        var->yres_virtual, var->bits_per_pixel);
 873                                 err = -ENOMEM;
 874                         }
 875                 }
 876         }
 877
 878         if (var->accel_flags) {
 879                 if (var->yres_virtual > 0x7fff)
 880                         var->yres_virtual = 0x7fff;
 881                 if (var->xres_virtual > 0x7fff)
 882                         var->xres_virtual = 0x7fff;
 883         }
 884
 885         var->xres_virtual &= ~63;
 886
 887         NVTRACE_LEAVE();
 888
 889         return err;
 890 }
 891
 892 static int nvidiafb_pan_display(struct fb_var_screeninfo *var,
 893                                 struct fb_info *info)
 894 {
 895         struct nvidia_par *par = info->par;
 896         u32 total;
 897
 898         total = var->yoffset * info->fix.line_length + var->xoffset;
 899
 900         NVSetStartAddress(par, total);
 901
 902         return 0;
 903 }
 904
 905 static int nvidiafb_blank(int blank, struct fb_info *info)
 906 {
 907         struct nvidia_par *par = info->par;
 908         unsigned char tmp, vesa;
 909
 910         tmp = NVReadSeq(par, 0x01) & ~0x20;     /* screen on/off */
 911         vesa = NVReadCrtc(par, 0x1a) & ~0xc0;   /* sync on/off */
 912
 913         NVTRACE_ENTER();
 914
 915         if (blank)
 916                 tmp |= 0x20;
 917
 918         switch (blank) {
 919         case FB_BLANK_UNBLANK:
 920         case FB_BLANK_NORMAL:
 921                 break;
 922         case FB_BLANK_VSYNC_SUSPEND:
 923                 vesa |= 0x80;
 924                 break;
 925         case FB_BLANK_HSYNC_SUSPEND:
 926                 vesa |= 0x40;
 927                 break;
 928         case FB_BLANK_POWERDOWN:
 929                 vesa |= 0xc0;
 930                 break;
 931         }
 932
 933         NVWriteSeq(par, 0x01, tmp);
 934         NVWriteCrtc(par, 0x1a, vesa);
 935
 936 #ifdef CONFIG_FB_NVIDIA_BACKLIGHT
 937         mutex_lock(&info->bl_mutex);
 938         if (info->bl_dev) {
 939                 down(&info->bl_dev->sem);
 940                 info->bl_dev->props->power = blank;
 941                 info->bl_dev->props->update_status(info->bl_dev);
 942                 up(&info->bl_dev->sem);
 943         }
 944         mutex_unlock(&info->bl_mutex);
 945 #endif
 946
 947         NVTRACE_LEAVE();
 948
 949         return 0;
 950 }
 951
 952 static struct fb_ops nvidia_fb_ops = {
 953         .owner          = THIS_MODULE,
 954         .fb_check_var   = nvidiafb_check_var,
 955         .fb_set_par     = nvidiafb_set_par,
 956         .fb_setcolreg   = nvidiafb_setcolreg,
 957         .fb_pan_display = nvidiafb_pan_display,
 958         .fb_blank       = nvidiafb_blank,
 959         .fb_fillrect    = nvidiafb_fillrect,
 960         .fb_copyarea    = nvidiafb_copyarea,
 961         .fb_imageblit   = nvidiafb_imageblit,
 962         .fb_cursor      = nvidiafb_cursor,
 963         .fb_sync        = nvidiafb_sync,
 964 };
 965
 966 #ifdef CONFIG_PM
 967 static int nvidiafb_suspend(struct pci_dev *dev, pm_message_t state)
 968 {
 969         struct fb_info *info = pci_get_drvdata(dev);
 970         struct nvidia_par *par = info->par;
 971
 972         acquire_console_sem();
 973         par->pm_state = state.event;
 974
 975         if (state.event == PM_EVENT_FREEZE) {
 976                 dev->dev.power.power_state = state;
 977         } else {
 978                 fb_set_suspend(info, 1);
 979                 nvidiafb_blank(FB_BLANK_POWERDOWN, info);
 980                 nvidia_write_regs(par, &par->SavedReg);
 981                 pci_save_state(dev);
 982                 pci_disable_device(dev);
 983                 pci_set_power_state(dev, pci_choose_state(dev, state));
 984         }
 985
 986         release_console_sem();
 987         return 0;
 988 }
 989
 990 static int nvidiafb_resume(struct pci_dev *dev)
 991 {
 992         struct fb_info *info = pci_get_drvdata(dev);
 993         struct nvidia_par *par = info->par;
 994
 995         acquire_console_sem();
 996         pci_set_power_state(dev, PCI_D0);
 997
 998         if (par->pm_state != PM_EVENT_FREEZE) {
 999                 pci_restore_state(dev);
1000                 pci_enable_device(dev);
1001                 pci_set_master(dev);
1002         }
1003
1004         par->pm_state = PM_EVENT_ON;
1005         nvidiafb_set_par(info);
1006         fb_set_suspend (info, 0);
1007         nvidiafb_blank(FB_BLANK_UNBLANK, info);
1008
1009         release_console_sem();
1010         return 0;
1011 }
1012 #else
1013 #define nvidiafb_suspend NULL
1014 #define nvidiafb_resume NULL
1015 #endif
1016
1017 static int __devinit nvidia_set_fbinfo(struct fb_info *info)
1018 {
1019         struct fb_monspecs *specs = &info->monspecs;
1020         struct fb_videomode modedb;
1021         struct nvidia_par *par = info->par;
1022         int lpitch;
1023
1024         NVTRACE_ENTER();
1025         info->flags = FBINFO_DEFAULT
1026             | FBINFO_HWACCEL_IMAGEBLIT
1027             | FBINFO_HWACCEL_FILLRECT
1028             | FBINFO_HWACCEL_COPYAREA
1029             | FBINFO_HWACCEL_YPAN;
1030
1031         fb_videomode_to_modelist(info->monspecs.modedb,
1032                                  info->monspecs.modedb_len, &info->modelist);
1033         fb_var_to_videomode(&modedb, &nvidiafb_default_var);
1034
1035         switch (bpp) {
1036         case 0 ... 8:
1037                 bpp = 8;
1038                 break;
1039         case 9 ... 16:
1040                 bpp = 16;
1041                 break;
1042         default:
1043                 bpp = 32;
1044                 break;
1045         }
1046
1047         if (specs->modedb != NULL) {
1048                 struct fb_videomode *modedb;
1049
1050                 modedb = fb_find_best_display(specs, &info->modelist);
1051                 fb_videomode_to_var(&nvidiafb_default_var, modedb);
1052                 nvidiafb_default_var.bits_per_pixel = bpp;
1053         } else if (par->fpWidth && par->fpHeight) {
1054                 char buf[16];
1055
1056                 memset(buf, 0, 16);
1057                 snprintf(buf, 15, "%dx%dMR", par->fpWidth, par->fpHeight);
1058                 fb_find_mode(&nvidiafb_default_var, info, buf, specs->modedb,
1059                              specs->modedb_len, &modedb, bpp);
1060         }
1061
1062         if (mode_option)
1063                 fb_find_mode(&nvidiafb_default_var, info, mode_option,
1064                              specs->modedb, specs->modedb_len, &modedb, bpp);
1065
1066         info->var = nvidiafb_default_var;
1067         info->fix.visual = (info->var.bits_per_pixel == 8) ?
1068                 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1069         info->pseudo_palette = par->pseudo_palette;
1070         fb_alloc_cmap(&info->cmap, 256, 0);
1071         fb_destroy_modedb(info->monspecs.modedb);
1072         info->monspecs.modedb = NULL;
1073
1074         /* maximize virtual vertical length */
1075         lpitch = info->var.xres_virtual *
1076                 ((info->var.bits_per_pixel + 7) >> 3);
1077         info->var.yres_virtual = info->screen_size / lpitch;
1078
1079         info->pixmap.scan_align = 4;
1080         info->pixmap.buf_align = 4;
1081         info->pixmap.access_align = 32;
1082         info->pixmap.size = 8 * 1024;
1083         info->pixmap.flags = FB_PIXMAP_SYSTEM;
1084
1085         if (!hwcur)
1086             info->fbops->fb_cursor = NULL;
1087
1088         info->var.accel_flags = (!noaccel);
1089
1090         switch (par->Architecture) {
1091         case NV_ARCH_04:
1092                 info->fix.accel = FB_ACCEL_NV4;
1093                 break;
1094         case NV_ARCH_10:
1095                 info->fix.accel = FB_ACCEL_NV_10;
1096                 break;
1097         case NV_ARCH_20:
1098                 info->fix.accel = FB_ACCEL_NV_20;
1099                 break;
1100         case NV_ARCH_30:
1101                 info->fix.accel = FB_ACCEL_NV_30;
1102                 break;
1103         case NV_ARCH_40:
1104                 info->fix.accel = FB_ACCEL_NV_40;
1105                 break;
1106         }
1107
1108         NVTRACE_LEAVE();
1109
1110         return nvidiafb_check_var(&info->var, info);
1111 }
1112
1113 static u32 __devinit nvidia_get_chipset(struct fb_info *info)
1114 {
1115         struct nvidia_par *par = info->par;
1116         u32 id = (par->pci_dev->vendor << 16) | par->pci_dev->device;
1117
1118         printk(KERN_INFO PFX "Device ID: %x \n", id);
1119
1120         if ((id & 0xfff0) == 0x00f0) {
1121                 /* pci-e */
1122                 id = NV_RD32(par->REGS, 0x1800);
1123
1124                 if ((id & 0x0000ffff) == 0x000010DE)
1125                         id = 0x10DE0000 | (id >> 16);
1126                 else if ((id & 0xffff0000) == 0xDE100000) /* wrong endian */
1127                         id = 0x10DE0000 | ((id << 8) & 0x0000ff00) |
1128                             ((id >> 8) & 0x000000ff);
1129                 printk(KERN_INFO PFX "Subsystem ID: %x \n", id);
1130         }
1131
1132         return id;
1133 }
1134
1135 static u32 __devinit nvidia_get_arch(struct fb_info *info)
1136 {
1137         struct nvidia_par *par = info->par;
1138         u32 arch = 0;
1139
1140         switch (par->Chipset & 0x0ff0) {
1141         case 0x0100:            /* GeForce 256 */
1142         case 0x0110:            /* GeForce2 MX */
1143         case 0x0150:            /* GeForce2 */
1144         case 0x0170:            /* GeForce4 MX */
1145         case 0x0180:            /* GeForce4 MX (8x AGP) */
1146         case 0x01A0:            /* nForce */
1147         case 0x01F0:            /* nForce2 */
1148                 arch = NV_ARCH_10;
1149                 break;
1150         case 0x0200:            /* GeForce3 */
1151         case 0x0250:            /* GeForce4 Ti */
1152         case 0x0280:            /* GeForce4 Ti (8x AGP) */
1153                 arch = NV_ARCH_20;
1154                 break;
1155         case 0x0300:            /* GeForceFX 5800 */
1156         case 0x0310:            /* GeForceFX 5600 */
1157         case 0x0320:            /* GeForceFX 5200 */
1158         case 0x0330:            /* GeForceFX 5900 */
1159         case 0x0340:            /* GeForceFX 5700 */
1160                 arch = NV_ARCH_30;
1161                 break;
1162         case 0x0040:
1163         case 0x00C0:
1164         case 0x0120:
1165         case 0x0130:
1166         case 0x0140:
1167         case 0x0160:
1168         case 0x01D0:
1169         case 0x0090:
1170         case 0x0210:
1171         case 0x0220:
1172         case 0x0230:
1173         case 0x0240:
1174         case 0x0290:
1175         case 0x0390:
1176                 arch = NV_ARCH_40;
1177                 break;
1178         case 0x0020:            /* TNT, TNT2 */
1179                 arch = NV_ARCH_04;
1180                 break;
1181         default:                /* unknown architecture */
1182                 break;
1183         }
1184
1185         return arch;
1186 }
1187
1188 static int __devinit nvidiafb_probe(struct pci_dev *pd,
1189                                     const struct pci_device_id *ent)
1190 {
1191         struct nvidia_par *par;
1192         struct fb_info *info;
1193         unsigned short cmd;
1194
1195
1196         NVTRACE_ENTER();
1197         assert(pd != NULL);
1198
1199         info = framebuffer_alloc(sizeof(struct nvidia_par), &pd->dev);
1200
1201         if (!info)
1202                 goto err_out;
1203
1204         par = info->par;
1205         par->pci_dev = pd;
1206
1207         info->pixmap.addr = kmalloc(8 * 1024, GFP_KERNEL);
1208
1209         if (info->pixmap.addr == NULL)
1210                 goto err_out_kfree;
1211
1212         memset(info->pixmap.addr, 0, 8 * 1024);
1213
1214         if (pci_enable_device(pd)) {
1215                 printk(KERN_ERR PFX "cannot enable PCI device\n");
1216                 goto err_out_enable;
1217         }
1218
1219         if (pci_request_regions(pd, "nvidiafb")) {
1220                 printk(KERN_ERR PFX "cannot request PCI regions\n");
1221                 goto err_out_enable;
1222         }
1223
1224         par->FlatPanel = flatpanel;
1225         if (flatpanel == 1)
1226                 printk(KERN_INFO PFX "flatpanel support enabled\n");
1227         par->FPDither = fpdither;
1228
1229         par->CRTCnumber = forceCRTC;
1230         par->FpScale = (!noscale);
1231         par->paneltweak = paneltweak;
1232
1233         /* enable IO and mem if not already done */
1234         pci_read_config_word(pd, PCI_COMMAND, &cmd);
1235         cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
1236         pci_write_config_word(pd, PCI_COMMAND, cmd);
1237
1238         nvidiafb_fix.mmio_start = pci_resource_start(pd, 0);
1239         nvidiafb_fix.smem_start = pci_resource_start(pd, 1);
1240         nvidiafb_fix.mmio_len = pci_resource_len(pd, 0);
1241
1242         par->REGS = ioremap(nvidiafb_fix.mmio_start, nvidiafb_fix.mmio_len);
1243
1244         if (!par->REGS) {
1245                 printk(KERN_ERR PFX "cannot ioremap MMIO base\n");
1246                 goto err_out_free_base0;
1247         }
1248
1249         par->Chipset = nvidia_get_chipset(info);
1250         par->Architecture = nvidia_get_arch(info);
1251
1252         if (par->Architecture == 0) {
1253                 printk(KERN_ERR PFX "unknown NV_ARCH\n");
1254                 goto err_out_arch;
1255         }
1256
1257         sprintf(nvidiafb_fix.id, "NV%x", (pd->device & 0x0ff0) >> 4);
1258
1259         if (NVCommonSetup(info))
1260                 goto err_out_arch;
1261
1262         par->FbAddress = nvidiafb_fix.smem_start;
1263         par->FbMapSize = par->RamAmountKBytes * 1024;
1264         if (vram && vram * 1024 * 1024 < par->FbMapSize)
1265                 par->FbMapSize = vram * 1024 * 1024;
1266
1267         /* Limit amount of vram to 64 MB */
1268         if (par->FbMapSize > 64 * 1024 * 1024)
1269                 par->FbMapSize = 64 * 1024 * 1024;
1270
1271         if(par->Architecture >= NV_ARCH_40)
1272                 par->FbUsableSize = par->FbMapSize - (560 * 1024);
1273         else
1274                 par->FbUsableSize = par->FbMapSize - (128 * 1024);
1275         par->ScratchBufferSize = (par->Architecture < NV_ARCH_10) ? 8 * 1024 :
1276             16 * 1024;
1277         par->ScratchBufferStart = par->FbUsableSize - par->ScratchBufferSize;
1278         par->CursorStart = par->FbUsableSize + (32 * 1024);
1279
1280         info->screen_base = ioremap(nvidiafb_fix.smem_start, par->FbMapSize);
1281         info->screen_size = par->FbUsableSize;
1282         nvidiafb_fix.smem_len = par->RamAmountKBytes * 1024;
1283
1284         if (!info->screen_base) {
1285                 printk(KERN_ERR PFX "cannot ioremap FB base\n");
1286                 goto err_out_free_base1;
1287         }
1288
1289         par->FbStart = info->screen_base;
1290
1291 #ifdef CONFIG_MTRR
1292         if (!nomtrr) {
1293                 par->mtrr.vram = mtrr_add(nvidiafb_fix.smem_start,
1294                                           par->RamAmountKBytes * 1024,
1295                                           MTRR_TYPE_WRCOMB, 1);
1296                 if (par->mtrr.vram < 0) {
1297                         printk(KERN_ERR PFX "unable to setup MTRR\n");
1298                 } else {
1299                         par->mtrr.vram_valid = 1;
1300                         /* let there be speed */
1301                         printk(KERN_INFO PFX "MTRR set to ON\n");
1302                 }
1303         }
1304 #endif                          /* CONFIG_MTRR */
1305
1306         info->fbops = &nvidia_fb_ops;
1307         info->fix = nvidiafb_fix;
1308
1309         if (nvidia_set_fbinfo(info) < 0) {
1310                 printk(KERN_ERR PFX "error setting initial video mode\n");
1311                 goto err_out_iounmap_fb;
1312         }
1313
1314         nvidia_save_vga(par, &par->SavedReg);
1315
1316         if (register_framebuffer(info) < 0) {
1317                 printk(KERN_ERR PFX "error registering nVidia framebuffer\n");
1318                 goto err_out_iounmap_fb;
1319         }
1320
1321         pci_set_drvdata(pd, info);
1322
1323         printk(KERN_INFO PFX
1324                "PCI nVidia %s framebuffer (%dMB @ 0x%lX)\n",
1325                info->fix.id,
1326                par->FbMapSize / (1024 * 1024), info->fix.smem_start);
1327
1328         nvidia_bl_init(par);
1329
1330         NVTRACE_LEAVE();
1331         return 0;
1332
1333 err_out_iounmap_fb:
1334         iounmap(info->screen_base);
1335 err_out_free_base1:
1336         fb_destroy_modedb(info->monspecs.modedb);
1337         nvidia_delete_i2c_busses(par);
1338 err_out_arch:
1339         iounmap(par->REGS);
1340  err_out_free_base0:
1341         pci_release_regions(pd);
1342 err_out_enable:
1343         kfree(info->pixmap.addr);
1344 err_out_kfree:
1345         framebuffer_release(info);
1346 err_out:
1347         return -ENODEV;
1348 }
1349
1350 static void __exit nvidiafb_remove(struct pci_dev *pd)
1351 {
1352         struct fb_info *info = pci_get_drvdata(pd);
1353         struct nvidia_par *par = info->par;
1354
1355         NVTRACE_ENTER();
1356
1357         nvidia_bl_exit(par);
1358
1359         unregister_framebuffer(info);
1360 #ifdef CONFIG_MTRR
1361         if (par->mtrr.vram_valid)
1362                 mtrr_del(par->mtrr.vram, info->fix.smem_start,
1363                          info->fix.smem_len);
1364 #endif                          /* CONFIG_MTRR */
1365
1366         iounmap(info->screen_base);
1367         fb_destroy_modedb(info->monspecs.modedb);
1368         nvidia_delete_i2c_busses(par);
1369         iounmap(par->REGS);
1370         pci_release_regions(pd);
1371         kfree(info->pixmap.addr);
1372         framebuffer_release(info);
1373         pci_set_drvdata(pd, NULL);
1374         NVTRACE_LEAVE();
1375 }
1376
1377 /* ------------------------------------------------------------------------- *
1378  *
1379  * initialization
1380  *
1381  * ------------------------------------------------------------------------- */
1382
1383 #ifndef MODULE
1384 static int __devinit nvidiafb_setup(char *options)
1385 {
1386         char *this_opt;
1387
1388         NVTRACE_ENTER();
1389         if (!options || !*options)
1390                 return 0;
1391
1392         while ((this_opt = strsep(&options, ",")) != NULL) {
1393                 if (!strncmp(this_opt, "forceCRTC", 9)) {
1394                         char *p;
1395
1396                         p = this_opt + 9;
1397                         if (!*p || !*(++p))
1398                                 continue;
1399                         forceCRTC = *p - '0';
1400                         if (forceCRTC < 0 || forceCRTC > 1)
1401                                 forceCRTC = -1;
1402                 } else if (!strncmp(this_opt, "flatpanel", 9)) {
1403                         flatpanel = 1;
1404                 } else if (!strncmp(this_opt, "hwcur", 5)) {
1405                         hwcur = 1;
1406                 } else if (!strncmp(this_opt, "noaccel", 6)) {
1407                         noaccel = 1;
1408                 } else if (!strncmp(this_opt, "noscale", 7)) {
1409                         noscale = 1;
1410                 } else if (!strncmp(this_opt, "paneltweak:", 11)) {
1411                         paneltweak = simple_strtoul(this_opt+11, NULL, 0);
1412                 } else if (!strncmp(this_opt, "vram:", 5)) {
1413                         vram = simple_strtoul(this_opt+5, NULL, 0);
1414 #ifdef CONFIG_MTRR
1415                 } else if (!strncmp(this_opt, "nomtrr", 6)) {
1416                         nomtrr = 1;
1417 #endif
1418                 } else if (!strncmp(this_opt, "fpdither:", 9)) {
1419                         fpdither = simple_strtol(this_opt+9, NULL, 0);
1420                 } else if (!strncmp(this_opt, "bpp:", 4)) {
1421                         bpp = simple_strtoul(this_opt+4, NULL, 0);
1422                 } else
1423                         mode_option = this_opt;
1424         }
1425         NVTRACE_LEAVE();
1426         return 0;
1427 }
1428 #endif                          /* !MODULE */
1429
1430 static struct pci_driver nvidiafb_driver = {
1431         .name = "nvidiafb",
1432         .id_table = nvidiafb_pci_tbl,
1433         .probe    = nvidiafb_probe,
1434         .suspend  = nvidiafb_suspend,
1435         .resume   = nvidiafb_resume,
1436         .remove   = __exit_p(nvidiafb_remove),
1437 };
1438
1439 /* ------------------------------------------------------------------------- *
1440  *
1441  * modularization
1442  *
1443  * ------------------------------------------------------------------------- */
1444
1445 static int __devinit nvidiafb_init(void)
1446 {
1447 #ifndef MODULE
1448         char *option = NULL;
1449
1450         if (fb_get_options("nvidiafb", &option))
1451                 return -ENODEV;
1452         nvidiafb_setup(option);
1453 #endif
1454         return pci_register_driver(&nvidiafb_driver);
1455 }
1456
1457 module_init(nvidiafb_init);
1458
1459 #ifdef MODULE
1460 static void __exit nvidiafb_exit(void)
1461 {
1462         pci_unregister_driver(&nvidiafb_driver);
1463 }
1464
1465 module_exit(nvidiafb_exit);
1466
1467 module_param(flatpanel, int, 0);
1468 MODULE_PARM_DESC(flatpanel,
1469                  "Enables experimental flat panel support for some chipsets. "
1470                  "(0=disabled, 1=enabled, -1=autodetect) (default=-1)");
1471 module_param(fpdither, int, 0);
1472 MODULE_PARM_DESC(fpdither,
1473                  "Enables dithering of flat panel for 6 bits panels. "
1474                  "(0=disabled, 1=enabled, -1=autodetect) (default=-1)");
1475 module_param(hwcur, int, 0);
1476 MODULE_PARM_DESC(hwcur,
1477                  "Enables hardware cursor implementation. (0 or 1=enabled) "
1478                  "(default=0)");
1479 module_param(noaccel, int, 0);
1480 MODULE_PARM_DESC(noaccel,
1481                  "Disables hardware acceleration. (0 or 1=disable) "
1482                  "(default=0)");
1483 module_param(noscale, int, 0);
1484 MODULE_PARM_DESC(noscale,
1485                  "Disables screen scaleing. (0 or 1=disable) "
1486                  "(default=0, do scaling)");
1487 module_param(paneltweak, int, 0);
1488 MODULE_PARM_DESC(paneltweak,
1489                  "Tweak display settings for flatpanels. "
1490                  "(default=0, no tweaks)");
1491 module_param(forceCRTC, int, 0);
1492 MODULE_PARM_DESC(forceCRTC,
1493                  "Forces usage of a particular CRTC in case autodetection "
1494                  "fails. (0 or 1) (default=autodetect)");
1495 module_param(vram, int, 0);
1496 MODULE_PARM_DESC(vram,
1497                  "amount of framebuffer memory to remap in MiB"
1498                  "(default=0 - remap entire memory)");
1499 module_param(mode_option, charp, 0);
1500 MODULE_PARM_DESC(mode_option, "Specify initial video mode");
1501 module_param(bpp, int, 0);
1502 MODULE_PARM_DESC(bpp, "pixel width in bits"
1503                  "(default=8)");
1504 #ifdef CONFIG_MTRR
1505 module_param(nomtrr, bool, 0);
1506 MODULE_PARM_DESC(nomtrr, "Disables MTRR support (0 or 1=disabled) "
1507                  "(default=0)");
1508 #endif
1509
1510 MODULE_AUTHOR("Antonino Daplas");
1511 MODULE_DESCRIPTION("Framebuffer driver for nVidia graphics chipset");
1512 MODULE_LICENSE("GPL");
1513 #endif                          /* MODULE */
1514