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   1 /*
   2  *  Copyright (C) 2004 by Basler Vision Technologies AG
   3  *  Author: Thomas Koeller <thomas.koeller@baslerweb.com>
   4  *
   5  *  This program is free software; you can redistribute it and/or modify
   6  *  it under the terms of the GNU General Public License as published by
   7  *  the Free Software Foundation; either version 2 of the License, or
   8  *  (at your option) any later version.
   9  *
  10  *  This program is distributed in the hope that it will be useful,
  11  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  *  GNU General Public License for more details.
  14  *
  15  *  You should have received a copy of the GNU General Public License
  16  *  along with this program; if not, write to the Free Software
  17  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  18  */
  19
  20 #include <linux/config.h>
  21 #include <linux/kernel.h>
  22 #include <linux/init.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/ioport.h>
  25 #include <linux/err.h>
  26 #include <linux/jiffies.h>
  27 #include <linux/sched.h>
  28 #include <asm/types.h>
  29 #include <asm/rm9k-ocd.h>
  30
  31 #include <excite.h>
  32 #include <rm9k_eth.h>
  33 #include <rm9k_wdt.h>
  34 #include <rm9k_xicap.h>
  35 #include <excite_nandflash.h>
  36
  37 #include "excite_iodev.h"
  38
  39 #define RM9K_GE_UNIT    0
  40 #define XICAP_UNIT      0
  41 #define NAND_UNIT       0
  42
  43 #define DLL_TIMEOUT     3               /* seconds */
  44
  45
  46 #define RINIT(__start__, __end__, __name__, __parent__) {       \
  47         .name   = __name__ "_0",                                \
  48         .start  = (__start__),                                  \
  49         .end    = (__end__),                                    \
  50         .flags  = 0,                                            \
  51         .parent = (__parent__)                                  \
  52 }
  53
  54 #define RINIT_IRQ(__irq__, __name__) {  \
  55         .name   = __name__ "_0",        \
  56         .start  = (__irq__),            \
  57         .end    = (__irq__),            \
  58         .flags  = IORESOURCE_IRQ,       \
  59         .parent = NULL                  \
  60 }
  61
  62
  63
  64 enum {
  65         slice_xicap,
  66         slice_eth
  67 };
  68
  69
  70
  71 static struct resource
  72         excite_ctr_resource = {
  73                 .name           = "GPI counters",
  74                 .start          = 0,
  75                 .end            = 5,
  76                 .flags          = 0,
  77                 .parent         = NULL,
  78                 .sibling        = NULL,
  79                 .child          = NULL
  80         },
  81         excite_gpislice_resource = {
  82                 .name           = "GPI slices",
  83                 .start          = 0,
  84                 .end            = 1,
  85                 .flags          = 0,
  86                 .parent         = NULL,
  87                 .sibling        = NULL,
  88                 .child          = NULL
  89         },
  90         excite_mdio_channel_resource = {
  91                 .name           = "MDIO channels",
  92                 .start          = 0,
  93                 .end            = 1,
  94                 .flags          = 0,
  95                 .parent         = NULL,
  96                 .sibling        = NULL,
  97                 .child          = NULL
  98         },
  99         excite_fifomem_resource = {
 100                 .name           = "FIFO memory",
 101                 .start          = 0,
 102                 .end            = 767,
 103                 .flags          = 0,
 104                 .parent         = NULL,
 105                 .sibling        = NULL,
 106                 .child          = NULL
 107         },
 108         excite_scram_resource = {
 109                 .name           = "Scratch RAM",
 110                 .start          = EXCITE_PHYS_SCRAM,
 111                 .end            = EXCITE_PHYS_SCRAM + EXCITE_SIZE_SCRAM - 1,
 112                 .flags          = IORESOURCE_MEM,
 113                 .parent         = NULL,
 114                 .sibling        = NULL,
 115                 .child          = NULL
 116         },
 117         excite_fpga_resource = {
 118                 .name           = "System FPGA",
 119                 .start          = EXCITE_PHYS_FPGA,
 120                 .end            = EXCITE_PHYS_FPGA + EXCITE_SIZE_FPGA - 1,
 121                 .flags          = IORESOURCE_MEM,
 122                 .parent         = NULL,
 123                 .sibling        = NULL,
 124                 .child          = NULL
 125         },
 126         excite_nand_resource = {
 127                 .name           = "NAND flash control",
 128                 .start          = EXCITE_PHYS_NAND,
 129                 .end            = EXCITE_PHYS_NAND + EXCITE_SIZE_NAND - 1,
 130                 .flags          = IORESOURCE_MEM,
 131                 .parent         = NULL,
 132                 .sibling        = NULL,
 133                 .child          = NULL
 134         },
 135         excite_titan_resource = {
 136                 .name           = "TITAN registers",
 137                 .start          = EXCITE_PHYS_TITAN,
 138                 .end            = EXCITE_PHYS_TITAN + EXCITE_SIZE_TITAN - 1,
 139                 .flags          = IORESOURCE_MEM,
 140                 .parent         = NULL,
 141                 .sibling        = NULL,
 142                 .child          = NULL
 143         };
 144
 145
 146
 147 static void adjust_resources(struct resource *res, unsigned int n)
 148 {
 149         struct resource *p;
 150         const unsigned long mask = IORESOURCE_IO | IORESOURCE_MEM
 151                                    | IORESOURCE_IRQ | IORESOURCE_DMA;
 152
 153         for (p = res; p < res + n; p++) {
 154                 const struct resource * const parent = p->parent;
 155                 if (parent) {
 156                         p->start += parent->start;
 157                         p->end   += parent->start;
 158                         p->flags =  parent->flags & mask;
 159                 }
 160         }
 161 }
 162
 163
 164
 165 #if defined(CONFIG_EXCITE_FCAP_GPI) || defined(CONFIG_EXCITE_FCAP_GPI_MODULE)
 166 static struct resource xicap_rsrc[] = {
 167         RINIT(0x4840, 0x486f, XICAP_RESOURCE_FIFO_RX, &excite_titan_resource),
 168         RINIT(0x4940, 0x494b, XICAP_RESOURCE_FIFO_TX, &excite_titan_resource),
 169         RINIT(0x5040, 0x5127, XICAP_RESOURCE_XDMA, &excite_titan_resource),
 170         RINIT(0x1000, 0x112f, XICAP_RESOURCE_PKTPROC, &excite_titan_resource),
 171         RINIT(0x1100, 0x110f, XICAP_RESOURCE_PKT_STREAM, &excite_fpga_resource),
 172         RINIT(0x0800, 0x0bff, XICAP_RESOURCE_DMADESC, &excite_scram_resource),
 173         RINIT(slice_xicap, slice_xicap, XICAP_RESOURCE_GPI_SLICE, &excite_gpislice_resource),
 174         RINIT(0x0100, 0x02ff, XICAP_RESOURCE_FIFO_BLK, &excite_fifomem_resource),
 175         RINIT_IRQ(TITAN_IRQ,  XICAP_RESOURCE_IRQ)
 176 };
 177
 178 static struct platform_device xicap_pdev = {
 179         .name           = XICAP_NAME,
 180         .id             = XICAP_UNIT,
 181         .num_resources  = ARRAY_SIZE(xicap_rsrc),
 182         .resource       = xicap_rsrc
 183 };
 184
 185 /*
 186  * Create a platform device for the GPI port that receives the
 187  * image data from the embedded camera.
 188  */
 189 static int __init xicap_devinit(void)
 190 {
 191         unsigned long tend;
 192         u32 reg;
 193         int retval;
 194
 195         adjust_resources(xicap_rsrc, ARRAY_SIZE(xicap_rsrc));
 196
 197         /* Power up the slice and configure it. */
 198         reg = titan_readl(CPTC1R);
 199         reg &= ~(0x11100 << slice_xicap);
 200         titan_writel(reg, CPTC1R);
 201
 202         /* Enable slice & DLL. */
 203         reg= titan_readl(CPRR);
 204         reg &= ~(0x00030003 << (slice_xicap * 2));
 205         titan_writel(reg, CPRR);
 206
 207         /* Wait for DLLs to lock */
 208         tend = jiffies + DLL_TIMEOUT * HZ;
 209         while (time_before(jiffies, tend)) {
 210                 if (!(~titan_readl(CPDSR) & (0x1 << (slice_xicap * 4))))
 211                         break;
 212                 yield();
 213         }
 214
 215         if (~titan_readl(CPDSR) & (0x1 << (slice_xicap * 4))) {
 216                 printk(KERN_ERR "%s: DLL not locked after %u seconds\n",
 217                        xicap_pdev.name, DLL_TIMEOUT);
 218                 retval = -ETIME;
 219         } else {
 220                 /* Register platform device */
 221                 retval = platform_device_register(&xicap_pdev);
 222         }
 223
 224         return retval;
 225 }
 226
 227 device_initcall(xicap_devinit);
 228 #endif /* defined(CONFIG_EXCITE_FCAP_GPI) || defined(CONFIG_EXCITE_FCAP_GPI_MODULE) */
 229
 230
 231
 232 #if defined(CONFIG_WDT_RM9K_GPI) || defined(CONFIG_WDT_RM9K_GPI_MODULE)
 233 static struct resource wdt_rsrc[] = {
 234         RINIT(0, 0, WDT_RESOURCE_COUNTER, &excite_ctr_resource),
 235         RINIT(0x0084, 0x008f, WDT_RESOURCE_REGS, &excite_titan_resource),
 236         RINIT_IRQ(TITAN_IRQ,  WDT_RESOURCE_IRQ)
 237 };
 238
 239 static struct platform_device wdt_pdev = {
 240         .name           = WDT_NAME,
 241         .id             = -1,
 242         .num_resources  = ARRAY_SIZE(wdt_rsrc),
 243         .resource       = wdt_rsrc
 244 };
 245
 246 /*
 247  * Create a platform device for the GPI port that receives the
 248  * image data from the embedded camera.
 249  */
 250 static int __init wdt_devinit(void)
 251 {
 252         adjust_resources(wdt_rsrc, ARRAY_SIZE(wdt_rsrc));
 253         return platform_device_register(&wdt_pdev);
 254 }
 255
 256 device_initcall(wdt_devinit);
 257 #endif /* defined(CONFIG_WDT_RM9K_GPI) || defined(CONFIG_WDT_RM9K_GPI_MODULE) */
 258
 259
 260
 261 static struct resource excite_nandflash_rsrc[] = {
 262         RINIT(0x2000, 0x201f, EXCITE_NANDFLASH_RESOURCE_REGS,  &excite_nand_resource)
 263 };
 264
 265 static struct platform_device excite_nandflash_pdev = {
 266         .name           = "excite_nand",
 267         .id             = NAND_UNIT,
 268         .num_resources  = ARRAY_SIZE(excite_nandflash_rsrc),
 269         .resource       = excite_nandflash_rsrc
 270 };
 271
 272 /*
 273  * Create a platform device for the access to the nand-flash
 274  * port
 275  */
 276 static int __init excite_nandflash_devinit(void)
 277 {
 278         adjust_resources(excite_nandflash_rsrc, ARRAY_SIZE(excite_nandflash_rsrc));
 279
 280         /* nothing to be done here */
 281
 282         /* Register platform device */
 283         return platform_device_register(&excite_nandflash_pdev);
 284 }
 285
 286 device_initcall(excite_nandflash_devinit);
 287
 288
 289
 290 static struct resource iodev_rsrc[] = {
 291         RINIT_IRQ(FPGA1_IRQ,  IODEV_RESOURCE_IRQ)
 292 };
 293
 294 static struct platform_device io_pdev = {
 295         .name           = IODEV_NAME,
 296         .id             = -1,
 297         .num_resources  = ARRAY_SIZE(iodev_rsrc),
 298         .resource       = iodev_rsrc
 299 };
 300
 301 /*
 302  * Create a platform device for the external I/O ports.
 303  */
 304 static int __init io_devinit(void)
 305 {
 306         adjust_resources(iodev_rsrc, ARRAY_SIZE(iodev_rsrc));
 307         return platform_device_register(&io_pdev);
 308 }
 309
 310 device_initcall(io_devinit);
 311
 312
 313
 314
 315 #if defined(CONFIG_RM9K_GE) || defined(CONFIG_RM9K_GE_MODULE)
 316 static struct resource rm9k_ge_rsrc[] = {
 317         RINIT(0x2200, 0x27ff, RM9K_GE_RESOURCE_MAC, &excite_titan_resource),
 318         RINIT(0x1800, 0x1fff, RM9K_GE_RESOURCE_MSTAT, &excite_titan_resource),
 319         RINIT(0x2000, 0x212f, RM9K_GE_RESOURCE_PKTPROC, &excite_titan_resource),
 320         RINIT(0x5140, 0x5227, RM9K_GE_RESOURCE_XDMA, &excite_titan_resource),
 321         RINIT(0x4870, 0x489f, RM9K_GE_RESOURCE_FIFO_RX, &excite_titan_resource),
 322         RINIT(0x494c, 0x4957, RM9K_GE_RESOURCE_FIFO_TX, &excite_titan_resource),
 323         RINIT(0x0000, 0x007f, RM9K_GE_RESOURCE_FIFOMEM_RX, &excite_fifomem_resource),
 324         RINIT(0x0080, 0x00ff, RM9K_GE_RESOURCE_FIFOMEM_TX, &excite_fifomem_resource),
 325         RINIT(0x0180, 0x019f, RM9K_GE_RESOURCE_PHY, &excite_titan_resource),
 326         RINIT(0x0000, 0x03ff, RM9K_GE_RESOURCE_DMADESC_RX, &excite_scram_resource),
 327         RINIT(0x0400, 0x07ff, RM9K_GE_RESOURCE_DMADESC_TX, &excite_scram_resource),
 328         RINIT(slice_eth, slice_eth, RM9K_GE_RESOURCE_GPI_SLICE, &excite_gpislice_resource),
 329         RINIT(0, 0, RM9K_GE_RESOURCE_MDIO_CHANNEL, &excite_mdio_channel_resource),
 330         RINIT_IRQ(TITAN_IRQ,  RM9K_GE_RESOURCE_IRQ_MAIN),
 331         RINIT_IRQ(PHY_IRQ, RM9K_GE_RESOURCE_IRQ_PHY)
 332 };
 333
 334 static struct platform_device rm9k_ge_pdev = {
 335         .name           = RM9K_GE_NAME,
 336         .id             = RM9K_GE_UNIT,
 337         .num_resources  = ARRAY_SIZE(rm9k_ge_rsrc),
 338         .resource       = rm9k_ge_rsrc
 339 };
 340
 341
 342
 343 /*
 344  * Create a platform device for the Ethernet port.
 345  */
 346 static int __init rm9k_ge_devinit(void)
 347 {
 348         u32 reg;
 349
 350         adjust_resources(rm9k_ge_rsrc, ARRAY_SIZE(rm9k_ge_rsrc));
 351
 352         /* Power up the slice and configure it. */
 353         reg = titan_readl(CPTC1R);
 354         reg &= ~(0x11000 << slice_eth);
 355         reg |= 0x100 << slice_eth;
 356         titan_writel(reg, CPTC1R);
 357
 358         /* Take the MAC out of reset, reset the DLLs. */
 359         reg = titan_readl(CPRR);
 360         reg &= ~(0x00030000 << (slice_eth * 2));
 361         reg |= 0x3 << (slice_eth * 2);
 362         titan_writel(reg, CPRR);
 363
 364         return platform_device_register(&rm9k_ge_pdev);
 365 }
 366
 367 device_initcall(rm9k_ge_devinit);
 368 #endif /* defined(CONFIG_RM9K_GE) || defined(CONFIG_RM9K_GE_MODULE) */
 369
 370
 371
 372 static int __init excite_setup_devs(void)
 373 {
 374         int res;
 375         u32 reg;
 376
 377         /* Enable xdma and fifo interrupts */
 378         reg = titan_readl(0x0050);
 379         titan_writel(reg | 0x18000000, 0x0050);
 380
 381         res = request_resource(&iomem_resource, &excite_titan_resource);
 382         if (res)
 383                 return res;
 384         res = request_resource(&iomem_resource, &excite_scram_resource);
 385         if (res)
 386                 return res;
 387         res = request_resource(&iomem_resource, &excite_fpga_resource);
 388         if (res)
 389                 return res;
 390         res = request_resource(&iomem_resource, &excite_nand_resource);
 391         if (res)
 392                 return res;
 393         excite_fpga_resource.flags = excite_fpga_resource.parent->flags &
 394                                    ( IORESOURCE_IO | IORESOURCE_MEM
 395                                    | IORESOURCE_IRQ | IORESOURCE_DMA);
 396         excite_nand_resource.flags = excite_nand_resource.parent->flags &
 397                                    ( IORESOURCE_IO | IORESOURCE_MEM
 398                                    | IORESOURCE_IRQ | IORESOURCE_DMA);
 399
 400         return 0;
 401 }
 402
 403 arch_initcall(excite_setup_devs);
 404