git.oblomov.eu Git - linux-2.6/blob - drivers/net/niu.c

   1 /* niu.c: Neptune ethernet driver.
   2  *
   3  * Copyright (C) 2007, 2008 David S. Miller (davem@davemloft.net)
   4  */
   5
   6 #include <linux/module.h>
   7 #include <linux/init.h>
   8 #include <linux/pci.h>
   9 #include <linux/dma-mapping.h>
  10 #include <linux/netdevice.h>
  11 #include <linux/ethtool.h>
  12 #include <linux/etherdevice.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/delay.h>
  15 #include <linux/bitops.h>
  16 #include <linux/mii.h>
  17 #include <linux/if_ether.h>
  18 #include <linux/if_vlan.h>
  19 #include <linux/ip.h>
  20 #include <linux/in.h>
  21 #include <linux/ipv6.h>
  22 #include <linux/log2.h>
  23 #include <linux/jiffies.h>
  24 #include <linux/crc32.h>
  25
  26 #include <linux/io.h>
  27
  28 #ifdef CONFIG_SPARC64
  29 #include <linux/of_device.h>
  30 #endif
  31
  32 #include "niu.h"
  33
  34 #define DRV_MODULE_NAME         "niu"
  35 #define PFX DRV_MODULE_NAME     ": "
  36 #define DRV_MODULE_VERSION      "1.0"
  37 #define DRV_MODULE_RELDATE      "Nov 14, 2008"
  38
  39 static char version[] __devinitdata =
  40         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  41
  42 MODULE_AUTHOR("David S. Miller (davem@davemloft.net)");
  43 MODULE_DESCRIPTION("NIU ethernet driver");
  44 MODULE_LICENSE("GPL");
  45 MODULE_VERSION(DRV_MODULE_VERSION);
  46
  47 #ifndef DMA_44BIT_MASK
  48 #define DMA_44BIT_MASK  0x00000fffffffffffULL
  49 #endif
  50
  51 #ifndef readq
  52 static u64 readq(void __iomem *reg)
  53 {
  54         return ((u64) readl(reg)) | (((u64) readl(reg + 4UL)) << 32);
  55 }
  56
  57 static void writeq(u64 val, void __iomem *reg)
  58 {
  59         writel(val & 0xffffffff, reg);
  60         writel(val >> 32, reg + 0x4UL);
  61 }
  62 #endif
  63
  64 static struct pci_device_id niu_pci_tbl[] = {
  65         {PCI_DEVICE(PCI_VENDOR_ID_SUN, 0xabcd)},
  66         {}
  67 };
  68
  69 MODULE_DEVICE_TABLE(pci, niu_pci_tbl);
  70
  71 #define NIU_TX_TIMEOUT                  (5 * HZ)
  72
  73 #define nr64(reg)               readq(np->regs + (reg))
  74 #define nw64(reg, val)          writeq((val), np->regs + (reg))
  75
  76 #define nr64_mac(reg)           readq(np->mac_regs + (reg))
  77 #define nw64_mac(reg, val)      writeq((val), np->mac_regs + (reg))
  78
  79 #define nr64_ipp(reg)           readq(np->regs + np->ipp_off + (reg))
  80 #define nw64_ipp(reg, val)      writeq((val), np->regs + np->ipp_off + (reg))
  81
  82 #define nr64_pcs(reg)           readq(np->regs + np->pcs_off + (reg))
  83 #define nw64_pcs(reg, val)      writeq((val), np->regs + np->pcs_off + (reg))
  84
  85 #define nr64_xpcs(reg)          readq(np->regs + np->xpcs_off + (reg))
  86 #define nw64_xpcs(reg, val)     writeq((val), np->regs + np->xpcs_off + (reg))
  87
  88 #define NIU_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
  89
  90 static int niu_debug;
  91 static int debug = -1;
  92 module_param(debug, int, 0);
  93 MODULE_PARM_DESC(debug, "NIU debug level");
  94
  95 #define niudbg(TYPE, f, a...) \
  96 do {    if ((np)->msg_enable & NETIF_MSG_##TYPE) \
  97                 printk(KERN_DEBUG PFX f, ## a); \
  98 } while (0)
  99
 100 #define niuinfo(TYPE, f, a...) \
 101 do {    if ((np)->msg_enable & NETIF_MSG_##TYPE) \
 102                 printk(KERN_INFO PFX f, ## a); \
 103 } while (0)
 104
 105 #define niuwarn(TYPE, f, a...) \
 106 do {    if ((np)->msg_enable & NETIF_MSG_##TYPE) \
 107                 printk(KERN_WARNING PFX f, ## a); \
 108 } while (0)
 109
 110 #define niu_lock_parent(np, flags) \
 111         spin_lock_irqsave(&np->parent->lock, flags)
 112 #define niu_unlock_parent(np, flags) \
 113         spin_unlock_irqrestore(&np->parent->lock, flags)
 114
 115 static int serdes_init_10g_serdes(struct niu *np);
 116
 117 static int __niu_wait_bits_clear_mac(struct niu *np, unsigned long reg,
 118                                      u64 bits, int limit, int delay)
 119 {
 120         while (--limit >= 0) {
 121                 u64 val = nr64_mac(reg);
 122
 123                 if (!(val & bits))
 124                         break;
 125                 udelay(delay);
 126         }
 127         if (limit < 0)
 128                 return -ENODEV;
 129         return 0;
 130 }
 131
 132 static int __niu_set_and_wait_clear_mac(struct niu *np, unsigned long reg,
 133                                         u64 bits, int limit, int delay,
 134                                         const char *reg_name)
 135 {
 136         int err;
 137
 138         nw64_mac(reg, bits);
 139         err = __niu_wait_bits_clear_mac(np, reg, bits, limit, delay);
 140         if (err)
 141                 dev_err(np->device, PFX "%s: bits (%llx) of register %s "
 142                         "would not clear, val[%llx]\n",
 143                         np->dev->name, (unsigned long long) bits, reg_name,
 144                         (unsigned long long) nr64_mac(reg));
 145         return err;
 146 }
 147
 148 #define niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
 149 ({      BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
 150         __niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
 151 })
 152
 153 static int __niu_wait_bits_clear_ipp(struct niu *np, unsigned long reg,
 154                                      u64 bits, int limit, int delay)
 155 {
 156         while (--limit >= 0) {
 157                 u64 val = nr64_ipp(reg);
 158
 159                 if (!(val & bits))
 160                         break;
 161                 udelay(delay);
 162         }
 163         if (limit < 0)
 164                 return -ENODEV;
 165         return 0;
 166 }
 167
 168 static int __niu_set_and_wait_clear_ipp(struct niu *np, unsigned long reg,
 169                                         u64 bits, int limit, int delay,
 170                                         const char *reg_name)
 171 {
 172         int err;
 173         u64 val;
 174
 175         val = nr64_ipp(reg);
 176         val |= bits;
 177         nw64_ipp(reg, val);
 178
 179         err = __niu_wait_bits_clear_ipp(np, reg, bits, limit, delay);
 180         if (err)
 181                 dev_err(np->device, PFX "%s: bits (%llx) of register %s "
 182                         "would not clear, val[%llx]\n",
 183                         np->dev->name, (unsigned long long) bits, reg_name,
 184                         (unsigned long long) nr64_ipp(reg));
 185         return err;
 186 }
 187
 188 #define niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
 189 ({      BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
 190         __niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
 191 })
 192
 193 static int __niu_wait_bits_clear(struct niu *np, unsigned long reg,
 194                                  u64 bits, int limit, int delay)
 195 {
 196         while (--limit >= 0) {
 197                 u64 val = nr64(reg);
 198
 199                 if (!(val & bits))
 200                         break;
 201                 udelay(delay);
 202         }
 203         if (limit < 0)
 204                 return -ENODEV;
 205         return 0;
 206 }
 207
 208 #define niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY) \
 209 ({      BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
 210         __niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY); \
 211 })
 212
 213 static int __niu_set_and_wait_clear(struct niu *np, unsigned long reg,
 214                                     u64 bits, int limit, int delay,
 215                                     const char *reg_name)
 216 {
 217         int err;
 218
 219         nw64(reg, bits);
 220         err = __niu_wait_bits_clear(np, reg, bits, limit, delay);
 221         if (err)
 222                 dev_err(np->device, PFX "%s: bits (%llx) of register %s "
 223                         "would not clear, val[%llx]\n",
 224                         np->dev->name, (unsigned long long) bits, reg_name,
 225                         (unsigned long long) nr64(reg));
 226         return err;
 227 }
 228
 229 #define niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
 230 ({      BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
 231         __niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
 232 })
 233
 234 static void niu_ldg_rearm(struct niu *np, struct niu_ldg *lp, int on)
 235 {
 236         u64 val = (u64) lp->timer;
 237
 238         if (on)
 239                 val |= LDG_IMGMT_ARM;
 240
 241         nw64(LDG_IMGMT(lp->ldg_num), val);
 242 }
 243
 244 static int niu_ldn_irq_enable(struct niu *np, int ldn, int on)
 245 {
 246         unsigned long mask_reg, bits;
 247         u64 val;
 248
 249         if (ldn < 0 || ldn > LDN_MAX)
 250                 return -EINVAL;
 251
 252         if (ldn < 64) {
 253                 mask_reg = LD_IM0(ldn);
 254                 bits = LD_IM0_MASK;
 255         } else {
 256                 mask_reg = LD_IM1(ldn - 64);
 257                 bits = LD_IM1_MASK;
 258         }
 259
 260         val = nr64(mask_reg);
 261         if (on)
 262                 val &= ~bits;
 263         else
 264                 val |= bits;
 265         nw64(mask_reg, val);
 266
 267         return 0;
 268 }
 269
 270 static int niu_enable_ldn_in_ldg(struct niu *np, struct niu_ldg *lp, int on)
 271 {
 272         struct niu_parent *parent = np->parent;
 273         int i;
 274
 275         for (i = 0; i <= LDN_MAX; i++) {
 276                 int err;
 277
 278                 if (parent->ldg_map[i] != lp->ldg_num)
 279                         continue;
 280
 281                 err = niu_ldn_irq_enable(np, i, on);
 282                 if (err)
 283                         return err;
 284         }
 285         return 0;
 286 }
 287
 288 static int niu_enable_interrupts(struct niu *np, int on)
 289 {
 290         int i;
 291
 292         for (i = 0; i < np->num_ldg; i++) {
 293                 struct niu_ldg *lp = &np->ldg[i];
 294                 int err;
 295
 296                 err = niu_enable_ldn_in_ldg(np, lp, on);
 297                 if (err)
 298                         return err;
 299         }
 300         for (i = 0; i < np->num_ldg; i++)
 301                 niu_ldg_rearm(np, &np->ldg[i], on);
 302
 303         return 0;
 304 }
 305
 306 static u32 phy_encode(u32 type, int port)
 307 {
 308         return (type << (port * 2));
 309 }
 310
 311 static u32 phy_decode(u32 val, int port)
 312 {
 313         return (val >> (port * 2)) & PORT_TYPE_MASK;
 314 }
 315
 316 static int mdio_wait(struct niu *np)
 317 {
 318         int limit = 1000;
 319         u64 val;
 320
 321         while (--limit > 0) {
 322                 val = nr64(MIF_FRAME_OUTPUT);
 323                 if ((val >> MIF_FRAME_OUTPUT_TA_SHIFT) & 0x1)
 324                         return val & MIF_FRAME_OUTPUT_DATA;
 325
 326                 udelay(10);
 327         }
 328
 329         return -ENODEV;
 330 }
 331
 332 static int mdio_read(struct niu *np, int port, int dev, int reg)
 333 {
 334         int err;
 335
 336         nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
 337         err = mdio_wait(np);
 338         if (err < 0)
 339                 return err;
 340
 341         nw64(MIF_FRAME_OUTPUT, MDIO_READ_OP(port, dev));
 342         return mdio_wait(np);
 343 }
 344
 345 static int mdio_write(struct niu *np, int port, int dev, int reg, int data)
 346 {
 347         int err;
 348
 349         nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
 350         err = mdio_wait(np);
 351         if (err < 0)
 352                 return err;
 353
 354         nw64(MIF_FRAME_OUTPUT, MDIO_WRITE_OP(port, dev, data));
 355         err = mdio_wait(np);
 356         if (err < 0)
 357                 return err;
 358
 359         return 0;
 360 }
 361
 362 static int mii_read(struct niu *np, int port, int reg)
 363 {
 364         nw64(MIF_FRAME_OUTPUT, MII_READ_OP(port, reg));
 365         return mdio_wait(np);
 366 }
 367
 368 static int mii_write(struct niu *np, int port, int reg, int data)
 369 {
 370         int err;
 371
 372         nw64(MIF_FRAME_OUTPUT, MII_WRITE_OP(port, reg, data));
 373         err = mdio_wait(np);
 374         if (err < 0)
 375                 return err;
 376
 377         return 0;
 378 }
 379
 380 static int esr2_set_tx_cfg(struct niu *np, unsigned long channel, u32 val)
 381 {
 382         int err;
 383
 384         err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 385                          ESR2_TI_PLL_TX_CFG_L(channel),
 386                          val & 0xffff);
 387         if (!err)
 388                 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 389                                  ESR2_TI_PLL_TX_CFG_H(channel),
 390                                  val >> 16);
 391         return err;
 392 }
 393
 394 static int esr2_set_rx_cfg(struct niu *np, unsigned long channel, u32 val)
 395 {
 396         int err;
 397
 398         err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 399                          ESR2_TI_PLL_RX_CFG_L(channel),
 400                          val & 0xffff);
 401         if (!err)
 402                 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 403                                  ESR2_TI_PLL_RX_CFG_H(channel),
 404                                  val >> 16);
 405         return err;
 406 }
 407
 408 /* Mode is always 10G fiber.  */
 409 static int serdes_init_niu_10g_fiber(struct niu *np)
 410 {
 411         struct niu_link_config *lp = &np->link_config;
 412         u32 tx_cfg, rx_cfg;
 413         unsigned long i;
 414
 415         tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV);
 416         rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
 417                   PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
 418                   PLL_RX_CFG_EQ_LP_ADAPTIVE);
 419
 420         if (lp->loopback_mode == LOOPBACK_PHY) {
 421                 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
 422
 423                 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 424                            ESR2_TI_PLL_TEST_CFG_L, test_cfg);
 425
 426                 tx_cfg |= PLL_TX_CFG_ENTEST;
 427                 rx_cfg |= PLL_RX_CFG_ENTEST;
 428         }
 429
 430         /* Initialize all 4 lanes of the SERDES.  */
 431         for (i = 0; i < 4; i++) {
 432                 int err = esr2_set_tx_cfg(np, i, tx_cfg);
 433                 if (err)
 434                         return err;
 435         }
 436
 437         for (i = 0; i < 4; i++) {
 438                 int err = esr2_set_rx_cfg(np, i, rx_cfg);
 439                 if (err)
 440                         return err;
 441         }
 442
 443         return 0;
 444 }
 445
 446 static int serdes_init_niu_1g_serdes(struct niu *np)
 447 {
 448         struct niu_link_config *lp = &np->link_config;
 449         u16 pll_cfg, pll_sts;
 450         int max_retry = 100;
 451         u64 uninitialized_var(sig), mask, val;
 452         u32 tx_cfg, rx_cfg;
 453         unsigned long i;
 454         int err;
 455
 456         tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV |
 457                   PLL_TX_CFG_RATE_HALF);
 458         rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
 459                   PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
 460                   PLL_RX_CFG_RATE_HALF);
 461
 462         if (np->port == 0)
 463                 rx_cfg |= PLL_RX_CFG_EQ_LP_ADAPTIVE;
 464
 465         if (lp->loopback_mode == LOOPBACK_PHY) {
 466                 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
 467
 468                 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 469                            ESR2_TI_PLL_TEST_CFG_L, test_cfg);
 470
 471                 tx_cfg |= PLL_TX_CFG_ENTEST;
 472                 rx_cfg |= PLL_RX_CFG_ENTEST;
 473         }
 474
 475         /* Initialize PLL for 1G */
 476         pll_cfg = (PLL_CFG_ENPLL | PLL_CFG_MPY_8X);
 477
 478         err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 479                          ESR2_TI_PLL_CFG_L, pll_cfg);
 480         if (err) {
 481                 dev_err(np->device, PFX "NIU Port %d "
 482                         "serdes_init_niu_1g_serdes: "
 483                         "mdio write to ESR2_TI_PLL_CFG_L failed", np->port);
 484                 return err;
 485         }
 486
 487         pll_sts = PLL_CFG_ENPLL;
 488
 489         err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 490                          ESR2_TI_PLL_STS_L, pll_sts);
 491         if (err) {
 492                 dev_err(np->device, PFX "NIU Port %d "
 493                         "serdes_init_niu_1g_serdes: "
 494                         "mdio write to ESR2_TI_PLL_STS_L failed", np->port);
 495                 return err;
 496         }
 497
 498         udelay(200);
 499
 500         /* Initialize all 4 lanes of the SERDES.  */
 501         for (i = 0; i < 4; i++) {
 502                 err = esr2_set_tx_cfg(np, i, tx_cfg);
 503                 if (err)
 504                         return err;
 505         }
 506
 507         for (i = 0; i < 4; i++) {
 508                 err = esr2_set_rx_cfg(np, i, rx_cfg);
 509                 if (err)
 510                         return err;
 511         }
 512
 513         switch (np->port) {
 514         case 0:
 515                 val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0);
 516                 mask = val;
 517                 break;
 518
 519         case 1:
 520                 val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1);
 521                 mask = val;
 522                 break;
 523
 524         default:
 525                 return -EINVAL;
 526         }
 527
 528         while (max_retry--) {
 529                 sig = nr64(ESR_INT_SIGNALS);
 530                 if ((sig & mask) == val)
 531                         break;
 532
 533                 mdelay(500);
 534         }
 535
 536         if ((sig & mask) != val) {
 537                 dev_err(np->device, PFX "Port %u signal bits [%08x] are not "
 538                         "[%08x]\n", np->port, (int) (sig & mask), (int) val);
 539                 return -ENODEV;
 540         }
 541
 542         return 0;
 543 }
 544
 545 static int serdes_init_niu_10g_serdes(struct niu *np)
 546 {
 547         struct niu_link_config *lp = &np->link_config;
 548         u32 tx_cfg, rx_cfg, pll_cfg, pll_sts;
 549         int max_retry = 100;
 550         u64 uninitialized_var(sig), mask, val;
 551         unsigned long i;
 552         int err;
 553
 554         tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV);
 555         rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
 556                   PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
 557                   PLL_RX_CFG_EQ_LP_ADAPTIVE);
 558
 559         if (lp->loopback_mode == LOOPBACK_PHY) {
 560                 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
 561
 562                 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 563                            ESR2_TI_PLL_TEST_CFG_L, test_cfg);
 564
 565                 tx_cfg |= PLL_TX_CFG_ENTEST;
 566                 rx_cfg |= PLL_RX_CFG_ENTEST;
 567         }
 568
 569         /* Initialize PLL for 10G */
 570         pll_cfg = (PLL_CFG_ENPLL | PLL_CFG_MPY_10X);
 571
 572         err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 573                          ESR2_TI_PLL_CFG_L, pll_cfg & 0xffff);
 574         if (err) {
 575                 dev_err(np->device, PFX "NIU Port %d "
 576                         "serdes_init_niu_10g_serdes: "
 577                         "mdio write to ESR2_TI_PLL_CFG_L failed", np->port);
 578                 return err;
 579         }
 580
 581         pll_sts = PLL_CFG_ENPLL;
 582
 583         err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 584                          ESR2_TI_PLL_STS_L, pll_sts & 0xffff);
 585         if (err) {
 586                 dev_err(np->device, PFX "NIU Port %d "
 587                         "serdes_init_niu_10g_serdes: "
 588                         "mdio write to ESR2_TI_PLL_STS_L failed", np->port);
 589                 return err;
 590         }
 591
 592         udelay(200);
 593
 594         /* Initialize all 4 lanes of the SERDES.  */
 595         for (i = 0; i < 4; i++) {
 596                 err = esr2_set_tx_cfg(np, i, tx_cfg);
 597                 if (err)
 598                         return err;
 599         }
 600
 601         for (i = 0; i < 4; i++) {
 602                 err = esr2_set_rx_cfg(np, i, rx_cfg);
 603                 if (err)
 604                         return err;
 605         }
 606
 607         /* check if serdes is ready */
 608
 609         switch (np->port) {
 610         case 0:
 611                 mask = ESR_INT_SIGNALS_P0_BITS;
 612                 val = (ESR_INT_SRDY0_P0 |
 613                        ESR_INT_DET0_P0 |
 614                        ESR_INT_XSRDY_P0 |
 615                        ESR_INT_XDP_P0_CH3 |
 616                        ESR_INT_XDP_P0_CH2 |
 617                        ESR_INT_XDP_P0_CH1 |
 618                        ESR_INT_XDP_P0_CH0);
 619                 break;
 620
 621         case 1:
 622                 mask = ESR_INT_SIGNALS_P1_BITS;
 623                 val = (ESR_INT_SRDY0_P1 |
 624                        ESR_INT_DET0_P1 |
 625                        ESR_INT_XSRDY_P1 |
 626                        ESR_INT_XDP_P1_CH3 |
 627                        ESR_INT_XDP_P1_CH2 |
 628                        ESR_INT_XDP_P1_CH1 |
 629                        ESR_INT_XDP_P1_CH0);
 630                 break;
 631
 632         default:
 633                 return -EINVAL;
 634         }
 635
 636         while (max_retry--) {
 637                 sig = nr64(ESR_INT_SIGNALS);
 638                 if ((sig & mask) == val)
 639                         break;
 640
 641                 mdelay(500);
 642         }
 643
 644         if ((sig & mask) != val) {
 645                 pr_info(PFX "NIU Port %u signal bits [%08x] are not "
 646                         "[%08x] for 10G...trying 1G\n",
 647                         np->port, (int) (sig & mask), (int) val);
 648
 649                 /* 10G failed, try initializing at 1G */
 650                 err = serdes_init_niu_1g_serdes(np);
 651                 if (!err) {
 652                         np->flags &= ~NIU_FLAGS_10G;
 653                         np->mac_xcvr = MAC_XCVR_PCS;
 654                 }  else {
 655                         dev_err(np->device, PFX "Port %u 10G/1G SERDES "
 656                                 "Link Failed \n", np->port);
 657                         return -ENODEV;
 658                 }
 659         }
 660         return 0;
 661 }
 662
 663 static int esr_read_rxtx_ctrl(struct niu *np, unsigned long chan, u32 *val)
 664 {
 665         int err;
 666
 667         err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, ESR_RXTX_CTRL_L(chan));
 668         if (err >= 0) {
 669                 *val = (err & 0xffff);
 670                 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
 671                                 ESR_RXTX_CTRL_H(chan));
 672                 if (err >= 0)
 673                         *val |= ((err & 0xffff) << 16);
 674                 err = 0;
 675         }
 676         return err;
 677 }
 678
 679 static int esr_read_glue0(struct niu *np, unsigned long chan, u32 *val)
 680 {
 681         int err;
 682
 683         err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
 684                         ESR_GLUE_CTRL0_L(chan));
 685         if (err >= 0) {
 686                 *val = (err & 0xffff);
 687                 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
 688                                 ESR_GLUE_CTRL0_H(chan));
 689                 if (err >= 0) {
 690                         *val |= ((err & 0xffff) << 16);
 691                         err = 0;
 692                 }
 693         }
 694         return err;
 695 }
 696
 697 static int esr_read_reset(struct niu *np, u32 *val)
 698 {
 699         int err;
 700
 701         err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
 702                         ESR_RXTX_RESET_CTRL_L);
 703         if (err >= 0) {
 704                 *val = (err & 0xffff);
 705                 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
 706                                 ESR_RXTX_RESET_CTRL_H);
 707                 if (err >= 0) {
 708                         *val |= ((err & 0xffff) << 16);
 709                         err = 0;
 710                 }
 711         }
 712         return err;
 713 }
 714
 715 static int esr_write_rxtx_ctrl(struct niu *np, unsigned long chan, u32 val)
 716 {
 717         int err;
 718
 719         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 720                          ESR_RXTX_CTRL_L(chan), val & 0xffff);
 721         if (!err)
 722                 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 723                                  ESR_RXTX_CTRL_H(chan), (val >> 16));
 724         return err;
 725 }
 726
 727 static int esr_write_glue0(struct niu *np, unsigned long chan, u32 val)
 728 {
 729         int err;
 730
 731         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 732                         ESR_GLUE_CTRL0_L(chan), val & 0xffff);
 733         if (!err)
 734                 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 735                                  ESR_GLUE_CTRL0_H(chan), (val >> 16));
 736         return err;
 737 }
 738
 739 static int esr_reset(struct niu *np)
 740 {
 741         u32 uninitialized_var(reset);
 742         int err;
 743
 744         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 745                          ESR_RXTX_RESET_CTRL_L, 0x0000);
 746         if (err)
 747                 return err;
 748         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 749                          ESR_RXTX_RESET_CTRL_H, 0xffff);
 750         if (err)
 751                 return err;
 752         udelay(200);
 753
 754         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 755                          ESR_RXTX_RESET_CTRL_L, 0xffff);
 756         if (err)
 757                 return err;
 758         udelay(200);
 759
 760         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 761                          ESR_RXTX_RESET_CTRL_H, 0x0000);
 762         if (err)
 763                 return err;
 764         udelay(200);
 765
 766         err = esr_read_reset(np, &reset);
 767         if (err)
 768                 return err;
 769         if (reset != 0) {
 770                 dev_err(np->device, PFX "Port %u ESR_RESET "
 771                         "did not clear [%08x]\n",
 772                         np->port, reset);
 773                 return -ENODEV;
 774         }
 775
 776         return 0;
 777 }
 778
 779 static int serdes_init_10g(struct niu *np)
 780 {
 781         struct niu_link_config *lp = &np->link_config;
 782         unsigned long ctrl_reg, test_cfg_reg, i;
 783         u64 ctrl_val, test_cfg_val, sig, mask, val;
 784         int err;
 785
 786         switch (np->port) {
 787         case 0:
 788                 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
 789                 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
 790                 break;
 791         case 1:
 792                 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
 793                 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
 794                 break;
 795
 796         default:
 797                 return -EINVAL;
 798         }
 799         ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
 800                     ENET_SERDES_CTRL_SDET_1 |
 801                     ENET_SERDES_CTRL_SDET_2 |
 802                     ENET_SERDES_CTRL_SDET_3 |
 803                     (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
 804                     (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
 805                     (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
 806                     (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
 807                     (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
 808                     (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
 809                     (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
 810                     (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
 811         test_cfg_val = 0;
 812
 813         if (lp->loopback_mode == LOOPBACK_PHY) {
 814                 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
 815                                   ENET_SERDES_TEST_MD_0_SHIFT) |
 816                                  (ENET_TEST_MD_PAD_LOOPBACK <<
 817                                   ENET_SERDES_TEST_MD_1_SHIFT) |
 818                                  (ENET_TEST_MD_PAD_LOOPBACK <<
 819                                   ENET_SERDES_TEST_MD_2_SHIFT) |
 820                                  (ENET_TEST_MD_PAD_LOOPBACK <<
 821                                   ENET_SERDES_TEST_MD_3_SHIFT));
 822         }
 823
 824         nw64(ctrl_reg, ctrl_val);
 825         nw64(test_cfg_reg, test_cfg_val);
 826
 827         /* Initialize all 4 lanes of the SERDES.  */
 828         for (i = 0; i < 4; i++) {
 829                 u32 rxtx_ctrl, glue0;
 830
 831                 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
 832                 if (err)
 833                         return err;
 834                 err = esr_read_glue0(np, i, &glue0);
 835                 if (err)
 836                         return err;
 837
 838                 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
 839                 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
 840                               (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
 841
 842                 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
 843                            ESR_GLUE_CTRL0_THCNT |
 844                            ESR_GLUE_CTRL0_BLTIME);
 845                 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
 846                           (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
 847                           (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
 848                           (BLTIME_300_CYCLES <<
 849                            ESR_GLUE_CTRL0_BLTIME_SHIFT));
 850
 851                 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
 852                 if (err)
 853                         return err;
 854                 err = esr_write_glue0(np, i, glue0);
 855                 if (err)
 856                         return err;
 857         }
 858
 859         err = esr_reset(np);
 860         if (err)
 861                 return err;
 862
 863         sig = nr64(ESR_INT_SIGNALS);
 864         switch (np->port) {
 865         case 0:
 866                 mask = ESR_INT_SIGNALS_P0_BITS;
 867                 val = (ESR_INT_SRDY0_P0 |
 868                        ESR_INT_DET0_P0 |
 869                        ESR_INT_XSRDY_P0 |
 870                        ESR_INT_XDP_P0_CH3 |
 871                        ESR_INT_XDP_P0_CH2 |
 872                        ESR_INT_XDP_P0_CH1 |
 873                        ESR_INT_XDP_P0_CH0);
 874                 break;
 875
 876         case 1:
 877                 mask = ESR_INT_SIGNALS_P1_BITS;
 878                 val = (ESR_INT_SRDY0_P1 |
 879                        ESR_INT_DET0_P1 |
 880                        ESR_INT_XSRDY_P1 |
 881                        ESR_INT_XDP_P1_CH3 |
 882                        ESR_INT_XDP_P1_CH2 |
 883                        ESR_INT_XDP_P1_CH1 |
 884                        ESR_INT_XDP_P1_CH0);
 885                 break;
 886
 887         default:
 888                 return -EINVAL;
 889         }
 890
 891         if ((sig & mask) != val) {
 892                 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
 893                         np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
 894                         return 0;
 895                 }
 896                 dev_err(np->device, PFX "Port %u signal bits [%08x] are not "
 897                         "[%08x]\n", np->port, (int) (sig & mask), (int) val);
 898                 return -ENODEV;
 899         }
 900         if (np->flags & NIU_FLAGS_HOTPLUG_PHY)
 901                 np->flags |= NIU_FLAGS_HOTPLUG_PHY_PRESENT;
 902         return 0;
 903 }
 904
 905 static int serdes_init_1g(struct niu *np)
 906 {
 907         u64 val;
 908
 909         val = nr64(ENET_SERDES_1_PLL_CFG);
 910         val &= ~ENET_SERDES_PLL_FBDIV2;
 911         switch (np->port) {
 912         case 0:
 913                 val |= ENET_SERDES_PLL_HRATE0;
 914                 break;
 915         case 1:
 916                 val |= ENET_SERDES_PLL_HRATE1;
 917                 break;
 918         case 2:
 919                 val |= ENET_SERDES_PLL_HRATE2;
 920                 break;
 921         case 3:
 922                 val |= ENET_SERDES_PLL_HRATE3;
 923                 break;
 924         default:
 925                 return -EINVAL;
 926         }
 927         nw64(ENET_SERDES_1_PLL_CFG, val);
 928
 929         return 0;
 930 }
 931
 932 static int serdes_init_1g_serdes(struct niu *np)
 933 {
 934         struct niu_link_config *lp = &np->link_config;
 935         unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i;
 936         u64 ctrl_val, test_cfg_val, sig, mask, val;
 937         int err;
 938         u64 reset_val, val_rd;
 939
 940         val = ENET_SERDES_PLL_HRATE0 | ENET_SERDES_PLL_HRATE1 |
 941                 ENET_SERDES_PLL_HRATE2 | ENET_SERDES_PLL_HRATE3 |
 942                 ENET_SERDES_PLL_FBDIV0;
 943         switch (np->port) {
 944         case 0:
 945                 reset_val =  ENET_SERDES_RESET_0;
 946                 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
 947                 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
 948                 pll_cfg = ENET_SERDES_0_PLL_CFG;
 949                 break;
 950         case 1:
 951                 reset_val =  ENET_SERDES_RESET_1;
 952                 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
 953                 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
 954                 pll_cfg = ENET_SERDES_1_PLL_CFG;
 955                 break;
 956
 957         default:
 958                 return -EINVAL;
 959         }
 960         ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
 961                     ENET_SERDES_CTRL_SDET_1 |
 962                     ENET_SERDES_CTRL_SDET_2 |
 963                     ENET_SERDES_CTRL_SDET_3 |
 964                     (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
 965                     (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
 966                     (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
 967                     (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
 968                     (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
 969                     (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
 970                     (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
 971                     (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
 972         test_cfg_val = 0;
 973
 974         if (lp->loopback_mode == LOOPBACK_PHY) {
 975                 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
 976                                   ENET_SERDES_TEST_MD_0_SHIFT) |
 977                                  (ENET_TEST_MD_PAD_LOOPBACK <<
 978                                   ENET_SERDES_TEST_MD_1_SHIFT) |
 979                                  (ENET_TEST_MD_PAD_LOOPBACK <<
 980                                   ENET_SERDES_TEST_MD_2_SHIFT) |
 981                                  (ENET_TEST_MD_PAD_LOOPBACK <<
 982                                   ENET_SERDES_TEST_MD_3_SHIFT));
 983         }
 984
 985         nw64(ENET_SERDES_RESET, reset_val);
 986         mdelay(20);
 987         val_rd = nr64(ENET_SERDES_RESET);
 988         val_rd &= ~reset_val;
 989         nw64(pll_cfg, val);
 990         nw64(ctrl_reg, ctrl_val);
 991         nw64(test_cfg_reg, test_cfg_val);
 992         nw64(ENET_SERDES_RESET, val_rd);
 993         mdelay(2000);
 994
 995         /* Initialize all 4 lanes of the SERDES.  */
 996         for (i = 0; i < 4; i++) {
 997                 u32 rxtx_ctrl, glue0;
 998
 999                 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
1000                 if (err)
1001                         return err;
1002                 err = esr_read_glue0(np, i, &glue0);
1003                 if (err)
1004                         return err;
1005
1006                 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
1007                 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
1008                               (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
1009
1010                 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
1011                            ESR_GLUE_CTRL0_THCNT |
1012                            ESR_GLUE_CTRL0_BLTIME);
1013                 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
1014                           (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
1015                           (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
1016                           (BLTIME_300_CYCLES <<
1017                            ESR_GLUE_CTRL0_BLTIME_SHIFT));
1018
1019                 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
1020                 if (err)
1021                         return err;
1022                 err = esr_write_glue0(np, i, glue0);
1023                 if (err)
1024                         return err;
1025         }
1026
1027
1028         sig = nr64(ESR_INT_SIGNALS);
1029         switch (np->port) {
1030         case 0:
1031                 val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0);
1032                 mask = val;
1033                 break;
1034
1035         case 1:
1036                 val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1);
1037                 mask = val;
1038                 break;
1039
1040         default:
1041                 return -EINVAL;
1042         }
1043
1044         if ((sig & mask) != val) {
1045                 dev_err(np->device, PFX "Port %u signal bits [%08x] are not "
1046                         "[%08x]\n", np->port, (int) (sig & mask), (int) val);
1047                 return -ENODEV;
1048         }
1049
1050         return 0;
1051 }
1052
1053 static int link_status_1g_serdes(struct niu *np, int *link_up_p)
1054 {
1055         struct niu_link_config *lp = &np->link_config;
1056         int link_up;
1057         u64 val;
1058         u16 current_speed;
1059         unsigned long flags;
1060         u8 current_duplex;
1061
1062         link_up = 0;
1063         current_speed = SPEED_INVALID;
1064         current_duplex = DUPLEX_INVALID;
1065
1066         spin_lock_irqsave(&np->lock, flags);
1067
1068         val = nr64_pcs(PCS_MII_STAT);
1069
1070         if (val & PCS_MII_STAT_LINK_STATUS) {
1071                 link_up = 1;
1072                 current_speed = SPEED_1000;
1073                 current_duplex = DUPLEX_FULL;
1074         }
1075
1076         lp->active_speed = current_speed;
1077         lp->active_duplex = current_duplex;
1078         spin_unlock_irqrestore(&np->lock, flags);
1079
1080         *link_up_p = link_up;
1081         return 0;
1082 }
1083
1084 static int link_status_10g_serdes(struct niu *np, int *link_up_p)
1085 {
1086         unsigned long flags;
1087         struct niu_link_config *lp = &np->link_config;
1088         int link_up = 0;
1089         int link_ok = 1;
1090         u64 val, val2;
1091         u16 current_speed;
1092         u8 current_duplex;
1093
1094         if (!(np->flags & NIU_FLAGS_10G))
1095                 return link_status_1g_serdes(np, link_up_p);
1096
1097         current_speed = SPEED_INVALID;
1098         current_duplex = DUPLEX_INVALID;
1099         spin_lock_irqsave(&np->lock, flags);
1100
1101         val = nr64_xpcs(XPCS_STATUS(0));
1102         val2 = nr64_mac(XMAC_INTER2);
1103         if (val2 & 0x01000000)
1104                 link_ok = 0;
1105
1106         if ((val & 0x1000ULL) && link_ok) {
1107                 link_up = 1;
1108                 current_speed = SPEED_10000;
1109                 current_duplex = DUPLEX_FULL;
1110         }
1111         lp->active_speed = current_speed;
1112         lp->active_duplex = current_duplex;
1113         spin_unlock_irqrestore(&np->lock, flags);
1114         *link_up_p = link_up;
1115         return 0;
1116 }
1117
1118 static int link_status_mii(struct niu *np, int *link_up_p)
1119 {
1120         struct niu_link_config *lp = &np->link_config;
1121         int err;
1122         int bmsr, advert, ctrl1000, stat1000, lpa, bmcr, estatus;
1123         int supported, advertising, active_speed, active_duplex;
1124
1125         err = mii_read(np, np->phy_addr, MII_BMCR);
1126         if (unlikely(err < 0))
1127                 return err;
1128         bmcr = err;
1129
1130         err = mii_read(np, np->phy_addr, MII_BMSR);
1131         if (unlikely(err < 0))
1132                 return err;
1133         bmsr = err;
1134
1135         err = mii_read(np, np->phy_addr, MII_ADVERTISE);
1136         if (unlikely(err < 0))
1137                 return err;
1138         advert = err;
1139
1140         err = mii_read(np, np->phy_addr, MII_LPA);
1141         if (unlikely(err < 0))
1142                 return err;
1143         lpa = err;
1144
1145         if (likely(bmsr & BMSR_ESTATEN)) {
1146                 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1147                 if (unlikely(err < 0))
1148                         return err;
1149                 estatus = err;
1150
1151                 err = mii_read(np, np->phy_addr, MII_CTRL1000);
1152                 if (unlikely(err < 0))
1153                         return err;
1154                 ctrl1000 = err;
1155
1156                 err = mii_read(np, np->phy_addr, MII_STAT1000);
1157                 if (unlikely(err < 0))
1158                         return err;
1159                 stat1000 = err;
1160         } else
1161                 estatus = ctrl1000 = stat1000 = 0;
1162
1163         supported = 0;
1164         if (bmsr & BMSR_ANEGCAPABLE)
1165                 supported |= SUPPORTED_Autoneg;
1166         if (bmsr & BMSR_10HALF)
1167                 supported |= SUPPORTED_10baseT_Half;
1168         if (bmsr & BMSR_10FULL)
1169                 supported |= SUPPORTED_10baseT_Full;
1170         if (bmsr & BMSR_100HALF)
1171                 supported |= SUPPORTED_100baseT_Half;
1172         if (bmsr & BMSR_100FULL)
1173                 supported |= SUPPORTED_100baseT_Full;
1174         if (estatus & ESTATUS_1000_THALF)
1175                 supported |= SUPPORTED_1000baseT_Half;
1176         if (estatus & ESTATUS_1000_TFULL)
1177                 supported |= SUPPORTED_1000baseT_Full;
1178         lp->supported = supported;
1179
1180         advertising = 0;
1181         if (advert & ADVERTISE_10HALF)
1182                 advertising |= ADVERTISED_10baseT_Half;
1183         if (advert & ADVERTISE_10FULL)
1184                 advertising |= ADVERTISED_10baseT_Full;
1185         if (advert & ADVERTISE_100HALF)
1186                 advertising |= ADVERTISED_100baseT_Half;
1187         if (advert & ADVERTISE_100FULL)
1188                 advertising |= ADVERTISED_100baseT_Full;
1189         if (ctrl1000 & ADVERTISE_1000HALF)
1190                 advertising |= ADVERTISED_1000baseT_Half;
1191         if (ctrl1000 & ADVERTISE_1000FULL)
1192                 advertising |= ADVERTISED_1000baseT_Full;
1193
1194         if (bmcr & BMCR_ANENABLE) {
1195                 int neg, neg1000;
1196
1197                 lp->active_autoneg = 1;
1198                 advertising |= ADVERTISED_Autoneg;
1199
1200                 neg = advert & lpa;
1201                 neg1000 = (ctrl1000 << 2) & stat1000;
1202
1203                 if (neg1000 & (LPA_1000FULL | LPA_1000HALF))
1204                         active_speed = SPEED_1000;
1205                 else if (neg & LPA_100)
1206                         active_speed = SPEED_100;
1207                 else if (neg & (LPA_10HALF | LPA_10FULL))
1208                         active_speed = SPEED_10;
1209                 else
1210                         active_speed = SPEED_INVALID;
1211
1212                 if ((neg1000 & LPA_1000FULL) || (neg & LPA_DUPLEX))
1213                         active_duplex = DUPLEX_FULL;
1214                 else if (active_speed != SPEED_INVALID)
1215                         active_duplex = DUPLEX_HALF;
1216                 else
1217                         active_duplex = DUPLEX_INVALID;
1218         } else {
1219                 lp->active_autoneg = 0;
1220
1221                 if ((bmcr & BMCR_SPEED1000) && !(bmcr & BMCR_SPEED100))
1222                         active_speed = SPEED_1000;
1223                 else if (bmcr & BMCR_SPEED100)
1224                         active_speed = SPEED_100;
1225                 else
1226                         active_speed = SPEED_10;
1227
1228                 if (bmcr & BMCR_FULLDPLX)
1229                         active_duplex = DUPLEX_FULL;
1230                 else
1231                         active_duplex = DUPLEX_HALF;
1232         }
1233
1234         lp->active_advertising = advertising;
1235         lp->active_speed = active_speed;
1236         lp->active_duplex = active_duplex;
1237         *link_up_p = !!(bmsr & BMSR_LSTATUS);
1238
1239         return 0;
1240 }
1241
1242 static int link_status_1g_rgmii(struct niu *np, int *link_up_p)
1243 {
1244         struct niu_link_config *lp = &np->link_config;
1245         u16 current_speed, bmsr;
1246         unsigned long flags;
1247         u8 current_duplex;
1248         int err, link_up;
1249
1250         link_up = 0;
1251         current_speed = SPEED_INVALID;
1252         current_duplex = DUPLEX_INVALID;
1253
1254         spin_lock_irqsave(&np->lock, flags);
1255
1256         err = -EINVAL;
1257
1258         err = mii_read(np, np->phy_addr, MII_BMSR);
1259         if (err < 0)
1260                 goto out;
1261
1262         bmsr = err;
1263         if (bmsr & BMSR_LSTATUS) {
1264                 u16 adv, lpa, common, estat;
1265
1266                 err = mii_read(np, np->phy_addr, MII_ADVERTISE);
1267                 if (err < 0)
1268                         goto out;
1269                 adv = err;
1270
1271                 err = mii_read(np, np->phy_addr, MII_LPA);
1272                 if (err < 0)
1273                         goto out;
1274                 lpa = err;
1275
1276                 common = adv & lpa;
1277
1278                 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1279                 if (err < 0)
1280                         goto out;
1281                 estat = err;
1282                 link_up = 1;
1283                 current_speed = SPEED_1000;
1284                 current_duplex = DUPLEX_FULL;
1285
1286         }
1287         lp->active_speed = current_speed;
1288         lp->active_duplex = current_duplex;
1289         err = 0;
1290
1291 out:
1292         spin_unlock_irqrestore(&np->lock, flags);
1293
1294         *link_up_p = link_up;
1295         return err;
1296 }
1297
1298 static int link_status_1g(struct niu *np, int *link_up_p)
1299 {
1300         struct niu_link_config *lp = &np->link_config;
1301         unsigned long flags;
1302         int err;
1303
1304         spin_lock_irqsave(&np->lock, flags);
1305
1306         err = link_status_mii(np, link_up_p);
1307         lp->supported |= SUPPORTED_TP;
1308         lp->active_advertising |= ADVERTISED_TP;
1309
1310         spin_unlock_irqrestore(&np->lock, flags);
1311         return err;
1312 }
1313
1314 static int bcm8704_reset(struct niu *np)
1315 {
1316         int err, limit;
1317
1318         err = mdio_read(np, np->phy_addr,
1319                         BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
1320         if (err < 0)
1321                 return err;
1322         err |= BMCR_RESET;
1323         err = mdio_write(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1324                          MII_BMCR, err);
1325         if (err)
1326                 return err;
1327
1328         limit = 1000;
1329         while (--limit >= 0) {
1330                 err = mdio_read(np, np->phy_addr,
1331                                 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
1332                 if (err < 0)
1333                         return err;
1334                 if (!(err & BMCR_RESET))
1335                         break;
1336         }
1337         if (limit < 0) {
1338                 dev_err(np->device, PFX "Port %u PHY will not reset "
1339                         "(bmcr=%04x)\n", np->port, (err & 0xffff));
1340                 return -ENODEV;
1341         }
1342         return 0;
1343 }
1344
1345 /* When written, certain PHY registers need to be read back twice
1346  * in order for the bits to settle properly.
1347  */
1348 static int bcm8704_user_dev3_readback(struct niu *np, int reg)
1349 {
1350         int err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
1351         if (err < 0)
1352                 return err;
1353         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
1354         if (err < 0)
1355                 return err;
1356         return 0;
1357 }
1358
1359 static int bcm8706_init_user_dev3(struct niu *np)
1360 {
1361         int err;
1362
1363
1364         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1365                         BCM8704_USER_OPT_DIGITAL_CTRL);
1366         if (err < 0)
1367                 return err;
1368         err &= ~USER_ODIG_CTRL_GPIOS;
1369         err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT);
1370         err |=  USER_ODIG_CTRL_RESV2;
1371         err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1372                          BCM8704_USER_OPT_DIGITAL_CTRL, err);
1373         if (err)
1374                 return err;
1375
1376         mdelay(1000);
1377
1378         return 0;
1379 }
1380
1381 static int bcm8704_init_user_dev3(struct niu *np)
1382 {
1383         int err;
1384
1385         err = mdio_write(np, np->phy_addr,
1386                          BCM8704_USER_DEV3_ADDR, BCM8704_USER_CONTROL,
1387                          (USER_CONTROL_OPTXRST_LVL |
1388                           USER_CONTROL_OPBIASFLT_LVL |
1389                           USER_CONTROL_OBTMPFLT_LVL |
1390                           USER_CONTROL_OPPRFLT_LVL |
1391                           USER_CONTROL_OPTXFLT_LVL |
1392                           USER_CONTROL_OPRXLOS_LVL |
1393                           USER_CONTROL_OPRXFLT_LVL |
1394                           USER_CONTROL_OPTXON_LVL |
1395                           (0x3f << USER_CONTROL_RES1_SHIFT)));
1396         if (err)
1397                 return err;
1398
1399         err = mdio_write(np, np->phy_addr,
1400                          BCM8704_USER_DEV3_ADDR, BCM8704_USER_PMD_TX_CONTROL,
1401                          (USER_PMD_TX_CTL_XFP_CLKEN |
1402                           (1 << USER_PMD_TX_CTL_TX_DAC_TXD_SH) |
1403                           (2 << USER_PMD_TX_CTL_TX_DAC_TXCK_SH) |
1404                           USER_PMD_TX_CTL_TSCK_LPWREN));
1405         if (err)
1406                 return err;
1407
1408         err = bcm8704_user_dev3_readback(np, BCM8704_USER_CONTROL);
1409         if (err)
1410                 return err;
1411         err = bcm8704_user_dev3_readback(np, BCM8704_USER_PMD_TX_CONTROL);
1412         if (err)
1413                 return err;
1414
1415         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1416                         BCM8704_USER_OPT_DIGITAL_CTRL);
1417         if (err < 0)
1418                 return err;
1419         err &= ~USER_ODIG_CTRL_GPIOS;
1420         err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT);
1421         err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1422                          BCM8704_USER_OPT_DIGITAL_CTRL, err);
1423         if (err)
1424                 return err;
1425
1426         mdelay(1000);
1427
1428         return 0;
1429 }
1430
1431 static int mrvl88x2011_act_led(struct niu *np, int val)
1432 {
1433         int     err;
1434
1435         err  = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1436                 MRVL88X2011_LED_8_TO_11_CTL);
1437         if (err < 0)
1438                 return err;
1439
1440         err &= ~MRVL88X2011_LED(MRVL88X2011_LED_ACT,MRVL88X2011_LED_CTL_MASK);
1441         err |=  MRVL88X2011_LED(MRVL88X2011_LED_ACT,val);
1442
1443         return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1444                           MRVL88X2011_LED_8_TO_11_CTL, err);
1445 }
1446
1447 static int mrvl88x2011_led_blink_rate(struct niu *np, int rate)
1448 {
1449         int     err;
1450
1451         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1452                         MRVL88X2011_LED_BLINK_CTL);
1453         if (err >= 0) {
1454                 err &= ~MRVL88X2011_LED_BLKRATE_MASK;
1455                 err |= (rate << 4);
1456
1457                 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1458                                  MRVL88X2011_LED_BLINK_CTL, err);
1459         }
1460
1461         return err;
1462 }
1463
1464 static int xcvr_init_10g_mrvl88x2011(struct niu *np)
1465 {
1466         int     err;
1467
1468         /* Set LED functions */
1469         err = mrvl88x2011_led_blink_rate(np, MRVL88X2011_LED_BLKRATE_134MS);
1470         if (err)
1471                 return err;
1472
1473         /* led activity */
1474         err = mrvl88x2011_act_led(np, MRVL88X2011_LED_CTL_OFF);
1475         if (err)
1476                 return err;
1477
1478         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1479                         MRVL88X2011_GENERAL_CTL);
1480         if (err < 0)
1481                 return err;
1482
1483         err |= MRVL88X2011_ENA_XFPREFCLK;
1484
1485         err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1486                          MRVL88X2011_GENERAL_CTL, err);
1487         if (err < 0)
1488                 return err;
1489
1490         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1491                         MRVL88X2011_PMA_PMD_CTL_1);
1492         if (err < 0)
1493                 return err;
1494
1495         if (np->link_config.loopback_mode == LOOPBACK_MAC)
1496                 err |= MRVL88X2011_LOOPBACK;
1497         else
1498                 err &= ~MRVL88X2011_LOOPBACK;
1499
1500         err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1501                          MRVL88X2011_PMA_PMD_CTL_1, err);
1502         if (err < 0)
1503                 return err;
1504
1505         /* Enable PMD  */
1506         return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1507                           MRVL88X2011_10G_PMD_TX_DIS, MRVL88X2011_ENA_PMDTX);
1508 }
1509
1510
1511 static int xcvr_diag_bcm870x(struct niu *np)
1512 {
1513         u16 analog_stat0, tx_alarm_status;
1514         int err = 0;
1515
1516 #if 1
1517         err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
1518                         MII_STAT1000);
1519         if (err < 0)
1520                 return err;
1521         pr_info(PFX "Port %u PMA_PMD(MII_STAT1000) [%04x]\n",
1522                 np->port, err);
1523
1524         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 0x20);
1525         if (err < 0)
1526                 return err;
1527         pr_info(PFX "Port %u USER_DEV3(0x20) [%04x]\n",
1528                 np->port, err);
1529
1530         err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1531                         MII_NWAYTEST);
1532         if (err < 0)
1533                 return err;
1534         pr_info(PFX "Port %u PHYXS(MII_NWAYTEST) [%04x]\n",
1535                 np->port, err);
1536 #endif
1537
1538         /* XXX dig this out it might not be so useful XXX */
1539         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1540                         BCM8704_USER_ANALOG_STATUS0);
1541         if (err < 0)
1542                 return err;
1543         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1544                         BCM8704_USER_ANALOG_STATUS0);
1545         if (err < 0)
1546                 return err;
1547         analog_stat0 = err;
1548
1549         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1550                         BCM8704_USER_TX_ALARM_STATUS);
1551         if (err < 0)
1552                 return err;
1553         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1554                         BCM8704_USER_TX_ALARM_STATUS);
1555         if (err < 0)
1556                 return err;
1557         tx_alarm_status = err;
1558
1559         if (analog_stat0 != 0x03fc) {
1560                 if ((analog_stat0 == 0x43bc) && (tx_alarm_status != 0)) {
1561                         pr_info(PFX "Port %u cable not connected "
1562                                 "or bad cable.\n", np->port);
1563                 } else if (analog_stat0 == 0x639c) {
1564                         pr_info(PFX "Port %u optical module is bad "
1565                                 "or missing.\n", np->port);
1566                 }
1567         }
1568
1569         return 0;
1570 }
1571
1572 static int xcvr_10g_set_lb_bcm870x(struct niu *np)
1573 {
1574         struct niu_link_config *lp = &np->link_config;
1575         int err;
1576
1577         err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1578                         MII_BMCR);
1579         if (err < 0)
1580                 return err;
1581
1582         err &= ~BMCR_LOOPBACK;
1583
1584         if (lp->loopback_mode == LOOPBACK_MAC)
1585                 err |= BMCR_LOOPBACK;
1586
1587         err = mdio_write(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1588                          MII_BMCR, err);
1589         if (err)
1590                 return err;
1591
1592         return 0;
1593 }
1594
1595 static int xcvr_init_10g_bcm8706(struct niu *np)
1596 {
1597         int err = 0;
1598         u64 val;
1599
1600         if ((np->flags & NIU_FLAGS_HOTPLUG_PHY) &&
1601             (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) == 0)
1602                         return err;
1603
1604         val = nr64_mac(XMAC_CONFIG);
1605         val &= ~XMAC_CONFIG_LED_POLARITY;
1606         val |= XMAC_CONFIG_FORCE_LED_ON;
1607         nw64_mac(XMAC_CONFIG, val);
1608
1609         val = nr64(MIF_CONFIG);
1610         val |= MIF_CONFIG_INDIRECT_MODE;
1611         nw64(MIF_CONFIG, val);
1612
1613         err = bcm8704_reset(np);
1614         if (err)
1615                 return err;
1616
1617         err = xcvr_10g_set_lb_bcm870x(np);
1618         if (err)
1619                 return err;
1620
1621         err = bcm8706_init_user_dev3(np);
1622         if (err)
1623                 return err;
1624
1625         err = xcvr_diag_bcm870x(np);
1626         if (err)
1627                 return err;
1628
1629         return 0;
1630 }
1631
1632 static int xcvr_init_10g_bcm8704(struct niu *np)
1633 {
1634         int err;
1635
1636         err = bcm8704_reset(np);
1637         if (err)
1638                 return err;
1639
1640         err = bcm8704_init_user_dev3(np);
1641         if (err)
1642                 return err;
1643
1644         err = xcvr_10g_set_lb_bcm870x(np);
1645         if (err)
1646                 return err;
1647
1648         err =  xcvr_diag_bcm870x(np);
1649         if (err)
1650                 return err;
1651
1652         return 0;
1653 }
1654
1655 static int xcvr_init_10g(struct niu *np)
1656 {
1657         int phy_id, err;
1658         u64 val;
1659
1660         val = nr64_mac(XMAC_CONFIG);
1661         val &= ~XMAC_CONFIG_LED_POLARITY;
1662         val |= XMAC_CONFIG_FORCE_LED_ON;
1663         nw64_mac(XMAC_CONFIG, val);
1664
1665         /* XXX shared resource, lock parent XXX */
1666         val = nr64(MIF_CONFIG);
1667         val |= MIF_CONFIG_INDIRECT_MODE;
1668         nw64(MIF_CONFIG, val);
1669
1670         phy_id = phy_decode(np->parent->port_phy, np->port);
1671         phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port];
1672
1673         /* handle different phy types */
1674         switch (phy_id & NIU_PHY_ID_MASK) {
1675         case NIU_PHY_ID_MRVL88X2011:
1676                 err = xcvr_init_10g_mrvl88x2011(np);
1677                 break;
1678
1679         default: /* bcom 8704 */
1680                 err = xcvr_init_10g_bcm8704(np);
1681                 break;
1682         }
1683
1684         return 0;
1685 }
1686
1687 static int mii_reset(struct niu *np)
1688 {
1689         int limit, err;
1690
1691         err = mii_write(np, np->phy_addr, MII_BMCR, BMCR_RESET);
1692         if (err)
1693                 return err;
1694
1695         limit = 1000;
1696         while (--limit >= 0) {
1697                 udelay(500);
1698                 err = mii_read(np, np->phy_addr, MII_BMCR);
1699                 if (err < 0)
1700                         return err;
1701                 if (!(err & BMCR_RESET))
1702                         break;
1703         }
1704         if (limit < 0) {
1705                 dev_err(np->device, PFX "Port %u MII would not reset, "
1706                         "bmcr[%04x]\n", np->port, err);
1707                 return -ENODEV;
1708         }
1709
1710         return 0;
1711 }
1712
1713 static int xcvr_init_1g_rgmii(struct niu *np)
1714 {
1715         int err;
1716         u64 val;
1717         u16 bmcr, bmsr, estat;
1718
1719         val = nr64(MIF_CONFIG);
1720         val &= ~MIF_CONFIG_INDIRECT_MODE;
1721         nw64(MIF_CONFIG, val);
1722
1723         err = mii_reset(np);
1724         if (err)
1725                 return err;
1726
1727         err = mii_read(np, np->phy_addr, MII_BMSR);
1728         if (err < 0)
1729                 return err;
1730         bmsr = err;
1731
1732         estat = 0;
1733         if (bmsr & BMSR_ESTATEN) {
1734                 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1735                 if (err < 0)
1736                         return err;
1737                 estat = err;
1738         }
1739
1740         bmcr = 0;
1741         err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1742         if (err)
1743                 return err;
1744
1745         if (bmsr & BMSR_ESTATEN) {
1746                 u16 ctrl1000 = 0;
1747
1748                 if (estat & ESTATUS_1000_TFULL)
1749                         ctrl1000 |= ADVERTISE_1000FULL;
1750                 err = mii_write(np, np->phy_addr, MII_CTRL1000, ctrl1000);
1751                 if (err)
1752                         return err;
1753         }
1754
1755         bmcr = (BMCR_SPEED1000 | BMCR_FULLDPLX);
1756
1757         err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1758         if (err)
1759                 return err;
1760
1761         err = mii_read(np, np->phy_addr, MII_BMCR);
1762         if (err < 0)
1763                 return err;
1764         bmcr = mii_read(np, np->phy_addr, MII_BMCR);
1765
1766         err = mii_read(np, np->phy_addr, MII_BMSR);
1767         if (err < 0)
1768                 return err;
1769
1770         return 0;
1771 }
1772
1773 static int mii_init_common(struct niu *np)
1774 {
1775         struct niu_link_config *lp = &np->link_config;
1776         u16 bmcr, bmsr, adv, estat;
1777         int err;
1778
1779         err = mii_reset(np);
1780         if (err)
1781                 return err;
1782
1783         err = mii_read(np, np->phy_addr, MII_BMSR);
1784         if (err < 0)
1785                 return err;
1786         bmsr = err;
1787
1788         estat = 0;
1789         if (bmsr & BMSR_ESTATEN) {
1790                 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1791                 if (err < 0)
1792                         return err;
1793                 estat = err;
1794         }
1795
1796         bmcr = 0;
1797         err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1798         if (err)
1799                 return err;
1800
1801         if (lp->loopback_mode == LOOPBACK_MAC) {
1802                 bmcr |= BMCR_LOOPBACK;
1803                 if (lp->active_speed == SPEED_1000)
1804                         bmcr |= BMCR_SPEED1000;
1805                 if (lp->active_duplex == DUPLEX_FULL)
1806                         bmcr |= BMCR_FULLDPLX;
1807         }
1808
1809         if (lp->loopback_mode == LOOPBACK_PHY) {
1810                 u16 aux;
1811
1812                 aux = (BCM5464R_AUX_CTL_EXT_LB |
1813                        BCM5464R_AUX_CTL_WRITE_1);
1814                 err = mii_write(np, np->phy_addr, BCM5464R_AUX_CTL, aux);
1815                 if (err)
1816                         return err;
1817         }
1818
1819         if (lp->autoneg) {
1820                 u16 ctrl1000;
1821
1822                 adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1823                 if ((bmsr & BMSR_10HALF) &&
1824                         (lp->advertising & ADVERTISED_10baseT_Half))
1825                         adv |= ADVERTISE_10HALF;
1826                 if ((bmsr & BMSR_10FULL) &&
1827                         (lp->advertising & ADVERTISED_10baseT_Full))
1828                         adv |= ADVERTISE_10FULL;
1829                 if ((bmsr & BMSR_100HALF) &&
1830                         (lp->advertising & ADVERTISED_100baseT_Half))
1831                         adv |= ADVERTISE_100HALF;
1832                 if ((bmsr & BMSR_100FULL) &&
1833                         (lp->advertising & ADVERTISED_100baseT_Full))
1834                         adv |= ADVERTISE_100FULL;
1835                 err = mii_write(np, np->phy_addr, MII_ADVERTISE, adv);
1836                 if (err)
1837                         return err;
1838
1839                 if (likely(bmsr & BMSR_ESTATEN)) {
1840                         ctrl1000 = 0;
1841                         if ((estat & ESTATUS_1000_THALF) &&
1842                                 (lp->advertising & ADVERTISED_1000baseT_Half))
1843                                 ctrl1000 |= ADVERTISE_1000HALF;
1844                         if ((estat & ESTATUS_1000_TFULL) &&
1845                                 (lp->advertising & ADVERTISED_1000baseT_Full))
1846                                 ctrl1000 |= ADVERTISE_1000FULL;
1847                         err = mii_write(np, np->phy_addr,
1848                                         MII_CTRL1000, ctrl1000);
1849                         if (err)
1850                                 return err;
1851                 }
1852
1853                 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1854         } else {
1855                 /* !lp->autoneg */
1856                 int fulldpx;
1857
1858                 if (lp->duplex == DUPLEX_FULL) {
1859                         bmcr |= BMCR_FULLDPLX;
1860                         fulldpx = 1;
1861                 } else if (lp->duplex == DUPLEX_HALF)
1862                         fulldpx = 0;
1863                 else
1864                         return -EINVAL;
1865
1866                 if (lp->speed == SPEED_1000) {
1867                         /* if X-full requested while not supported, or
1868                            X-half requested while not supported... */
1869                         if ((fulldpx && !(estat & ESTATUS_1000_TFULL)) ||
1870                                 (!fulldpx && !(estat & ESTATUS_1000_THALF)))
1871                                 return -EINVAL;
1872                         bmcr |= BMCR_SPEED1000;
1873                 } else if (lp->speed == SPEED_100) {
1874                         if ((fulldpx && !(bmsr & BMSR_100FULL)) ||
1875                                 (!fulldpx && !(bmsr & BMSR_100HALF)))
1876                                 return -EINVAL;
1877                         bmcr |= BMCR_SPEED100;
1878                 } else if (lp->speed == SPEED_10) {
1879                         if ((fulldpx && !(bmsr & BMSR_10FULL)) ||
1880                                 (!fulldpx && !(bmsr & BMSR_10HALF)))
1881                                 return -EINVAL;
1882                 } else
1883                         return -EINVAL;
1884         }
1885
1886         err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1887         if (err)
1888                 return err;
1889
1890 #if 0
1891         err = mii_read(np, np->phy_addr, MII_BMCR);
1892         if (err < 0)
1893                 return err;
1894         bmcr = err;
1895
1896         err = mii_read(np, np->phy_addr, MII_BMSR);
1897         if (err < 0)
1898                 return err;
1899         bmsr = err;
1900
1901         pr_info(PFX "Port %u after MII init bmcr[%04x] bmsr[%04x]\n",
1902                 np->port, bmcr, bmsr);
1903 #endif
1904
1905         return 0;
1906 }
1907
1908 static int xcvr_init_1g(struct niu *np)
1909 {
1910         u64 val;
1911
1912         /* XXX shared resource, lock parent XXX */
1913         val = nr64(MIF_CONFIG);
1914         val &= ~MIF_CONFIG_INDIRECT_MODE;
1915         nw64(MIF_CONFIG, val);
1916
1917         return mii_init_common(np);
1918 }
1919
1920 static int niu_xcvr_init(struct niu *np)
1921 {
1922         const struct niu_phy_ops *ops = np->phy_ops;
1923         int err;
1924
1925         err = 0;
1926         if (ops->xcvr_init)
1927                 err = ops->xcvr_init(np);
1928
1929         return err;
1930 }
1931
1932 static int niu_serdes_init(struct niu *np)
1933 {
1934         const struct niu_phy_ops *ops = np->phy_ops;
1935         int err;
1936
1937         err = 0;
1938         if (ops->serdes_init)
1939                 err = ops->serdes_init(np);
1940
1941         return err;
1942 }
1943
1944 static void niu_init_xif(struct niu *);
1945 static void niu_handle_led(struct niu *, int status);
1946
1947 static int niu_link_status_common(struct niu *np, int link_up)
1948 {
1949         struct niu_link_config *lp = &np->link_config;
1950         struct net_device *dev = np->dev;
1951         unsigned long flags;
1952
1953         if (!netif_carrier_ok(dev) && link_up) {
1954                 niuinfo(LINK, "%s: Link is up at %s, %s duplex\n",
1955                        dev->name,
1956                        (lp->active_speed == SPEED_10000 ?
1957                         "10Gb/sec" :
1958                         (lp->active_speed == SPEED_1000 ?
1959                          "1Gb/sec" :
1960                          (lp->active_speed == SPEED_100 ?
1961                           "100Mbit/sec" : "10Mbit/sec"))),
1962                        (lp->active_duplex == DUPLEX_FULL ?
1963                         "full" : "half"));
1964
1965                 spin_lock_irqsave(&np->lock, flags);
1966                 niu_init_xif(np);
1967                 niu_handle_led(np, 1);
1968                 spin_unlock_irqrestore(&np->lock, flags);
1969
1970                 netif_carrier_on(dev);
1971         } else if (netif_carrier_ok(dev) && !link_up) {
1972                 niuwarn(LINK, "%s: Link is down\n", dev->name);
1973                 spin_lock_irqsave(&np->lock, flags);
1974                 niu_handle_led(np, 0);
1975                 spin_unlock_irqrestore(&np->lock, flags);
1976                 netif_carrier_off(dev);
1977         }
1978
1979         return 0;
1980 }
1981
1982 static int link_status_10g_mrvl(struct niu *np, int *link_up_p)
1983 {
1984         int err, link_up, pma_status, pcs_status;
1985
1986         link_up = 0;
1987
1988         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1989                         MRVL88X2011_10G_PMD_STATUS_2);
1990         if (err < 0)
1991                 goto out;
1992
1993         /* Check PMA/PMD Register: 1.0001.2 == 1 */
1994         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1995                         MRVL88X2011_PMA_PMD_STATUS_1);
1996         if (err < 0)
1997                 goto out;
1998
1999         pma_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0);
2000
2001         /* Check PMC Register : 3.0001.2 == 1: read twice */
2002         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
2003                         MRVL88X2011_PMA_PMD_STATUS_1);
2004         if (err < 0)
2005                 goto out;
2006
2007         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
2008                         MRVL88X2011_PMA_PMD_STATUS_1);
2009         if (err < 0)
2010                 goto out;
2011
2012         pcs_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0);
2013
2014         /* Check XGXS Register : 4.0018.[0-3,12] */
2015         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV4_ADDR,
2016                         MRVL88X2011_10G_XGXS_LANE_STAT);
2017         if (err < 0)
2018                 goto out;
2019
2020         if (err == (PHYXS_XGXS_LANE_STAT_ALINGED | PHYXS_XGXS_LANE_STAT_LANE3 |
2021                     PHYXS_XGXS_LANE_STAT_LANE2 | PHYXS_XGXS_LANE_STAT_LANE1 |
2022                     PHYXS_XGXS_LANE_STAT_LANE0 | PHYXS_XGXS_LANE_STAT_MAGIC |
2023                     0x800))
2024                 link_up = (pma_status && pcs_status) ? 1 : 0;
2025
2026         np->link_config.active_speed = SPEED_10000;
2027         np->link_config.active_duplex = DUPLEX_FULL;
2028         err = 0;
2029 out:
2030         mrvl88x2011_act_led(np, (link_up ?
2031                                  MRVL88X2011_LED_CTL_PCS_ACT :
2032                                  MRVL88X2011_LED_CTL_OFF));
2033
2034         *link_up_p = link_up;
2035         return err;
2036 }
2037
2038 static int link_status_10g_bcm8706(struct niu *np, int *link_up_p)
2039 {
2040         int err, link_up;
2041         link_up = 0;
2042
2043         err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
2044                         BCM8704_PMD_RCV_SIGDET);
2045         if (err < 0)
2046                 goto out;
2047         if (!(err & PMD_RCV_SIGDET_GLOBAL)) {
2048                 err = 0;
2049                 goto out;
2050         }
2051
2052         err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
2053                         BCM8704_PCS_10G_R_STATUS);
2054         if (err < 0)
2055                 goto out;
2056
2057         if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) {
2058                 err = 0;
2059                 goto out;
2060         }
2061
2062         err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
2063                         BCM8704_PHYXS_XGXS_LANE_STAT);
2064         if (err < 0)
2065                 goto out;
2066         if (err != (PHYXS_XGXS_LANE_STAT_ALINGED |
2067                     PHYXS_XGXS_LANE_STAT_MAGIC |
2068                     PHYXS_XGXS_LANE_STAT_PATTEST |
2069                     PHYXS_XGXS_LANE_STAT_LANE3 |
2070                     PHYXS_XGXS_LANE_STAT_LANE2 |
2071                     PHYXS_XGXS_LANE_STAT_LANE1 |
2072                     PHYXS_XGXS_LANE_STAT_LANE0)) {
2073                 err = 0;
2074                 np->link_config.active_speed = SPEED_INVALID;
2075                 np->link_config.active_duplex = DUPLEX_INVALID;
2076                 goto out;
2077         }
2078
2079         link_up = 1;
2080         np->link_config.active_speed = SPEED_10000;
2081         np->link_config.active_duplex = DUPLEX_FULL;
2082         err = 0;
2083
2084 out:
2085         *link_up_p = link_up;
2086         if (np->flags & NIU_FLAGS_HOTPLUG_PHY)
2087                 err = 0;
2088         return err;
2089 }
2090
2091 static int link_status_10g_bcom(struct niu *np, int *link_up_p)
2092 {
2093         int err, link_up;
2094
2095         link_up = 0;
2096
2097         err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
2098                         BCM8704_PMD_RCV_SIGDET);
2099         if (err < 0)
2100                 goto out;
2101         if (!(err & PMD_RCV_SIGDET_GLOBAL)) {
2102                 err = 0;
2103                 goto out;
2104         }
2105
2106         err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
2107                         BCM8704_PCS_10G_R_STATUS);
2108         if (err < 0)
2109                 goto out;
2110         if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) {
2111                 err = 0;
2112                 goto out;
2113         }
2114
2115         err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
2116                         BCM8704_PHYXS_XGXS_LANE_STAT);
2117         if (err < 0)
2118                 goto out;
2119
2120         if (err != (PHYXS_XGXS_LANE_STAT_ALINGED |
2121                     PHYXS_XGXS_LANE_STAT_MAGIC |
2122                     PHYXS_XGXS_LANE_STAT_LANE3 |
2123                     PHYXS_XGXS_LANE_STAT_LANE2 |
2124                     PHYXS_XGXS_LANE_STAT_LANE1 |
2125                     PHYXS_XGXS_LANE_STAT_LANE0)) {
2126                 err = 0;
2127                 goto out;
2128         }
2129
2130         link_up = 1;
2131         np->link_config.active_speed = SPEED_10000;
2132         np->link_config.active_duplex = DUPLEX_FULL;
2133         err = 0;
2134
2135 out:
2136         *link_up_p = link_up;
2137         return err;
2138 }
2139
2140 static int link_status_10g(struct niu *np, int *link_up_p)
2141 {
2142         unsigned long flags;
2143         int err = -EINVAL;
2144
2145         spin_lock_irqsave(&np->lock, flags);
2146
2147         if (np->link_config.loopback_mode == LOOPBACK_DISABLED) {
2148                 int phy_id;
2149
2150                 phy_id = phy_decode(np->parent->port_phy, np->port);
2151                 phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port];
2152
2153                 /* handle different phy types */
2154                 switch (phy_id & NIU_PHY_ID_MASK) {
2155                 case NIU_PHY_ID_MRVL88X2011:
2156                         err = link_status_10g_mrvl(np, link_up_p);
2157                         break;
2158
2159                 default: /* bcom 8704 */
2160                         err = link_status_10g_bcom(np, link_up_p);
2161                         break;
2162                 }
2163         }
2164
2165         spin_unlock_irqrestore(&np->lock, flags);
2166
2167         return err;
2168 }
2169
2170 static int niu_10g_phy_present(struct niu *np)
2171 {
2172         u64 sig, mask, val;
2173
2174         sig = nr64(ESR_INT_SIGNALS);
2175         switch (np->port) {
2176         case 0:
2177                 mask = ESR_INT_SIGNALS_P0_BITS;
2178                 val = (ESR_INT_SRDY0_P0 |
2179                        ESR_INT_DET0_P0 |
2180                        ESR_INT_XSRDY_P0 |
2181                        ESR_INT_XDP_P0_CH3 |
2182                        ESR_INT_XDP_P0_CH2 |
2183                        ESR_INT_XDP_P0_CH1 |
2184                        ESR_INT_XDP_P0_CH0);
2185                 break;
2186
2187         case 1:
2188                 mask = ESR_INT_SIGNALS_P1_BITS;
2189                 val = (ESR_INT_SRDY0_P1 |
2190                        ESR_INT_DET0_P1 |
2191                        ESR_INT_XSRDY_P1 |
2192                        ESR_INT_XDP_P1_CH3 |
2193                        ESR_INT_XDP_P1_CH2 |
2194                        ESR_INT_XDP_P1_CH1 |
2195                        ESR_INT_XDP_P1_CH0);
2196                 break;
2197
2198         default:
2199                 return 0;
2200         }
2201
2202         if ((sig & mask) != val)
2203                 return 0;
2204         return 1;
2205 }
2206
2207 static int link_status_10g_hotplug(struct niu *np, int *link_up_p)
2208 {
2209         unsigned long flags;
2210         int err = 0;
2211         int phy_present;
2212         int phy_present_prev;
2213
2214         spin_lock_irqsave(&np->lock, flags);
2215
2216         if (np->link_config.loopback_mode == LOOPBACK_DISABLED) {
2217                 phy_present_prev = (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) ?
2218                         1 : 0;
2219                 phy_present = niu_10g_phy_present(np);
2220                 if (phy_present != phy_present_prev) {
2221                         /* state change */
2222                         if (phy_present) {
2223                                 np->flags |= NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2224                                 if (np->phy_ops->xcvr_init)
2225                                         err = np->phy_ops->xcvr_init(np);
2226                                 if (err) {
2227                                         /* debounce */
2228                                         np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2229                                 }
2230                         } else {
2231                                 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2232                                 *link_up_p = 0;
2233                                 niuwarn(LINK, "%s: Hotplug PHY Removed\n",
2234                                         np->dev->name);
2235                         }
2236                 }
2237                 if (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT)
2238                         err = link_status_10g_bcm8706(np, link_up_p);
2239         }
2240
2241         spin_unlock_irqrestore(&np->lock, flags);
2242
2243         return err;
2244 }
2245
2246 static int niu_link_status(struct niu *np, int *link_up_p)
2247 {
2248         const struct niu_phy_ops *ops = np->phy_ops;
2249         int err;
2250
2251         err = 0;
2252         if (ops->link_status)
2253                 err = ops->link_status(np, link_up_p);
2254
2255         return err;
2256 }
2257
2258 static void niu_timer(unsigned long __opaque)
2259 {
2260         struct niu *np = (struct niu *) __opaque;
2261         unsigned long off;
2262         int err, link_up;
2263
2264         err = niu_link_status(np, &link_up);
2265         if (!err)
2266                 niu_link_status_common(np, link_up);
2267
2268         if (netif_carrier_ok(np->dev))
2269                 off = 5 * HZ;
2270         else
2271                 off = 1 * HZ;
2272         np->timer.expires = jiffies + off;
2273
2274         add_timer(&np->timer);
2275 }
2276
2277 static const struct niu_phy_ops phy_ops_10g_serdes = {
2278         .serdes_init            = serdes_init_10g_serdes,
2279         .link_status            = link_status_10g_serdes,
2280 };
2281
2282 static const struct niu_phy_ops phy_ops_10g_serdes_niu = {
2283         .serdes_init            = serdes_init_niu_10g_serdes,
2284         .link_status            = link_status_10g_serdes,
2285 };
2286
2287 static const struct niu_phy_ops phy_ops_1g_serdes_niu = {
2288         .serdes_init            = serdes_init_niu_1g_serdes,
2289         .link_status            = link_status_1g_serdes,
2290 };
2291
2292 static const struct niu_phy_ops phy_ops_1g_rgmii = {
2293         .xcvr_init              = xcvr_init_1g_rgmii,
2294         .link_status            = link_status_1g_rgmii,
2295 };
2296
2297 static const struct niu_phy_ops phy_ops_10g_fiber_niu = {
2298         .serdes_init            = serdes_init_niu_10g_fiber,
2299         .xcvr_init              = xcvr_init_10g,
2300         .link_status            = link_status_10g,
2301 };
2302
2303 static const struct niu_phy_ops phy_ops_10g_fiber = {
2304         .serdes_init            = serdes_init_10g,
2305         .xcvr_init              = xcvr_init_10g,
2306         .link_status            = link_status_10g,
2307 };
2308
2309 static const struct niu_phy_ops phy_ops_10g_fiber_hotplug = {
2310         .serdes_init            = serdes_init_10g,
2311         .xcvr_init              = xcvr_init_10g_bcm8706,
2312         .link_status            = link_status_10g_hotplug,
2313 };
2314
2315 static const struct niu_phy_ops phy_ops_10g_copper = {
2316         .serdes_init            = serdes_init_10g,
2317         .link_status            = link_status_10g, /* XXX */
2318 };
2319
2320 static const struct niu_phy_ops phy_ops_1g_fiber = {
2321         .serdes_init            = serdes_init_1g,
2322         .xcvr_init              = xcvr_init_1g,
2323         .link_status            = link_status_1g,
2324 };
2325
2326 static const struct niu_phy_ops phy_ops_1g_copper = {
2327         .xcvr_init              = xcvr_init_1g,
2328         .link_status            = link_status_1g,
2329 };
2330
2331 struct niu_phy_template {
2332         const struct niu_phy_ops        *ops;
2333         u32                             phy_addr_base;
2334 };
2335
2336 static const struct niu_phy_template phy_template_niu_10g_fiber = {
2337         .ops            = &phy_ops_10g_fiber_niu,
2338         .phy_addr_base  = 16,
2339 };
2340
2341 static const struct niu_phy_template phy_template_niu_10g_serdes = {
2342         .ops            = &phy_ops_10g_serdes_niu,
2343         .phy_addr_base  = 0,
2344 };
2345
2346 static const struct niu_phy_template phy_template_niu_1g_serdes = {
2347         .ops            = &phy_ops_1g_serdes_niu,
2348         .phy_addr_base  = 0,
2349 };
2350
2351 static const struct niu_phy_template phy_template_10g_fiber = {
2352         .ops            = &phy_ops_10g_fiber,
2353         .phy_addr_base  = 8,
2354 };
2355
2356 static const struct niu_phy_template phy_template_10g_fiber_hotplug = {
2357         .ops            = &phy_ops_10g_fiber_hotplug,
2358         .phy_addr_base  = 8,
2359 };
2360
2361 static const struct niu_phy_template phy_template_10g_copper = {
2362         .ops            = &phy_ops_10g_copper,
2363         .phy_addr_base  = 10,
2364 };
2365
2366 static const struct niu_phy_template phy_template_1g_fiber = {
2367         .ops            = &phy_ops_1g_fiber,
2368         .phy_addr_base  = 0,
2369 };
2370
2371 static const struct niu_phy_template phy_template_1g_copper = {
2372         .ops            = &phy_ops_1g_copper,
2373         .phy_addr_base  = 0,
2374 };
2375
2376 static const struct niu_phy_template phy_template_1g_rgmii = {
2377         .ops            = &phy_ops_1g_rgmii,
2378         .phy_addr_base  = 0,
2379 };
2380
2381 static const struct niu_phy_template phy_template_10g_serdes = {
2382         .ops            = &phy_ops_10g_serdes,
2383         .phy_addr_base  = 0,
2384 };
2385
2386 static int niu_atca_port_num[4] = {
2387         0, 0,  11, 10
2388 };
2389
2390 static int serdes_init_10g_serdes(struct niu *np)
2391 {
2392         struct niu_link_config *lp = &np->link_config;
2393         unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i;
2394         u64 ctrl_val, test_cfg_val, sig, mask, val;
2395         u64 reset_val;
2396
2397         switch (np->port) {
2398         case 0:
2399                 reset_val =  ENET_SERDES_RESET_0;
2400                 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
2401                 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
2402                 pll_cfg = ENET_SERDES_0_PLL_CFG;
2403                 break;
2404         case 1:
2405                 reset_val =  ENET_SERDES_RESET_1;
2406                 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
2407                 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
2408                 pll_cfg = ENET_SERDES_1_PLL_CFG;
2409                 break;
2410
2411         default:
2412                 return -EINVAL;
2413         }
2414         ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
2415                     ENET_SERDES_CTRL_SDET_1 |
2416                     ENET_SERDES_CTRL_SDET_2 |
2417                     ENET_SERDES_CTRL_SDET_3 |
2418                     (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
2419                     (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
2420                     (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
2421                     (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
2422                     (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
2423                     (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
2424                     (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
2425                     (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
2426         test_cfg_val = 0;
2427
2428         if (lp->loopback_mode == LOOPBACK_PHY) {
2429                 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
2430                                   ENET_SERDES_TEST_MD_0_SHIFT) |
2431                                  (ENET_TEST_MD_PAD_LOOPBACK <<
2432                                   ENET_SERDES_TEST_MD_1_SHIFT) |
2433                                  (ENET_TEST_MD_PAD_LOOPBACK <<
2434                                   ENET_SERDES_TEST_MD_2_SHIFT) |
2435                                  (ENET_TEST_MD_PAD_LOOPBACK <<
2436                                   ENET_SERDES_TEST_MD_3_SHIFT));
2437         }
2438
2439         esr_reset(np);
2440         nw64(pll_cfg, ENET_SERDES_PLL_FBDIV2);
2441         nw64(ctrl_reg, ctrl_val);
2442         nw64(test_cfg_reg, test_cfg_val);
2443
2444         /* Initialize all 4 lanes of the SERDES.  */
2445         for (i = 0; i < 4; i++) {
2446                 u32 rxtx_ctrl, glue0;
2447                 int err;
2448
2449                 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
2450                 if (err)
2451                         return err;
2452                 err = esr_read_glue0(np, i, &glue0);
2453                 if (err)
2454                         return err;
2455
2456                 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
2457                 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
2458                               (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
2459
2460                 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
2461                            ESR_GLUE_CTRL0_THCNT |
2462                            ESR_GLUE_CTRL0_BLTIME);
2463                 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
2464                           (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
2465                           (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
2466                           (BLTIME_300_CYCLES <<
2467                            ESR_GLUE_CTRL0_BLTIME_SHIFT));
2468
2469                 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
2470                 if (err)
2471                         return err;
2472                 err = esr_write_glue0(np, i, glue0);
2473                 if (err)
2474                         return err;
2475         }
2476
2477
2478         sig = nr64(ESR_INT_SIGNALS);
2479         switch (np->port) {
2480         case 0:
2481                 mask = ESR_INT_SIGNALS_P0_BITS;
2482                 val = (ESR_INT_SRDY0_P0 |
2483                        ESR_INT_DET0_P0 |
2484                        ESR_INT_XSRDY_P0 |
2485                        ESR_INT_XDP_P0_CH3 |
2486                        ESR_INT_XDP_P0_CH2 |
2487                        ESR_INT_XDP_P0_CH1 |
2488                        ESR_INT_XDP_P0_CH0);
2489                 break;
2490
2491         case 1:
2492                 mask = ESR_INT_SIGNALS_P1_BITS;
2493                 val = (ESR_INT_SRDY0_P1 |
2494                        ESR_INT_DET0_P1 |
2495                        ESR_INT_XSRDY_P1 |
2496                        ESR_INT_XDP_P1_CH3 |
2497                        ESR_INT_XDP_P1_CH2 |
2498                        ESR_INT_XDP_P1_CH1 |
2499                        ESR_INT_XDP_P1_CH0);
2500                 break;
2501
2502         default:
2503                 return -EINVAL;
2504         }
2505
2506         if ((sig & mask) != val) {
2507                 int err;
2508                 err = serdes_init_1g_serdes(np);
2509                 if (!err) {
2510                         np->flags &= ~NIU_FLAGS_10G;
2511                         np->mac_xcvr = MAC_XCVR_PCS;
2512                 }  else {
2513                         dev_err(np->device, PFX "Port %u 10G/1G SERDES Link Failed \n",
2514                          np->port);
2515                         return -ENODEV;
2516                 }
2517         }
2518
2519         return 0;
2520 }
2521
2522 static int niu_determine_phy_disposition(struct niu *np)
2523 {
2524         struct niu_parent *parent = np->parent;
2525         u8 plat_type = parent->plat_type;
2526         const struct niu_phy_template *tp;
2527         u32 phy_addr_off = 0;
2528
2529         if (plat_type == PLAT_TYPE_NIU) {
2530                 switch (np->flags &
2531                         (NIU_FLAGS_10G |
2532                          NIU_FLAGS_FIBER |
2533                          NIU_FLAGS_XCVR_SERDES)) {
2534                 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
2535                         /* 10G Serdes */
2536                         tp = &phy_template_niu_10g_serdes;
2537                         break;
2538                 case NIU_FLAGS_XCVR_SERDES:
2539                         /* 1G Serdes */
2540                         tp = &phy_template_niu_1g_serdes;
2541                         break;
2542                 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
2543                         /* 10G Fiber */
2544                 default:
2545                         tp = &phy_template_niu_10g_fiber;
2546                         phy_addr_off += np->port;
2547                         break;
2548                 }
2549         } else {
2550                 switch (np->flags &
2551                         (NIU_FLAGS_10G |
2552                          NIU_FLAGS_FIBER |
2553                          NIU_FLAGS_XCVR_SERDES)) {
2554                 case 0:
2555                         /* 1G copper */
2556                         tp = &phy_template_1g_copper;
2557                         if (plat_type == PLAT_TYPE_VF_P0)
2558                                 phy_addr_off = 10;
2559                         else if (plat_type == PLAT_TYPE_VF_P1)
2560                                 phy_addr_off = 26;
2561
2562                         phy_addr_off += (np->port ^ 0x3);
2563                         break;
2564
2565                 case NIU_FLAGS_10G:
2566                         /* 10G copper */
2567                         tp = &phy_template_10g_copper;
2568                         break;
2569
2570                 case NIU_FLAGS_FIBER:
2571                         /* 1G fiber */
2572                         tp = &phy_template_1g_fiber;
2573                         break;
2574
2575                 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
2576                         /* 10G fiber */
2577                         tp = &phy_template_10g_fiber;
2578                         if (plat_type == PLAT_TYPE_VF_P0 ||
2579                             plat_type == PLAT_TYPE_VF_P1)
2580                                 phy_addr_off = 8;
2581                         phy_addr_off += np->port;
2582                         if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
2583                                 tp = &phy_template_10g_fiber_hotplug;
2584                                 if (np->port == 0)
2585                                         phy_addr_off = 8;
2586                                 if (np->port == 1)
2587                                         phy_addr_off = 12;
2588                         }
2589                         break;
2590
2591                 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
2592                 case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER:
2593                 case NIU_FLAGS_XCVR_SERDES:
2594                         switch(np->port) {
2595                         case 0:
2596                         case 1:
2597                                 tp = &phy_template_10g_serdes;
2598                                 break;
2599                         case 2:
2600                         case 3:
2601                                 tp = &phy_template_1g_rgmii;
2602                                 break;
2603                         default:
2604                                 return -EINVAL;
2605                                 break;
2606                         }
2607                         phy_addr_off = niu_atca_port_num[np->port];
2608                         break;
2609
2610                 default:
2611                         return -EINVAL;
2612                 }
2613         }
2614
2615         np->phy_ops = tp->ops;
2616         np->phy_addr = tp->phy_addr_base + phy_addr_off;
2617
2618         return 0;
2619 }
2620
2621 static int niu_init_link(struct niu *np)
2622 {
2623         struct niu_parent *parent = np->parent;
2624         int err, ignore;
2625
2626         if (parent->plat_type == PLAT_TYPE_NIU) {
2627                 err = niu_xcvr_init(np);
2628                 if (err)
2629                         return err;
2630                 msleep(200);
2631         }
2632         err = niu_serdes_init(np);
2633         if (err)
2634                 return err;
2635         msleep(200);
2636         err = niu_xcvr_init(np);
2637         if (!err)
2638                 niu_link_status(np, &ignore);
2639         return 0;
2640 }
2641
2642 static void niu_set_primary_mac(struct niu *np, unsigned char *addr)
2643 {
2644         u16 reg0 = addr[4] << 8 | addr[5];
2645         u16 reg1 = addr[2] << 8 | addr[3];
2646         u16 reg2 = addr[0] << 8 | addr[1];
2647
2648         if (np->flags & NIU_FLAGS_XMAC) {
2649                 nw64_mac(XMAC_ADDR0, reg0);
2650                 nw64_mac(XMAC_ADDR1, reg1);
2651                 nw64_mac(XMAC_ADDR2, reg2);
2652         } else {
2653                 nw64_mac(BMAC_ADDR0, reg0);
2654                 nw64_mac(BMAC_ADDR1, reg1);
2655                 nw64_mac(BMAC_ADDR2, reg2);
2656         }
2657 }
2658
2659 static int niu_num_alt_addr(struct niu *np)
2660 {
2661         if (np->flags & NIU_FLAGS_XMAC)
2662                 return XMAC_NUM_ALT_ADDR;
2663         else
2664                 return BMAC_NUM_ALT_ADDR;
2665 }
2666
2667 static int niu_set_alt_mac(struct niu *np, int index, unsigned char *addr)
2668 {
2669         u16 reg0 = addr[4] << 8 | addr[5];
2670         u16 reg1 = addr[2] << 8 | addr[3];
2671         u16 reg2 = addr[0] << 8 | addr[1];
2672
2673         if (index >= niu_num_alt_addr(np))
2674                 return -EINVAL;
2675
2676         if (np->flags & NIU_FLAGS_XMAC) {
2677                 nw64_mac(XMAC_ALT_ADDR0(index), reg0);
2678                 nw64_mac(XMAC_ALT_ADDR1(index), reg1);
2679                 nw64_mac(XMAC_ALT_ADDR2(index), reg2);
2680         } else {
2681                 nw64_mac(BMAC_ALT_ADDR0(index), reg0);
2682                 nw64_mac(BMAC_ALT_ADDR1(index), reg1);
2683                 nw64_mac(BMAC_ALT_ADDR2(index), reg2);
2684         }
2685
2686         return 0;
2687 }
2688
2689 static int niu_enable_alt_mac(struct niu *np, int index, int on)
2690 {
2691         unsigned long reg;
2692         u64 val, mask;
2693
2694         if (index >= niu_num_alt_addr(np))
2695                 return -EINVAL;
2696
2697         if (np->flags & NIU_FLAGS_XMAC) {
2698                 reg = XMAC_ADDR_CMPEN;
2699                 mask = 1 << index;
2700         } else {
2701                 reg = BMAC_ADDR_CMPEN;
2702                 mask = 1 << (index + 1);
2703         }
2704
2705         val = nr64_mac(reg);
2706         if (on)
2707                 val |= mask;
2708         else
2709                 val &= ~mask;
2710         nw64_mac(reg, val);
2711
2712         return 0;
2713 }
2714
2715 static void __set_rdc_table_num_hw(struct niu *np, unsigned long reg,
2716                                    int num, int mac_pref)
2717 {
2718         u64 val = nr64_mac(reg);
2719         val &= ~(HOST_INFO_MACRDCTBLN | HOST_INFO_MPR);
2720         val |= num;
2721         if (mac_pref)
2722                 val |= HOST_INFO_MPR;
2723         nw64_mac(reg, val);
2724 }
2725
2726 static int __set_rdc_table_num(struct niu *np,
2727                                int xmac_index, int bmac_index,
2728                                int rdc_table_num, int mac_pref)
2729 {
2730         unsigned long reg;
2731
2732         if (rdc_table_num & ~HOST_INFO_MACRDCTBLN)
2733                 return -EINVAL;
2734         if (np->flags & NIU_FLAGS_XMAC)
2735                 reg = XMAC_HOST_INFO(xmac_index);
2736         else
2737                 reg = BMAC_HOST_INFO(bmac_index);
2738         __set_rdc_table_num_hw(np, reg, rdc_table_num, mac_pref);
2739         return 0;
2740 }
2741
2742 static int niu_set_primary_mac_rdc_table(struct niu *np, int table_num,
2743                                          int mac_pref)
2744 {
2745         return __set_rdc_table_num(np, 17, 0, table_num, mac_pref);
2746 }
2747
2748 static int niu_set_multicast_mac_rdc_table(struct niu *np, int table_num,
2749                                            int mac_pref)
2750 {
2751         return __set_rdc_table_num(np, 16, 8, table_num, mac_pref);
2752 }
2753
2754 static int niu_set_alt_mac_rdc_table(struct niu *np, int idx,
2755                                      int table_num, int mac_pref)
2756 {
2757         if (idx >= niu_num_alt_addr(np))
2758                 return -EINVAL;
2759         return __set_rdc_table_num(np, idx, idx + 1, table_num, mac_pref);
2760 }
2761
2762 static u64 vlan_entry_set_parity(u64 reg_val)
2763 {
2764         u64 port01_mask;
2765         u64 port23_mask;
2766
2767         port01_mask = 0x00ff;
2768         port23_mask = 0xff00;
2769
2770         if (hweight64(reg_val & port01_mask) & 1)
2771                 reg_val |= ENET_VLAN_TBL_PARITY0;
2772         else
2773                 reg_val &= ~ENET_VLAN_TBL_PARITY0;
2774
2775         if (hweight64(reg_val & port23_mask) & 1)
2776                 reg_val |= ENET_VLAN_TBL_PARITY1;
2777         else
2778                 reg_val &= ~ENET_VLAN_TBL_PARITY1;
2779
2780         return reg_val;
2781 }
2782
2783 static void vlan_tbl_write(struct niu *np, unsigned long index,
2784                            int port, int vpr, int rdc_table)
2785 {
2786         u64 reg_val = nr64(ENET_VLAN_TBL(index));
2787
2788         reg_val &= ~((ENET_VLAN_TBL_VPR |
2789                       ENET_VLAN_TBL_VLANRDCTBLN) <<
2790                      ENET_VLAN_TBL_SHIFT(port));
2791         if (vpr)
2792                 reg_val |= (ENET_VLAN_TBL_VPR <<
2793                             ENET_VLAN_TBL_SHIFT(port));
2794         reg_val |= (rdc_table << ENET_VLAN_TBL_SHIFT(port));
2795
2796         reg_val = vlan_entry_set_parity(reg_val);
2797
2798         nw64(ENET_VLAN_TBL(index), reg_val);
2799 }
2800
2801 static void vlan_tbl_clear(struct niu *np)
2802 {
2803         int i;
2804
2805         for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++)
2806                 nw64(ENET_VLAN_TBL(i), 0);
2807 }
2808
2809 static int tcam_wait_bit(struct niu *np, u64 bit)
2810 {
2811         int limit = 1000;
2812
2813         while (--limit > 0) {
2814                 if (nr64(TCAM_CTL) & bit)
2815                         break;
2816                 udelay(1);
2817         }
2818         if (limit < 0)
2819                 return -ENODEV;
2820
2821         return 0;
2822 }
2823
2824 static int tcam_flush(struct niu *np, int index)
2825 {
2826         nw64(TCAM_KEY_0, 0x00);
2827         nw64(TCAM_KEY_MASK_0, 0xff);
2828         nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
2829
2830         return tcam_wait_bit(np, TCAM_CTL_STAT);
2831 }
2832
2833 #if 0
2834 static int tcam_read(struct niu *np, int index,
2835                      u64 *key, u64 *mask)
2836 {
2837         int err;
2838
2839         nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_READ | index));
2840         err = tcam_wait_bit(np, TCAM_CTL_STAT);
2841         if (!err) {
2842                 key[0] = nr64(TCAM_KEY_0);
2843                 key[1] = nr64(TCAM_KEY_1);
2844                 key[2] = nr64(TCAM_KEY_2);
2845                 key[3] = nr64(TCAM_KEY_3);
2846                 mask[0] = nr64(TCAM_KEY_MASK_0);
2847                 mask[1] = nr64(TCAM_KEY_MASK_1);
2848                 mask[2] = nr64(TCAM_KEY_MASK_2);
2849                 mask[3] = nr64(TCAM_KEY_MASK_3);
2850         }
2851         return err;
2852 }
2853 #endif
2854
2855 static int tcam_write(struct niu *np, int index,
2856                       u64 *key, u64 *mask)
2857 {
2858         nw64(TCAM_KEY_0, key[0]);
2859         nw64(TCAM_KEY_1, key[1]);
2860         nw64(TCAM_KEY_2, key[2]);
2861         nw64(TCAM_KEY_3, key[3]);
2862         nw64(TCAM_KEY_MASK_0, mask[0]);
2863         nw64(TCAM_KEY_MASK_1, mask[1]);
2864         nw64(TCAM_KEY_MASK_2, mask[2]);
2865         nw64(TCAM_KEY_MASK_3, mask[3]);
2866         nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
2867
2868         return tcam_wait_bit(np, TCAM_CTL_STAT);
2869 }
2870
2871 #if 0
2872 static int tcam_assoc_read(struct niu *np, int index, u64 *data)
2873 {
2874         int err;
2875
2876         nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_READ | index));
2877         err = tcam_wait_bit(np, TCAM_CTL_STAT);
2878         if (!err)
2879                 *data = nr64(TCAM_KEY_1);
2880
2881         return err;
2882 }
2883 #endif
2884
2885 static int tcam_assoc_write(struct niu *np, int index, u64 assoc_data)
2886 {
2887         nw64(TCAM_KEY_1, assoc_data);
2888         nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_WRITE | index));
2889
2890         return tcam_wait_bit(np, TCAM_CTL_STAT);
2891 }
2892
2893 static void tcam_enable(struct niu *np, int on)
2894 {
2895         u64 val = nr64(FFLP_CFG_1);
2896
2897         if (on)
2898                 val &= ~FFLP_CFG_1_TCAM_DIS;
2899         else
2900                 val |= FFLP_CFG_1_TCAM_DIS;
2901         nw64(FFLP_CFG_1, val);
2902 }
2903
2904 static void tcam_set_lat_and_ratio(struct niu *np, u64 latency, u64 ratio)
2905 {
2906         u64 val = nr64(FFLP_CFG_1);
2907
2908         val &= ~(FFLP_CFG_1_FFLPINITDONE |
2909                  FFLP_CFG_1_CAMLAT |
2910                  FFLP_CFG_1_CAMRATIO);
2911         val |= (latency << FFLP_CFG_1_CAMLAT_SHIFT);
2912         val |= (ratio << FFLP_CFG_1_CAMRATIO_SHIFT);
2913         nw64(FFLP_CFG_1, val);
2914
2915         val = nr64(FFLP_CFG_1);
2916         val |= FFLP_CFG_1_FFLPINITDONE;
2917         nw64(FFLP_CFG_1, val);
2918 }
2919
2920 static int tcam_user_eth_class_enable(struct niu *np, unsigned long class,
2921                                       int on)
2922 {
2923         unsigned long reg;
2924         u64 val;
2925
2926         if (class < CLASS_CODE_ETHERTYPE1 ||
2927             class > CLASS_CODE_ETHERTYPE2)
2928                 return -EINVAL;
2929
2930         reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1);
2931         val = nr64(reg);
2932         if (on)
2933                 val |= L2_CLS_VLD;
2934         else
2935                 val &= ~L2_CLS_VLD;
2936         nw64(reg, val);
2937
2938         return 0;
2939 }
2940
2941 #if 0
2942 static int tcam_user_eth_class_set(struct niu *np, unsigned long class,
2943                                    u64 ether_type)
2944 {
2945         unsigned long reg;
2946         u64 val;
2947
2948         if (class < CLASS_CODE_ETHERTYPE1 ||
2949             class > CLASS_CODE_ETHERTYPE2 ||
2950             (ether_type & ~(u64)0xffff) != 0)
2951                 return -EINVAL;
2952
2953         reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1);
2954         val = nr64(reg);
2955         val &= ~L2_CLS_ETYPE;
2956         val |= (ether_type << L2_CLS_ETYPE_SHIFT);
2957         nw64(reg, val);
2958
2959         return 0;
2960 }
2961 #endif
2962
2963 static int tcam_user_ip_class_enable(struct niu *np, unsigned long class,
2964                                      int on)
2965 {
2966         unsigned long reg;
2967         u64 val;
2968
2969         if (class < CLASS_CODE_USER_PROG1 ||
2970             class > CLASS_CODE_USER_PROG4)
2971                 return -EINVAL;
2972
2973         reg = L3_CLS(class - CLASS_CODE_USER_PROG1);
2974         val = nr64(reg);
2975         if (on)
2976                 val |= L3_CLS_VALID;
2977         else
2978                 val &= ~L3_CLS_VALID;
2979         nw64(reg, val);
2980
2981         return 0;
2982 }
2983
2984 static int tcam_user_ip_class_set(struct niu *np, unsigned long class,
2985                                   int ipv6, u64 protocol_id,
2986                                   u64 tos_mask, u64 tos_val)
2987 {
2988         unsigned long reg;
2989         u64 val;
2990
2991         if (class < CLASS_CODE_USER_PROG1 ||
2992             class > CLASS_CODE_USER_PROG4 ||
2993             (protocol_id & ~(u64)0xff) != 0 ||
2994             (tos_mask & ~(u64)0xff) != 0 ||
2995             (tos_val & ~(u64)0xff) != 0)
2996                 return -EINVAL;
2997
2998         reg = L3_CLS(class - CLASS_CODE_USER_PROG1);
2999         val = nr64(reg);
3000         val &= ~(L3_CLS_IPVER | L3_CLS_PID |
3001                  L3_CLS_TOSMASK | L3_CLS_TOS);
3002         if (ipv6)
3003                 val |= L3_CLS_IPVER;
3004         val |= (protocol_id << L3_CLS_PID_SHIFT);
3005         val |= (tos_mask << L3_CLS_TOSMASK_SHIFT);
3006         val |= (tos_val << L3_CLS_TOS_SHIFT);
3007         nw64(reg, val);
3008
3009         return 0;
3010 }
3011
3012 static int tcam_early_init(struct niu *np)
3013 {
3014         unsigned long i;
3015         int err;
3016
3017         tcam_enable(np, 0);
3018         tcam_set_lat_and_ratio(np,
3019                                DEFAULT_TCAM_LATENCY,
3020                                DEFAULT_TCAM_ACCESS_RATIO);
3021         for (i = CLASS_CODE_ETHERTYPE1; i <= CLASS_CODE_ETHERTYPE2; i++) {
3022                 err = tcam_user_eth_class_enable(np, i, 0);
3023                 if (err)
3024                         return err;
3025         }
3026         for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_USER_PROG4; i++) {
3027                 err = tcam_user_ip_class_enable(np, i, 0);
3028                 if (err)
3029                         return err;
3030         }
3031
3032         return 0;
3033 }
3034
3035 static int tcam_flush_all(struct niu *np)
3036 {
3037         unsigned long i;
3038
3039         for (i = 0; i < np->parent->tcam_num_entries; i++) {
3040                 int err = tcam_flush(np, i);
3041                 if (err)
3042                         return err;
3043         }
3044         return 0;
3045 }
3046
3047 static u64 hash_addr_regval(unsigned long index, unsigned long num_entries)
3048 {
3049         return ((u64)index | (num_entries == 1 ?
3050                               HASH_TBL_ADDR_AUTOINC : 0));
3051 }
3052
3053 #if 0
3054 static int hash_read(struct niu *np, unsigned long partition,
3055                      unsigned long index, unsigned long num_entries,
3056                      u64 *data)
3057 {
3058         u64 val = hash_addr_regval(index, num_entries);
3059         unsigned long i;
3060
3061         if (partition >= FCRAM_NUM_PARTITIONS ||
3062             index + num_entries > FCRAM_SIZE)
3063                 return -EINVAL;
3064
3065         nw64(HASH_TBL_ADDR(partition), val);
3066         for (i = 0; i < num_entries; i++)
3067                 data[i] = nr64(HASH_TBL_DATA(partition));
3068
3069         return 0;
3070 }
3071 #endif
3072
3073 static int hash_write(struct niu *np, unsigned long partition,
3074                       unsigned long index, unsigned long num_entries,
3075                       u64 *data)
3076 {
3077         u64 val = hash_addr_regval(index, num_entries);
3078         unsigned long i;
3079
3080         if (partition >= FCRAM_NUM_PARTITIONS ||
3081             index + (num_entries * 8) > FCRAM_SIZE)
3082                 return -EINVAL;
3083
3084         nw64(HASH_TBL_ADDR(partition), val);
3085         for (i = 0; i < num_entries; i++)
3086                 nw64(HASH_TBL_DATA(partition), data[i]);
3087
3088         return 0;
3089 }
3090
3091 static void fflp_reset(struct niu *np)
3092 {
3093         u64 val;
3094
3095         nw64(FFLP_CFG_1, FFLP_CFG_1_PIO_FIO_RST);
3096         udelay(10);
3097         nw64(FFLP_CFG_1, 0);
3098
3099         val = FFLP_CFG_1_FCRAMOUTDR_NORMAL | FFLP_CFG_1_FFLPINITDONE;
3100         nw64(FFLP_CFG_1, val);
3101 }
3102
3103 static void fflp_set_timings(struct niu *np)
3104 {
3105         u64 val = nr64(FFLP_CFG_1);
3106
3107         val &= ~FFLP_CFG_1_FFLPINITDONE;
3108         val |= (DEFAULT_FCRAMRATIO << FFLP_CFG_1_FCRAMRATIO_SHIFT);
3109         nw64(FFLP_CFG_1, val);
3110
3111         val = nr64(FFLP_CFG_1);
3112         val |= FFLP_CFG_1_FFLPINITDONE;
3113         nw64(FFLP_CFG_1, val);
3114
3115         val = nr64(FCRAM_REF_TMR);
3116         val &= ~(FCRAM_REF_TMR_MAX | FCRAM_REF_TMR_MIN);
3117         val |= (DEFAULT_FCRAM_REFRESH_MAX << FCRAM_REF_TMR_MAX_SHIFT);
3118         val |= (DEFAULT_FCRAM_REFRESH_MIN << FCRAM_REF_TMR_MIN_SHIFT);
3119         nw64(FCRAM_REF_TMR, val);
3120 }
3121
3122 static int fflp_set_partition(struct niu *np, u64 partition,
3123                               u64 mask, u64 base, int enable)
3124 {
3125         unsigned long reg;
3126         u64 val;
3127
3128         if (partition >= FCRAM_NUM_PARTITIONS ||
3129             (mask & ~(u64)0x1f) != 0 ||
3130             (base & ~(u64)0x1f) != 0)
3131                 return -EINVAL;
3132
3133         reg = FLW_PRT_SEL(partition);
3134
3135         val = nr64(reg);
3136         val &= ~(FLW_PRT_SEL_EXT | FLW_PRT_SEL_MASK | FLW_PRT_SEL_BASE);
3137         val |= (mask << FLW_PRT_SEL_MASK_SHIFT);
3138         val |= (base << FLW_PRT_SEL_BASE_SHIFT);
3139         if (enable)
3140                 val |= FLW_PRT_SEL_EXT;
3141         nw64(reg, val);
3142
3143         return 0;
3144 }
3145
3146 static int fflp_disable_all_partitions(struct niu *np)
3147 {
3148         unsigned long i;
3149
3150         for (i = 0; i < FCRAM_NUM_PARTITIONS; i++) {
3151                 int err = fflp_set_partition(np, 0, 0, 0, 0);
3152                 if (err)
3153                         return err;
3154         }
3155         return 0;
3156 }
3157
3158 static void fflp_llcsnap_enable(struct niu *np, int on)
3159 {
3160         u64 val = nr64(FFLP_CFG_1);
3161
3162         if (on)
3163                 val |= FFLP_CFG_1_LLCSNAP;
3164         else
3165                 val &= ~FFLP_CFG_1_LLCSNAP;
3166         nw64(FFLP_CFG_1, val);
3167 }
3168
3169 static void fflp_errors_enable(struct niu *np, int on)
3170 {
3171         u64 val = nr64(FFLP_CFG_1);
3172
3173         if (on)
3174                 val &= ~FFLP_CFG_1_ERRORDIS;
3175         else
3176                 val |= FFLP_CFG_1_ERRORDIS;
3177         nw64(FFLP_CFG_1, val);
3178 }
3179
3180 static int fflp_hash_clear(struct niu *np)
3181 {
3182         struct fcram_hash_ipv4 ent;
3183         unsigned long i;
3184
3185         /* IPV4 hash entry with valid bit clear, rest is don't care.  */
3186         memset(&ent, 0, sizeof(ent));
3187         ent.header = HASH_HEADER_EXT;
3188
3189         for (i = 0; i < FCRAM_SIZE; i += sizeof(ent)) {
3190                 int err = hash_write(np, 0, i, 1, (u64 *) &ent);
3191                 if (err)
3192                         return err;
3193         }
3194         return 0;
3195 }
3196
3197 static int fflp_early_init(struct niu *np)
3198 {
3199         struct niu_parent *parent;
3200         unsigned long flags;
3201         int err;
3202
3203         niu_lock_parent(np, flags);
3204
3205         parent = np->parent;
3206         err = 0;
3207         if (!(parent->flags & PARENT_FLGS_CLS_HWINIT)) {
3208                 niudbg(PROBE, "fflp_early_init: Initting hw on port %u\n",
3209                        np->port);
3210                 if (np->parent->plat_type != PLAT_TYPE_NIU) {
3211                         fflp_reset(np);
3212                         fflp_set_timings(np);
3213                         err = fflp_disable_all_partitions(np);
3214                         if (err) {
3215                                 niudbg(PROBE, "fflp_disable_all_partitions "
3216                                        "failed, err=%d\n", err);
3217                                 goto out;
3218                         }
3219                 }
3220
3221                 err = tcam_early_init(np);
3222                 if (err) {
3223                         niudbg(PROBE, "tcam_early_init failed, err=%d\n",
3224                                err);
3225                         goto out;
3226                 }
3227                 fflp_llcsnap_enable(np, 1);
3228                 fflp_errors_enable(np, 0);
3229                 nw64(H1POLY, 0);
3230                 nw64(H2POLY, 0);
3231
3232                 err = tcam_flush_all(np);
3233                 if (err) {
3234                         niudbg(PROBE, "tcam_flush_all failed, err=%d\n",
3235                                err);
3236                         goto out;
3237                 }
3238                 if (np->parent->plat_type != PLAT_TYPE_NIU) {
3239                         err = fflp_hash_clear(np);
3240                         if (err) {
3241                                 niudbg(PROBE, "fflp_hash_clear failed, "
3242                                        "err=%d\n", err);
3243                                 goto out;
3244                         }
3245                 }
3246
3247                 vlan_tbl_clear(np);
3248
3249                 niudbg(PROBE, "fflp_early_init: Success\n");
3250                 parent->flags |= PARENT_FLGS_CLS_HWINIT;
3251         }
3252 out:
3253         niu_unlock_parent(np, flags);
3254         return err;
3255 }
3256
3257 static int niu_set_flow_key(struct niu *np, unsigned long class_code, u64 key)
3258 {
3259         if (class_code < CLASS_CODE_USER_PROG1 ||
3260             class_code > CLASS_CODE_SCTP_IPV6)
3261                 return -EINVAL;
3262
3263         nw64(FLOW_KEY(class_code - CLASS_CODE_USER_PROG1), key);
3264         return 0;
3265 }
3266
3267 static int niu_set_tcam_key(struct niu *np, unsigned long class_code, u64 key)
3268 {
3269         if (class_code < CLASS_CODE_USER_PROG1 ||
3270             class_code > CLASS_CODE_SCTP_IPV6)
3271                 return -EINVAL;
3272
3273         nw64(TCAM_KEY(class_code - CLASS_CODE_USER_PROG1), key);
3274         return 0;
3275 }
3276
3277 /* Entries for the ports are interleaved in the TCAM */
3278 static u16 tcam_get_index(struct niu *np, u16 idx)
3279 {
3280         /* One entry reserved for IP fragment rule */
3281         if (idx >= (np->clas.tcam_sz - 1))
3282                 idx = 0;
3283         return (np->clas.tcam_top + ((idx+1) * np->parent->num_ports));
3284 }
3285
3286 static u16 tcam_get_size(struct niu *np)
3287 {
3288         /* One entry reserved for IP fragment rule */
3289         return np->clas.tcam_sz - 1;
3290 }
3291
3292 static u16 tcam_get_valid_entry_cnt(struct niu *np)
3293 {
3294         /* One entry reserved for IP fragment rule */
3295         return np->clas.tcam_valid_entries - 1;
3296 }
3297
3298 static void niu_rx_skb_append(struct sk_buff *skb, struct page *page,
3299                               u32 offset, u32 size)
3300 {
3301         int i = skb_shinfo(skb)->nr_frags;
3302         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3303
3304         frag->page = page;
3305         frag->page_offset = offset;
3306         frag->size = size;
3307
3308         skb->len += size;
3309         skb->data_len += size;
3310         skb->truesize += size;
3311
3312         skb_shinfo(skb)->nr_frags = i + 1;
3313 }
3314
3315 static unsigned int niu_hash_rxaddr(struct rx_ring_info *rp, u64 a)
3316 {
3317         a >>= PAGE_SHIFT;
3318         a ^= (a >> ilog2(MAX_RBR_RING_SIZE));
3319
3320         return (a & (MAX_RBR_RING_SIZE - 1));
3321 }
3322
3323 static struct page *niu_find_rxpage(struct rx_ring_info *rp, u64 addr,
3324                                     struct page ***link)
3325 {
3326         unsigned int h = niu_hash_rxaddr(rp, addr);
3327         struct page *p, **pp;
3328
3329         addr &= PAGE_MASK;
3330         pp = &rp->rxhash[h];
3331         for (; (p = *pp) != NULL; pp = (struct page **) &p->mapping) {
3332                 if (p->index == addr) {
3333                         *link = pp;
3334                         break;
3335                 }
3336         }
3337
3338         return p;
3339 }
3340
3341 static void niu_hash_page(struct rx_ring_info *rp, struct page *page, u64 base)
3342 {
3343         unsigned int h = niu_hash_rxaddr(rp, base);
3344
3345         page->index = base;
3346         page->mapping = (struct address_space *) rp->rxhash[h];
3347         rp->rxhash[h] = page;
3348 }
3349
3350 static int niu_rbr_add_page(struct niu *np, struct rx_ring_info *rp,
3351                             gfp_t mask, int start_index)
3352 {
3353         struct page *page;
3354         u64 addr;
3355         int i;
3356
3357         page = alloc_page(mask);
3358         if (!page)
3359                 return -ENOMEM;
3360
3361         addr = np->ops->map_page(np->device, page, 0,
3362                                  PAGE_SIZE, DMA_FROM_DEVICE);
3363
3364         niu_hash_page(rp, page, addr);
3365         if (rp->rbr_blocks_per_page > 1)
3366                 atomic_add(rp->rbr_blocks_per_page - 1,
3367                            &compound_head(page)->_count);
3368
3369         for (i = 0; i < rp->rbr_blocks_per_page; i++) {
3370                 __le32 *rbr = &rp->rbr[start_index + i];
3371
3372                 *rbr = cpu_to_le32(addr >> RBR_DESCR_ADDR_SHIFT);
3373                 addr += rp->rbr_block_size;
3374         }
3375
3376         return 0;
3377 }
3378
3379 static void niu_rbr_refill(struct niu *np, struct rx_ring_info *rp, gfp_t mask)
3380 {
3381         int index = rp->rbr_index;
3382
3383         rp->rbr_pending++;
3384         if ((rp->rbr_pending % rp->rbr_blocks_per_page) == 0) {
3385                 int err = niu_rbr_add_page(np, rp, mask, index);
3386
3387                 if (unlikely(err)) {
3388                         rp->rbr_pending--;
3389                         return;
3390                 }
3391
3392                 rp->rbr_index += rp->rbr_blocks_per_page;
3393                 BUG_ON(rp->rbr_index > rp->rbr_table_size);
3394                 if (rp->rbr_index == rp->rbr_table_size)
3395                         rp->rbr_index = 0;
3396
3397                 if (rp->rbr_pending >= rp->rbr_kick_thresh) {
3398                         nw64(RBR_KICK(rp->rx_channel), rp->rbr_pending);
3399                         rp->rbr_pending = 0;
3400                 }
3401         }
3402 }
3403
3404 static int niu_rx_pkt_ignore(struct niu *np, struct rx_ring_info *rp)
3405 {
3406         unsigned int index = rp->rcr_index;
3407         int num_rcr = 0;
3408
3409         rp->rx_dropped++;
3410         while (1) {
3411                 struct page *page, **link;
3412                 u64 addr, val;
3413                 u32 rcr_size;
3414
3415                 num_rcr++;
3416
3417                 val = le64_to_cpup(&rp->rcr[index]);
3418                 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
3419                         RCR_ENTRY_PKT_BUF_ADDR_SHIFT;
3420                 page = niu_find_rxpage(rp, addr, &link);
3421
3422                 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
3423                                          RCR_ENTRY_PKTBUFSZ_SHIFT];
3424                 if ((page->index + PAGE_SIZE) - rcr_size == addr) {
3425                         *link = (struct page *) page->mapping;
3426                         np->ops->unmap_page(np->device, page->index,
3427                                             PAGE_SIZE, DMA_FROM_DEVICE);
3428                         page->index = 0;
3429                         page->mapping = NULL;
3430                         __free_page(page);
3431                         rp->rbr_refill_pending++;
3432                 }
3433
3434                 index = NEXT_RCR(rp, index);
3435                 if (!(val & RCR_ENTRY_MULTI))
3436                         break;
3437
3438         }
3439         rp->rcr_index = index;
3440
3441         return num_rcr;
3442 }
3443
3444 static int niu_process_rx_pkt(struct niu *np, struct rx_ring_info *rp)
3445 {
3446         unsigned int index = rp->rcr_index;
3447         struct sk_buff *skb;
3448         int len, num_rcr;
3449
3450         skb = netdev_alloc_skb(np->dev, RX_SKB_ALLOC_SIZE);
3451         if (unlikely(!skb))
3452                 return niu_rx_pkt_ignore(np, rp);
3453
3454         num_rcr = 0;
3455         while (1) {
3456                 struct page *page, **link;
3457                 u32 rcr_size, append_size;
3458                 u64 addr, val, off;
3459
3460                 num_rcr++;
3461
3462                 val = le64_to_cpup(&rp->rcr[index]);
3463
3464                 len = (val & RCR_ENTRY_L2_LEN) >>
3465                         RCR_ENTRY_L2_LEN_SHIFT;
3466                 len -= ETH_FCS_LEN;
3467
3468                 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
3469                         RCR_ENTRY_PKT_BUF_ADDR_SHIFT;
3470                 page = niu_find_rxpage(rp, addr, &link);
3471
3472                 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
3473                                          RCR_ENTRY_PKTBUFSZ_SHIFT];
3474
3475                 off = addr & ~PAGE_MASK;
3476                 append_size = rcr_size;
3477                 if (num_rcr == 1) {
3478                         int ptype;
3479
3480                         off += 2;
3481                         append_size -= 2;
3482
3483                         ptype = (val >> RCR_ENTRY_PKT_TYPE_SHIFT);
3484                         if ((ptype == RCR_PKT_TYPE_TCP ||
3485                              ptype == RCR_PKT_TYPE_UDP) &&
3486                             !(val & (RCR_ENTRY_NOPORT |
3487                                      RCR_ENTRY_ERROR)))
3488                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
3489                         else
3490                                 skb->ip_summed = CHECKSUM_NONE;
3491                 }
3492                 if (!(val & RCR_ENTRY_MULTI))
3493                         append_size = len - skb->len;
3494
3495                 niu_rx_skb_append(skb, page, off, append_size);
3496                 if ((page->index + rp->rbr_block_size) - rcr_size == addr) {
3497                         *link = (struct page *) page->mapping;
3498                         np->ops->unmap_page(np->device, page->index,
3499                                             PAGE_SIZE, DMA_FROM_DEVICE);
3500                         page->index = 0;
3501                         page->mapping = NULL;
3502                         rp->rbr_refill_pending++;
3503                 } else
3504                         get_page(page);
3505
3506                 index = NEXT_RCR(rp, index);
3507                 if (!(val & RCR_ENTRY_MULTI))
3508                         break;
3509
3510         }
3511         rp->rcr_index = index;
3512
3513         skb_reserve(skb, NET_IP_ALIGN);
3514         __pskb_pull_tail(skb, min(len, NIU_RXPULL_MAX));
3515
3516         rp->rx_packets++;
3517         rp->rx_bytes += skb->len;
3518
3519         skb->protocol = eth_type_trans(skb, np->dev);
3520         skb_record_rx_queue(skb, rp->rx_channel);
3521         netif_receive_skb(skb);
3522
3523         return num_rcr;
3524 }
3525
3526 static int niu_rbr_fill(struct niu *np, struct rx_ring_info *rp, gfp_t mask)
3527 {
3528         int blocks_per_page = rp->rbr_blocks_per_page;
3529         int err, index = rp->rbr_index;
3530
3531         err = 0;
3532         while (index < (rp->rbr_table_size - blocks_per_page)) {
3533                 err = niu_rbr_add_page(np, rp, mask, index);
3534                 if (err)
3535                         break;
3536
3537                 index += blocks_per_page;
3538         }
3539
3540         rp->rbr_index = index;
3541         return err;
3542 }
3543
3544 static void niu_rbr_free(struct niu *np, struct rx_ring_info *rp)
3545 {
3546         int i;
3547
3548         for (i = 0; i < MAX_RBR_RING_SIZE; i++) {
3549                 struct page *page;
3550
3551                 page = rp->rxhash[i];
3552                 while (page) {
3553                         struct page *next = (struct page *) page->mapping;
3554                         u64 base = page->index;
3555
3556                         np->ops->unmap_page(np->device, base, PAGE_SIZE,
3557                                             DMA_FROM_DEVICE);
3558                         page->index = 0;
3559                         page->mapping = NULL;
3560
3561                         __free_page(page);
3562
3563                         page = next;
3564                 }
3565         }
3566
3567         for (i = 0; i < rp->rbr_table_size; i++)
3568                 rp->rbr[i] = cpu_to_le32(0);
3569         rp->rbr_index = 0;
3570 }
3571
3572 static int release_tx_packet(struct niu *np, struct tx_ring_info *rp, int idx)
3573 {
3574         struct tx_buff_info *tb = &rp->tx_buffs[idx];
3575         struct sk_buff *skb = tb->skb;
3576         struct tx_pkt_hdr *tp;
3577         u64 tx_flags;
3578         int i, len;
3579
3580         tp = (struct tx_pkt_hdr *) skb->data;
3581         tx_flags = le64_to_cpup(&tp->flags);
3582
3583         rp->tx_packets++;
3584         rp->tx_bytes += (((tx_flags & TXHDR_LEN) >> TXHDR_LEN_SHIFT) -
3585                          ((tx_flags & TXHDR_PAD) / 2));
3586
3587         len = skb_headlen(skb);
3588         np->ops->unmap_single(np->device, tb->mapping,
3589                               len, DMA_TO_DEVICE);
3590
3591         if (le64_to_cpu(rp->descr[idx]) & TX_DESC_MARK)
3592                 rp->mark_pending--;
3593
3594         tb->skb = NULL;
3595         do {
3596                 idx = NEXT_TX(rp, idx);
3597                 len -= MAX_TX_DESC_LEN;
3598         } while (len > 0);
3599
3600         for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
3601                 tb = &rp->tx_buffs[idx];
3602                 BUG_ON(tb->skb != NULL);
3603                 np->ops->unmap_page(np->device, tb->mapping,
3604                                     skb_shinfo(skb)->frags[i].size,
3605                                     DMA_TO_DEVICE);
3606                 idx = NEXT_TX(rp, idx);
3607         }
3608
3609         dev_kfree_skb(skb);
3610
3611         return idx;
3612 }
3613
3614 #define NIU_TX_WAKEUP_THRESH(rp)                ((rp)->pending / 4)
3615
3616 static void niu_tx_work(struct niu *np, struct tx_ring_info *rp)
3617 {
3618         struct netdev_queue *txq;
3619         u16 pkt_cnt, tmp;
3620         int cons, index;
3621         u64 cs;
3622
3623         index = (rp - np->tx_rings);
3624         txq = netdev_get_tx_queue(np->dev, index);
3625
3626         cs = rp->tx_cs;
3627         if (unlikely(!(cs & (TX_CS_MK | TX_CS_MMK))))
3628                 goto out;
3629
3630         tmp = pkt_cnt = (cs & TX_CS_PKT_CNT) >> TX_CS_PKT_CNT_SHIFT;
3631         pkt_cnt = (pkt_cnt - rp->last_pkt_cnt) &
3632                 (TX_CS_PKT_CNT >> TX_CS_PKT_CNT_SHIFT);
3633
3634         rp->last_pkt_cnt = tmp;
3635
3636         cons = rp->cons;
3637
3638         niudbg(TX_DONE, "%s: niu_tx_work() pkt_cnt[%u] cons[%d]\n",
3639                np->dev->name, pkt_cnt, cons);
3640
3641         while (pkt_cnt--)
3642                 cons = release_tx_packet(np, rp, cons);
3643
3644         rp->cons = cons;
3645         smp_mb();
3646
3647 out:
3648         if (unlikely(netif_tx_queue_stopped(txq) &&
3649                      (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))) {
3650                 __netif_tx_lock(txq, smp_processor_id());
3651                 if (netif_tx_queue_stopped(txq) &&
3652                     (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))
3653                         netif_tx_wake_queue(txq);
3654                 __netif_tx_unlock(txq);
3655         }
3656 }
3657
3658 static inline void niu_sync_rx_discard_stats(struct niu *np,
3659                                              struct rx_ring_info *rp,
3660                                              const int limit)
3661 {
3662         /* This elaborate scheme is needed for reading the RX discard
3663          * counters, as they are only 16-bit and can overflow quickly,
3664          * and because the overflow indication bit is not usable as
3665          * the counter value does not wrap, but remains at max value
3666          * 0xFFFF.
3667          *
3668          * In theory and in practice counters can be lost in between
3669          * reading nr64() and clearing the counter nw64().  For this
3670          * reason, the number of counter clearings nw64() is
3671          * limited/reduced though the limit parameter.
3672          */
3673         int rx_channel = rp->rx_channel;
3674         u32 misc, wred;
3675
3676         /* RXMISC (Receive Miscellaneous Discard Count), covers the
3677          * following discard events: IPP (Input Port Process),
3678          * FFLP/TCAM, Full RCR (Receive Completion Ring) RBR (Receive
3679          * Block Ring) prefetch buffer is empty.
3680          */
3681         misc = nr64(RXMISC(rx_channel));
3682         if (unlikely((misc & RXMISC_COUNT) > limit)) {
3683                 nw64(RXMISC(rx_channel), 0);
3684                 rp->rx_errors += misc & RXMISC_COUNT;
3685
3686                 if (unlikely(misc & RXMISC_OFLOW))
3687                         dev_err(np->device, "rx-%d: Counter overflow "
3688                                 "RXMISC discard\n", rx_channel);
3689
3690                 niudbg(RX_ERR, "%s-rx-%d: MISC drop=%u over=%u\n",
3691                        np->dev->name, rx_channel, misc, misc-limit);
3692         }
3693
3694         /* WRED (Weighted Random Early Discard) by hardware */
3695         wred = nr64(RED_DIS_CNT(rx_channel));
3696         if (unlikely((wred & RED_DIS_CNT_COUNT) > limit)) {
3697                 nw64(RED_DIS_CNT(rx_channel), 0);
3698                 rp->rx_dropped += wred & RED_DIS_CNT_COUNT;
3699
3700                 if (unlikely(wred & RED_DIS_CNT_OFLOW))
3701                         dev_err(np->device, "rx-%d: Counter overflow "
3702                                 "WRED discard\n", rx_channel);
3703
3704                 niudbg(RX_ERR, "%s-rx-%d: WRED drop=%u over=%u\n",
3705                        np->dev->name, rx_channel, wred, wred-limit);
3706         }
3707 }
3708
3709 static int niu_rx_work(struct niu *np, struct rx_ring_info *rp, int budget)
3710 {
3711         int qlen, rcr_done = 0, work_done = 0;
3712         struct rxdma_mailbox *mbox = rp->mbox;
3713         u64 stat;
3714
3715 #if 1
3716         stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
3717         qlen = nr64(RCRSTAT_A(rp->rx_channel)) & RCRSTAT_A_QLEN;
3718 #else
3719         stat = le64_to_cpup(&mbox->rx_dma_ctl_stat);
3720         qlen = (le64_to_cpup(&mbox->rcrstat_a) & RCRSTAT_A_QLEN);
3721 #endif
3722         mbox->rx_dma_ctl_stat = 0;
3723         mbox->rcrstat_a = 0;
3724
3725         niudbg(RX_STATUS, "%s: niu_rx_work(chan[%d]), stat[%llx] qlen=%d\n",
3726                np->dev->name, rp->rx_channel, (unsigned long long) stat, qlen);
3727
3728         rcr_done = work_done = 0;
3729         qlen = min(qlen, budget);
3730         while (work_done < qlen) {
3731                 rcr_done += niu_process_rx_pkt(np, rp);
3732                 work_done++;
3733         }
3734
3735         if (rp->rbr_refill_pending >= rp->rbr_kick_thresh) {
3736                 unsigned int i;
3737
3738                 for (i = 0; i < rp->rbr_refill_pending; i++)
3739                         niu_rbr_refill(np, rp, GFP_ATOMIC);
3740                 rp->rbr_refill_pending = 0;
3741         }
3742
3743         stat = (RX_DMA_CTL_STAT_MEX |
3744                 ((u64)work_done << RX_DMA_CTL_STAT_PKTREAD_SHIFT) |
3745                 ((u64)rcr_done << RX_DMA_CTL_STAT_PTRREAD_SHIFT));
3746
3747         nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat);
3748
3749         /* Only sync discards stats when qlen indicate potential for drops */
3750         if (qlen > 10)
3751                 niu_sync_rx_discard_stats(np, rp, 0x7FFF);
3752
3753         return work_done;
3754 }
3755
3756 static int niu_poll_core(struct niu *np, struct niu_ldg *lp, int budget)
3757 {
3758         u64 v0 = lp->v0;
3759         u32 tx_vec = (v0 >> 32);
3760         u32 rx_vec = (v0 & 0xffffffff);
3761         int i, work_done = 0;
3762
3763         niudbg(INTR, "%s: niu_poll_core() v0[%016llx]\n",
3764                np->dev->name, (unsigned long long) v0);
3765
3766         for (i = 0; i < np->num_tx_rings; i++) {
3767                 struct tx_ring_info *rp = &np->tx_rings[i];
3768                 if (tx_vec & (1 << rp->tx_channel))
3769                         niu_tx_work(np, rp);
3770                 nw64(LD_IM0(LDN_TXDMA(rp->tx_channel)), 0);
3771         }
3772
3773         for (i = 0; i < np->num_rx_rings; i++) {
3774                 struct rx_ring_info *rp = &np->rx_rings[i];
3775
3776                 if (rx_vec & (1 << rp->rx_channel)) {
3777                         int this_work_done;
3778
3779                         this_work_done = niu_rx_work(np, rp,
3780                                                      budget);
3781
3782                         budget -= this_work_done;
3783                         work_done += this_work_done;
3784                 }
3785                 nw64(LD_IM0(LDN_RXDMA(rp->rx_channel)), 0);
3786         }
3787
3788         return work_done;
3789 }
3790
3791 static int niu_poll(struct napi_struct *napi, int budget)
3792 {
3793         struct niu_ldg *lp = container_of(napi, struct niu_ldg, napi);
3794         struct niu *np = lp->np;
3795         int work_done;
3796
3797         work_done = niu_poll_core(np, lp, budget);
3798
3799         if (work_done < budget) {
3800                 napi_complete(napi);
3801                 niu_ldg_rearm(np, lp, 1);
3802         }
3803         return work_done;
3804 }
3805
3806 static void niu_log_rxchan_errors(struct niu *np, struct rx_ring_info *rp,
3807                                   u64 stat)
3808 {
3809         dev_err(np->device, PFX "%s: RX channel %u errors ( ",
3810                 np->dev->name, rp->rx_channel);
3811
3812         if (stat & RX_DMA_CTL_STAT_RBR_TMOUT)
3813                 printk("RBR_TMOUT ");
3814         if (stat & RX_DMA_CTL_STAT_RSP_CNT_ERR)
3815                 printk("RSP_CNT ");
3816         if (stat & RX_DMA_CTL_STAT_BYTE_EN_BUS)
3817                 printk("BYTE_EN_BUS ");
3818         if (stat & RX_DMA_CTL_STAT_RSP_DAT_ERR)
3819                 printk("RSP_DAT ");
3820         if (stat & RX_DMA_CTL_STAT_RCR_ACK_ERR)
3821                 printk("RCR_ACK ");
3822         if (stat & RX_DMA_CTL_STAT_RCR_SHA_PAR)
3823                 printk("RCR_SHA_PAR ");
3824         if (stat & RX_DMA_CTL_STAT_RBR_PRE_PAR)
3825                 printk("RBR_PRE_PAR ");
3826         if (stat & RX_DMA_CTL_STAT_CONFIG_ERR)
3827                 printk("CONFIG ");
3828         if (stat & RX_DMA_CTL_STAT_RCRINCON)
3829                 printk("RCRINCON ");
3830         if (stat & RX_DMA_CTL_STAT_RCRFULL)
3831                 printk("RCRFULL ");
3832         if (stat & RX_DMA_CTL_STAT_RBRFULL)
3833                 printk("RBRFULL ");
3834         if (stat & RX_DMA_CTL_STAT_RBRLOGPAGE)
3835                 printk("RBRLOGPAGE ");
3836         if (stat & RX_DMA_CTL_STAT_CFIGLOGPAGE)
3837                 printk("CFIGLOGPAGE ");
3838         if (stat & RX_DMA_CTL_STAT_DC_FIFO_ERR)
3839                 printk("DC_FIDO ");
3840
3841         printk(")\n");
3842 }
3843
3844 static int niu_rx_error(struct niu *np, struct rx_ring_info *rp)
3845 {
3846         u64 stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
3847         int err = 0;
3848
3849
3850         if (stat & (RX_DMA_CTL_STAT_CHAN_FATAL |
3851                     RX_DMA_CTL_STAT_PORT_FATAL))
3852                 err = -EINVAL;
3853
3854         if (err) {
3855                 dev_err(np->device, PFX "%s: RX channel %u error, stat[%llx]\n",
3856                         np->dev->name, rp->rx_channel,
3857                         (unsigned long long) stat);
3858
3859                 niu_log_rxchan_errors(np, rp, stat);
3860         }
3861
3862         nw64(RX_DMA_CTL_STAT(rp->rx_channel),
3863              stat & RX_DMA_CTL_WRITE_CLEAR_ERRS);
3864
3865         return err;
3866 }
3867
3868 static void niu_log_txchan_errors(struct niu *np, struct tx_ring_info *rp,
3869                                   u64 cs)
3870 {
3871         dev_err(np->device, PFX "%s: TX channel %u errors ( ",
3872                 np->dev->name, rp->tx_channel);
3873
3874         if (cs & TX_CS_MBOX_ERR)
3875                 printk("MBOX ");
3876         if (cs & TX_CS_PKT_SIZE_ERR)
3877                 printk("PKT_SIZE ");
3878         if (cs & TX_CS_TX_RING_OFLOW)
3879                 printk("TX_RING_OFLOW ");
3880         if (cs & TX_CS_PREF_BUF_PAR_ERR)
3881                 printk("PREF_BUF_PAR ");
3882         if (cs & TX_CS_NACK_PREF)
3883                 printk("NACK_PREF ");
3884         if (cs & TX_CS_NACK_PKT_RD)
3885                 printk("NACK_PKT_RD ");
3886         if (cs & TX_CS_CONF_PART_ERR)
3887                 printk("CONF_PART ");
3888         if (cs & TX_CS_PKT_PRT_ERR)
3889                 printk("PKT_PTR ");
3890
3891         printk(")\n");
3892 }
3893
3894 static int niu_tx_error(struct niu *np, struct tx_ring_info *rp)
3895 {
3896         u64 cs, logh, logl;
3897
3898         cs = nr64(TX_CS(rp->tx_channel));
3899         logh = nr64(TX_RNG_ERR_LOGH(rp->tx_channel));
3900         logl = nr64(TX_RNG_ERR_LOGL(rp->tx_channel));
3901
3902         dev_err(np->device, PFX "%s: TX channel %u error, "
3903                 "cs[%llx] logh[%llx] logl[%llx]\n",
3904                 np->dev->name, rp->tx_channel,
3905                 (unsigned long long) cs,
3906                 (unsigned long long) logh,
3907                 (unsigned long long) logl);
3908
3909         niu_log_txchan_errors(np, rp, cs);
3910
3911         return -ENODEV;
3912 }
3913
3914 static int niu_mif_interrupt(struct niu *np)
3915 {
3916         u64 mif_status = nr64(MIF_STATUS);
3917         int phy_mdint = 0;
3918
3919         if (np->flags & NIU_FLAGS_XMAC) {
3920                 u64 xrxmac_stat = nr64_mac(XRXMAC_STATUS);
3921
3922                 if (xrxmac_stat & XRXMAC_STATUS_PHY_MDINT)
3923                         phy_mdint = 1;
3924         }
3925
3926         dev_err(np->device, PFX "%s: MIF interrupt, "
3927                 "stat[%llx] phy_mdint(%d)\n",
3928                 np->dev->name, (unsigned long long) mif_status, phy_mdint);
3929
3930         return -ENODEV;
3931 }
3932
3933 static void niu_xmac_interrupt(struct niu *np)
3934 {
3935         struct niu_xmac_stats *mp = &np->mac_stats.xmac;
3936         u64 val;
3937
3938         val = nr64_mac(XTXMAC_STATUS);
3939         if (val & XTXMAC_STATUS_FRAME_CNT_EXP)
3940                 mp->tx_frames += TXMAC_FRM_CNT_COUNT;
3941         if (val & XTXMAC_STATUS_BYTE_CNT_EXP)
3942                 mp->tx_bytes += TXMAC_BYTE_CNT_COUNT;
3943         if (val & XTXMAC_STATUS_TXFIFO_XFR_ERR)
3944                 mp->tx_fifo_errors++;
3945         if (val & XTXMAC_STATUS_TXMAC_OFLOW)
3946                 mp->tx_overflow_errors++;
3947         if (val & XTXMAC_STATUS_MAX_PSIZE_ERR)
3948                 mp->tx_max_pkt_size_errors++;
3949         if (val & XTXMAC_STATUS_TXMAC_UFLOW)
3950                 mp->tx_underflow_errors++;
3951
3952         val = nr64_mac(XRXMAC_STATUS);
3953         if (val & XRXMAC_STATUS_LCL_FLT_STATUS)
3954                 mp->rx_local_faults++;
3955         if (val & XRXMAC_STATUS_RFLT_DET)
3956                 mp->rx_remote_faults++;
3957         if (val & XRXMAC_STATUS_LFLT_CNT_EXP)
3958                 mp->rx_link_faults += LINK_FAULT_CNT_COUNT;
3959         if (val & XRXMAC_STATUS_ALIGNERR_CNT_EXP)
3960                 mp->rx_align_errors += RXMAC_ALIGN_ERR_CNT_COUNT;
3961         if (val & XRXMAC_STATUS_RXFRAG_CNT_EXP)
3962                 mp->rx_frags += RXMAC_FRAG_CNT_COUNT;
3963         if (val & XRXMAC_STATUS_RXMULTF_CNT_EXP)
3964                 mp->rx_mcasts += RXMAC_MC_FRM_CNT_COUNT;
3965         if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP)
3966                 mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT;
3967         if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP)
3968                 mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT;
3969         if (val & XRXMAC_STATUS_RXHIST1_CNT_EXP)
3970                 mp->rx_hist_cnt1 += RXMAC_HIST_CNT1_COUNT;
3971         if (val & XRXMAC_STATUS_RXHIST2_CNT_EXP)
3972                 mp->rx_hist_cnt2 += RXMAC_HIST_CNT2_COUNT;
3973         if (val & XRXMAC_STATUS_RXHIST3_CNT_EXP)
3974                 mp->rx_hist_cnt3 += RXMAC_HIST_CNT3_COUNT;
3975         if (val & XRXMAC_STATUS_RXHIST4_CNT_EXP)
3976                 mp->rx_hist_cnt4 += RXMAC_HIST_CNT4_COUNT;
3977         if (val & XRXMAC_STATUS_RXHIST5_CNT_EXP)
3978                 mp->rx_hist_cnt5 += RXMAC_HIST_CNT5_COUNT;
3979         if (val & XRXMAC_STATUS_RXHIST6_CNT_EXP)
3980                 mp->rx_hist_cnt6 += RXMAC_HIST_CNT6_COUNT;
3981         if (val & XRXMAC_STATUS_RXHIST7_CNT_EXP)
3982                 mp->rx_hist_cnt7 += RXMAC_HIST_CNT7_COUNT;
3983         if (val & XRXMAC_STAT_MSK_RXOCTET_CNT_EXP)
3984                 mp->rx_octets += RXMAC_BT_CNT_COUNT;
3985         if (val & XRXMAC_STATUS_CVIOLERR_CNT_EXP)
3986                 mp->rx_code_violations += RXMAC_CD_VIO_CNT_COUNT;
3987         if (val & XRXMAC_STATUS_LENERR_CNT_EXP)
3988                 mp->rx_len_errors += RXMAC_MPSZER_CNT_COUNT;
3989         if (val & XRXMAC_STATUS_CRCERR_CNT_EXP)
3990                 mp->rx_crc_errors += RXMAC_CRC_ER_CNT_COUNT;
3991         if (val & XRXMAC_STATUS_RXUFLOW)
3992                 mp->rx_underflows++;
3993         if (val & XRXMAC_STATUS_RXOFLOW)
3994                 mp->rx_overflows++;
3995
3996         val = nr64_mac(XMAC_FC_STAT);
3997         if (val & XMAC_FC_STAT_TX_MAC_NPAUSE)
3998                 mp->pause_off_state++;
3999         if (val & XMAC_FC_STAT_TX_MAC_PAUSE)
4000                 mp->pause_on_state++;
4001         if (val & XMAC_FC_STAT_RX_MAC_RPAUSE)
4002                 mp->pause_received++;
4003 }
4004
4005 static void niu_bmac_interrupt(struct niu *np)
4006 {
4007         struct niu_bmac_stats *mp = &np->mac_stats.bmac;
4008         u64 val;
4009
4010         val = nr64_mac(BTXMAC_STATUS);
4011         if (val & BTXMAC_STATUS_UNDERRUN)
4012                 mp->tx_underflow_errors++;
4013         if (val & BTXMAC_STATUS_MAX_PKT_ERR)
4014                 mp->tx_max_pkt_size_errors++;
4015         if (val & BTXMAC_STATUS_BYTE_CNT_EXP)
4016                 mp->tx_bytes += BTXMAC_BYTE_CNT_COUNT;
4017         if (val & BTXMAC_STATUS_FRAME_CNT_EXP)
4018                 mp->tx_frames += BTXMAC_FRM_CNT_COUNT;
4019
4020         val = nr64_mac(BRXMAC_STATUS);
4021         if (val & BRXMAC_STATUS_OVERFLOW)
4022                 mp->rx_overflows++;
4023         if (val & BRXMAC_STATUS_FRAME_CNT_EXP)
4024                 mp->rx_frames += BRXMAC_FRAME_CNT_COUNT;
4025         if (val & BRXMAC_STATUS_ALIGN_ERR_EXP)
4026                 mp->rx_align_errors += BRXMAC_ALIGN_ERR_CNT_COUNT;
4027         if (val & BRXMAC_STATUS_CRC_ERR_EXP)
4028                 mp->rx_crc_errors += BRXMAC_ALIGN_ERR_CNT_COUNT;
4029         if (val & BRXMAC_STATUS_LEN_ERR_EXP)
4030                 mp->rx_len_errors += BRXMAC_CODE_VIOL_ERR_CNT_COUNT;
4031
4032         val = nr64_mac(BMAC_CTRL_STATUS);
4033         if (val & BMAC_CTRL_STATUS_NOPAUSE)
4034                 mp->pause_off_state++;
4035         if (val & BMAC_CTRL_STATUS_PAUSE)
4036                 mp->pause_on_state++;
4037         if (val & BMAC_CTRL_STATUS_PAUSE_RECV)
4038                 mp->pause_received++;
4039 }
4040
4041 static int niu_mac_interrupt(struct niu *np)
4042 {
4043         if (np->flags & NIU_FLAGS_XMAC)
4044                 niu_xmac_interrupt(np);
4045         else
4046                 niu_bmac_interrupt(np);
4047
4048         return 0;
4049 }
4050
4051 static void niu_log_device_error(struct niu *np, u64 stat)
4052 {
4053         dev_err(np->device, PFX "%s: Core device errors ( ",
4054                 np->dev->name);
4055
4056         if (stat & SYS_ERR_MASK_META2)
4057                 printk("META2 ");
4058         if (stat & SYS_ERR_MASK_META1)
4059                 printk("META1 ");
4060         if (stat & SYS_ERR_MASK_PEU)
4061                 printk("PEU ");
4062         if (stat & SYS_ERR_MASK_TXC)
4063                 printk("TXC ");
4064         if (stat & SYS_ERR_MASK_RDMC)
4065                 printk("RDMC ");
4066         if (stat & SYS_ERR_MASK_TDMC)
4067                 printk("TDMC ");
4068         if (stat & SYS_ERR_MASK_ZCP)
4069                 printk("ZCP ");
4070         if (stat & SYS_ERR_MASK_FFLP)
4071                 printk("FFLP ");
4072         if (stat & SYS_ERR_MASK_IPP)
4073                 printk("IPP ");
4074         if (stat & SYS_ERR_MASK_MAC)
4075                 printk("MAC ");
4076         if (stat & SYS_ERR_MASK_SMX)
4077                 printk("SMX ");
4078
4079         printk(")\n");
4080 }
4081
4082 static int niu_device_error(struct niu *np)
4083 {
4084         u64 stat = nr64(SYS_ERR_STAT);
4085
4086         dev_err(np->device, PFX "%s: Core device error, stat[%llx]\n",
4087                 np->dev->name, (unsigned long long) stat);
4088
4089         niu_log_device_error(np, stat);
4090
4091         return -ENODEV;
4092 }
4093
4094 static int niu_slowpath_interrupt(struct niu *np, struct niu_ldg *lp,
4095                               u64 v0, u64 v1, u64 v2)
4096 {
4097
4098         int i, err = 0;
4099
4100         lp->v0 = v0;
4101         lp->v1 = v1;
4102         lp->v2 = v2;
4103
4104         if (v1 & 0x00000000ffffffffULL) {
4105                 u32 rx_vec = (v1 & 0xffffffff);
4106
4107                 for (i = 0; i < np->num_rx_rings; i++) {
4108                         struct rx_ring_info *rp = &np->rx_rings[i];
4109
4110                         if (rx_vec & (1 << rp->rx_channel)) {
4111                                 int r = niu_rx_error(np, rp);
4112                                 if (r) {
4113                                         err = r;
4114                                 } else {
4115                                         if (!v0)
4116                                                 nw64(RX_DMA_CTL_STAT(rp->rx_channel),
4117                                                      RX_DMA_CTL_STAT_MEX);
4118                                 }
4119                         }
4120                 }
4121         }
4122         if (v1 & 0x7fffffff00000000ULL) {
4123                 u32 tx_vec = (v1 >> 32) & 0x7fffffff;
4124
4125                 for (i = 0; i < np->num_tx_rings; i++) {
4126                         struct tx_ring_info *rp = &np->tx_rings[i];
4127
4128                         if (tx_vec & (1 << rp->tx_channel)) {
4129                                 int r = niu_tx_error(np, rp);
4130                                 if (r)
4131                                         err = r;
4132                         }
4133                 }
4134         }
4135         if ((v0 | v1) & 0x8000000000000000ULL) {
4136                 int r = niu_mif_interrupt(np);
4137                 if (r)
4138                         err = r;
4139         }
4140         if (v2) {
4141                 if (v2 & 0x01ef) {
4142                         int r = niu_mac_interrupt(np);
4143                         if (r)
4144                                 err = r;
4145                 }
4146                 if (v2 & 0x0210) {
4147                         int r = niu_device_error(np);
4148                         if (r)
4149                                 err = r;
4150                 }
4151         }
4152
4153         if (err)
4154                 niu_enable_interrupts(np, 0);
4155
4156         return err;
4157 }
4158
4159 static void niu_rxchan_intr(struct niu *np, struct rx_ring_info *rp,
4160                             int ldn)
4161 {
4162         struct rxdma_mailbox *mbox = rp->mbox;
4163         u64 stat_write, stat = le64_to_cpup(&mbox->rx_dma_ctl_stat);
4164
4165         stat_write = (RX_DMA_CTL_STAT_RCRTHRES |
4166                       RX_DMA_CTL_STAT_RCRTO);
4167         nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat_write);
4168
4169         niudbg(INTR, "%s: rxchan_intr stat[%llx]\n",
4170                np->dev->name, (unsigned long long) stat);
4171 }
4172
4173 static void niu_txchan_intr(struct niu *np, struct tx_ring_info *rp,
4174                             int ldn)
4175 {
4176         rp->tx_cs = nr64(TX_CS(rp->tx_channel));
4177
4178         niudbg(INTR, "%s: txchan_intr cs[%llx]\n",
4179                np->dev->name, (unsigned long long) rp->tx_cs);
4180 }
4181
4182 static void __niu_fastpath_interrupt(struct niu *np, int ldg, u64 v0)
4183 {
4184         struct niu_parent *parent = np->parent;
4185         u32 rx_vec, tx_vec;
4186         int i;
4187
4188         tx_vec = (v0 >> 32);
4189         rx_vec = (v0 & 0xffffffff);
4190
4191         for (i = 0; i < np->num_rx_rings; i++) {
4192                 struct rx_ring_info *rp = &np->rx_rings[i];
4193                 int ldn = LDN_RXDMA(rp->rx_channel);
4194
4195                 if (parent->ldg_map[ldn] != ldg)
4196                         continue;
4197
4198                 nw64(LD_IM0(ldn), LD_IM0_MASK);
4199                 if (rx_vec & (1 << rp->rx_channel))
4200                         niu_rxchan_intr(np, rp, ldn);
4201         }
4202
4203         for (i = 0; i < np->num_tx_rings; i++) {
4204                 struct tx_ring_info *rp = &np->tx_rings[i];
4205                 int ldn = LDN_TXDMA(rp->tx_channel);
4206
4207                 if (parent->ldg_map[ldn] != ldg)
4208                         continue;
4209
4210                 nw64(LD_IM0(ldn), LD_IM0_MASK);
4211                 if (tx_vec & (1 << rp->tx_channel))
4212                         niu_txchan_intr(np, rp, ldn);
4213         }
4214 }
4215
4216 static void niu_schedule_napi(struct niu *np, struct niu_ldg *lp,
4217                               u64 v0, u64 v1, u64 v2)
4218 {
4219         if (likely(napi_schedule_prep(&lp->napi))) {
4220                 lp->v0 = v0;
4221                 lp->v1 = v1;
4222                 lp->v2 = v2;
4223                 __niu_fastpath_interrupt(np, lp->ldg_num, v0);
4224                 __napi_schedule(&lp->napi);
4225         }
4226 }
4227
4228 static irqreturn_t niu_interrupt(int irq, void *dev_id)
4229 {
4230         struct niu_ldg *lp = dev_id;
4231         struct niu *np = lp->np;
4232         int ldg = lp->ldg_num;
4233         unsigned long flags;
4234         u64 v0, v1, v2;
4235
4236         if (netif_msg_intr(np))
4237                 printk(KERN_DEBUG PFX "niu_interrupt() ldg[%p](%d) ",
4238                        lp, ldg);
4239
4240         spin_lock_irqsave(&np->lock, flags);
4241
4242         v0 = nr64(LDSV0(ldg));
4243         v1 = nr64(LDSV1(ldg));
4244         v2 = nr64(LDSV2(ldg));
4245
4246         if (netif_msg_intr(np))
4247                 printk("v0[%llx] v1[%llx] v2[%llx]\n",
4248                        (unsigned long long) v0,
4249                        (unsigned long long) v1,
4250                        (unsigned long long) v2);
4251
4252         if (unlikely(!v0 && !v1 && !v2)) {
4253                 spin_unlock_irqrestore(&np->lock, flags);
4254                 return IRQ_NONE;
4255         }
4256
4257         if (unlikely((v0 & ((u64)1 << LDN_MIF)) || v1 || v2)) {
4258                 int err = niu_slowpath_interrupt(np, lp, v0, v1, v2);
4259                 if (err)
4260                         goto out;
4261         }
4262         if (likely(v0 & ~((u64)1 << LDN_MIF)))
4263                 niu_schedule_napi(np, lp, v0, v1, v2);
4264         else
4265                 niu_ldg_rearm(np, lp, 1);
4266 out:
4267         spin_unlock_irqrestore(&np->lock, flags);
4268
4269         return IRQ_HANDLED;
4270 }
4271
4272 static void niu_free_rx_ring_info(struct niu *np, struct rx_ring_info *rp)
4273 {
4274         if (rp->mbox) {
4275                 np->ops->free_coherent(np->device,
4276                                        sizeof(struct rxdma_mailbox),
4277                                        rp->mbox, rp->mbox_dma);
4278                 rp->mbox = NULL;
4279         }
4280         if (rp->rcr) {
4281                 np->ops->free_coherent(np->device,
4282                                        MAX_RCR_RING_SIZE * sizeof(__le64),
4283                                        rp->rcr, rp->rcr_dma);
4284                 rp->rcr = NULL;
4285                 rp->rcr_table_size = 0;
4286                 rp->rcr_index = 0;
4287         }
4288         if (rp->rbr) {
4289                 niu_rbr_free(np, rp);
4290
4291                 np->ops->free_coherent(np->device,
4292                                        MAX_RBR_RING_SIZE * sizeof(__le32),
4293                                        rp->rbr, rp->rbr_dma);
4294                 rp->rbr = NULL;
4295                 rp->rbr_table_size = 0;
4296                 rp->rbr_index = 0;
4297         }
4298         kfree(rp->rxhash);
4299         rp->rxhash = NULL;
4300 }
4301
4302 static void niu_free_tx_ring_info(struct niu *np, struct tx_ring_info *rp)
4303 {
4304         if (rp->mbox) {
4305                 np->ops->free_coherent(np->device,
4306                                        sizeof(struct txdma_mailbox),
4307                                        rp->mbox, rp->mbox_dma);
4308                 rp->mbox = NULL;
4309         }
4310         if (rp->descr) {
4311                 int i;
4312
4313                 for (i = 0; i < MAX_TX_RING_SIZE; i++) {
4314                         if (rp->tx_buffs[i].skb)
4315                                 (void) release_tx_packet(np, rp, i);
4316                 }
4317
4318                 np->ops->free_coherent(np->device,
4319                                        MAX_TX_RING_SIZE * sizeof(__le64),
4320                                        rp->descr, rp->descr_dma);
4321                 rp->descr = NULL;
4322                 rp->pending = 0;
4323                 rp->prod = 0;
4324                 rp->cons = 0;
4325                 rp->wrap_bit = 0;
4326         }
4327 }
4328
4329 static void niu_free_channels(struct niu *np)
4330 {
4331         int i;
4332
4333         if (np->rx_rings) {
4334                 for (i = 0; i < np->num_rx_rings; i++) {
4335                         struct rx_ring_info *rp = &np->rx_rings[i];
4336
4337                         niu_free_rx_ring_info(np, rp);
4338                 }
4339                 kfree(np->rx_rings);
4340                 np->rx_rings = NULL;
4341                 np->num_rx_rings = 0;
4342         }
4343
4344         if (np->tx_rings) {
4345                 for (i = 0; i < np->num_tx_rings; i++) {
4346                         struct tx_ring_info *rp = &np->tx_rings[i];
4347
4348                         niu_free_tx_ring_info(np, rp);
4349                 }
4350                 kfree(np->tx_rings);
4351                 np->tx_rings = NULL;
4352                 np->num_tx_rings = 0;
4353         }
4354 }
4355
4356 static int niu_alloc_rx_ring_info(struct niu *np,
4357                                   struct rx_ring_info *rp)
4358 {
4359         BUILD_BUG_ON(sizeof(struct rxdma_mailbox) != 64);
4360
4361         rp->rxhash = kzalloc(MAX_RBR_RING_SIZE * sizeof(struct page *),
4362                              GFP_KERNEL);
4363         if (!rp->rxhash)
4364                 return -ENOMEM;
4365
4366         rp->mbox = np->ops->alloc_coherent(np->device,
4367                                            sizeof(struct rxdma_mailbox),
4368                                            &rp->mbox_dma, GFP_KERNEL);
4369         if (!rp->mbox)
4370                 return -ENOMEM;
4371         if ((unsigned long)rp->mbox & (64UL - 1)) {
4372                 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
4373                         "RXDMA mailbox %p\n", np->dev->name, rp->mbox);
4374                 return -EINVAL;
4375         }
4376
4377         rp->rcr = np->ops->alloc_coherent(np->device,
4378                                           MAX_RCR_RING_SIZE * sizeof(__le64),
4379                                           &rp->rcr_dma, GFP_KERNEL);
4380         if (!rp->rcr)
4381                 return -ENOMEM;
4382         if ((unsigned long)rp->rcr & (64UL - 1)) {
4383                 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
4384                         "RXDMA RCR table %p\n", np->dev->name, rp->rcr);
4385                 return -EINVAL;
4386         }
4387         rp->rcr_table_size = MAX_RCR_RING_SIZE;
4388         rp->rcr_index = 0;
4389
4390         rp->rbr = np->ops->alloc_coherent(np->device,
4391                                           MAX_RBR_RING_SIZE * sizeof(__le32),
4392                                           &rp->rbr_dma, GFP_KERNEL);
4393         if (!rp->rbr)
4394                 return -ENOMEM;
4395         if ((unsigned long)rp->rbr & (64UL - 1)) {
4396                 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
4397                         "RXDMA RBR table %p\n", np->dev->name, rp->rbr);
4398                 return -EINVAL;
4399         }
4400         rp->rbr_table_size = MAX_RBR_RING_SIZE;
4401         rp->rbr_index = 0;
4402         rp->rbr_pending = 0;
4403
4404         return 0;
4405 }
4406
4407 static void niu_set_max_burst(struct niu *np, struct tx_ring_info *rp)
4408 {
4409         int mtu = np->dev->mtu;
4410
4411         /* These values are recommended by the HW designers for fair
4412          * utilization of DRR amongst the rings.
4413          */
4414         rp->max_burst = mtu + 32;
4415         if (rp->max_burst > 4096)
4416                 rp->max_burst = 4096;
4417 }
4418
4419 static int niu_alloc_tx_ring_info(struct niu *np,
4420                                   struct tx_ring_info *rp)
4421 {
4422         BUILD_BUG_ON(sizeof(struct txdma_mailbox) != 64);
4423
4424         rp->mbox = np->ops->alloc_coherent(np->device,
4425                                            sizeof(struct txdma_mailbox),
4426                                            &rp->mbox_dma, GFP_KERNEL);
4427         if (!rp->mbox)
4428                 return -ENOMEM;
4429         if ((unsigned long)rp->mbox & (64UL - 1)) {
4430                 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
4431                         "TXDMA mailbox %p\n", np->dev->name, rp->mbox);
4432                 return -EINVAL;
4433         }
4434
4435         rp->descr = np->ops->alloc_coherent(np->device,
4436                                             MAX_TX_RING_SIZE * sizeof(__le64),
4437                                             &rp->descr_dma, GFP_KERNEL);
4438         if (!rp->descr)
4439                 return -ENOMEM;
4440         if ((unsigned long)rp->descr & (64UL - 1)) {
4441                 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
4442                         "TXDMA descr table %p\n", np->dev->name, rp->descr);
4443                 return -EINVAL;
4444         }
4445
4446         rp->pending = MAX_TX_RING_SIZE;
4447         rp->prod = 0;
4448         rp->cons = 0;
4449         rp->wrap_bit = 0;
4450
4451         /* XXX make these configurable... XXX */
4452         rp->mark_freq = rp->pending / 4;
4453
4454         niu_set_max_burst(np, rp);
4455
4456         return 0;
4457 }
4458
4459 static void niu_size_rbr(struct niu *np, struct rx_ring_info *rp)
4460 {
4461         u16 bss;
4462
4463         bss = min(PAGE_SHIFT, 15);
4464
4465         rp->rbr_block_size = 1 << bss;
4466         rp->rbr_blocks_per_page = 1 << (PAGE_SHIFT-bss);
4467
4468         rp->rbr_sizes[0] = 256;
4469         rp->rbr_sizes[1] = 1024;
4470         if (np->dev->mtu > ETH_DATA_LEN) {
4471                 switch (PAGE_SIZE) {
4472                 case 4 * 1024:
4473                         rp->rbr_sizes[2] = 4096;
4474                         break;
4475
4476                 default:
4477                         rp->rbr_sizes[2] = 8192;
4478                         break;
4479                 }
4480         } else {
4481                 rp->rbr_sizes[2] = 2048;
4482         }
4483         rp->rbr_sizes[3] = rp->rbr_block_size;
4484 }
4485
4486 static int niu_alloc_channels(struct niu *np)
4487 {
4488         struct niu_parent *parent = np->parent;
4489         int first_rx_channel, first_tx_channel;
4490         int i, port, err;
4491
4492         port = np->port;
4493         first_rx_channel = first_tx_channel = 0;
4494         for (i = 0; i < port; i++) {
4495                 first_rx_channel += parent->rxchan_per_port[i];
4496                 first_tx_channel += parent->txchan_per_port[i];
4497         }
4498
4499         np->num_rx_rings = parent->rxchan_per_port[port];
4500         np->num_tx_rings = parent->txchan_per_port[port];
4501
4502         np->dev->real_num_tx_queues = np->num_tx_rings;
4503
4504         np->rx_rings = kzalloc(np->num_rx_rings * sizeof(struct rx_ring_info),
4505                                GFP_KERNEL);
4506         err = -ENOMEM;
4507         if (!np->rx_rings)
4508                 goto out_err;
4509
4510         for (i = 0; i < np->num_rx_rings; i++) {
4511                 struct rx_ring_info *rp = &np->rx_rings[i];
4512
4513                 rp->np = np;
4514                 rp->rx_channel = first_rx_channel + i;
4515
4516                 err = niu_alloc_rx_ring_info(np, rp);
4517                 if (err)
4518                         goto out_err;
4519
4520                 niu_size_rbr(np, rp);
4521
4522                 /* XXX better defaults, configurable, etc... XXX */
4523                 rp->nonsyn_window = 64;
4524                 rp->nonsyn_threshold = rp->rcr_table_size - 64;
4525                 rp->syn_window = 64;
4526                 rp->syn_threshold = rp->rcr_table_size - 64;
4527                 rp->rcr_pkt_threshold = 16;
4528                 rp->rcr_timeout = 8;
4529                 rp->rbr_kick_thresh = RBR_REFILL_MIN;
4530                 if (rp->rbr_kick_thresh < rp->rbr_blocks_per_page)
4531                         rp->rbr_kick_thresh = rp->rbr_blocks_per_page;
4532
4533                 err = niu_rbr_fill(np, rp, GFP_KERNEL);
4534                 if (err)
4535                         return err;
4536         }
4537
4538         np->tx_rings = kzalloc(np->num_tx_rings * sizeof(struct tx_ring_info),
4539                                GFP_KERNEL);
4540         err = -ENOMEM;
4541         if (!np->tx_rings)
4542                 goto out_err;
4543
4544         for (i = 0; i < np->num_tx_rings; i++) {
4545                 struct tx_ring_info *rp = &np->tx_rings[i];
4546
4547                 rp->np = np;
4548                 rp->tx_channel = first_tx_channel + i;
4549
4550                 err = niu_alloc_tx_ring_info(np, rp);
4551                 if (err)
4552                         goto out_err;
4553         }
4554
4555         return 0;
4556
4557 out_err:
4558         niu_free_channels(np);
4559         return err;
4560 }
4561
4562 static int niu_tx_cs_sng_poll(struct niu *np, int channel)
4563 {
4564         int limit = 1000;
4565
4566         while (--limit > 0) {
4567                 u64 val = nr64(TX_CS(channel));
4568                 if (val & TX_CS_SNG_STATE)
4569                         return 0;
4570         }
4571         return -ENODEV;
4572 }
4573
4574 static int niu_tx_channel_stop(struct niu *np, int channel)
4575 {
4576         u64 val = nr64(TX_CS(channel));
4577
4578         val |= TX_CS_STOP_N_GO;
4579         nw64(TX_CS(channel), val);
4580
4581         return niu_tx_cs_sng_poll(np, channel);
4582 }
4583
4584 static int niu_tx_cs_reset_poll(struct niu *np, int channel)
4585 {
4586         int limit = 1000;
4587
4588         while (--limit > 0) {
4589                 u64 val = nr64(TX_CS(channel));
4590                 if (!(val & TX_CS_RST))
4591                         return 0;
4592         }
4593         return -ENODEV;
4594 }
4595
4596 static int niu_tx_channel_reset(struct niu *np, int channel)
4597 {
4598         u64 val = nr64(TX_CS(channel));
4599         int err;
4600
4601         val |= TX_CS_RST;
4602         nw64(TX_CS(channel), val);
4603
4604         err = niu_tx_cs_reset_poll(np, channel);
4605         if (!err)
4606                 nw64(TX_RING_KICK(channel), 0);
4607
4608         return err;
4609 }
4610
4611 static int niu_tx_channel_lpage_init(struct niu *np, int channel)
4612 {
4613         u64 val;
4614
4615         nw64(TX_LOG_MASK1(channel), 0);
4616         nw64(TX_LOG_VAL1(channel), 0);
4617         nw64(TX_LOG_MASK2(channel), 0);
4618         nw64(TX_LOG_VAL2(channel), 0);
4619         nw64(TX_LOG_PAGE_RELO1(channel), 0);
4620         nw64(TX_LOG_PAGE_RELO2(channel), 0);
4621         nw64(TX_LOG_PAGE_HDL(channel), 0);
4622
4623         val  = (u64)np->port << TX_LOG_PAGE_VLD_FUNC_SHIFT;
4624         val |= (TX_LOG_PAGE_VLD_PAGE0 | TX_LOG_PAGE_VLD_PAGE1);
4625         nw64(TX_LOG_PAGE_VLD(channel), val);
4626
4627         /* XXX TXDMA 32bit mode? XXX */
4628
4629         return 0;
4630 }
4631
4632 static void niu_txc_enable_port(struct niu *np, int on)
4633 {
4634         unsigned long flags;
4635         u64 val, mask;
4636
4637         niu_lock_parent(np, flags);
4638         val = nr64(TXC_CONTROL);
4639         mask = (u64)1 << np->port;
4640         if (on) {
4641                 val |= TXC_CONTROL_ENABLE | mask;
4642         } else {
4643                 val &= ~mask;
4644                 if ((val & ~TXC_CONTROL_ENABLE) == 0)
4645                         val &= ~TXC_CONTROL_ENABLE;
4646         }
4647         nw64(TXC_CONTROL, val);
4648         niu_unlock_parent(np, flags);
4649 }
4650
4651 static void niu_txc_set_imask(struct niu *np, u64 imask)
4652 {
4653         unsigned long flags;
4654         u64 val;
4655
4656         niu_lock_parent(np, flags);
4657         val = nr64(TXC_INT_MASK);
4658         val &= ~TXC_INT_MASK_VAL(np->port);
4659         val |= (imask << TXC_INT_MASK_VAL_SHIFT(np->port));
4660         niu_unlock_parent(np, flags);
4661 }
4662
4663 static void niu_txc_port_dma_enable(struct niu *np, int on)
4664 {
4665         u64 val = 0;
4666
4667         if (on) {
4668                 int i;
4669
4670                 for (i = 0; i < np->num_tx_rings; i++)
4671                         val |= (1 << np->tx_rings[i].tx_channel);
4672         }
4673         nw64(TXC_PORT_DMA(np->port), val);
4674 }
4675
4676 static int niu_init_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
4677 {
4678         int err, channel = rp->tx_channel;
4679         u64 val, ring_len;
4680
4681         err = niu_tx_channel_stop(np, channel);
4682         if (err)
4683                 return err;
4684
4685         err = niu_tx_channel_reset(np, channel);
4686         if (err)
4687                 return err;
4688
4689         err = niu_tx_channel_lpage_init(np, channel);
4690         if (err)
4691                 return err;
4692
4693         nw64(TXC_DMA_MAX(channel), rp->max_burst);
4694         nw64(TX_ENT_MSK(channel), 0);
4695
4696         if (rp->descr_dma & ~(TX_RNG_CFIG_STADDR_BASE |
4697                               TX_RNG_CFIG_STADDR)) {
4698                 dev_err(np->device, PFX "%s: TX ring channel %d "
4699                         "DMA addr (%llx) is not aligned.\n",
4700                         np->dev->name, channel,
4701                         (unsigned long long) rp->descr_dma);
4702                 return -EINVAL;
4703         }
4704
4705         /* The length field in TX_RNG_CFIG is measured in 64-byte
4706          * blocks.  rp->pending is the number of TX descriptors in
4707          * our ring, 8 bytes each, thus we divide by 8 bytes more
4708          * to get the proper value the chip wants.
4709          */
4710         ring_len = (rp->pending / 8);
4711
4712         val = ((ring_len << TX_RNG_CFIG_LEN_SHIFT) |
4713                rp->descr_dma);
4714         nw64(TX_RNG_CFIG(channel), val);
4715
4716         if (((rp->mbox_dma >> 32) & ~TXDMA_MBH_MBADDR) ||
4717             ((u32)rp->mbox_dma & ~TXDMA_MBL_MBADDR)) {
4718                 dev_err(np->device, PFX "%s: TX ring channel %d "
4719                         "MBOX addr (%llx) is has illegal bits.\n",
4720                         np->dev->name, channel,
4721                         (unsigned long long) rp->mbox_dma);
4722                 return -EINVAL;
4723         }
4724         nw64(TXDMA_MBH(channel), rp->mbox_dma >> 32);
4725         nw64(TXDMA_MBL(channel), rp->mbox_dma & TXDMA_MBL_MBADDR);
4726
4727         nw64(TX_CS(channel), 0);
4728
4729         rp->last_pkt_cnt = 0;
4730
4731         return 0;
4732 }
4733
4734 static void niu_init_rdc_groups(struct niu *np)
4735 {
4736         struct niu_rdc_tables *tp = &np->parent->rdc_group_cfg[np->port];
4737         int i, first_table_num = tp->first_table_num;
4738
4739         for (i = 0; i < tp->num_tables; i++) {
4740                 struct rdc_table *tbl = &tp->tables[i];
4741                 int this_table = first_table_num + i;
4742                 int slot;
4743
4744                 for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++)
4745                         nw64(RDC_TBL(this_table, slot),
4746                              tbl->rxdma_channel[slot]);
4747         }
4748
4749         nw64(DEF_RDC(np->port), np->parent->rdc_default[np->port]);
4750 }
4751
4752 static void niu_init_drr_weight(struct niu *np)
4753 {
4754         int type = phy_decode(np->parent->port_phy, np->port);
4755         u64 val;
4756
4757         switch (type) {
4758         case PORT_TYPE_10G:
4759                 val = PT_DRR_WEIGHT_DEFAULT_10G;
4760                 break;
4761
4762         case PORT_TYPE_1G:
4763         default:
4764                 val = PT_DRR_WEIGHT_DEFAULT_1G;
4765                 break;
4766         }
4767         nw64(PT_DRR_WT(np->port), val);
4768 }
4769
4770 static int niu_init_hostinfo(struct niu *np)
4771 {
4772         struct niu_parent *parent = np->parent;
4773         struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
4774         int i, err, num_alt = niu_num_alt_addr(np);
4775         int first_rdc_table = tp->first_table_num;
4776
4777         err = niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
4778         if (err)
4779                 return err;
4780
4781         err = niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
4782         if (err)
4783                 return err;
4784
4785         for (i = 0; i < num_alt; i++) {
4786                 err = niu_set_alt_mac_rdc_table(np, i, first_rdc_table, 1);
4787                 if (err)
4788                         return err;
4789         }
4790
4791         return 0;
4792 }
4793
4794 static int niu_rx_channel_reset(struct niu *np, int channel)
4795 {
4796         return niu_set_and_wait_clear(np, RXDMA_CFIG1(channel),
4797                                       RXDMA_CFIG1_RST, 1000, 10,
4798                                       "RXDMA_CFIG1");
4799 }
4800
4801 static int niu_rx_channel_lpage_init(struct niu *np, int channel)
4802 {
4803         u64 val;
4804
4805         nw64(RX_LOG_MASK1(channel), 0);
4806         nw64(RX_LOG_VAL1(channel), 0);
4807         nw64(RX_LOG_MASK2(channel), 0);
4808         nw64(RX_LOG_VAL2(channel), 0);
4809         nw64(RX_LOG_PAGE_RELO1(channel), 0);
4810         nw64(RX_LOG_PAGE_RELO2(channel), 0);
4811         nw64(RX_LOG_PAGE_HDL(channel), 0);
4812
4813         val  = (u64)np->port << RX_LOG_PAGE_VLD_FUNC_SHIFT;
4814         val |= (RX_LOG_PAGE_VLD_PAGE0 | RX_LOG_PAGE_VLD_PAGE1);
4815         nw64(RX_LOG_PAGE_VLD(channel), val);
4816
4817         return 0;
4818 }
4819
4820 static void niu_rx_channel_wred_init(struct niu *np, struct rx_ring_info *rp)
4821 {
4822         u64 val;
4823
4824         val = (((u64)rp->nonsyn_window << RDC_RED_PARA_WIN_SHIFT) |
4825                ((u64)rp->nonsyn_threshold << RDC_RED_PARA_THRE_SHIFT) |
4826                ((u64)rp->syn_window << RDC_RED_PARA_WIN_SYN_SHIFT) |
4827                ((u64)rp->syn_threshold << RDC_RED_PARA_THRE_SYN_SHIFT));
4828         nw64(RDC_RED_PARA(rp->rx_channel), val);
4829 }
4830
4831 static int niu_compute_rbr_cfig_b(struct rx_ring_info *rp, u64 *ret)
4832 {
4833         u64 val = 0;
4834
4835         switch (rp->rbr_block_size) {
4836         case 4 * 1024:
4837                 val |= (RBR_BLKSIZE_4K << RBR_CFIG_B_BLKSIZE_SHIFT);
4838                 break;
4839         case 8 * 1024:
4840                 val |= (RBR_BLKSIZE_8K << RBR_CFIG_B_BLKSIZE_SHIFT);
4841                 break;
4842         case 16 * 1024:
4843                 val |= (RBR_BLKSIZE_16K << RBR_CFIG_B_BLKSIZE_SHIFT);
4844                 break;
4845         case 32 * 1024:
4846                 val |= (RBR_BLKSIZE_32K << RBR_CFIG_B_BLKSIZE_SHIFT);
4847                 break;
4848         default:
4849                 return -EINVAL;
4850         }
4851         val |= RBR_CFIG_B_VLD2;
4852         switch (rp->rbr_sizes[2]) {
4853         case 2 * 1024:
4854                 val |= (RBR_BUFSZ2_2K << RBR_CFIG_B_BUFSZ2_SHIFT);
4855                 break;
4856         case 4 * 1024:
4857                 val |= (RBR_BUFSZ2_4K << RBR_CFIG_B_BUFSZ2_SHIFT);
4858                 break;
4859         case 8 * 1024:
4860                 val |= (RBR_BUFSZ2_8K << RBR_CFIG_B_BUFSZ2_SHIFT);
4861                 break;
4862         case 16 * 1024:
4863                 val |= (RBR_BUFSZ2_16K << RBR_CFIG_B_BUFSZ2_SHIFT);
4864                 break;
4865
4866         default:
4867                 return -EINVAL;
4868         }
4869         val |= RBR_CFIG_B_VLD1;
4870         switch (rp->rbr_sizes[1]) {
4871         case 1 * 1024:
4872                 val |= (RBR_BUFSZ1_1K << RBR_CFIG_B_BUFSZ1_SHIFT);
4873                 break;
4874         case 2 * 1024:
4875                 val |= (RBR_BUFSZ1_2K << RBR_CFIG_B_BUFSZ1_SHIFT);
4876                 break;
4877         case 4 * 1024:
4878                 val |= (RBR_BUFSZ1_4K << RBR_CFIG_B_BUFSZ1_SHIFT);
4879                 break;
4880         case 8 * 1024:
4881                 val |= (RBR_BUFSZ1_8K << RBR_CFIG_B_BUFSZ1_SHIFT);
4882                 break;
4883
4884         default:
4885                 return -EINVAL;
4886         }
4887         val |= RBR_CFIG_B_VLD0;
4888         switch (rp->rbr_sizes[0]) {
4889         case 256:
4890                 val |= (RBR_BUFSZ0_256 << RBR_CFIG_B_BUFSZ0_SHIFT);
4891                 break;
4892         case 512:
4893                 val |= (RBR_BUFSZ0_512 << RBR_CFIG_B_BUFSZ0_SHIFT);
4894                 break;
4895         case 1 * 1024:
4896                 val |= (RBR_BUFSZ0_1K << RBR_CFIG_B_BUFSZ0_SHIFT);
4897                 break;
4898         case 2 * 1024:
4899                 val |= (RBR_BUFSZ0_2K << RBR_CFIG_B_BUFSZ0_SHIFT);
4900                 break;
4901
4902         default:
4903                 return -EINVAL;
4904         }
4905
4906         *ret = val;
4907         return 0;
4908 }
4909
4910 static int niu_enable_rx_channel(struct niu *np, int channel, int on)
4911 {
4912         u64 val = nr64(RXDMA_CFIG1(channel));
4913         int limit;
4914
4915         if (on)
4916                 val |= RXDMA_CFIG1_EN;
4917         else
4918                 val &= ~RXDMA_CFIG1_EN;
4919         nw64(RXDMA_CFIG1(channel), val);
4920
4921         limit = 1000;
4922         while (--limit > 0) {
4923                 if (nr64(RXDMA_CFIG1(channel)) & RXDMA_CFIG1_QST)
4924                         break;
4925                 udelay(10);
4926         }
4927         if (limit <= 0)
4928                 return -ENODEV;
4929         return 0;
4930 }
4931
4932 static int niu_init_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
4933 {
4934         int err, channel = rp->rx_channel;
4935         u64 val;
4936
4937         err = niu_rx_channel_reset(np, channel);
4938         if (err)
4939                 return err;
4940
4941         err = niu_rx_channel_lpage_init(np, channel);
4942         if (err)
4943                 return err;
4944
4945         niu_rx_channel_wred_init(np, rp);
4946
4947         nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_RBR_EMPTY);
4948         nw64(RX_DMA_CTL_STAT(channel),
4949              (RX_DMA_CTL_STAT_MEX |
4950               RX_DMA_CTL_STAT_RCRTHRES |
4951               RX_DMA_CTL_STAT_RCRTO |
4952               RX_DMA_CTL_STAT_RBR_EMPTY));
4953         nw64(RXDMA_CFIG1(channel), rp->mbox_dma >> 32);
4954         nw64(RXDMA_CFIG2(channel), (rp->mbox_dma & 0x00000000ffffffc0));
4955         nw64(RBR_CFIG_A(channel),
4956              ((u64)rp->rbr_table_size << RBR_CFIG_A_LEN_SHIFT) |
4957              (rp->rbr_dma & (RBR_CFIG_A_STADDR_BASE | RBR_CFIG_A_STADDR)));
4958         err = niu_compute_rbr_cfig_b(rp, &val);
4959         if (err)
4960                 return err;
4961         nw64(RBR_CFIG_B(channel), val);
4962         nw64(RCRCFIG_A(channel),
4963              ((u64)rp->rcr_table_size << RCRCFIG_A_LEN_SHIFT) |
4964              (rp->rcr_dma & (RCRCFIG_A_STADDR_BASE | RCRCFIG_A_STADDR)));
4965         nw64(RCRCFIG_B(channel),
4966              ((u64)rp->rcr_pkt_threshold << RCRCFIG_B_PTHRES_SHIFT) |
4967              RCRCFIG_B_ENTOUT |
4968              ((u64)rp->rcr_timeout << RCRCFIG_B_TIMEOUT_SHIFT));
4969
4970         err = niu_enable_rx_channel(np, channel, 1);
4971         if (err)
4972                 return err;
4973
4974         nw64(RBR_KICK(channel), rp->rbr_index);
4975
4976         val = nr64(RX_DMA_CTL_STAT(channel));
4977         val |= RX_DMA_CTL_STAT_RBR_EMPTY;
4978         nw64(RX_DMA_CTL_STAT(channel), val);
4979
4980         return 0;
4981 }
4982
4983 static int niu_init_rx_channels(struct niu *np)
4984 {
4985         unsigned long flags;
4986         u64 seed = jiffies_64;
4987         int err, i;
4988
4989         niu_lock_parent(np, flags);
4990         nw64(RX_DMA_CK_DIV, np->parent->rxdma_clock_divider);
4991         nw64(RED_RAN_INIT, RED_RAN_INIT_OPMODE | (seed & RED_RAN_INIT_VAL));
4992         niu_unlock_parent(np, flags);
4993
4994         /* XXX RXDMA 32bit mode? XXX */
4995
4996         niu_init_rdc_groups(np);
4997         niu_init_drr_weight(np);
4998
4999         err = niu_init_hostinfo(np);
5000         if (err)
5001                 return err;
5002
5003         for (i = 0; i < np->num_rx_rings; i++) {
5004                 struct rx_ring_info *rp = &np->rx_rings[i];
5005
5006                 err = niu_init_one_rx_channel(np, rp);
5007                 if (err)
5008                         return err;
5009         }
5010
5011         return 0;
5012 }
5013
5014 static int niu_set_ip_frag_rule(struct niu *np)
5015 {
5016         struct niu_parent *parent = np->parent;
5017         struct niu_classifier *cp = &np->clas;
5018         struct niu_tcam_entry *tp;
5019         int index, err;
5020
5021         index = cp->tcam_top;
5022         tp = &parent->tcam[index];
5023
5024         /* Note that the noport bit is the same in both ipv4 and
5025          * ipv6 format TCAM entries.
5026          */
5027         memset(tp, 0, sizeof(*tp));
5028         tp->key[1] = TCAM_V4KEY1_NOPORT;
5029         tp->key_mask[1] = TCAM_V4KEY1_NOPORT;
5030         tp->assoc_data = (TCAM_ASSOCDATA_TRES_USE_OFFSET |
5031                           ((u64)0 << TCAM_ASSOCDATA_OFFSET_SHIFT));
5032         err = tcam_write(np, index, tp->key, tp->key_mask);
5033         if (err)
5034                 return err;
5035         err = tcam_assoc_write(np, index, tp->assoc_data);
5036         if (err)
5037                 return err;
5038         tp->valid = 1;
5039         cp->tcam_valid_entries++;
5040
5041         return 0;
5042 }
5043
5044 static int niu_init_classifier_hw(struct niu *np)
5045 {
5046         struct niu_parent *parent = np->parent;
5047         struct niu_classifier *cp = &np->clas;
5048         int i, err;
5049
5050         nw64(H1POLY, cp->h1_init);
5051         nw64(H2POLY, cp->h2_init);
5052
5053         err = niu_init_hostinfo(np);
5054         if (err)
5055                 return err;
5056
5057         for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++) {
5058                 struct niu_vlan_rdc *vp = &cp->vlan_mappings[i];
5059
5060                 vlan_tbl_write(np, i, np->port,
5061                                vp->vlan_pref, vp->rdc_num);
5062         }
5063
5064         for (i = 0; i < cp->num_alt_mac_mappings; i++) {
5065                 struct niu_altmac_rdc *ap = &cp->alt_mac_mappings[i];
5066
5067                 err = niu_set_alt_mac_rdc_table(np, ap->alt_mac_num,
5068                                                 ap->rdc_num, ap->mac_pref);
5069                 if (err)
5070                         return err;
5071         }
5072
5073         for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) {
5074                 int index = i - CLASS_CODE_USER_PROG1;
5075
5076                 err = niu_set_tcam_key(np, i, parent->tcam_key[index]);
5077                 if (err)
5078                         return err;
5079                 err = niu_set_flow_key(np, i, parent->flow_key[index]);
5080                 if (err)
5081                         return err;
5082         }
5083
5084         err = niu_set_ip_frag_rule(np);
5085         if (err)
5086                 return err;
5087
5088         tcam_enable(np, 1);
5089
5090         return 0;
5091 }
5092
5093 static int niu_zcp_write(struct niu *np, int index, u64 *data)
5094 {
5095         nw64(ZCP_RAM_DATA0, data[0]);
5096         nw64(ZCP_RAM_DATA1, data[1]);
5097         nw64(ZCP_RAM_DATA2, data[2]);
5098         nw64(ZCP_RAM_DATA3, data[3]);
5099         nw64(ZCP_RAM_DATA4, data[4]);
5100         nw64(ZCP_RAM_BE, ZCP_RAM_BE_VAL);
5101         nw64(ZCP_RAM_ACC,
5102              (ZCP_RAM_ACC_WRITE |
5103               (0 << ZCP_RAM_ACC_ZFCID_SHIFT) |
5104               (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
5105
5106         return niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5107                                    1000, 100);
5108 }
5109
5110 static int niu_zcp_read(struct niu *np, int index, u64 *data)
5111 {
5112         int err;
5113
5114         err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5115                                   1000, 100);
5116         if (err) {
5117                 dev_err(np->device, PFX "%s: ZCP read busy won't clear, "
5118                         "ZCP_RAM_ACC[%llx]\n", np->dev->name,
5119                         (unsigned long long) nr64(ZCP_RAM_ACC));
5120                 return err;
5121         }
5122
5123         nw64(ZCP_RAM_ACC,
5124              (ZCP_RAM_ACC_READ |
5125               (0 << ZCP_RAM_ACC_ZFCID_SHIFT) |
5126               (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
5127
5128         err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5129                                   1000, 100);
5130         if (err) {
5131                 dev_err(np->device, PFX "%s: ZCP read busy2 won't clear, "
5132                         "ZCP_RAM_ACC[%llx]\n", np->dev->name,
5133                         (unsigned long long) nr64(ZCP_RAM_ACC));
5134                 return err;
5135         }
5136
5137         data[0] = nr64(ZCP_RAM_DATA0);
5138         data[1] = nr64(ZCP_RAM_DATA1);
5139         data[2] = nr64(ZCP_RAM_DATA2);
5140         data[3] = nr64(ZCP_RAM_DATA3);
5141         data[4] = nr64(ZCP_RAM_DATA4);
5142
5143         return 0;
5144 }
5145
5146 static void niu_zcp_cfifo_reset(struct niu *np)
5147 {
5148         u64 val = nr64(RESET_CFIFO);
5149
5150         val |= RESET_CFIFO_RST(np->port);
5151         nw64(RESET_CFIFO, val);
5152         udelay(10);
5153
5154         val &= ~RESET_CFIFO_RST(np->port);
5155         nw64(RESET_CFIFO, val);
5156 }
5157
5158 static int niu_init_zcp(struct niu *np)
5159 {
5160         u64 data[5], rbuf[5];
5161         int i, max, err;
5162
5163         if (np->parent->plat_type != PLAT_TYPE_NIU) {
5164                 if (np->port == 0 || np->port == 1)
5165                         max = ATLAS_P0_P1_CFIFO_ENTRIES;
5166                 else
5167                         max = ATLAS_P2_P3_CFIFO_ENTRIES;
5168         } else
5169                 max = NIU_CFIFO_ENTRIES;
5170
5171         data[0] = 0;
5172         data[1] = 0;
5173         data[2] = 0;
5174         data[3] = 0;
5175         data[4] = 0;
5176
5177         for (i = 0; i < max; i++) {
5178                 err = niu_zcp_write(np, i, data);
5179                 if (err)
5180                         return err;
5181                 err = niu_zcp_read(np, i, rbuf);
5182                 if (err)
5183                         return err;
5184         }
5185
5186         niu_zcp_cfifo_reset(np);
5187         nw64(CFIFO_ECC(np->port), 0);
5188         nw64(ZCP_INT_STAT, ZCP_INT_STAT_ALL);
5189         (void) nr64(ZCP_INT_STAT);
5190         nw64(ZCP_INT_MASK, ZCP_INT_MASK_ALL);
5191
5192         return 0;
5193 }
5194
5195 static void niu_ipp_write(struct niu *np, int index, u64 *data)
5196 {
5197         u64 val = nr64_ipp(IPP_CFIG);
5198
5199         nw64_ipp(IPP_CFIG, val | IPP_CFIG_DFIFO_PIO_W);
5200         nw64_ipp(IPP_DFIFO_WR_PTR, index);
5201         nw64_ipp(IPP_DFIFO_WR0, data[0]);
5202         nw64_ipp(IPP_DFIFO_WR1, data[1]);
5203         nw64_ipp(IPP_DFIFO_WR2, data[2]);
5204         nw64_ipp(IPP_DFIFO_WR3, data[3]);
5205         nw64_ipp(IPP_DFIFO_WR4, data[4]);
5206         nw64_ipp(IPP_CFIG, val & ~IPP_CFIG_DFIFO_PIO_W);
5207 }
5208
5209 static void niu_ipp_read(struct niu *np, int index, u64 *data)
5210 {
5211         nw64_ipp(IPP_DFIFO_RD_PTR, index);
5212         data[0] = nr64_ipp(IPP_DFIFO_RD0);
5213         data[1] = nr64_ipp(IPP_DFIFO_RD1);
5214         data[2] = nr64_ipp(IPP_DFIFO_RD2);
5215         data[3] = nr64_ipp(IPP_DFIFO_RD3);
5216         data[4] = nr64_ipp(IPP_DFIFO_RD4);
5217 }
5218
5219 static int niu_ipp_reset(struct niu *np)
5220 {
5221         return niu_set_and_wait_clear_ipp(np, IPP_CFIG, IPP_CFIG_SOFT_RST,
5222                                           1000, 100, "IPP_CFIG");
5223 }
5224
5225 static int niu_init_ipp(struct niu *np)
5226 {
5227         u64 data[5], rbuf[5], val;
5228         int i, max, err;
5229
5230         if (np->parent->plat_type != PLAT_TYPE_NIU) {
5231                 if (np->port == 0 || np->port == 1)
5232                         max = ATLAS_P0_P1_DFIFO_ENTRIES;
5233                 else
5234                         max = ATLAS_P2_P3_DFIFO_ENTRIES;
5235         } else
5236                 max = NIU_DFIFO_ENTRIES;
5237
5238         data[0] = 0;
5239         data[1] = 0;
5240         data[2] = 0;
5241         data[3] = 0;
5242         data[4] = 0;
5243
5244         for (i = 0; i < max; i++) {
5245                 niu_ipp_write(np, i, data);
5246                 niu_ipp_read(np, i, rbuf);
5247         }
5248
5249         (void) nr64_ipp(IPP_INT_STAT);
5250         (void) nr64_ipp(IPP_INT_STAT);
5251
5252         err = niu_ipp_reset(np);
5253         if (err)
5254                 return err;
5255
5256         (void) nr64_ipp(IPP_PKT_DIS);
5257         (void) nr64_ipp(IPP_BAD_CS_CNT);
5258         (void) nr64_ipp(IPP_ECC);
5259
5260         (void) nr64_ipp(IPP_INT_STAT);
5261
5262         nw64_ipp(IPP_MSK, ~IPP_MSK_ALL);
5263
5264         val = nr64_ipp(IPP_CFIG);
5265         val &= ~IPP_CFIG_IP_MAX_PKT;
5266         val |= (IPP_CFIG_IPP_ENABLE |
5267                 IPP_CFIG_DFIFO_ECC_EN |
5268                 IPP_CFIG_DROP_BAD_CRC |
5269                 IPP_CFIG_CKSUM_EN |
5270                 (0x1ffff << IPP_CFIG_IP_MAX_PKT_SHIFT));
5271         nw64_ipp(IPP_CFIG, val);
5272
5273         return 0;
5274 }
5275
5276 static void niu_handle_led(struct niu *np, int status)
5277 {
5278         u64 val;
5279         val = nr64_mac(XMAC_CONFIG);
5280
5281         if ((np->flags & NIU_FLAGS_10G) != 0 &&
5282             (np->flags & NIU_FLAGS_FIBER) != 0) {
5283                 if (status) {
5284                         val |= XMAC_CONFIG_LED_POLARITY;
5285                         val &= ~XMAC_CONFIG_FORCE_LED_ON;
5286                 } else {
5287                         val |= XMAC_CONFIG_FORCE_LED_ON;
5288                         val &= ~XMAC_CONFIG_LED_POLARITY;
5289                 }
5290         }
5291
5292         nw64_mac(XMAC_CONFIG, val);
5293 }
5294
5295 static void niu_init_xif_xmac(struct niu *np)
5296 {
5297         struct niu_link_config *lp = &np->link_config;
5298         u64 val;
5299
5300         if (np->flags & NIU_FLAGS_XCVR_SERDES) {
5301                 val = nr64(MIF_CONFIG);
5302                 val |= MIF_CONFIG_ATCA_GE;
5303                 nw64(MIF_CONFIG, val);
5304         }
5305
5306         val = nr64_mac(XMAC_CONFIG);
5307         val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
5308
5309         val |= XMAC_CONFIG_TX_OUTPUT_EN;
5310
5311         if (lp->loopback_mode == LOOPBACK_MAC) {
5312                 val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
5313                 val |= XMAC_CONFIG_LOOPBACK;
5314         } else {
5315                 val &= ~XMAC_CONFIG_LOOPBACK;
5316         }
5317
5318         if (np->flags & NIU_FLAGS_10G) {
5319                 val &= ~XMAC_CONFIG_LFS_DISABLE;
5320         } else {
5321                 val |= XMAC_CONFIG_LFS_DISABLE;
5322                 if (!(np->flags & NIU_FLAGS_FIBER) &&
5323                     !(np->flags & NIU_FLAGS_XCVR_SERDES))
5324                         val |= XMAC_CONFIG_1G_PCS_BYPASS;
5325                 else
5326                         val &= ~XMAC_CONFIG_1G_PCS_BYPASS;
5327         }
5328
5329         val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
5330
5331         if (lp->active_speed == SPEED_100)
5332                 val |= XMAC_CONFIG_SEL_CLK_25MHZ;
5333         else
5334                 val &= ~XMAC_CONFIG_SEL_CLK_25MHZ;
5335
5336         nw64_mac(XMAC_CONFIG, val);
5337
5338         val = nr64_mac(XMAC_CONFIG);
5339         val &= ~XMAC_CONFIG_MODE_MASK;
5340         if (np->flags & NIU_FLAGS_10G) {
5341                 val |= XMAC_CONFIG_MODE_XGMII;
5342         } else {
5343                 if (lp->active_speed == SPEED_1000)
5344                         val |= XMAC_CONFIG_MODE_GMII;
5345                 else
5346                         val |= XMAC_CONFIG_MODE_MII;
5347         }
5348
5349         nw64_mac(XMAC_CONFIG, val);
5350 }
5351
5352 static void niu_init_xif_bmac(struct niu *np)
5353 {
5354         struct niu_link_config *lp = &np->link_config;
5355         u64 val;
5356
5357         val = BMAC_XIF_CONFIG_TX_OUTPUT_EN;
5358
5359         if (lp->loopback_mode == LOOPBACK_MAC)
5360                 val |= BMAC_XIF_CONFIG_MII_LOOPBACK;
5361         else
5362                 val &= ~BMAC_XIF_CONFIG_MII_LOOPBACK;
5363
5364         if (lp->active_speed == SPEED_1000)
5365                 val |= BMAC_XIF_CONFIG_GMII_MODE;
5366         else
5367                 val &= ~BMAC_XIF_CONFIG_GMII_MODE;
5368
5369         val &= ~(BMAC_XIF_CONFIG_LINK_LED |
5370                  BMAC_XIF_CONFIG_LED_POLARITY);
5371
5372         if (!(np->flags & NIU_FLAGS_10G) &&
5373             !(np->flags & NIU_FLAGS_FIBER) &&
5374             lp->active_speed == SPEED_100)
5375                 val |= BMAC_XIF_CONFIG_25MHZ_CLOCK;
5376         else
5377                 val &= ~BMAC_XIF_CONFIG_25MHZ_CLOCK;
5378
5379         nw64_mac(BMAC_XIF_CONFIG, val);
5380 }
5381
5382 static void niu_init_xif(struct niu *np)
5383 {
5384         if (np->flags & NIU_FLAGS_XMAC)
5385                 niu_init_xif_xmac(np);
5386         else
5387                 niu_init_xif_bmac(np);
5388 }
5389
5390 static void niu_pcs_mii_reset(struct niu *np)
5391 {
5392         int limit = 1000;
5393         u64 val = nr64_pcs(PCS_MII_CTL);
5394         val |= PCS_MII_CTL_RST;
5395         nw64_pcs(PCS_MII_CTL, val);
5396         while ((--limit >= 0) && (val & PCS_MII_CTL_RST)) {
5397                 udelay(100);
5398                 val = nr64_pcs(PCS_MII_CTL);
5399         }
5400 }
5401
5402 static void niu_xpcs_reset(struct niu *np)
5403 {
5404         int limit = 1000;
5405         u64 val = nr64_xpcs(XPCS_CONTROL1);
5406         val |= XPCS_CONTROL1_RESET;
5407         nw64_xpcs(XPCS_CONTROL1, val);
5408         while ((--limit >= 0) && (val & XPCS_CONTROL1_RESET)) {
5409                 udelay(100);
5410                 val = nr64_xpcs(XPCS_CONTROL1);
5411         }
5412 }
5413
5414 static int niu_init_pcs(struct niu *np)
5415 {
5416         struct niu_link_config *lp = &np->link_config;
5417         u64 val;
5418
5419         switch (np->flags & (NIU_FLAGS_10G |
5420                              NIU_FLAGS_FIBER |
5421                              NIU_FLAGS_XCVR_SERDES)) {
5422         case NIU_FLAGS_FIBER:
5423                 /* 1G fiber */
5424                 nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE);
5425                 nw64_pcs(PCS_DPATH_MODE, 0);
5426                 niu_pcs_mii_reset(np);
5427                 break;
5428
5429         case NIU_FLAGS_10G:
5430         case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
5431         case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
5432                 /* 10G SERDES */
5433                 if (!(np->flags & NIU_FLAGS_XMAC))
5434                         return -EINVAL;
5435
5436                 /* 10G copper or fiber */
5437                 val = nr64_mac(XMAC_CONFIG);
5438                 val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
5439                 nw64_mac(XMAC_CONFIG, val);
5440
5441                 niu_xpcs_reset(np);
5442
5443                 val = nr64_xpcs(XPCS_CONTROL1);
5444                 if (lp->loopback_mode == LOOPBACK_PHY)
5445                         val |= XPCS_CONTROL1_LOOPBACK;
5446                 else
5447                         val &= ~XPCS_CONTROL1_LOOPBACK;
5448                 nw64_xpcs(XPCS_CONTROL1, val);
5449
5450                 nw64_xpcs(XPCS_DESKEW_ERR_CNT, 0);
5451                 (void) nr64_xpcs(XPCS_SYMERR_CNT01);
5452                 (void) nr64_xpcs(XPCS_SYMERR_CNT23);
5453                 break;
5454
5455
5456         case NIU_FLAGS_XCVR_SERDES:
5457                 /* 1G SERDES */
5458                 niu_pcs_mii_reset(np);
5459                 nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE);
5460                 nw64_pcs(PCS_DPATH_MODE, 0);
5461                 break;
5462
5463         case 0:
5464                 /* 1G copper */
5465         case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER:
5466                 /* 1G RGMII FIBER */
5467                 nw64_pcs(PCS_DPATH_MODE, PCS_DPATH_MODE_MII);
5468                 niu_pcs_mii_reset(np);
5469                 break;
5470
5471         default:
5472                 return -EINVAL;
5473         }
5474
5475         return 0;
5476 }
5477
5478 static int niu_reset_tx_xmac(struct niu *np)
5479 {
5480         return niu_set_and_wait_clear_mac(np, XTXMAC_SW_RST,
5481                                           (XTXMAC_SW_RST_REG_RS |
5482                                            XTXMAC_SW_RST_SOFT_RST),
5483                                           1000, 100, "XTXMAC_SW_RST");
5484 }
5485
5486 static int niu_reset_tx_bmac(struct niu *np)
5487 {
5488         int limit;
5489
5490         nw64_mac(BTXMAC_SW_RST, BTXMAC_SW_RST_RESET);
5491         limit = 1000;
5492         while (--limit >= 0) {
5493                 if (!(nr64_mac(BTXMAC_SW_RST) & BTXMAC_SW_RST_RESET))
5494                         break;
5495                 udelay(100);
5496         }
5497         if (limit < 0) {
5498                 dev_err(np->device, PFX "Port %u TX BMAC would not reset, "
5499                         "BTXMAC_SW_RST[%llx]\n",
5500                         np->port,
5501                         (unsigned long long) nr64_mac(BTXMAC_SW_RST));
5502                 return -ENODEV;
5503         }
5504
5505         return 0;
5506 }
5507
5508 static int niu_reset_tx_mac(struct niu *np)
5509 {
5510         if (np->flags & NIU_FLAGS_XMAC)
5511                 return niu_reset_tx_xmac(np);
5512         else
5513                 return niu_reset_tx_bmac(np);
5514 }
5515
5516 static void niu_init_tx_xmac(struct niu *np, u64 min, u64 max)
5517 {
5518         u64 val;
5519
5520         val = nr64_mac(XMAC_MIN);
5521         val &= ~(XMAC_MIN_TX_MIN_PKT_SIZE |
5522                  XMAC_MIN_RX_MIN_PKT_SIZE);
5523         val |= (min << XMAC_MIN_RX_MIN_PKT_SIZE_SHFT);
5524         val |= (min << XMAC_MIN_TX_MIN_PKT_SIZE_SHFT);
5525         nw64_mac(XMAC_MIN, val);
5526
5527         nw64_mac(XMAC_MAX, max);
5528
5529         nw64_mac(XTXMAC_STAT_MSK, ~(u64)0);
5530
5531         val = nr64_mac(XMAC_IPG);
5532         if (np->flags & NIU_FLAGS_10G) {
5533                 val &= ~XMAC_IPG_IPG_XGMII;
5534                 val |= (IPG_12_15_XGMII << XMAC_IPG_IPG_XGMII_SHIFT);
5535         } else {
5536                 val &= ~XMAC_IPG_IPG_MII_GMII;
5537                 val |= (IPG_12_MII_GMII << XMAC_IPG_IPG_MII_GMII_SHIFT);
5538         }
5539         nw64_mac(XMAC_IPG, val);
5540
5541         val = nr64_mac(XMAC_CONFIG);
5542         val &= ~(XMAC_CONFIG_ALWAYS_NO_CRC |
5543                  XMAC_CONFIG_STRETCH_MODE |
5544                  XMAC_CONFIG_VAR_MIN_IPG_EN |
5545                  XMAC_CONFIG_TX_ENABLE);
5546         nw64_mac(XMAC_CONFIG, val);
5547
5548         nw64_mac(TXMAC_FRM_CNT, 0);
5549         nw64_mac(TXMAC_BYTE_CNT, 0);
5550 }
5551
5552 static void niu_init_tx_bmac(struct niu *np, u64 min, u64 max)
5553 {
5554         u64 val;
5555
5556         nw64_mac(BMAC_MIN_FRAME, min);
5557         nw64_mac(BMAC_MAX_FRAME, max);
5558
5559         nw64_mac(BTXMAC_STATUS_MASK, ~(u64)0);
5560         nw64_mac(BMAC_CTRL_TYPE, 0x8808);
5561         nw64_mac(BMAC_PREAMBLE_SIZE, 7);
5562
5563         val = nr64_mac(BTXMAC_CONFIG);
5564         val &= ~(BTXMAC_CONFIG_FCS_DISABLE |
5565                  BTXMAC_CONFIG_ENABLE);
5566         nw64_mac(BTXMAC_CONFIG, val);
5567 }
5568
5569 static void niu_init_tx_mac(struct niu *np)
5570 {
5571         u64 min, max;
5572
5573         min = 64;
5574         if (np->dev->mtu > ETH_DATA_LEN)
5575                 max = 9216;
5576         else
5577                 max = 1522;
5578
5579         /* The XMAC_MIN register only accepts values for TX min which
5580          * have the low 3 bits cleared.
5581          */
5582         BUILD_BUG_ON(min & 0x7);
5583
5584         if (np->flags & NIU_FLAGS_XMAC)
5585                 niu_init_tx_xmac(np, min, max);
5586         else
5587                 niu_init_tx_bmac(np, min, max);
5588 }
5589
5590 static int niu_reset_rx_xmac(struct niu *np)
5591 {
5592         int limit;
5593
5594         nw64_mac(XRXMAC_SW_RST,
5595                  XRXMAC_SW_RST_REG_RS | XRXMAC_SW_RST_SOFT_RST);
5596         limit = 1000;
5597         while (--limit >= 0) {
5598                 if (!(nr64_mac(XRXMAC_SW_RST) & (XRXMAC_SW_RST_REG_RS |
5599                                                  XRXMAC_SW_RST_SOFT_RST)))
5600                     break;
5601                 udelay(100);
5602         }
5603         if (limit < 0) {
5604                 dev_err(np->device, PFX "Port %u RX XMAC would not reset, "
5605                         "XRXMAC_SW_RST[%llx]\n",
5606                         np->port,
5607                         (unsigned long long) nr64_mac(XRXMAC_SW_RST));
5608                 return -ENODEV;
5609         }
5610
5611         return 0;
5612 }
5613
5614 static int niu_reset_rx_bmac(struct niu *np)
5615 {
5616         int limit;
5617
5618         nw64_mac(BRXMAC_SW_RST, BRXMAC_SW_RST_RESET);
5619         limit = 1000;
5620         while (--limit >= 0) {
5621                 if (!(nr64_mac(BRXMAC_SW_RST) & BRXMAC_SW_RST_RESET))
5622                         break;
5623                 udelay(100);
5624         }
5625         if (limit < 0) {
5626                 dev_err(np->device, PFX "Port %u RX BMAC would not reset, "
5627                         "BRXMAC_SW_RST[%llx]\n",
5628                         np->port,
5629                         (unsigned long long) nr64_mac(BRXMAC_SW_RST));
5630                 return -ENODEV;
5631         }
5632
5633         return 0;
5634 }
5635
5636 static int niu_reset_rx_mac(struct niu *np)
5637 {
5638         if (np->flags & NIU_FLAGS_XMAC)
5639                 return niu_reset_rx_xmac(np);
5640         else
5641                 return niu_reset_rx_bmac(np);
5642 }
5643
5644 static void niu_init_rx_xmac(struct niu *np)
5645 {
5646         struct niu_parent *parent = np->parent;
5647         struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
5648         int first_rdc_table = tp->first_table_num;
5649         unsigned long i;
5650         u64 val;
5651
5652         nw64_mac(XMAC_ADD_FILT0, 0);
5653         nw64_mac(XMAC_ADD_FILT1, 0);
5654         nw64_mac(XMAC_ADD_FILT2, 0);
5655         nw64_mac(XMAC_ADD_FILT12_MASK, 0);
5656         nw64_mac(XMAC_ADD_FILT00_MASK, 0);
5657         for (i = 0; i < MAC_NUM_HASH; i++)
5658                 nw64_mac(XMAC_HASH_TBL(i), 0);
5659         nw64_mac(XRXMAC_STAT_MSK, ~(u64)0);
5660         niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
5661         niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
5662
5663         val = nr64_mac(XMAC_CONFIG);
5664         val &= ~(XMAC_CONFIG_RX_MAC_ENABLE |
5665                  XMAC_CONFIG_PROMISCUOUS |
5666                  XMAC_CONFIG_PROMISC_GROUP |
5667                  XMAC_CONFIG_ERR_CHK_DIS |
5668                  XMAC_CONFIG_RX_CRC_CHK_DIS |
5669                  XMAC_CONFIG_RESERVED_MULTICAST |
5670                  XMAC_CONFIG_RX_CODEV_CHK_DIS |
5671                  XMAC_CONFIG_ADDR_FILTER_EN |
5672                  XMAC_CONFIG_RCV_PAUSE_ENABLE |
5673                  XMAC_CONFIG_STRIP_CRC |
5674                  XMAC_CONFIG_PASS_FLOW_CTRL |
5675                  XMAC_CONFIG_MAC2IPP_PKT_CNT_EN);
5676         val |= (XMAC_CONFIG_HASH_FILTER_EN);
5677         nw64_mac(XMAC_CONFIG, val);
5678
5679         nw64_mac(RXMAC_BT_CNT, 0);
5680         nw64_mac(RXMAC_BC_FRM_CNT, 0);
5681         nw64_mac(RXMAC_MC_FRM_CNT, 0);
5682         nw64_mac(RXMAC_FRAG_CNT, 0);
5683         nw64_mac(RXMAC_HIST_CNT1, 0);
5684         nw64_mac(RXMAC_HIST_CNT2, 0);
5685         nw64_mac(RXMAC_HIST_CNT3, 0);
5686         nw64_mac(RXMAC_HIST_CNT4, 0);
5687         nw64_mac(RXMAC_HIST_CNT5, 0);
5688         nw64_mac(RXMAC_HIST_CNT6, 0);
5689         nw64_mac(RXMAC_HIST_CNT7, 0);
5690         nw64_mac(RXMAC_MPSZER_CNT, 0);
5691         nw64_mac(RXMAC_CRC_ER_CNT, 0);
5692         nw64_mac(RXMAC_CD_VIO_CNT, 0);
5693         nw64_mac(LINK_FAULT_CNT, 0);
5694 }
5695
5696 static void niu_init_rx_bmac(struct niu *np)
5697 {
5698         struct niu_parent *parent = np->parent;
5699         struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
5700         int first_rdc_table = tp->first_table_num;
5701         unsigned long i;
5702         u64 val;
5703
5704         nw64_mac(BMAC_ADD_FILT0, 0);
5705         nw64_mac(BMAC_ADD_FILT1, 0);
5706         nw64_mac(BMAC_ADD_FILT2, 0);
5707         nw64_mac(BMAC_ADD_FILT12_MASK, 0);
5708         nw64_mac(BMAC_ADD_FILT00_MASK, 0);
5709         for (i = 0; i < MAC_NUM_HASH; i++)
5710                 nw64_mac(BMAC_HASH_TBL(i), 0);
5711         niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
5712         niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
5713         nw64_mac(BRXMAC_STATUS_MASK, ~(u64)0);
5714
5715         val = nr64_mac(BRXMAC_CONFIG);
5716         val &= ~(BRXMAC_CONFIG_ENABLE |
5717                  BRXMAC_CONFIG_STRIP_PAD |
5718                  BRXMAC_CONFIG_STRIP_FCS |
5719                  BRXMAC_CONFIG_PROMISC |
5720                  BRXMAC_CONFIG_PROMISC_GRP |
5721                  BRXMAC_CONFIG_ADDR_FILT_EN |
5722                  BRXMAC_CONFIG_DISCARD_DIS);
5723         val |= (BRXMAC_CONFIG_HASH_FILT_EN);
5724         nw64_mac(BRXMAC_CONFIG, val);
5725
5726         val = nr64_mac(BMAC_ADDR_CMPEN);
5727         val |= BMAC_ADDR_CMPEN_EN0;
5728         nw64_mac(BMAC_ADDR_CMPEN, val);
5729 }
5730
5731 static void niu_init_rx_mac(struct niu *np)
5732 {
5733         niu_set_primary_mac(np, np->dev->dev_addr);
5734
5735         if (np->flags & NIU_FLAGS_XMAC)
5736                 niu_init_rx_xmac(np);
5737         else
5738                 niu_init_rx_bmac(np);
5739 }
5740
5741 static void niu_enable_tx_xmac(struct niu *np, int on)
5742 {
5743         u64 val = nr64_mac(XMAC_CONFIG);
5744
5745         if (on)
5746                 val |= XMAC_CONFIG_TX_ENABLE;
5747         else
5748                 val &= ~XMAC_CONFIG_TX_ENABLE;
5749         nw64_mac(XMAC_CONFIG, val);
5750 }
5751
5752 static void niu_enable_tx_bmac(struct niu *np, int on)
5753 {
5754         u64 val = nr64_mac(BTXMAC_CONFIG);
5755
5756         if (on)
5757                 val |= BTXMAC_CONFIG_ENABLE;
5758         else
5759                 val &= ~BTXMAC_CONFIG_ENABLE;
5760         nw64_mac(BTXMAC_CONFIG, val);
5761 }
5762
5763 static void niu_enable_tx_mac(struct niu *np, int on)
5764 {
5765         if (np->flags & NIU_FLAGS_XMAC)
5766                 niu_enable_tx_xmac(np, on);
5767         else
5768                 niu_enable_tx_bmac(np, on);
5769 }
5770
5771 static void niu_enable_rx_xmac(struct niu *np, int on)
5772 {
5773         u64 val = nr64_mac(XMAC_CONFIG);
5774
5775         val &= ~(XMAC_CONFIG_HASH_FILTER_EN |
5776                  XMAC_CONFIG_PROMISCUOUS);
5777
5778         if (np->flags & NIU_FLAGS_MCAST)
5779                 val |= XMAC_CONFIG_HASH_FILTER_EN;
5780         if (np->flags & NIU_FLAGS_PROMISC)
5781                 val |= XMAC_CONFIG_PROMISCUOUS;
5782
5783         if (on)
5784                 val |= XMAC_CONFIG_RX_MAC_ENABLE;
5785         else
5786                 val &= ~XMAC_CONFIG_RX_MAC_ENABLE;
5787         nw64_mac(XMAC_CONFIG, val);
5788 }
5789
5790 static void niu_enable_rx_bmac(struct niu *np, int on)
5791 {
5792         u64 val = nr64_mac(BRXMAC_CONFIG);
5793
5794         val &= ~(BRXMAC_CONFIG_HASH_FILT_EN |
5795                  BRXMAC_CONFIG_PROMISC);
5796
5797         if (np->flags & NIU_FLAGS_MCAST)
5798                 val |= BRXMAC_CONFIG_HASH_FILT_EN;
5799         if (np->flags & NIU_FLAGS_PROMISC)
5800                 val |= BRXMAC_CONFIG_PROMISC;
5801
5802         if (on)
5803                 val |= BRXMAC_CONFIG_ENABLE;
5804         else
5805                 val &= ~BRXMAC_CONFIG_ENABLE;
5806         nw64_mac(BRXMAC_CONFIG, val);
5807 }
5808
5809 static void niu_enable_rx_mac(struct niu *np, int on)
5810 {
5811         if (np->flags & NIU_FLAGS_XMAC)
5812                 niu_enable_rx_xmac(np, on);
5813         else
5814                 niu_enable_rx_bmac(np, on);
5815 }
5816
5817 static int niu_init_mac(struct niu *np)
5818 {
5819         int err;
5820
5821         niu_init_xif(np);
5822         err = niu_init_pcs(np);
5823         if (err)
5824                 return err;
5825
5826         err = niu_reset_tx_mac(np);
5827         if (err)
5828                 return err;
5829         niu_init_tx_mac(np);
5830         err = niu_reset_rx_mac(np);
5831         if (err)
5832                 return err;
5833         niu_init_rx_mac(np);
5834
5835         /* This looks hookey but the RX MAC reset we just did will
5836          * undo some of the state we setup in niu_init_tx_mac() so we
5837          * have to call it again.  In particular, the RX MAC reset will
5838          * set the XMAC_MAX register back to it's default value.
5839          */
5840         niu_init_tx_mac(np);
5841         niu_enable_tx_mac(np, 1);
5842
5843         niu_enable_rx_mac(np, 1);
5844
5845         return 0;
5846 }
5847
5848 static void niu_stop_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
5849 {
5850         (void) niu_tx_channel_stop(np, rp->tx_channel);
5851 }
5852
5853 static void niu_stop_tx_channels(struct niu *np)
5854 {
5855         int i;
5856
5857         for (i = 0; i < np->num_tx_rings; i++) {
5858                 struct tx_ring_info *rp = &np->tx_rings[i];
5859
5860                 niu_stop_one_tx_channel(np, rp);
5861         }
5862 }
5863
5864 static void niu_reset_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
5865 {
5866         (void) niu_tx_channel_reset(np, rp->tx_channel);
5867 }
5868
5869 static void niu_reset_tx_channels(struct niu *np)
5870 {
5871         int i;
5872
5873         for (i = 0; i < np->num_tx_rings; i++) {
5874                 struct tx_ring_info *rp = &np->tx_rings[i];
5875
5876                 niu_reset_one_tx_channel(np, rp);
5877         }
5878 }
5879
5880 static void niu_stop_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
5881 {
5882         (void) niu_enable_rx_channel(np, rp->rx_channel, 0);
5883 }
5884
5885 static void niu_stop_rx_channels(struct niu *np)
5886 {
5887         int i;
5888
5889         for (i = 0; i < np->num_rx_rings; i++) {
5890                 struct rx_ring_info *rp = &np->rx_rings[i];
5891
5892                 niu_stop_one_rx_channel(np, rp);
5893         }
5894 }
5895
5896 static void niu_reset_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
5897 {
5898         int channel = rp->rx_channel;
5899
5900         (void) niu_rx_channel_reset(np, channel);
5901         nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_ALL);
5902         nw64(RX_DMA_CTL_STAT(channel), 0);
5903         (void) niu_enable_rx_channel(np, channel, 0);
5904 }
5905
5906 static void niu_reset_rx_channels(struct niu *np)
5907 {
5908         int i;
5909
5910         for (i = 0; i < np->num_rx_rings; i++) {
5911                 struct rx_ring_info *rp = &np->rx_rings[i];
5912
5913                 niu_reset_one_rx_channel(np, rp);
5914         }
5915 }
5916
5917 static void niu_disable_ipp(struct niu *np)
5918 {
5919         u64 rd, wr, val;
5920         int limit;
5921
5922         rd = nr64_ipp(IPP_DFIFO_RD_PTR);
5923         wr = nr64_ipp(IPP_DFIFO_WR_PTR);
5924         limit = 100;
5925         while (--limit >= 0 && (rd != wr)) {
5926                 rd = nr64_ipp(IPP_DFIFO_RD_PTR);
5927                 wr = nr64_ipp(IPP_DFIFO_WR_PTR);
5928         }
5929         if (limit < 0 &&
5930             (rd != 0 && wr != 1)) {
5931                 dev_err(np->device, PFX "%s: IPP would not quiesce, "
5932                         "rd_ptr[%llx] wr_ptr[%llx]\n",
5933                         np->dev->name,
5934                         (unsigned long long) nr64_ipp(IPP_DFIFO_RD_PTR),
5935                         (unsigned long long) nr64_ipp(IPP_DFIFO_WR_PTR));
5936         }
5937
5938         val = nr64_ipp(IPP_CFIG);
5939         val &= ~(IPP_CFIG_IPP_ENABLE |
5940                  IPP_CFIG_DFIFO_ECC_EN |
5941                  IPP_CFIG_DROP_BAD_CRC |
5942                  IPP_CFIG_CKSUM_EN);
5943         nw64_ipp(IPP_CFIG, val);
5944
5945         (void) niu_ipp_reset(np);
5946 }
5947
5948 static int niu_init_hw(struct niu *np)
5949 {
5950         int i, err;
5951
5952         niudbg(IFUP, "%s: Initialize TXC\n", np->dev->name);
5953         niu_txc_enable_port(np, 1);
5954         niu_txc_port_dma_enable(np, 1);
5955         niu_txc_set_imask(np, 0);
5956
5957         niudbg(IFUP, "%s: Initialize TX channels\n", np->dev->name);
5958         for (i = 0; i < np->num_tx_rings; i++) {
5959                 struct tx_ring_info *rp = &np->tx_rings[i];
5960
5961                 err = niu_init_one_tx_channel(np, rp);
5962                 if (err)
5963                         return err;
5964         }
5965
5966         niudbg(IFUP, "%s: Initialize RX channels\n", np->dev->name);
5967         err = niu_init_rx_channels(np);
5968         if (err)
5969                 goto out_uninit_tx_channels;
5970
5971         niudbg(IFUP, "%s: Initialize classifier\n", np->dev->name);
5972         err = niu_init_classifier_hw(np);
5973         if (err)
5974                 goto out_uninit_rx_channels;
5975
5976         niudbg(IFUP, "%s: Initialize ZCP\n", np->dev->name);
5977         err = niu_init_zcp(np);
5978         if (err)
5979                 goto out_uninit_rx_channels;
5980
5981         niudbg(IFUP, "%s: Initialize IPP\n", np->dev->name);
5982         err = niu_init_ipp(np);
5983         if (err)
5984                 goto out_uninit_rx_channels;
5985
5986         niudbg(IFUP, "%s: Initialize MAC\n", np->dev->name);
5987         err = niu_init_mac(np);
5988         if (err)
5989                 goto out_uninit_ipp;
5990
5991         return 0;
5992
5993 out_uninit_ipp:
5994         niudbg(IFUP, "%s: Uninit IPP\n", np->dev->name);
5995         niu_disable_ipp(np);
5996
5997 out_uninit_rx_channels:
5998         niudbg(IFUP, "%s: Uninit RX channels\n", np->dev->name);
5999         niu_stop_rx_channels(np);
6000         niu_reset_rx_channels(np);
6001
6002 out_uninit_tx_channels:
6003         niudbg(IFUP, "%s: Uninit TX channels\n", np->dev->name);
6004         niu_stop_tx_channels(np);
6005         niu_reset_tx_channels(np);
6006
6007         return err;
6008 }
6009
6010 static void niu_stop_hw(struct niu *np)
6011 {
6012         niudbg(IFDOWN, "%s: Disable interrupts\n", np->dev->name);
6013         niu_enable_interrupts(np, 0);
6014
6015         niudbg(IFDOWN, "%s: Disable RX MAC\n", np->dev->name);
6016         niu_enable_rx_mac(np, 0);
6017
6018         niudbg(IFDOWN, "%s: Disable IPP\n", np->dev->name);
6019         niu_disable_ipp(np);
6020
6021         niudbg(IFDOWN, "%s: Stop TX channels\n", np->dev->name);
6022         niu_stop_tx_channels(np);
6023
6024         niudbg(IFDOWN, "%s: Stop RX channels\n", np->dev->name);
6025         niu_stop_rx_channels(np);
6026
6027         niudbg(IFDOWN, "%s: Reset TX channels\n", np->dev->name);
6028         niu_reset_tx_channels(np);
6029
6030         niudbg(IFDOWN, "%s: Reset RX channels\n", np->dev->name);
6031         niu_reset_rx_channels(np);
6032 }
6033
6034 static void niu_set_irq_name(struct niu *np)
6035 {
6036         int port = np->port;
6037         int i, j = 1;
6038
6039         sprintf(np->irq_name[0], "%s:MAC", np->dev->name);
6040
6041         if (port == 0) {
6042                 sprintf(np->irq_name[1], "%s:MIF", np->dev->name);
6043                 sprintf(np->irq_name[2], "%s:SYSERR", np->dev->name);
6044                 j = 3;
6045         }
6046
6047         for (i = 0; i < np->num_ldg - j; i++) {
6048                 if (i < np->num_rx_rings)
6049                         sprintf(np->irq_name[i+j], "%s-rx-%d",
6050                                 np->dev->name, i);
6051                 else if (i < np->num_tx_rings + np->num_rx_rings)
6052                         sprintf(np->irq_name[i+j], "%s-tx-%d", np->dev->name,
6053                                 i - np->num_rx_rings);
6054         }
6055 }
6056
6057 static int niu_request_irq(struct niu *np)
6058 {
6059         int i, j, err;
6060
6061         niu_set_irq_name(np);
6062
6063         err = 0;
6064         for (i = 0; i < np->num_ldg; i++) {
6065                 struct niu_ldg *lp = &np->ldg[i];
6066
6067                 err = request_irq(lp->irq, niu_interrupt,
6068                                   IRQF_SHARED | IRQF_SAMPLE_RANDOM,
6069                                   np->irq_name[i], lp);
6070                 if (err)
6071                         goto out_free_irqs;
6072
6073         }
6074
6075         return 0;
6076
6077 out_free_irqs:
6078         for (j = 0; j < i; j++) {
6079                 struct niu_ldg *lp = &np->ldg[j];
6080
6081                 free_irq(lp->irq, lp);
6082         }
6083         return err;
6084 }
6085
6086 static void niu_free_irq(struct niu *np)
6087 {
6088         int i;
6089
6090         for (i = 0; i < np->num_ldg; i++) {
6091                 struct niu_ldg *lp = &np->ldg[i];
6092
6093                 free_irq(lp->irq, lp);
6094         }
6095 }
6096
6097 static void niu_enable_napi(struct niu *np)
6098 {
6099         int i;
6100
6101         for (i = 0; i < np->num_ldg; i++)
6102                 napi_enable(&np->ldg[i].napi);
6103 }
6104
6105 static void niu_disable_napi(struct niu *np)
6106 {
6107         int i;
6108
6109         for (i = 0; i < np->num_ldg; i++)
6110                 napi_disable(&np->ldg[i].napi);
6111 }
6112
6113 static int niu_open(struct net_device *dev)
6114 {
6115         struct niu *np = netdev_priv(dev);
6116         int err;
6117
6118         netif_carrier_off(dev);
6119
6120         err = niu_alloc_channels(np);
6121         if (err)
6122                 goto out_err;
6123
6124         err = niu_enable_interrupts(np, 0);
6125         if (err)
6126                 goto out_free_channels;
6127
6128         err = niu_request_irq(np);
6129         if (err)
6130                 goto out_free_channels;
6131
6132         niu_enable_napi(np);
6133
6134         spin_lock_irq(&np->lock);
6135
6136         err = niu_init_hw(np);
6137         if (!err) {
6138                 init_timer(&np->timer);
6139                 np->timer.expires = jiffies + HZ;
6140                 np->timer.data = (unsigned long) np;
6141                 np->timer.function = niu_timer;
6142
6143                 err = niu_enable_interrupts(np, 1);
6144                 if (err)
6145                         niu_stop_hw(np);
6146         }
6147
6148         spin_unlock_irq(&np->lock);
6149
6150         if (err) {
6151                 niu_disable_napi(np);
6152                 goto out_free_irq;
6153         }
6154
6155         netif_tx_start_all_queues(dev);
6156
6157         if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
6158                 netif_carrier_on(dev);
6159
6160         add_timer(&np->timer);
6161
6162         return 0;
6163
6164 out_free_irq:
6165         niu_free_irq(np);
6166
6167 out_free_channels:
6168         niu_free_channels(np);
6169
6170 out_err:
6171         return err;
6172 }
6173
6174 static void niu_full_shutdown(struct niu *np, struct net_device *dev)
6175 {
6176         cancel_work_sync(&np->reset_task);
6177
6178         niu_disable_napi(np);
6179         netif_tx_stop_all_queues(dev);
6180
6181         del_timer_sync(&np->timer);
6182
6183         spin_lock_irq(&np->lock);
6184
6185         niu_stop_hw(np);
6186
6187         spin_unlock_irq(&np->lock);
6188 }
6189
6190 static int niu_close(struct net_device *dev)
6191 {
6192         struct niu *np = netdev_priv(dev);
6193
6194         niu_full_shutdown(np, dev);
6195
6196         niu_free_irq(np);
6197
6198         niu_free_channels(np);
6199
6200         niu_handle_led(np, 0);
6201
6202         return 0;
6203 }
6204
6205 static void niu_sync_xmac_stats(struct niu *np)
6206 {
6207         struct niu_xmac_stats *mp = &np->mac_stats.xmac;
6208
6209         mp->tx_frames += nr64_mac(TXMAC_FRM_CNT);
6210         mp->tx_bytes += nr64_mac(TXMAC_BYTE_CNT);
6211
6212         mp->rx_link_faults += nr64_mac(LINK_FAULT_CNT);
6213         mp->rx_align_errors += nr64_mac(RXMAC_ALIGN_ERR_CNT);
6214         mp->rx_frags += nr64_mac(RXMAC_FRAG_CNT);
6215         mp->rx_mcasts += nr64_mac(RXMAC_MC_FRM_CNT);
6216         mp->rx_bcasts += nr64_mac(RXMAC_BC_FRM_CNT);
6217         mp->rx_hist_cnt1 += nr64_mac(RXMAC_HIST_CNT1);
6218         mp->rx_hist_cnt2 += nr64_mac(RXMAC_HIST_CNT2);
6219         mp->rx_hist_cnt3 += nr64_mac(RXMAC_HIST_CNT3);
6220         mp->rx_hist_cnt4 += nr64_mac(RXMAC_HIST_CNT4);
6221         mp->rx_hist_cnt5 += nr64_mac(RXMAC_HIST_CNT5);
6222         mp->rx_hist_cnt6 += nr64_mac(RXMAC_HIST_CNT6);
6223         mp->rx_hist_cnt7 += nr64_mac(RXMAC_HIST_CNT7);
6224         mp->rx_octets += nr64_mac(RXMAC_BT_CNT);
6225         mp->rx_code_violations += nr64_mac(RXMAC_CD_VIO_CNT);
6226         mp->rx_len_errors += nr64_mac(RXMAC_MPSZER_CNT);
6227         mp->rx_crc_errors += nr64_mac(RXMAC_CRC_ER_CNT);
6228 }
6229
6230 static void niu_sync_bmac_stats(struct niu *np)
6231 {
6232         struct niu_bmac_stats *mp = &np->mac_stats.bmac;
6233
6234         mp->tx_bytes += nr64_mac(BTXMAC_BYTE_CNT);
6235         mp->tx_frames += nr64_mac(BTXMAC_FRM_CNT);
6236
6237         mp->rx_frames += nr64_mac(BRXMAC_FRAME_CNT);
6238         mp->rx_align_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT);
6239         mp->rx_crc_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT);
6240         mp->rx_len_errors += nr64_mac(BRXMAC_CODE_VIOL_ERR_CNT);
6241 }
6242
6243 static void niu_sync_mac_stats(struct niu *np)
6244 {
6245         if (np->flags & NIU_FLAGS_XMAC)
6246                 niu_sync_xmac_stats(np);
6247         else
6248                 niu_sync_bmac_stats(np);
6249 }
6250
6251 static void niu_get_rx_stats(struct niu *np)
6252 {
6253         unsigned long pkts, dropped, errors, bytes;
6254         int i;
6255
6256         pkts = dropped = errors = bytes = 0;
6257         for (i = 0; i < np->num_rx_rings; i++) {
6258                 struct rx_ring_info *rp = &np->rx_rings[i];
6259
6260                 niu_sync_rx_discard_stats(np, rp, 0);
6261
6262                 pkts += rp->rx_packets;
6263                 bytes += rp->rx_bytes;
6264                 dropped += rp->rx_dropped;
6265                 errors += rp->rx_errors;
6266         }
6267         np->dev->stats.rx_packets = pkts;
6268         np->dev->stats.rx_bytes = bytes;
6269         np->dev->stats.rx_dropped = dropped;
6270         np->dev->stats.rx_errors = errors;
6271 }
6272
6273 static void niu_get_tx_stats(struct niu *np)
6274 {
6275         unsigned long pkts, errors, bytes;
6276         int i;
6277
6278         pkts = errors = bytes = 0;
6279         for (i = 0; i < np->num_tx_rings; i++) {
6280                 struct tx_ring_info *rp = &np->tx_rings[i];
6281
6282                 pkts += rp->tx_packets;
6283                 bytes += rp->tx_bytes;
6284                 errors += rp->tx_errors;
6285         }
6286         np->dev->stats.tx_packets = pkts;
6287         np->dev->stats.tx_bytes = bytes;
6288         np->dev->stats.tx_errors = errors;
6289 }
6290
6291 static struct net_device_stats *niu_get_stats(struct net_device *dev)
6292 {
6293         struct niu *np = netdev_priv(dev);
6294
6295         niu_get_rx_stats(np);
6296         niu_get_tx_stats(np);
6297
6298         return &dev->stats;
6299 }
6300
6301 static void niu_load_hash_xmac(struct niu *np, u16 *hash)
6302 {
6303         int i;
6304
6305         for (i = 0; i < 16; i++)
6306                 nw64_mac(XMAC_HASH_TBL(i), hash[i]);
6307 }
6308
6309 static void niu_load_hash_bmac(struct niu *np, u16 *hash)
6310 {
6311         int i;
6312
6313         for (i = 0; i < 16; i++)
6314                 nw64_mac(BMAC_HASH_TBL(i), hash[i]);
6315 }
6316
6317 static void niu_load_hash(struct niu *np, u16 *hash)
6318 {
6319         if (np->flags & NIU_FLAGS_XMAC)
6320                 niu_load_hash_xmac(np, hash);
6321         else
6322                 niu_load_hash_bmac(np, hash);
6323 }
6324
6325 static void niu_set_rx_mode(struct net_device *dev)
6326 {
6327         struct niu *np = netdev_priv(dev);
6328         int i, alt_cnt, err;
6329         struct dev_addr_list *addr;
6330         unsigned long flags;
6331         u16 hash[16] = { 0, };
6332
6333         spin_lock_irqsave(&np->lock, flags);
6334         niu_enable_rx_mac(np, 0);
6335
6336         np->flags &= ~(NIU_FLAGS_MCAST | NIU_FLAGS_PROMISC);
6337         if (dev->flags & IFF_PROMISC)
6338                 np->flags |= NIU_FLAGS_PROMISC;
6339         if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 0))
6340                 np->flags |= NIU_FLAGS_MCAST;
6341
6342         alt_cnt = dev->uc_count;
6343         if (alt_cnt > niu_num_alt_addr(np)) {
6344                 alt_cnt = 0;
6345                 np->flags |= NIU_FLAGS_PROMISC;
6346         }
6347
6348         if (alt_cnt) {
6349                 int index = 0;
6350
6351                 for (addr = dev->uc_list; addr; addr = addr->next) {
6352                         err = niu_set_alt_mac(np, index,
6353                                               addr->da_addr);
6354                         if (err)
6355                                 printk(KERN_WARNING PFX "%s: Error %d "
6356                                        "adding alt mac %d\n",
6357                                        dev->name, err, index);
6358                         err = niu_enable_alt_mac(np, index, 1);
6359                         if (err)
6360                                 printk(KERN_WARNING PFX "%s: Error %d "
6361                                        "enabling alt mac %d\n",
6362                                        dev->name, err, index);
6363
6364                         index++;
6365                 }
6366         } else {
6367                 int alt_start;
6368                 if (np->flags & NIU_FLAGS_XMAC)
6369                         alt_start = 0;
6370                 else
6371                         alt_start = 1;
6372                 for (i = alt_start; i < niu_num_alt_addr(np); i++) {
6373                         err = niu_enable_alt_mac(np, i, 0);
6374                         if (err)
6375                                 printk(KERN_WARNING PFX "%s: Error %d "
6376                                        "disabling alt mac %d\n",
6377                                        dev->name, err, i);
6378                 }
6379         }
6380         if (dev->flags & IFF_ALLMULTI) {
6381                 for (i = 0; i < 16; i++)
6382                         hash[i] = 0xffff;
6383         } else if (dev->mc_count > 0) {
6384                 for (addr = dev->mc_list; addr; addr = addr->next) {
6385                         u32 crc = ether_crc_le(ETH_ALEN, addr->da_addr);
6386
6387                         crc >>= 24;
6388                         hash[crc >> 4] |= (1 << (15 - (crc & 0xf)));
6389                 }
6390         }
6391
6392         if (np->flags & NIU_FLAGS_MCAST)
6393                 niu_load_hash(np, hash);
6394
6395         niu_enable_rx_mac(np, 1);
6396         spin_unlock_irqrestore(&np->lock, flags);
6397 }
6398
6399 static int niu_set_mac_addr(struct net_device *dev, void *p)
6400 {
6401         struct niu *np = netdev_priv(dev);
6402         struct sockaddr *addr = p;
6403         unsigned long flags;
6404
6405         if (!is_valid_ether_addr(addr->sa_data))
6406                 return -EINVAL;
6407
6408         memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
6409
6410         if (!netif_running(dev))
6411                 return 0;
6412
6413         spin_lock_irqsave(&np->lock, flags);
6414         niu_enable_rx_mac(np, 0);
6415         niu_set_primary_mac(np, dev->dev_addr);
6416         niu_enable_rx_mac(np, 1);
6417         spin_unlock_irqrestore(&np->lock, flags);
6418
6419         return 0;
6420 }
6421
6422 static int niu_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
6423 {
6424         return -EOPNOTSUPP;
6425 }
6426
6427 static void niu_netif_stop(struct niu *np)
6428 {
6429         np->dev->trans_start = jiffies; /* prevent tx timeout */
6430
6431         niu_disable_napi(np);
6432
6433         netif_tx_disable(np->dev);
6434 }
6435
6436 static void niu_netif_start(struct niu *np)
6437 {
6438         /* NOTE: unconditional netif_wake_queue is only appropriate
6439          * so long as all callers are assured to have free tx slots
6440          * (such as after niu_init_hw).
6441          */
6442         netif_tx_wake_all_queues(np->dev);
6443
6444         niu_enable_napi(np);
6445
6446         niu_enable_interrupts(np, 1);
6447 }
6448
6449 static void niu_reset_buffers(struct niu *np)
6450 {
6451         int i, j, k, err;
6452
6453         if (np->rx_rings) {
6454                 for (i = 0; i < np->num_rx_rings; i++) {
6455                         struct rx_ring_info *rp = &np->rx_rings[i];
6456
6457                         for (j = 0, k = 0; j < MAX_RBR_RING_SIZE; j++) {
6458                                 struct page *page;
6459
6460                                 page = rp->rxhash[j];
6461                                 while (page) {
6462                                         struct page *next =
6463                                                 (struct page *) page->mapping;
6464                                         u64 base = page->index;
6465                                         base = base >> RBR_DESCR_ADDR_SHIFT;
6466                                         rp->rbr[k++] = cpu_to_le32(base);
6467                                         page = next;
6468                                 }
6469                         }
6470                         for (; k < MAX_RBR_RING_SIZE; k++) {
6471                                 err = niu_rbr_add_page(np, rp, GFP_ATOMIC, k);
6472                                 if (unlikely(err))
6473                                         break;
6474                         }
6475
6476                         rp->rbr_index = rp->rbr_table_size - 1;
6477                         rp->rcr_index = 0;
6478                         rp->rbr_pending = 0;
6479                         rp->rbr_refill_pending = 0;
6480                 }
6481         }
6482         if (np->tx_rings) {
6483                 for (i = 0; i < np->num_tx_rings; i++) {
6484                         struct tx_ring_info *rp = &np->tx_rings[i];
6485
6486                         for (j = 0; j < MAX_TX_RING_SIZE; j++) {
6487                                 if (rp->tx_buffs[j].skb)
6488                                         (void) release_tx_packet(np, rp, j);
6489                         }
6490
6491                         rp->pending = MAX_TX_RING_SIZE;
6492                         rp->prod = 0;
6493                         rp->cons = 0;
6494                         rp->wrap_bit = 0;
6495                 }
6496         }
6497 }
6498
6499 static void niu_reset_task(struct work_struct *work)
6500 {
6501         struct niu *np = container_of(work, struct niu, reset_task);
6502         unsigned long flags;
6503         int err;
6504
6505         spin_lock_irqsave(&np->lock, flags);
6506         if (!netif_running(np->dev)) {
6507                 spin_unlock_irqrestore(&np->lock, flags);
6508                 return;
6509         }
6510
6511         spin_unlock_irqrestore(&np->lock, flags);
6512
6513         del_timer_sync(&np->timer);
6514
6515         niu_netif_stop(np);
6516
6517         spin_lock_irqsave(&np->lock, flags);
6518
6519         niu_stop_hw(np);
6520
6521         spin_unlock_irqrestore(&np->lock, flags);
6522
6523         niu_reset_buffers(np);
6524
6525         spin_lock_irqsave(&np->lock, flags);
6526
6527         err = niu_init_hw(np);
6528         if (!err) {
6529                 np->timer.expires = jiffies + HZ;
6530                 add_timer(&np->timer);
6531                 niu_netif_start(np);
6532         }
6533
6534         spin_unlock_irqrestore(&np->lock, flags);
6535 }
6536
6537 static void niu_tx_timeout(struct net_device *dev)
6538 {
6539         struct niu *np = netdev_priv(dev);
6540
6541         dev_err(np->device, PFX "%s: Transmit timed out, resetting\n",
6542                 dev->name);
6543
6544         schedule_work(&np->reset_task);
6545 }
6546
6547 static void niu_set_txd(struct tx_ring_info *rp, int index,
6548                         u64 mapping, u64 len, u64 mark,
6549                         u64 n_frags)
6550 {
6551         __le64 *desc = &rp->descr[index];
6552
6553         *desc = cpu_to_le64(mark |
6554                             (n_frags << TX_DESC_NUM_PTR_SHIFT) |
6555                             (len << TX_DESC_TR_LEN_SHIFT) |
6556                             (mapping & TX_DESC_SAD));
6557 }
6558
6559 static u64 niu_compute_tx_flags(struct sk_buff *skb, struct ethhdr *ehdr,
6560                                 u64 pad_bytes, u64 len)
6561 {
6562         u16 eth_proto, eth_proto_inner;
6563         u64 csum_bits, l3off, ihl, ret;
6564         u8 ip_proto;
6565         int ipv6;
6566
6567         eth_proto = be16_to_cpu(ehdr->h_proto);
6568         eth_proto_inner = eth_proto;
6569         if (eth_proto == ETH_P_8021Q) {
6570                 struct vlan_ethhdr *vp = (struct vlan_ethhdr *) ehdr;
6571                 __be16 val = vp->h_vlan_encapsulated_proto;
6572
6573                 eth_proto_inner = be16_to_cpu(val);
6574         }
6575
6576         ipv6 = ihl = 0;
6577         switch (skb->protocol) {
6578         case cpu_to_be16(ETH_P_IP):
6579                 ip_proto = ip_hdr(skb)->protocol;
6580                 ihl = ip_hdr(skb)->ihl;
6581                 break;
6582         case cpu_to_be16(ETH_P_IPV6):
6583                 ip_proto = ipv6_hdr(skb)->nexthdr;
6584                 ihl = (40 >> 2);
6585                 ipv6 = 1;
6586                 break;
6587         default:
6588                 ip_proto = ihl = 0;
6589                 break;
6590         }
6591
6592         csum_bits = TXHDR_CSUM_NONE;
6593         if (skb->ip_summed == CHECKSUM_PARTIAL) {
6594                 u64 start, stuff;
6595
6596                 csum_bits = (ip_proto == IPPROTO_TCP ?
6597                              TXHDR_CSUM_TCP :
6598                              (ip_proto == IPPROTO_UDP ?
6599                               TXHDR_CSUM_UDP : TXHDR_CSUM_SCTP));
6600
6601                 start = skb_transport_offset(skb) -
6602                         (pad_bytes + sizeof(struct tx_pkt_hdr));
6603                 stuff = start + skb->csum_offset;
6604
6605                 csum_bits |= (start / 2) << TXHDR_L4START_SHIFT;
6606                 csum_bits |= (stuff / 2) << TXHDR_L4STUFF_SHIFT;
6607         }
6608
6609         l3off = skb_network_offset(skb) -
6610                 (pad_bytes + sizeof(struct tx_pkt_hdr));
6611
6612         ret = (((pad_bytes / 2) << TXHDR_PAD_SHIFT) |
6613                (len << TXHDR_LEN_SHIFT) |
6614                ((l3off / 2) << TXHDR_L3START_SHIFT) |
6615                (ihl << TXHDR_IHL_SHIFT) |
6616                ((eth_proto_inner < 1536) ? TXHDR_LLC : 0) |
6617                ((eth_proto == ETH_P_8021Q) ? TXHDR_VLAN : 0) |
6618                (ipv6 ? TXHDR_IP_VER : 0) |
6619                csum_bits);
6620
6621         return ret;
6622 }
6623
6624 static int niu_start_xmit(struct sk_buff *skb, struct net_device *dev)
6625 {
6626         struct niu *np = netdev_priv(dev);
6627         unsigned long align, headroom;
6628         struct netdev_queue *txq;
6629         struct tx_ring_info *rp;
6630         struct tx_pkt_hdr *tp;
6631         unsigned int len, nfg;
6632         struct ethhdr *ehdr;
6633         int prod, i, tlen;
6634         u64 mapping, mrk;
6635
6636         i = skb_get_queue_mapping(skb);
6637         rp = &np->tx_rings[i];
6638         txq = netdev_get_tx_queue(dev, i);
6639
6640         if (niu_tx_avail(rp) <= (skb_shinfo(skb)->nr_frags + 1)) {
6641                 netif_tx_stop_queue(txq);
6642                 dev_err(np->device, PFX "%s: BUG! Tx ring full when "
6643                         "queue awake!\n", dev->name);
6644                 rp->tx_errors++;
6645                 return NETDEV_TX_BUSY;
6646         }
6647
6648         if (skb->len < ETH_ZLEN) {
6649                 unsigned int pad_bytes = ETH_ZLEN - skb->len;
6650
6651                 if (skb_pad(skb, pad_bytes))
6652                         goto out;
6653                 skb_put(skb, pad_bytes);
6654         }
6655
6656         len = sizeof(struct tx_pkt_hdr) + 15;
6657         if (skb_headroom(skb) < len) {
6658                 struct sk_buff *skb_new;
6659
6660                 skb_new = skb_realloc_headroom(skb, len);
6661                 if (!skb_new) {
6662                         rp->tx_errors++;
6663                         goto out_drop;
6664                 }
6665                 kfree_skb(skb);
6666                 skb = skb_new;
6667         } else
6668                 skb_orphan(skb);
6669
6670         align = ((unsigned long) skb->data & (16 - 1));
6671         headroom = align + sizeof(struct tx_pkt_hdr);
6672
6673         ehdr = (struct ethhdr *) skb->data;
6674         tp = (struct tx_pkt_hdr *) skb_push(skb, headroom);
6675
6676         len = skb->len - sizeof(struct tx_pkt_hdr);
6677         tp->flags = cpu_to_le64(niu_compute_tx_flags(skb, ehdr, align, len));
6678         tp->resv = 0;
6679
6680         len = skb_headlen(skb);
6681         mapping = np->ops->map_single(np->device, skb->data,
6682                                       len, DMA_TO_DEVICE);
6683
6684         prod = rp->prod;
6685
6686         rp->tx_buffs[prod].skb = skb;
6687         rp->tx_buffs[prod].mapping = mapping;
6688
6689         mrk = TX_DESC_SOP;
6690         if (++rp->mark_counter == rp->mark_freq) {
6691                 rp->mark_counter = 0;
6692                 mrk |= TX_DESC_MARK;
6693                 rp->mark_pending++;
6694         }
6695
6696         tlen = len;
6697         nfg = skb_shinfo(skb)->nr_frags;
6698         while (tlen > 0) {
6699                 tlen -= MAX_TX_DESC_LEN;
6700                 nfg++;
6701         }
6702
6703         while (len > 0) {
6704                 unsigned int this_len = len;
6705
6706                 if (this_len > MAX_TX_DESC_LEN)
6707                         this_len = MAX_TX_DESC_LEN;
6708
6709                 niu_set_txd(rp, prod, mapping, this_len, mrk, nfg);
6710                 mrk = nfg = 0;
6711
6712                 prod = NEXT_TX(rp, prod);
6713                 mapping += this_len;
6714                 len -= this_len;
6715         }
6716
6717         for (i = 0; i <  skb_shinfo(skb)->nr_frags; i++) {
6718                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6719
6720                 len = frag->size;
6721                 mapping = np->ops->map_page(np->device, frag->page,
6722                                             frag->page_offset, len,
6723                                             DMA_TO_DEVICE);
6724
6725                 rp->tx_buffs[prod].skb = NULL;
6726                 rp->tx_buffs[prod].mapping = mapping;
6727
6728                 niu_set_txd(rp, prod, mapping, len, 0, 0);
6729
6730                 prod = NEXT_TX(rp, prod);
6731         }
6732
6733         if (prod < rp->prod)
6734                 rp->wrap_bit ^= TX_RING_KICK_WRAP;
6735         rp->prod = prod;
6736
6737         nw64(TX_RING_KICK(rp->tx_channel), rp->wrap_bit | (prod << 3));
6738
6739         if (unlikely(niu_tx_avail(rp) <= (MAX_SKB_FRAGS + 1))) {
6740                 netif_tx_stop_queue(txq);
6741                 if (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp))
6742                         netif_tx_wake_queue(txq);
6743         }
6744
6745         dev->trans_start = jiffies;
6746
6747 out:
6748         return NETDEV_TX_OK;
6749
6750 out_drop:
6751         rp->tx_errors++;
6752         kfree_skb(skb);
6753         goto out;
6754 }
6755
6756 static int niu_change_mtu(struct net_device *dev, int new_mtu)
6757 {
6758         struct niu *np = netdev_priv(dev);
6759         int err, orig_jumbo, new_jumbo;
6760
6761         if (new_mtu < 68 || new_mtu > NIU_MAX_MTU)
6762                 return -EINVAL;
6763
6764         orig_jumbo = (dev->mtu > ETH_DATA_LEN);
6765         new_jumbo = (new_mtu > ETH_DATA_LEN);
6766
6767         dev->mtu = new_mtu;
6768
6769         if (!netif_running(dev) ||
6770             (orig_jumbo == new_jumbo))
6771                 return 0;
6772
6773         niu_full_shutdown(np, dev);
6774
6775         niu_free_channels(np);
6776
6777         niu_enable_napi(np);
6778
6779         err = niu_alloc_channels(np);
6780         if (err)
6781                 return err;
6782
6783         spin_lock_irq(&np->lock);
6784
6785         err = niu_init_hw(np);
6786         if (!err) {
6787                 init_timer(&np->timer);
6788                 np->timer.expires = jiffies + HZ;
6789                 np->timer.data = (unsigned long) np;
6790                 np->timer.function = niu_timer;
6791
6792                 err = niu_enable_interrupts(np, 1);
6793                 if (err)
6794                         niu_stop_hw(np);
6795         }
6796
6797         spin_unlock_irq(&np->lock);
6798
6799         if (!err) {
6800                 netif_tx_start_all_queues(dev);
6801                 if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
6802                         netif_carrier_on(dev);
6803
6804                 add_timer(&np->timer);
6805         }
6806
6807         return err;
6808 }
6809
6810 static void niu_get_drvinfo(struct net_device *dev,
6811                             struct ethtool_drvinfo *info)
6812 {
6813         struct niu *np = netdev_priv(dev);
6814         struct niu_vpd *vpd = &np->vpd;
6815
6816         strcpy(info->driver, DRV_MODULE_NAME);
6817         strcpy(info->version, DRV_MODULE_VERSION);
6818         sprintf(info->fw_version, "%d.%d",
6819                 vpd->fcode_major, vpd->fcode_minor);
6820         if (np->parent->plat_type != PLAT_TYPE_NIU)
6821                 strcpy(info->bus_info, pci_name(np->pdev));
6822 }
6823
6824 static int niu_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6825 {
6826         struct niu *np = netdev_priv(dev);
6827         struct niu_link_config *lp;
6828
6829         lp = &np->link_config;
6830
6831         memset(cmd, 0, sizeof(*cmd));
6832         cmd->phy_address = np->phy_addr;
6833         cmd->supported = lp->supported;
6834         cmd->advertising = lp->active_advertising;
6835         cmd->autoneg = lp->active_autoneg;
6836         cmd->speed = lp->active_speed;
6837         cmd->duplex = lp->active_duplex;
6838         cmd->port = (np->flags & NIU_FLAGS_FIBER) ? PORT_FIBRE : PORT_TP;
6839         cmd->transceiver = (np->flags & NIU_FLAGS_XCVR_SERDES) ?
6840                 XCVR_EXTERNAL : XCVR_INTERNAL;
6841
6842         return 0;
6843 }
6844
6845 static int niu_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6846 {
6847         struct niu *np = netdev_priv(dev);
6848         struct niu_link_config *lp = &np->link_config;
6849
6850         lp->advertising = cmd->advertising;
6851         lp->speed = cmd->speed;
6852         lp->duplex = cmd->duplex;
6853         lp->autoneg = cmd->autoneg;
6854         return niu_init_link(np);
6855 }
6856
6857 static u32 niu_get_msglevel(struct net_device *dev)
6858 {
6859         struct niu *np = netdev_priv(dev);
6860         return np->msg_enable;
6861 }
6862
6863 static void niu_set_msglevel(struct net_device *dev, u32 value)
6864 {
6865         struct niu *np = netdev_priv(dev);
6866         np->msg_enable = value;
6867 }
6868
6869 static int niu_nway_reset(struct net_device *dev)
6870 {
6871         struct niu *np = netdev_priv(dev);
6872
6873         if (np->link_config.autoneg)
6874                 return niu_init_link(np);
6875
6876         return 0;
6877 }
6878
6879 static int niu_get_eeprom_len(struct net_device *dev)
6880 {
6881         struct niu *np = netdev_priv(dev);
6882
6883         return np->eeprom_len;
6884 }
6885
6886 static int niu_get_eeprom(struct net_device *dev,
6887                           struct ethtool_eeprom *eeprom, u8 *data)
6888 {
6889         struct niu *np = netdev_priv(dev);
6890         u32 offset, len, val;
6891
6892         offset = eeprom->offset;
6893         len = eeprom->len;
6894
6895         if (offset + len < offset)
6896                 return -EINVAL;
6897         if (offset >= np->eeprom_len)
6898                 return -EINVAL;
6899         if (offset + len > np->eeprom_len)
6900                 len = eeprom->len = np->eeprom_len - offset;
6901
6902         if (offset & 3) {
6903                 u32 b_offset, b_count;
6904
6905                 b_offset = offset & 3;
6906                 b_count = 4 - b_offset;
6907                 if (b_count > len)
6908                         b_count = len;
6909
6910                 val = nr64(ESPC_NCR((offset - b_offset) / 4));
6911                 memcpy(data, ((char *)&val) + b_offset, b_count);
6912                 data += b_count;
6913                 len -= b_count;
6914                 offset += b_count;
6915         }
6916         while (len >= 4) {
6917                 val = nr64(ESPC_NCR(offset / 4));
6918                 memcpy(data, &val, 4);
6919                 data += 4;
6920                 len -= 4;
6921                 offset += 4;
6922         }
6923         if (len) {
6924                 val = nr64(ESPC_NCR(offset / 4));
6925                 memcpy(data, &val, len);
6926         }
6927         return 0;
6928 }
6929
6930 static void niu_ethflow_to_l3proto(int flow_type, u8 *pid)
6931 {
6932         switch (flow_type) {
6933         case TCP_V4_FLOW:
6934         case TCP_V6_FLOW:
6935                 *pid = IPPROTO_TCP;
6936                 break;
6937         case UDP_V4_FLOW:
6938         case UDP_V6_FLOW:
6939                 *pid = IPPROTO_UDP;
6940                 break;
6941         case SCTP_V4_FLOW:
6942         case SCTP_V6_FLOW:
6943                 *pid = IPPROTO_SCTP;
6944                 break;
6945         case AH_V4_FLOW:
6946         case AH_V6_FLOW:
6947                 *pid = IPPROTO_AH;
6948                 break;
6949         case ESP_V4_FLOW:
6950         case ESP_V6_FLOW:
6951                 *pid = IPPROTO_ESP;
6952                 break;
6953         default:
6954                 *pid = 0;
6955                 break;
6956         }
6957 }
6958
6959 static int niu_class_to_ethflow(u64 class, int *flow_type)
6960 {
6961         switch (class) {
6962         case CLASS_CODE_TCP_IPV4:
6963                 *flow_type = TCP_V4_FLOW;
6964                 break;
6965         case CLASS_CODE_UDP_IPV4:
6966                 *flow_type = UDP_V4_FLOW;
6967                 break;
6968         case CLASS_CODE_AH_ESP_IPV4:
6969                 *flow_type = AH_V4_FLOW;
6970                 break;
6971         case CLASS_CODE_SCTP_IPV4:
6972                 *flow_type = SCTP_V4_FLOW;
6973                 break;
6974         case CLASS_CODE_TCP_IPV6:
6975                 *flow_type = TCP_V6_FLOW;
6976                 break;
6977         case CLASS_CODE_UDP_IPV6:
6978                 *flow_type = UDP_V6_FLOW;
6979                 break;
6980         case CLASS_CODE_AH_ESP_IPV6:
6981                 *flow_type = AH_V6_FLOW;
6982                 break;
6983         case CLASS_CODE_SCTP_IPV6:
6984                 *flow_type = SCTP_V6_FLOW;
6985                 break;
6986         case CLASS_CODE_USER_PROG1:
6987         case CLASS_CODE_USER_PROG2:
6988         case CLASS_CODE_USER_PROG3:
6989         case CLASS_CODE_USER_PROG4:
6990                 *flow_type = IP_USER_FLOW;
6991                 break;
6992         default:
6993                 return 0;
6994         }
6995
6996         return 1;
6997 }
6998
6999 static int niu_ethflow_to_class(int flow_type, u64 *class)
7000 {
7001         switch (flow_type) {
7002         case TCP_V4_FLOW:
7003                 *class = CLASS_CODE_TCP_IPV4;
7004                 break;
7005         case UDP_V4_FLOW:
7006                 *class = CLASS_CODE_UDP_IPV4;
7007                 break;
7008         case AH_V4_FLOW:
7009         case ESP_V4_FLOW:
7010                 *class = CLASS_CODE_AH_ESP_IPV4;
7011                 break;
7012         case SCTP_V4_FLOW:
7013                 *class = CLASS_CODE_SCTP_IPV4;
7014                 break;
7015         case TCP_V6_FLOW:
7016                 *class = CLASS_CODE_TCP_IPV6;
7017                 break;
7018         case UDP_V6_FLOW:
7019                 *class = CLASS_CODE_UDP_IPV6;
7020                 break;
7021         case AH_V6_FLOW:
7022         case ESP_V6_FLOW:
7023                 *class = CLASS_CODE_AH_ESP_IPV6;
7024                 break;
7025         case SCTP_V6_FLOW:
7026                 *class = CLASS_CODE_SCTP_IPV6;
7027                 break;
7028         default:
7029                 return 0;
7030         }
7031
7032         return 1;
7033 }
7034
7035 static u64 niu_flowkey_to_ethflow(u64 flow_key)
7036 {
7037         u64 ethflow = 0;
7038
7039         if (flow_key & FLOW_KEY_L2DA)
7040                 ethflow |= RXH_L2DA;
7041         if (flow_key & FLOW_KEY_VLAN)
7042                 ethflow |= RXH_VLAN;
7043         if (flow_key & FLOW_KEY_IPSA)
7044                 ethflow |= RXH_IP_SRC;
7045         if (flow_key & FLOW_KEY_IPDA)
7046                 ethflow |= RXH_IP_DST;
7047         if (flow_key & FLOW_KEY_PROTO)
7048                 ethflow |= RXH_L3_PROTO;
7049         if (flow_key & (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_0_SHIFT))
7050                 ethflow |= RXH_L4_B_0_1;
7051         if (flow_key & (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_1_SHIFT))
7052                 ethflow |= RXH_L4_B_2_3;
7053
7054         return ethflow;
7055
7056 }
7057
7058 static int niu_ethflow_to_flowkey(u64 ethflow, u64 *flow_key)
7059 {
7060         u64 key = 0;
7061
7062         if (ethflow & RXH_L2DA)
7063                 key |= FLOW_KEY_L2DA;
7064         if (ethflow & RXH_VLAN)
7065                 key |= FLOW_KEY_VLAN;
7066         if (ethflow & RXH_IP_SRC)
7067                 key |= FLOW_KEY_IPSA;
7068         if (ethflow & RXH_IP_DST)
7069                 key |= FLOW_KEY_IPDA;
7070         if (ethflow & RXH_L3_PROTO)
7071                 key |= FLOW_KEY_PROTO;
7072         if (ethflow & RXH_L4_B_0_1)
7073                 key |= (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_0_SHIFT);
7074         if (ethflow & RXH_L4_B_2_3)
7075                 key |= (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_1_SHIFT);
7076
7077         *flow_key = key;
7078
7079         return 1;
7080
7081 }
7082
7083 static int niu_get_hash_opts(struct niu *np, struct ethtool_rxnfc *nfc)
7084 {
7085         u64 class;
7086
7087         nfc->data = 0;
7088
7089         if (!niu_ethflow_to_class(nfc->flow_type, &class))
7090                 return -EINVAL;
7091
7092         if (np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] &
7093             TCAM_KEY_DISC)
7094                 nfc->data = RXH_DISCARD;
7095         else
7096                 nfc->data = niu_flowkey_to_ethflow(np->parent->flow_key[class -
7097                                                       CLASS_CODE_USER_PROG1]);
7098         return 0;
7099 }
7100
7101 static void niu_get_ip4fs_from_tcam_key(struct niu_tcam_entry *tp,
7102                                         struct ethtool_rx_flow_spec *fsp)
7103 {
7104
7105         fsp->h_u.tcp_ip4_spec.ip4src = (tp->key[3] & TCAM_V4KEY3_SADDR) >>
7106                 TCAM_V4KEY3_SADDR_SHIFT;
7107         fsp->h_u.tcp_ip4_spec.ip4dst = (tp->key[3] & TCAM_V4KEY3_DADDR) >>
7108                 TCAM_V4KEY3_DADDR_SHIFT;
7109         fsp->m_u.tcp_ip4_spec.ip4src = (tp->key_mask[3] & TCAM_V4KEY3_SADDR) >>
7110                 TCAM_V4KEY3_SADDR_SHIFT;
7111         fsp->m_u.tcp_ip4_spec.ip4dst = (tp->key_mask[3] & TCAM_V4KEY3_DADDR) >>
7112                 TCAM_V4KEY3_DADDR_SHIFT;
7113
7114         fsp->h_u.tcp_ip4_spec.ip4src =
7115                 cpu_to_be32(fsp->h_u.tcp_ip4_spec.ip4src);
7116         fsp->m_u.tcp_ip4_spec.ip4src =
7117                 cpu_to_be32(fsp->m_u.tcp_ip4_spec.ip4src);
7118         fsp->h_u.tcp_ip4_spec.ip4dst =
7119                 cpu_to_be32(fsp->h_u.tcp_ip4_spec.ip4dst);
7120         fsp->m_u.tcp_ip4_spec.ip4dst =
7121                 cpu_to_be32(fsp->m_u.tcp_ip4_spec.ip4dst);
7122
7123         fsp->h_u.tcp_ip4_spec.tos = (tp->key[2] & TCAM_V4KEY2_TOS) >>
7124                 TCAM_V4KEY2_TOS_SHIFT;
7125         fsp->m_u.tcp_ip4_spec.tos = (tp->key_mask[2] & TCAM_V4KEY2_TOS) >>
7126                 TCAM_V4KEY2_TOS_SHIFT;
7127
7128         switch (fsp->flow_type) {
7129         case TCP_V4_FLOW:
7130         case UDP_V4_FLOW:
7131         case SCTP_V4_FLOW:
7132                 fsp->h_u.tcp_ip4_spec.psrc =
7133                         ((tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
7134                          TCAM_V4KEY2_PORT_SPI_SHIFT) >> 16;
7135                 fsp->h_u.tcp_ip4_spec.pdst =
7136                         ((tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
7137                          TCAM_V4KEY2_PORT_SPI_SHIFT) & 0xffff;
7138                 fsp->m_u.tcp_ip4_spec.psrc =
7139                         ((tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7140                          TCAM_V4KEY2_PORT_SPI_SHIFT) >> 16;
7141                 fsp->m_u.tcp_ip4_spec.pdst =
7142                         ((tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7143                          TCAM_V4KEY2_PORT_SPI_SHIFT) & 0xffff;
7144
7145                 fsp->h_u.tcp_ip4_spec.psrc =
7146                         cpu_to_be16(fsp->h_u.tcp_ip4_spec.psrc);
7147                 fsp->h_u.tcp_ip4_spec.pdst =
7148                         cpu_to_be16(fsp->h_u.tcp_ip4_spec.pdst);
7149                 fsp->m_u.tcp_ip4_spec.psrc =
7150                         cpu_to_be16(fsp->m_u.tcp_ip4_spec.psrc);
7151                 fsp->m_u.tcp_ip4_spec.pdst =
7152                         cpu_to_be16(fsp->m_u.tcp_ip4_spec.pdst);
7153                 break;
7154         case AH_V4_FLOW:
7155         case ESP_V4_FLOW:
7156                 fsp->h_u.ah_ip4_spec.spi =
7157                         (tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
7158                         TCAM_V4KEY2_PORT_SPI_SHIFT;
7159                 fsp->m_u.ah_ip4_spec.spi =
7160                         (tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7161                         TCAM_V4KEY2_PORT_SPI_SHIFT;
7162
7163                 fsp->h_u.ah_ip4_spec.spi =
7164                         cpu_to_be32(fsp->h_u.ah_ip4_spec.spi);
7165                 fsp->m_u.ah_ip4_spec.spi =
7166                         cpu_to_be32(fsp->m_u.ah_ip4_spec.spi);
7167                 break;
7168         case IP_USER_FLOW:
7169                 fsp->h_u.usr_ip4_spec.l4_4_bytes =
7170                         (tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
7171                         TCAM_V4KEY2_PORT_SPI_SHIFT;
7172                 fsp->m_u.usr_ip4_spec.l4_4_bytes =
7173                         (tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7174                         TCAM_V4KEY2_PORT_SPI_SHIFT;
7175
7176                 fsp->h_u.usr_ip4_spec.l4_4_bytes =
7177                         cpu_to_be32(fsp->h_u.usr_ip4_spec.l4_4_bytes);
7178                 fsp->m_u.usr_ip4_spec.l4_4_bytes =
7179                         cpu_to_be32(fsp->m_u.usr_ip4_spec.l4_4_bytes);
7180
7181                 fsp->h_u.usr_ip4_spec.proto =
7182                         (tp->key[2] & TCAM_V4KEY2_PROTO) >>
7183                         TCAM_V4KEY2_PROTO_SHIFT;
7184                 fsp->m_u.usr_ip4_spec.proto =
7185                         (tp->key_mask[2] & TCAM_V4KEY2_PROTO) >>
7186                         TCAM_V4KEY2_PROTO_SHIFT;
7187
7188                 fsp->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4;
7189                 break;
7190         default:
7191                 break;
7192         }
7193 }
7194
7195 static int niu_get_ethtool_tcam_entry(struct niu *np,
7196                                       struct ethtool_rxnfc *nfc)
7197 {
7198         struct niu_parent *parent = np->parent;
7199         struct niu_tcam_entry *tp;
7200         struct ethtool_rx_flow_spec *fsp = &nfc->fs;
7201         u16 idx;
7202         u64 class;
7203         int ret = 0;
7204
7205         idx = tcam_get_index(np, (u16)nfc->fs.location);
7206
7207         tp = &parent->tcam[idx];
7208         if (!tp->valid) {
7209                 pr_info(PFX "niu%d: %s entry [%d] invalid for idx[%d]\n",
7210                 parent->index, np->dev->name, (u16)nfc->fs.location, idx);
7211                 return -EINVAL;
7212         }
7213
7214         /* fill the flow spec entry */
7215         class = (tp->key[0] & TCAM_V4KEY0_CLASS_CODE) >>
7216                 TCAM_V4KEY0_CLASS_CODE_SHIFT;
7217         ret = niu_class_to_ethflow(class, &fsp->flow_type);
7218
7219         if (ret < 0) {
7220                 pr_info(PFX "niu%d: %s niu_class_to_ethflow failed\n",
7221                 parent->index, np->dev->name);
7222                 ret = -EINVAL;
7223                 goto out;
7224         }
7225
7226         if (fsp->flow_type == AH_V4_FLOW || fsp->flow_type == AH_V6_FLOW) {
7227                 u32 proto = (tp->key[2] & TCAM_V4KEY2_PROTO) >>
7228                         TCAM_V4KEY2_PROTO_SHIFT;
7229                 if (proto == IPPROTO_ESP) {
7230                         if (fsp->flow_type == AH_V4_FLOW)
7231                                 fsp->flow_type = ESP_V4_FLOW;
7232                         else
7233                                 fsp->flow_type = ESP_V6_FLOW;
7234                 }
7235         }
7236
7237         switch (fsp->flow_type) {
7238         case TCP_V4_FLOW:
7239         case UDP_V4_FLOW:
7240         case SCTP_V4_FLOW:
7241         case AH_V4_FLOW:
7242         case ESP_V4_FLOW:
7243                 niu_get_ip4fs_from_tcam_key(tp, fsp);
7244                 break;
7245         case TCP_V6_FLOW:
7246         case UDP_V6_FLOW:
7247         case SCTP_V6_FLOW:
7248         case AH_V6_FLOW:
7249         case ESP_V6_FLOW:
7250                 /* Not yet implemented */
7251                 ret = -EINVAL;
7252                 break;
7253         case IP_USER_FLOW:
7254                 niu_get_ip4fs_from_tcam_key(tp, fsp);
7255                 break;
7256         default:
7257                 ret = -EINVAL;
7258                 break;
7259         }
7260
7261         if (ret < 0)
7262                 goto out;
7263
7264         if (tp->assoc_data & TCAM_ASSOCDATA_DISC)
7265                 fsp->ring_cookie = RX_CLS_FLOW_DISC;
7266         else
7267                 fsp->ring_cookie = (tp->assoc_data & TCAM_ASSOCDATA_OFFSET) >>
7268                         TCAM_ASSOCDATA_OFFSET_SHIFT;
7269
7270         /* put the tcam size here */
7271         nfc->data = tcam_get_size(np);
7272 out:
7273         return ret;
7274 }
7275
7276 static int niu_get_ethtool_tcam_all(struct niu *np,
7277                                     struct ethtool_rxnfc *nfc,
7278                                     u32 *rule_locs)
7279 {
7280         struct niu_parent *parent = np->parent;
7281         struct niu_tcam_entry *tp;
7282         int i, idx, cnt;
7283         u16 n_entries;
7284         unsigned long flags;
7285
7286
7287         /* put the tcam size here */
7288         nfc->data = tcam_get_size(np);
7289
7290         niu_lock_parent(np, flags);
7291         n_entries = nfc->rule_cnt;
7292         for (cnt = 0, i = 0; i < nfc->data; i++) {
7293                 idx = tcam_get_index(np, i);
7294                 tp = &parent->tcam[idx];
7295                 if (!tp->valid)
7296                         continue;
7297                 rule_locs[cnt] = i;
7298                 cnt++;
7299         }
7300         niu_unlock_parent(np, flags);
7301
7302         if (n_entries != cnt) {
7303                 /* print warning, this should not happen */
7304                 pr_info(PFX "niu%d: %s In niu_get_ethtool_tcam_all, "
7305                         "n_entries[%d] != cnt[%d]!!!\n\n",
7306                         np->parent->index, np->dev->name, n_entries, cnt);
7307         }
7308
7309         return 0;
7310 }
7311
7312 static int niu_get_nfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
7313                        void *rule_locs)
7314 {
7315         struct niu *np = netdev_priv(dev);
7316         int ret = 0;
7317
7318         switch (cmd->cmd) {
7319         case ETHTOOL_GRXFH:
7320                 ret = niu_get_hash_opts(np, cmd);
7321                 break;
7322         case ETHTOOL_GRXRINGS:
7323                 cmd->data = np->num_rx_rings;
7324                 break;
7325         case ETHTOOL_GRXCLSRLCNT:
7326                 cmd->rule_cnt = tcam_get_valid_entry_cnt(np);
7327                 break;
7328         case ETHTOOL_GRXCLSRULE:
7329                 ret = niu_get_ethtool_tcam_entry(np, cmd);
7330                 break;
7331         case ETHTOOL_GRXCLSRLALL:
7332                 ret = niu_get_ethtool_tcam_all(np, cmd, (u32 *)rule_locs);
7333                 break;
7334         default:
7335                 ret = -EINVAL;
7336                 break;
7337         }
7338
7339         return ret;
7340 }
7341
7342 static int niu_set_hash_opts(struct niu *np, struct ethtool_rxnfc *nfc)
7343 {
7344         u64 class;
7345         u64 flow_key = 0;
7346         unsigned long flags;
7347
7348         if (!niu_ethflow_to_class(nfc->flow_type, &class))
7349                 return -EINVAL;
7350
7351         if (class < CLASS_CODE_USER_PROG1 ||
7352             class > CLASS_CODE_SCTP_IPV6)
7353                 return -EINVAL;
7354
7355         if (nfc->data & RXH_DISCARD) {
7356                 niu_lock_parent(np, flags);
7357                 flow_key = np->parent->tcam_key[class -
7358                                                CLASS_CODE_USER_PROG1];
7359                 flow_key |= TCAM_KEY_DISC;
7360                 nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1), flow_key);
7361                 np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] = flow_key;
7362                 niu_unlock_parent(np, flags);
7363                 return 0;
7364         } else {
7365                 /* Discard was set before, but is not set now */
7366                 if (np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] &
7367                     TCAM_KEY_DISC) {
7368                         niu_lock_parent(np, flags);
7369                         flow_key = np->parent->tcam_key[class -
7370                                                CLASS_CODE_USER_PROG1];
7371                         flow_key &= ~TCAM_KEY_DISC;
7372                         nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1),
7373                              flow_key);
7374                         np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] =
7375                                 flow_key;
7376                         niu_unlock_parent(np, flags);
7377                 }
7378         }
7379
7380         if (!niu_ethflow_to_flowkey(nfc->data, &flow_key))
7381                 return -EINVAL;
7382
7383         niu_lock_parent(np, flags);
7384         nw64(FLOW_KEY(class - CLASS_CODE_USER_PROG1), flow_key);
7385         np->parent->flow_key[class - CLASS_CODE_USER_PROG1] = flow_key;
7386         niu_unlock_parent(np, flags);
7387
7388         return 0;
7389 }
7390
7391 static void niu_get_tcamkey_from_ip4fs(struct ethtool_rx_flow_spec *fsp,
7392                                        struct niu_tcam_entry *tp,
7393                                        int l2_rdc_tab, u64 class)
7394 {
7395         u8 pid = 0;
7396         u32 sip, dip, sipm, dipm, spi, spim;
7397         u16 sport, dport, spm, dpm;
7398
7399         sip = be32_to_cpu(fsp->h_u.tcp_ip4_spec.ip4src);
7400         sipm = be32_to_cpu(fsp->m_u.tcp_ip4_spec.ip4src);
7401         dip = be32_to_cpu(fsp->h_u.tcp_ip4_spec.ip4dst);
7402         dipm = be32_to_cpu(fsp->m_u.tcp_ip4_spec.ip4dst);
7403
7404         tp->key[0] = class << TCAM_V4KEY0_CLASS_CODE_SHIFT;
7405         tp->key_mask[0] = TCAM_V4KEY0_CLASS_CODE;
7406         tp->key[1] = (u64)l2_rdc_tab << TCAM_V4KEY1_L2RDCNUM_SHIFT;
7407         tp->key_mask[1] = TCAM_V4KEY1_L2RDCNUM;
7408
7409         tp->key[3] = (u64)sip << TCAM_V4KEY3_SADDR_SHIFT;
7410         tp->key[3] |= dip;
7411
7412         tp->key_mask[3] = (u64)sipm << TCAM_V4KEY3_SADDR_SHIFT;
7413         tp->key_mask[3] |= dipm;
7414
7415         tp->key[2] |= ((u64)fsp->h_u.tcp_ip4_spec.tos <<
7416                        TCAM_V4KEY2_TOS_SHIFT);
7417         tp->key_mask[2] |= ((u64)fsp->m_u.tcp_ip4_spec.tos <<
7418                             TCAM_V4KEY2_TOS_SHIFT);
7419         switch (fsp->flow_type) {
7420         case TCP_V4_FLOW:
7421         case UDP_V4_FLOW:
7422         case SCTP_V4_FLOW:
7423                 sport = be16_to_cpu(fsp->h_u.tcp_ip4_spec.psrc);
7424                 spm = be16_to_cpu(fsp->m_u.tcp_ip4_spec.psrc);
7425                 dport = be16_to_cpu(fsp->h_u.tcp_ip4_spec.pdst);
7426                 dpm = be16_to_cpu(fsp->m_u.tcp_ip4_spec.pdst);
7427
7428                 tp->key[2] |= (((u64)sport << 16) | dport);
7429                 tp->key_mask[2] |= (((u64)spm << 16) | dpm);
7430                 niu_ethflow_to_l3proto(fsp->flow_type, &pid);
7431                 break;
7432         case AH_V4_FLOW:
7433         case ESP_V4_FLOW:
7434                 spi = be32_to_cpu(fsp->h_u.ah_ip4_spec.spi);
7435                 spim = be32_to_cpu(fsp->m_u.ah_ip4_spec.spi);
7436
7437                 tp->key[2] |= spi;
7438                 tp->key_mask[2] |= spim;
7439                 niu_ethflow_to_l3proto(fsp->flow_type, &pid);
7440                 break;
7441         case IP_USER_FLOW:
7442                 spi = be32_to_cpu(fsp->h_u.usr_ip4_spec.l4_4_bytes);
7443                 spim = be32_to_cpu(fsp->m_u.usr_ip4_spec.l4_4_bytes);
7444
7445                 tp->key[2] |= spi;
7446                 tp->key_mask[2] |= spim;
7447                 pid = fsp->h_u.usr_ip4_spec.proto;
7448                 break;
7449         default:
7450                 break;
7451         }
7452
7453         tp->key[2] |= ((u64)pid << TCAM_V4KEY2_PROTO_SHIFT);
7454         if (pid) {
7455                 tp->key_mask[2] |= TCAM_V4KEY2_PROTO;
7456         }
7457 }
7458
7459 static int niu_add_ethtool_tcam_entry(struct niu *np,
7460                                       struct ethtool_rxnfc *nfc)
7461 {
7462         struct niu_parent *parent = np->parent;
7463         struct niu_tcam_entry *tp;
7464         struct ethtool_rx_flow_spec *fsp = &nfc->fs;
7465         struct niu_rdc_tables *rdc_table = &parent->rdc_group_cfg[np->port];
7466         int l2_rdc_table = rdc_table->first_table_num;
7467         u16 idx;
7468         u64 class;
7469         unsigned long flags;
7470         int err, ret;
7471
7472         ret = 0;
7473
7474         idx = nfc->fs.location;
7475         if (idx >= tcam_get_size(np))
7476                 return -EINVAL;
7477
7478         if (fsp->flow_type == IP_USER_FLOW) {
7479                 int i;
7480                 int add_usr_cls = 0;
7481                 int ipv6 = 0;
7482                 struct ethtool_usrip4_spec *uspec = &fsp->h_u.usr_ip4_spec;
7483                 struct ethtool_usrip4_spec *umask = &fsp->m_u.usr_ip4_spec;
7484
7485                 niu_lock_parent(np, flags);
7486
7487                 for (i = 0; i < NIU_L3_PROG_CLS; i++) {
7488                         if (parent->l3_cls[i]) {
7489                                 if (uspec->proto == parent->l3_cls_pid[i]) {
7490                                         class = parent->l3_cls[i];
7491                                         parent->l3_cls_refcnt[i]++;
7492                                         add_usr_cls = 1;
7493                                         break;
7494                                 }
7495                         } else {
7496                                 /* Program new user IP class */
7497                                 switch (i) {
7498                                 case 0:
7499                                         class = CLASS_CODE_USER_PROG1;
7500                                         break;
7501                                 case 1:
7502                                         class = CLASS_CODE_USER_PROG2;
7503                                         break;
7504                                 case 2:
7505                                         class = CLASS_CODE_USER_PROG3;
7506                                         break;
7507                                 case 3:
7508                                         class = CLASS_CODE_USER_PROG4;
7509                                         break;
7510                                 default:
7511                                         break;
7512                                 }
7513                                 if (uspec->ip_ver == ETH_RX_NFC_IP6)
7514                                         ipv6 = 1;
7515                                 ret = tcam_user_ip_class_set(np, class, ipv6,
7516                                                              uspec->proto,
7517                                                              uspec->tos,
7518                                                              umask->tos);
7519                                 if (ret)
7520                                         goto out;
7521
7522                                 ret = tcam_user_ip_class_enable(np, class, 1);
7523                                 if (ret)
7524                                         goto out;
7525                                 parent->l3_cls[i] = class;
7526                                 parent->l3_cls_pid[i] = uspec->proto;
7527                                 parent->l3_cls_refcnt[i]++;
7528                                 add_usr_cls = 1;
7529                                 break;
7530                         }
7531                 }
7532                 if (!add_usr_cls) {
7533                         pr_info(PFX "niu%d: %s niu_add_ethtool_tcam_entry: "
7534                                 "Could not find/insert class for pid %d\n",
7535                                 parent->index, np->dev->name, uspec->proto);
7536                         ret = -EINVAL;
7537                         goto out;
7538                 }
7539                 niu_unlock_parent(np, flags);
7540         } else {
7541                 if (!niu_ethflow_to_class(fsp->flow_type, &class)) {
7542                         return -EINVAL;
7543                 }
7544         }
7545
7546         niu_lock_parent(np, flags);
7547
7548         idx = tcam_get_index(np, idx);
7549         tp = &parent->tcam[idx];
7550
7551         memset(tp, 0, sizeof(*tp));
7552
7553         /* fill in the tcam key and mask */
7554         switch (fsp->flow_type) {
7555         case TCP_V4_FLOW:
7556         case UDP_V4_FLOW:
7557         case SCTP_V4_FLOW:
7558         case AH_V4_FLOW:
7559         case ESP_V4_FLOW:
7560                 niu_get_tcamkey_from_ip4fs(fsp, tp, l2_rdc_table, class);
7561                 break;
7562         case TCP_V6_FLOW:
7563         case UDP_V6_FLOW:
7564         case SCTP_V6_FLOW:
7565         case AH_V6_FLOW:
7566         case ESP_V6_FLOW:
7567                 /* Not yet implemented */
7568                 pr_info(PFX "niu%d: %s In niu_add_ethtool_tcam_entry: "
7569                         "flow %d for IPv6 not implemented\n\n",
7570                         parent->index, np->dev->name, fsp->flow_type);
7571                 ret = -EINVAL;
7572                 goto out;
7573         case IP_USER_FLOW:
7574                 if (fsp->h_u.usr_ip4_spec.ip_ver == ETH_RX_NFC_IP4) {
7575                         niu_get_tcamkey_from_ip4fs(fsp, tp, l2_rdc_table,
7576                                                    class);
7577                 } else {
7578                         /* Not yet implemented */
7579                         pr_info(PFX "niu%d: %s In niu_add_ethtool_tcam_entry: "
7580                         "usr flow for IPv6 not implemented\n\n",
7581                         parent->index, np->dev->name);
7582                         ret = -EINVAL;
7583                         goto out;
7584                 }
7585                 break;
7586         default:
7587                 pr_info(PFX "niu%d: %s In niu_add_ethtool_tcam_entry: "
7588                         "Unknown flow type %d\n\n",
7589                         parent->index, np->dev->name, fsp->flow_type);
7590                 ret = -EINVAL;
7591                 goto out;
7592         }
7593
7594         /* fill in the assoc data */
7595         if (fsp->ring_cookie == RX_CLS_FLOW_DISC) {
7596                 tp->assoc_data = TCAM_ASSOCDATA_DISC;
7597         } else {
7598                 if (fsp->ring_cookie >= np->num_rx_rings) {
7599                         pr_info(PFX "niu%d: %s In niu_add_ethtool_tcam_entry: "
7600                                 "Invalid RX ring %lld\n\n",
7601                                 parent->index, np->dev->name,
7602                                 (long long) fsp->ring_cookie);
7603                         ret = -EINVAL;
7604                         goto out;
7605                 }
7606                 tp->assoc_data = (TCAM_ASSOCDATA_TRES_USE_OFFSET |
7607                                   (fsp->ring_cookie <<
7608                                    TCAM_ASSOCDATA_OFFSET_SHIFT));
7609         }
7610
7611         err = tcam_write(np, idx, tp->key, tp->key_mask);
7612         if (err) {
7613                 ret = -EINVAL;
7614                 goto out;
7615         }
7616         err = tcam_assoc_write(np, idx, tp->assoc_data);
7617         if (err) {
7618                 ret = -EINVAL;
7619                 goto out;
7620         }
7621
7622         /* validate the entry */
7623         tp->valid = 1;
7624         np->clas.tcam_valid_entries++;
7625 out:
7626         niu_unlock_parent(np, flags);
7627
7628         return ret;
7629 }
7630
7631 static int niu_del_ethtool_tcam_entry(struct niu *np, u32 loc)
7632 {
7633         struct niu_parent *parent = np->parent;
7634         struct niu_tcam_entry *tp;
7635         u16 idx;
7636         unsigned long flags;
7637         u64 class;
7638         int ret = 0;
7639
7640         if (loc >= tcam_get_size(np))
7641                 return -EINVAL;
7642
7643         niu_lock_parent(np, flags);
7644
7645         idx = tcam_get_index(np, loc);
7646         tp = &parent->tcam[idx];
7647
7648         /* if the entry is of a user defined class, then update*/
7649         class = (tp->key[0] & TCAM_V4KEY0_CLASS_CODE) >>
7650                 TCAM_V4KEY0_CLASS_CODE_SHIFT;
7651
7652         if (class >= CLASS_CODE_USER_PROG1 && class <= CLASS_CODE_USER_PROG4) {
7653                 int i;
7654                 for (i = 0; i < NIU_L3_PROG_CLS; i++) {
7655                         if (parent->l3_cls[i] == class) {
7656                                 parent->l3_cls_refcnt[i]--;
7657                                 if (!parent->l3_cls_refcnt[i]) {
7658                                         /* disable class */
7659                                         ret = tcam_user_ip_class_enable(np,
7660                                                                         class,
7661                                                                         0);
7662                                         if (ret)
7663                                                 goto out;
7664                                         parent->l3_cls[i] = 0;
7665                                         parent->l3_cls_pid[i] = 0;
7666                                 }
7667                                 break;
7668                         }
7669                 }
7670                 if (i == NIU_L3_PROG_CLS) {
7671                         pr_info(PFX "niu%d: %s In niu_del_ethtool_tcam_entry,"
7672                                 "Usr class 0x%llx not found \n",
7673                                 parent->index, np->dev->name,
7674                                 (unsigned long long) class);
7675                         ret = -EINVAL;
7676                         goto out;
7677                 }
7678         }
7679
7680         ret = tcam_flush(np, idx);
7681         if (ret)
7682                 goto out;
7683
7684         /* invalidate the entry */
7685         tp->valid = 0;
7686         np->clas.tcam_valid_entries--;
7687 out:
7688         niu_unlock_parent(np, flags);
7689
7690         return ret;
7691 }
7692
7693 static int niu_set_nfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
7694 {
7695         struct niu *np = netdev_priv(dev);
7696         int ret = 0;
7697
7698         switch (cmd->cmd) {
7699         case ETHTOOL_SRXFH:
7700                 ret = niu_set_hash_opts(np, cmd);
7701                 break;
7702         case ETHTOOL_SRXCLSRLINS:
7703                 ret = niu_add_ethtool_tcam_entry(np, cmd);
7704                 break;
7705         case ETHTOOL_SRXCLSRLDEL:
7706                 ret = niu_del_ethtool_tcam_entry(np, cmd->fs.location);
7707                 break;
7708         default:
7709                 ret = -EINVAL;
7710                 break;
7711         }
7712
7713         return ret;
7714 }
7715
7716 static const struct {
7717         const char string[ETH_GSTRING_LEN];
7718 } niu_xmac_stat_keys[] = {
7719         { "tx_frames" },
7720         { "tx_bytes" },
7721         { "tx_fifo_errors" },
7722         { "tx_overflow_errors" },
7723         { "tx_max_pkt_size_errors" },
7724         { "tx_underflow_errors" },
7725         { "rx_local_faults" },
7726         { "rx_remote_faults" },
7727         { "rx_link_faults" },
7728         { "rx_align_errors" },
7729         { "rx_frags" },
7730         { "rx_mcasts" },
7731         { "rx_bcasts" },
7732         { "rx_hist_cnt1" },
7733         { "rx_hist_cnt2" },
7734         { "rx_hist_cnt3" },
7735         { "rx_hist_cnt4" },
7736         { "rx_hist_cnt5" },
7737         { "rx_hist_cnt6" },
7738         { "rx_hist_cnt7" },
7739         { "rx_octets" },
7740         { "rx_code_violations" },
7741         { "rx_len_errors" },
7742         { "rx_crc_errors" },
7743         { "rx_underflows" },
7744         { "rx_overflows" },
7745         { "pause_off_state" },
7746         { "pause_on_state" },
7747         { "pause_received" },
7748 };
7749
7750 #define NUM_XMAC_STAT_KEYS      ARRAY_SIZE(niu_xmac_stat_keys)
7751
7752 static const struct {
7753         const char string[ETH_GSTRING_LEN];
7754 } niu_bmac_stat_keys[] = {
7755         { "tx_underflow_errors" },
7756         { "tx_max_pkt_size_errors" },
7757         { "tx_bytes" },
7758         { "tx_frames" },
7759         { "rx_overflows" },
7760         { "rx_frames" },
7761         { "rx_align_errors" },
7762         { "rx_crc_errors" },
7763         { "rx_len_errors" },
7764         { "pause_off_state" },
7765         { "pause_on_state" },
7766         { "pause_received" },
7767 };
7768
7769 #define NUM_BMAC_STAT_KEYS      ARRAY_SIZE(niu_bmac_stat_keys)
7770
7771 static const struct {
7772         const char string[ETH_GSTRING_LEN];
7773 } niu_rxchan_stat_keys[] = {
7774         { "rx_channel" },
7775         { "rx_packets" },
7776         { "rx_bytes" },
7777         { "rx_dropped" },
7778         { "rx_errors" },
7779 };
7780
7781 #define NUM_RXCHAN_STAT_KEYS    ARRAY_SIZE(niu_rxchan_stat_keys)
7782
7783 static const struct {
7784         const char string[ETH_GSTRING_LEN];
7785 } niu_txchan_stat_keys[] = {
7786         { "tx_channel" },
7787         { "tx_packets" },
7788         { "tx_bytes" },
7789         { "tx_errors" },
7790 };
7791
7792 #define NUM_TXCHAN_STAT_KEYS    ARRAY_SIZE(niu_txchan_stat_keys)
7793
7794 static void niu_get_strings(struct net_device *dev, u32 stringset, u8 *data)
7795 {
7796         struct niu *np = netdev_priv(dev);
7797         int i;
7798
7799         if (stringset != ETH_SS_STATS)
7800                 return;
7801
7802         if (np->flags & NIU_FLAGS_XMAC) {
7803                 memcpy(data, niu_xmac_stat_keys,
7804                        sizeof(niu_xmac_stat_keys));
7805                 data += sizeof(niu_xmac_stat_keys);
7806         } else {
7807                 memcpy(data, niu_bmac_stat_keys,
7808                        sizeof(niu_bmac_stat_keys));
7809                 data += sizeof(niu_bmac_stat_keys);
7810         }
7811         for (i = 0; i < np->num_rx_rings; i++) {
7812                 memcpy(data, niu_rxchan_stat_keys,
7813                        sizeof(niu_rxchan_stat_keys));
7814                 data += sizeof(niu_rxchan_stat_keys);
7815         }
7816         for (i = 0; i < np->num_tx_rings; i++) {
7817                 memcpy(data, niu_txchan_stat_keys,
7818                        sizeof(niu_txchan_stat_keys));
7819                 data += sizeof(niu_txchan_stat_keys);
7820         }
7821 }
7822
7823 static int niu_get_stats_count(struct net_device *dev)
7824 {
7825         struct niu *np = netdev_priv(dev);
7826
7827         return ((np->flags & NIU_FLAGS_XMAC ?
7828                  NUM_XMAC_STAT_KEYS :
7829                  NUM_BMAC_STAT_KEYS) +
7830                 (np->num_rx_rings * NUM_RXCHAN_STAT_KEYS) +
7831                 (np->num_tx_rings * NUM_TXCHAN_STAT_KEYS));
7832 }
7833
7834 static void niu_get_ethtool_stats(struct net_device *dev,
7835                                   struct ethtool_stats *stats, u64 *data)
7836 {
7837         struct niu *np = netdev_priv(dev);
7838         int i;
7839
7840         niu_sync_mac_stats(np);
7841         if (np->flags & NIU_FLAGS_XMAC) {
7842                 memcpy(data, &np->mac_stats.xmac,
7843                        sizeof(struct niu_xmac_stats));
7844                 data += (sizeof(struct niu_xmac_stats) / sizeof(u64));
7845         } else {
7846                 memcpy(data, &np->mac_stats.bmac,
7847                        sizeof(struct niu_bmac_stats));
7848                 data += (sizeof(struct niu_bmac_stats) / sizeof(u64));
7849         }
7850         for (i = 0; i < np->num_rx_rings; i++) {
7851                 struct rx_ring_info *rp = &np->rx_rings[i];
7852
7853                 niu_sync_rx_discard_stats(np, rp, 0);
7854
7855                 data[0] = rp->rx_channel;
7856                 data[1] = rp->rx_packets;
7857                 data[2] = rp->rx_bytes;
7858                 data[3] = rp->rx_dropped;
7859                 data[4] = rp->rx_errors;
7860                 data += 5;
7861         }
7862         for (i = 0; i < np->num_tx_rings; i++) {
7863                 struct tx_ring_info *rp = &np->tx_rings[i];
7864
7865                 data[0] = rp->tx_channel;
7866                 data[1] = rp->tx_packets;
7867                 data[2] = rp->tx_bytes;
7868                 data[3] = rp->tx_errors;
7869                 data += 4;
7870         }
7871 }
7872
7873 static u64 niu_led_state_save(struct niu *np)
7874 {
7875         if (np->flags & NIU_FLAGS_XMAC)
7876                 return nr64_mac(XMAC_CONFIG);
7877         else
7878                 return nr64_mac(BMAC_XIF_CONFIG);
7879 }
7880
7881 static void niu_led_state_restore(struct niu *np, u64 val)
7882 {
7883         if (np->flags & NIU_FLAGS_XMAC)
7884                 nw64_mac(XMAC_CONFIG, val);
7885         else
7886                 nw64_mac(BMAC_XIF_CONFIG, val);
7887 }
7888
7889 static void niu_force_led(struct niu *np, int on)
7890 {
7891         u64 val, reg, bit;
7892
7893         if (np->flags & NIU_FLAGS_XMAC) {
7894                 reg = XMAC_CONFIG;
7895                 bit = XMAC_CONFIG_FORCE_LED_ON;
7896         } else {
7897                 reg = BMAC_XIF_CONFIG;
7898                 bit = BMAC_XIF_CONFIG_LINK_LED;
7899         }
7900
7901         val = nr64_mac(reg);
7902         if (on)
7903                 val |= bit;
7904         else
7905                 val &= ~bit;
7906         nw64_mac(reg, val);
7907 }
7908
7909 static int niu_phys_id(struct net_device *dev, u32 data)
7910 {
7911         struct niu *np = netdev_priv(dev);
7912         u64 orig_led_state;
7913         int i;
7914
7915         if (!netif_running(dev))
7916                 return -EAGAIN;
7917
7918         if (data == 0)
7919                 data = 2;
7920
7921         orig_led_state = niu_led_state_save(np);
7922         for (i = 0; i < (data * 2); i++) {
7923                 int on = ((i % 2) == 0);
7924
7925                 niu_force_led(np, on);
7926
7927                 if (msleep_interruptible(500))
7928                         break;
7929         }
7930         niu_led_state_restore(np, orig_led_state);
7931
7932         return 0;
7933 }
7934
7935 static const struct ethtool_ops niu_ethtool_ops = {
7936         .get_drvinfo            = niu_get_drvinfo,
7937         .get_link               = ethtool_op_get_link,
7938         .get_msglevel           = niu_get_msglevel,
7939         .set_msglevel           = niu_set_msglevel,
7940         .nway_reset             = niu_nway_reset,
7941         .get_eeprom_len         = niu_get_eeprom_len,
7942         .get_eeprom             = niu_get_eeprom,
7943         .get_settings           = niu_get_settings,
7944         .set_settings           = niu_set_settings,
7945         .get_strings            = niu_get_strings,
7946         .get_stats_count        = niu_get_stats_count,
7947         .get_ethtool_stats      = niu_get_ethtool_stats,
7948         .phys_id                = niu_phys_id,
7949         .get_rxnfc              = niu_get_nfc,
7950         .set_rxnfc              = niu_set_nfc,
7951 };
7952
7953 static int niu_ldg_assign_ldn(struct niu *np, struct niu_parent *parent,
7954                               int ldg, int ldn)
7955 {
7956         if (ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX)
7957                 return -EINVAL;
7958         if (ldn < 0 || ldn > LDN_MAX)
7959                 return -EINVAL;
7960
7961         parent->ldg_map[ldn] = ldg;
7962
7963         if (np->parent->plat_type == PLAT_TYPE_NIU) {
7964                 /* On N2 NIU, the ldn-->ldg assignments are setup and fixed by
7965                  * the firmware, and we're not supposed to change them.
7966                  * Validate the mapping, because if it's wrong we probably
7967                  * won't get any interrupts and that's painful to debug.
7968                  */
7969                 if (nr64(LDG_NUM(ldn)) != ldg) {
7970                         dev_err(np->device, PFX "Port %u, mis-matched "
7971                                 "LDG assignment "
7972                                 "for ldn %d, should be %d is %llu\n",
7973                                 np->port, ldn, ldg,
7974                                 (unsigned long long) nr64(LDG_NUM(ldn)));
7975                         return -EINVAL;
7976                 }
7977         } else
7978                 nw64(LDG_NUM(ldn), ldg);
7979
7980         return 0;
7981 }
7982
7983 static int niu_set_ldg_timer_res(struct niu *np, int res)
7984 {
7985         if (res < 0 || res > LDG_TIMER_RES_VAL)
7986                 return -EINVAL;
7987
7988
7989         nw64(LDG_TIMER_RES, res);
7990
7991         return 0;
7992 }
7993
7994 static int niu_set_ldg_sid(struct niu *np, int ldg, int func, int vector)
7995 {
7996         if ((ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX) ||
7997             (func < 0 || func > 3) ||
7998             (vector < 0 || vector > 0x1f))
7999                 return -EINVAL;
8000
8001         nw64(SID(ldg), (func << SID_FUNC_SHIFT) | vector);
8002
8003         return 0;
8004 }
8005
8006 static int __devinit niu_pci_eeprom_read(struct niu *np, u32 addr)
8007 {
8008         u64 frame, frame_base = (ESPC_PIO_STAT_READ_START |
8009                                  (addr << ESPC_PIO_STAT_ADDR_SHIFT));
8010         int limit;
8011
8012         if (addr > (ESPC_PIO_STAT_ADDR >> ESPC_PIO_STAT_ADDR_SHIFT))
8013                 return -EINVAL;
8014
8015         frame = frame_base;
8016         nw64(ESPC_PIO_STAT, frame);
8017         limit = 64;
8018         do {
8019                 udelay(5);
8020                 frame = nr64(ESPC_PIO_STAT);
8021                 if (frame & ESPC_PIO_STAT_READ_END)
8022                         break;
8023         } while (limit--);
8024         if (!(frame & ESPC_PIO_STAT_READ_END)) {
8025                 dev_err(np->device, PFX "EEPROM read timeout frame[%llx]\n",
8026                         (unsigned long long) frame);
8027                 return -ENODEV;
8028         }
8029
8030         frame = frame_base;
8031         nw64(ESPC_PIO_STAT, frame);
8032         limit = 64;
8033         do {
8034                 udelay(5);
8035                 frame = nr64(ESPC_PIO_STAT);
8036                 if (frame & ESPC_PIO_STAT_READ_END)
8037                         break;
8038         } while (limit--);
8039         if (!(frame & ESPC_PIO_STAT_READ_END)) {
8040                 dev_err(np->device, PFX "EEPROM read timeout frame[%llx]\n",
8041                         (unsigned long long) frame);
8042                 return -ENODEV;
8043         }
8044
8045         frame = nr64(ESPC_PIO_STAT);
8046         return (frame & ESPC_PIO_STAT_DATA) >> ESPC_PIO_STAT_DATA_SHIFT;
8047 }
8048
8049 static int __devinit niu_pci_eeprom_read16(struct niu *np, u32 off)
8050 {
8051         int err = niu_pci_eeprom_read(np, off);
8052         u16 val;
8053
8054         if (err < 0)
8055                 return err;
8056         val = (err << 8);
8057         err = niu_pci_eeprom_read(np, off + 1);
8058         if (err < 0)
8059                 return err;
8060         val |= (err & 0xff);
8061
8062         return val;
8063 }
8064
8065 static int __devinit niu_pci_eeprom_read16_swp(struct niu *np, u32 off)
8066 {
8067         int err = niu_pci_eeprom_read(np, off);
8068         u16 val;
8069
8070         if (err < 0)
8071                 return err;
8072
8073         val = (err & 0xff);
8074         err = niu_pci_eeprom_read(np, off + 1);
8075         if (err < 0)
8076                 return err;
8077
8078         val |= (err & 0xff) << 8;
8079
8080         return val;
8081 }
8082
8083 static int __devinit niu_pci_vpd_get_propname(struct niu *np,
8084                                               u32 off,
8085                                               char *namebuf,
8086                                               int namebuf_len)
8087 {
8088         int i;
8089
8090         for (i = 0; i < namebuf_len; i++) {
8091                 int err = niu_pci_eeprom_read(np, off + i);
8092                 if (err < 0)
8093                         return err;
8094                 *namebuf++ = err;
8095                 if (!err)
8096                         break;
8097         }
8098         if (i >= namebuf_len)
8099                 return -EINVAL;
8100
8101         return i + 1;
8102 }
8103
8104 static void __devinit niu_vpd_parse_version(struct niu *np)
8105 {
8106         struct niu_vpd *vpd = &np->vpd;
8107         int len = strlen(vpd->version) + 1;
8108         const char *s = vpd->version;
8109         int i;
8110
8111         for (i = 0; i < len - 5; i++) {
8112                 if (!strncmp(s + i, "FCode ", 5))
8113                         break;
8114         }
8115         if (i >= len - 5)
8116                 return;
8117
8118         s += i + 5;
8119         sscanf(s, "%d.%d", &vpd->fcode_major, &vpd->fcode_minor);
8120
8121         niudbg(PROBE, "VPD_SCAN: FCODE major(%d) minor(%d)\n",
8122                vpd->fcode_major, vpd->fcode_minor);
8123         if (vpd->fcode_major > NIU_VPD_MIN_MAJOR ||
8124             (vpd->fcode_major == NIU_VPD_MIN_MAJOR &&
8125              vpd->fcode_minor >= NIU_VPD_MIN_MINOR))
8126                 np->flags |= NIU_FLAGS_VPD_VALID;
8127 }
8128
8129 /* ESPC_PIO_EN_ENABLE must be set */
8130 static int __devinit niu_pci_vpd_scan_props(struct niu *np,
8131                                             u32 start, u32 end)
8132 {
8133         unsigned int found_mask = 0;
8134 #define FOUND_MASK_MODEL        0x00000001
8135 #define FOUND_MASK_BMODEL       0x00000002
8136 #define FOUND_MASK_VERS         0x00000004
8137 #define FOUND_MASK_MAC          0x00000008
8138 #define FOUND_MASK_NMAC         0x00000010
8139 #define FOUND_MASK_PHY          0x00000020
8140 #define FOUND_MASK_ALL          0x0000003f
8141
8142         niudbg(PROBE, "VPD_SCAN: start[%x] end[%x]\n",
8143                start, end);
8144         while (start < end) {
8145                 int len, err, instance, type, prop_len;
8146                 char namebuf[64];
8147                 u8 *prop_buf;
8148                 int max_len;
8149
8150                 if (found_mask == FOUND_MASK_ALL) {
8151                         niu_vpd_parse_version(np);
8152                         return 1;
8153                 }
8154
8155                 err = niu_pci_eeprom_read(np, start + 2);
8156                 if (err < 0)
8157                         return err;
8158                 len = err;
8159                 start += 3;
8160
8161                 instance = niu_pci_eeprom_read(np, start);
8162                 type = niu_pci_eeprom_read(np, start + 3);
8163                 prop_len = niu_pci_eeprom_read(np, start + 4);
8164                 err = niu_pci_vpd_get_propname(np, start + 5, namebuf, 64);
8165                 if (err < 0)
8166                         return err;
8167
8168                 prop_buf = NULL;
8169                 max_len = 0;
8170                 if (!strcmp(namebuf, "model")) {
8171                         prop_buf = np->vpd.model;
8172                         max_len = NIU_VPD_MODEL_MAX;
8173                         found_mask |= FOUND_MASK_MODEL;
8174                 } else if (!strcmp(namebuf, "board-model")) {
8175                         prop_buf = np->vpd.board_model;
8176                         max_len = NIU_VPD_BD_MODEL_MAX;
8177                         found_mask |= FOUND_MASK_BMODEL;
8178                 } else if (!strcmp(namebuf, "version")) {
8179                         prop_buf = np->vpd.version;
8180                         max_len = NIU_VPD_VERSION_MAX;
8181                         found_mask |= FOUND_MASK_VERS;
8182                 } else if (!strcmp(namebuf, "local-mac-address")) {
8183                         prop_buf = np->vpd.local_mac;
8184                         max_len = ETH_ALEN;
8185                         found_mask |= FOUND_MASK_MAC;
8186                 } else if (!strcmp(namebuf, "num-mac-addresses")) {
8187                         prop_buf = &np->vpd.mac_num;
8188                         max_len = 1;
8189                         found_mask |= FOUND_MASK_NMAC;
8190                 } else if (!strcmp(namebuf, "phy-type")) {
8191                         prop_buf = np->vpd.phy_type;
8192                         max_len = NIU_VPD_PHY_TYPE_MAX;
8193                         found_mask |= FOUND_MASK_PHY;
8194                 }
8195
8196                 if (max_len && prop_len > max_len) {
8197                         dev_err(np->device, PFX "Property '%s' length (%d) is "
8198                                 "too long.\n", namebuf, prop_len);
8199                         return -EINVAL;
8200                 }
8201
8202                 if (prop_buf) {
8203                         u32 off = start + 5 + err;
8204                         int i;
8205
8206                         niudbg(PROBE, "VPD_SCAN: Reading in property [%s] "
8207                                "len[%d]\n", namebuf, prop_len);
8208                         for (i = 0; i < prop_len; i++)
8209                                 *prop_buf++ = niu_pci_eeprom_read(np, off + i);
8210                 }
8211
8212                 start += len;
8213         }
8214
8215         return 0;
8216 }
8217
8218 /* ESPC_PIO_EN_ENABLE must be set */
8219 static void __devinit niu_pci_vpd_fetch(struct niu *np, u32 start)
8220 {
8221         u32 offset;
8222         int err;
8223
8224         err = niu_pci_eeprom_read16_swp(np, start + 1);
8225         if (err < 0)
8226                 return;
8227
8228         offset = err + 3;
8229
8230         while (start + offset < ESPC_EEPROM_SIZE) {
8231                 u32 here = start + offset;
8232                 u32 end;
8233
8234                 err = niu_pci_eeprom_read(np, here);
8235                 if (err != 0x90)
8236                         return;
8237
8238                 err = niu_pci_eeprom_read16_swp(np, here + 1);
8239                 if (err < 0)
8240                         return;
8241
8242                 here = start + offset + 3;
8243                 end = start + offset + err;
8244
8245                 offset += err;
8246
8247                 err = niu_pci_vpd_scan_props(np, here, end);
8248                 if (err < 0 || err == 1)
8249                         return;
8250         }
8251 }
8252
8253 /* ESPC_PIO_EN_ENABLE must be set */
8254 static u32 __devinit niu_pci_vpd_offset(struct niu *np)
8255 {
8256         u32 start = 0, end = ESPC_EEPROM_SIZE, ret;
8257         int err;
8258
8259         while (start < end) {
8260                 ret = start;
8261
8262                 /* ROM header signature?  */
8263                 err = niu_pci_eeprom_read16(np, start +  0);
8264                 if (err != 0x55aa)
8265                         return 0;
8266
8267                 /* Apply offset to PCI data structure.  */
8268                 err = niu_pci_eeprom_read16(np, start + 23);
8269                 if (err < 0)
8270                         return 0;
8271                 start += err;
8272
8273                 /* Check for "PCIR" signature.  */
8274                 err = niu_pci_eeprom_read16(np, start +  0);
8275                 if (err != 0x5043)
8276                         return 0;
8277                 err = niu_pci_eeprom_read16(np, start +  2);
8278                 if (err != 0x4952)
8279                         return 0;
8280
8281                 /* Check for OBP image type.  */
8282                 err = niu_pci_eeprom_read(np, start + 20);
8283                 if (err < 0)
8284                         return 0;
8285                 if (err != 0x01) {
8286                         err = niu_pci_eeprom_read(np, ret + 2);
8287                         if (err < 0)
8288                                 return 0;
8289
8290                         start = ret + (err * 512);
8291                         continue;
8292                 }
8293
8294                 err = niu_pci_eeprom_read16_swp(np, start + 8);
8295                 if (err < 0)
8296                         return err;
8297                 ret += err;
8298
8299                 err = niu_pci_eeprom_read(np, ret + 0);
8300                 if (err != 0x82)
8301                         return 0;
8302
8303                 return ret;
8304         }
8305
8306         return 0;
8307 }
8308
8309 static int __devinit niu_phy_type_prop_decode(struct niu *np,
8310                                               const char *phy_prop)
8311 {
8312         if (!strcmp(phy_prop, "mif")) {
8313                 /* 1G copper, MII */
8314                 np->flags &= ~(NIU_FLAGS_FIBER |
8315                                NIU_FLAGS_10G);
8316                 np->mac_xcvr = MAC_XCVR_MII;
8317         } else if (!strcmp(phy_prop, "xgf")) {
8318                 /* 10G fiber, XPCS */
8319                 np->flags |= (NIU_FLAGS_10G |
8320                               NIU_FLAGS_FIBER);
8321                 np->mac_xcvr = MAC_XCVR_XPCS;
8322         } else if (!strcmp(phy_prop, "pcs")) {
8323                 /* 1G fiber, PCS */
8324                 np->flags &= ~NIU_FLAGS_10G;
8325                 np->flags |= NIU_FLAGS_FIBER;
8326                 np->mac_xcvr = MAC_XCVR_PCS;
8327         } else if (!strcmp(phy_prop, "xgc")) {
8328                 /* 10G copper, XPCS */
8329                 np->flags |= NIU_FLAGS_10G;
8330                 np->flags &= ~NIU_FLAGS_FIBER;
8331                 np->mac_xcvr = MAC_XCVR_XPCS;
8332         } else if (!strcmp(phy_prop, "xgsd") || !strcmp(phy_prop, "gsd")) {
8333                 /* 10G Serdes or 1G Serdes, default to 10G */
8334                 np->flags |= NIU_FLAGS_10G;
8335                 np->flags &= ~NIU_FLAGS_FIBER;
8336                 np->flags |= NIU_FLAGS_XCVR_SERDES;
8337                 np->mac_xcvr = MAC_XCVR_XPCS;
8338         } else {
8339                 return -EINVAL;
8340         }
8341         return 0;
8342 }
8343
8344 static int niu_pci_vpd_get_nports(struct niu *np)
8345 {
8346         int ports = 0;
8347
8348         if ((!strcmp(np->vpd.model, NIU_QGC_LP_MDL_STR)) ||
8349             (!strcmp(np->vpd.model, NIU_QGC_PEM_MDL_STR)) ||
8350             (!strcmp(np->vpd.model, NIU_MARAMBA_MDL_STR)) ||
8351             (!strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) ||
8352             (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR))) {
8353                 ports = 4;
8354         } else if ((!strcmp(np->vpd.model, NIU_2XGF_LP_MDL_STR)) ||
8355                    (!strcmp(np->vpd.model, NIU_2XGF_PEM_MDL_STR)) ||
8356                    (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) ||
8357                    (!strcmp(np->vpd.model, NIU_2XGF_MRVL_MDL_STR))) {
8358                 ports = 2;
8359         }
8360
8361         return ports;
8362 }
8363
8364 static void __devinit niu_pci_vpd_validate(struct niu *np)
8365 {
8366         struct net_device *dev = np->dev;
8367         struct niu_vpd *vpd = &np->vpd;
8368         u8 val8;
8369
8370         if (!is_valid_ether_addr(&vpd->local_mac[0])) {
8371                 dev_err(np->device, PFX "VPD MAC invalid, "
8372                         "falling back to SPROM.\n");
8373
8374                 np->flags &= ~NIU_FLAGS_VPD_VALID;
8375                 return;
8376         }
8377
8378         if (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR) ||
8379             !strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) {
8380                 np->flags |= NIU_FLAGS_10G;
8381                 np->flags &= ~NIU_FLAGS_FIBER;
8382                 np->flags |= NIU_FLAGS_XCVR_SERDES;
8383                 np->mac_xcvr = MAC_XCVR_PCS;
8384                 if (np->port > 1) {
8385                         np->flags |= NIU_FLAGS_FIBER;
8386                         np->flags &= ~NIU_FLAGS_10G;
8387                 }
8388                 if (np->flags & NIU_FLAGS_10G)
8389                          np->mac_xcvr = MAC_XCVR_XPCS;
8390         } else if (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) {
8391                 np->flags |= (NIU_FLAGS_10G | NIU_FLAGS_FIBER |
8392                               NIU_FLAGS_HOTPLUG_PHY);
8393         } else if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) {
8394                 dev_err(np->device, PFX "Illegal phy string [%s].\n",
8395                         np->vpd.phy_type);
8396                 dev_err(np->device, PFX "Falling back to SPROM.\n");
8397                 np->flags &= ~NIU_FLAGS_VPD_VALID;
8398                 return;
8399         }
8400
8401         memcpy(dev->perm_addr, vpd->local_mac, ETH_ALEN);
8402
8403         val8 = dev->perm_addr[5];
8404         dev->perm_addr[5] += np->port;
8405         if (dev->perm_addr[5] < val8)
8406                 dev->perm_addr[4]++;
8407
8408         memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
8409 }
8410
8411 static int __devinit niu_pci_probe_sprom(struct niu *np)
8412 {
8413         struct net_device *dev = np->dev;
8414         int len, i;
8415         u64 val, sum;
8416         u8 val8;
8417
8418         val = (nr64(ESPC_VER_IMGSZ) & ESPC_VER_IMGSZ_IMGSZ);
8419         val >>= ESPC_VER_IMGSZ_IMGSZ_SHIFT;
8420         len = val / 4;
8421
8422         np->eeprom_len = len;
8423
8424         niudbg(PROBE, "SPROM: Image size %llu\n", (unsigned long long) val);
8425
8426         sum = 0;
8427         for (i = 0; i < len; i++) {
8428                 val = nr64(ESPC_NCR(i));
8429                 sum += (val >>  0) & 0xff;
8430                 sum += (val >>  8) & 0xff;
8431                 sum += (val >> 16) & 0xff;
8432                 sum += (val >> 24) & 0xff;
8433         }
8434         niudbg(PROBE, "SPROM: Checksum %x\n", (int)(sum & 0xff));
8435         if ((sum & 0xff) != 0xab) {
8436                 dev_err(np->device, PFX "Bad SPROM checksum "
8437                         "(%x, should be 0xab)\n", (int) (sum & 0xff));
8438                 return -EINVAL;
8439         }
8440
8441         val = nr64(ESPC_PHY_TYPE);
8442         switch (np->port) {
8443         case 0:
8444                 val8 = (val & ESPC_PHY_TYPE_PORT0) >>
8445                         ESPC_PHY_TYPE_PORT0_SHIFT;
8446                 break;
8447         case 1:
8448                 val8 = (val & ESPC_PHY_TYPE_PORT1) >>
8449                         ESPC_PHY_TYPE_PORT1_SHIFT;
8450                 break;
8451         case 2:
8452                 val8 = (val & ESPC_PHY_TYPE_PORT2) >>
8453                         ESPC_PHY_TYPE_PORT2_SHIFT;
8454                 break;
8455         case 3:
8456                 val8 = (val & ESPC_PHY_TYPE_PORT3) >>
8457                         ESPC_PHY_TYPE_PORT3_SHIFT;
8458                 break;
8459         default:
8460                 dev_err(np->device, PFX "Bogus port number %u\n",
8461                         np->port);
8462                 return -EINVAL;
8463         }
8464         niudbg(PROBE, "SPROM: PHY type %x\n", val8);
8465
8466         switch (val8) {
8467         case ESPC_PHY_TYPE_1G_COPPER:
8468                 /* 1G copper, MII */
8469                 np->flags &= ~(NIU_FLAGS_FIBER |
8470                                NIU_FLAGS_10G);
8471                 np->mac_xcvr = MAC_XCVR_MII;
8472                 break;
8473
8474         case ESPC_PHY_TYPE_1G_FIBER:
8475                 /* 1G fiber, PCS */
8476                 np->flags &= ~NIU_FLAGS_10G;
8477                 np->flags |= NIU_FLAGS_FIBER;
8478                 np->mac_xcvr = MAC_XCVR_PCS;
8479                 break;
8480
8481         case ESPC_PHY_TYPE_10G_COPPER:
8482                 /* 10G copper, XPCS */
8483                 np->flags |= NIU_FLAGS_10G;
8484                 np->flags &= ~NIU_FLAGS_FIBER;
8485                 np->mac_xcvr = MAC_XCVR_XPCS;
8486                 break;
8487
8488         case ESPC_PHY_TYPE_10G_FIBER:
8489                 /* 10G fiber, XPCS */
8490                 np->flags |= (NIU_FLAGS_10G |
8491                               NIU_FLAGS_FIBER);
8492                 np->mac_xcvr = MAC_XCVR_XPCS;
8493                 break;
8494
8495         default:
8496                 dev_err(np->device, PFX "Bogus SPROM phy type %u\n", val8);
8497                 return -EINVAL;
8498         }
8499
8500         val = nr64(ESPC_MAC_ADDR0);
8501         niudbg(PROBE, "SPROM: MAC_ADDR0[%08llx]\n",
8502                (unsigned long long) val);
8503         dev->perm_addr[0] = (val >>  0) & 0xff;
8504         dev->perm_addr[1] = (val >>  8) & 0xff;
8505         dev->perm_addr[2] = (val >> 16) & 0xff;
8506         dev->perm_addr[3] = (val >> 24) & 0xff;
8507
8508         val = nr64(ESPC_MAC_ADDR1);
8509         niudbg(PROBE, "SPROM: MAC_ADDR1[%08llx]\n",
8510                (unsigned long long) val);
8511         dev->perm_addr[4] = (val >>  0) & 0xff;
8512         dev->perm_addr[5] = (val >>  8) & 0xff;
8513
8514         if (!is_valid_ether_addr(&dev->perm_addr[0])) {
8515                 dev_err(np->device, PFX "SPROM MAC address invalid\n");
8516                 dev_err(np->device, PFX "[ \n");
8517                 for (i = 0; i < 6; i++)
8518                         printk("%02x ", dev->perm_addr[i]);
8519                 printk("]\n");
8520                 return -EINVAL;
8521         }
8522
8523         val8 = dev->perm_addr[5];
8524         dev->perm_addr[5] += np->port;
8525         if (dev->perm_addr[5] < val8)
8526                 dev->perm_addr[4]++;
8527
8528         memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
8529
8530         val = nr64(ESPC_MOD_STR_LEN);
8531         niudbg(PROBE, "SPROM: MOD_STR_LEN[%llu]\n",
8532                (unsigned long long) val);
8533         if (val >= 8 * 4)
8534                 return -EINVAL;
8535
8536         for (i = 0; i < val; i += 4) {
8537                 u64 tmp = nr64(ESPC_NCR(5 + (i / 4)));
8538
8539                 np->vpd.model[i + 3] = (tmp >>  0) & 0xff;
8540                 np->vpd.model[i + 2] = (tmp >>  8) & 0xff;
8541                 np->vpd.model[i + 1] = (tmp >> 16) & 0xff;
8542                 np->vpd.model[i + 0] = (tmp >> 24) & 0xff;
8543         }
8544         np->vpd.model[val] = '\0';
8545
8546         val = nr64(ESPC_BD_MOD_STR_LEN);
8547         niudbg(PROBE, "SPROM: BD_MOD_STR_LEN[%llu]\n",
8548                (unsigned long long) val);
8549         if (val >= 4 * 4)
8550                 return -EINVAL;
8551
8552         for (i = 0; i < val; i += 4) {
8553                 u64 tmp = nr64(ESPC_NCR(14 + (i / 4)));
8554
8555                 np->vpd.board_model[i + 3] = (tmp >>  0) & 0xff;
8556                 np->vpd.board_model[i + 2] = (tmp >>  8) & 0xff;
8557                 np->vpd.board_model[i + 1] = (tmp >> 16) & 0xff;
8558                 np->vpd.board_model[i + 0] = (tmp >> 24) & 0xff;
8559         }
8560         np->vpd.board_model[val] = '\0';
8561
8562         np->vpd.mac_num =
8563                 nr64(ESPC_NUM_PORTS_MACS) & ESPC_NUM_PORTS_MACS_VAL;
8564         niudbg(PROBE, "SPROM: NUM_PORTS_MACS[%d]\n",
8565                np->vpd.mac_num);
8566
8567         return 0;
8568 }
8569
8570 static int __devinit niu_get_and_validate_port(struct niu *np)
8571 {
8572         struct niu_parent *parent = np->parent;
8573
8574         if (np->port <= 1)
8575                 np->flags |= NIU_FLAGS_XMAC;
8576
8577         if (!parent->num_ports) {
8578                 if (parent->plat_type == PLAT_TYPE_NIU) {
8579                         parent->num_ports = 2;
8580                 } else {
8581                         parent->num_ports = niu_pci_vpd_get_nports(np);
8582                         if (!parent->num_ports) {
8583                                 /* Fall back to SPROM as last resort.
8584                                  * This will fail on most cards.
8585                                  */
8586                                 parent->num_ports = nr64(ESPC_NUM_PORTS_MACS) &
8587                                         ESPC_NUM_PORTS_MACS_VAL;
8588
8589                                 /* All of the current probing methods fail on
8590                                  * Maramba on-board parts.
8591                                  */
8592                                 if (!parent->num_ports)
8593                                         parent->num_ports = 4;
8594                         }
8595                 }
8596         }
8597
8598         niudbg(PROBE, "niu_get_and_validate_port: port[%d] num_ports[%d]\n",
8599                np->port, parent->num_ports);
8600         if (np->port >= parent->num_ports)
8601                 return -ENODEV;
8602
8603         return 0;
8604 }
8605
8606 static int __devinit phy_record(struct niu_parent *parent,
8607                                 struct phy_probe_info *p,
8608                                 int dev_id_1, int dev_id_2, u8 phy_port,
8609                                 int type)
8610 {
8611         u32 id = (dev_id_1 << 16) | dev_id_2;
8612         u8 idx;
8613
8614         if (dev_id_1 < 0 || dev_id_2 < 0)
8615                 return 0;
8616         if (type == PHY_TYPE_PMA_PMD || type == PHY_TYPE_PCS) {
8617                 if (((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM8704) &&
8618                     ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_MRVL88X2011) &&
8619                     ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM8706))
8620                         return 0;
8621         } else {
8622                 if ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM5464R)
8623                         return 0;
8624         }
8625
8626         pr_info("niu%d: Found PHY %08x type %s at phy_port %u\n",
8627                 parent->index, id,
8628                 (type == PHY_TYPE_PMA_PMD ?
8629                  "PMA/PMD" :
8630                  (type == PHY_TYPE_PCS ?
8631                   "PCS" : "MII")),
8632                 phy_port);
8633
8634         if (p->cur[type] >= NIU_MAX_PORTS) {
8635                 printk(KERN_ERR PFX "Too many PHY ports.\n");
8636                 return -EINVAL;
8637         }
8638         idx = p->cur[type];
8639         p->phy_id[type][idx] = id;
8640         p->phy_port[type][idx] = phy_port;
8641         p->cur[type] = idx + 1;
8642         return 0;
8643 }
8644
8645 static int __devinit port_has_10g(struct phy_probe_info *p, int port)
8646 {
8647         int i;
8648
8649         for (i = 0; i < p->cur[PHY_TYPE_PMA_PMD]; i++) {
8650                 if (p->phy_port[PHY_TYPE_PMA_PMD][i] == port)
8651                         return 1;
8652         }
8653         for (i = 0; i < p->cur[PHY_TYPE_PCS]; i++) {
8654                 if (p->phy_port[PHY_TYPE_PCS][i] == port)
8655                         return 1;
8656         }
8657
8658         return 0;
8659 }
8660
8661 static int __devinit count_10g_ports(struct phy_probe_info *p, int *lowest)
8662 {
8663         int port, cnt;
8664
8665         cnt = 0;
8666         *lowest = 32;
8667         for (port = 8; port < 32; port++) {
8668                 if (port_has_10g(p, port)) {
8669                         if (!cnt)
8670                                 *lowest = port;
8671                         cnt++;
8672                 }
8673         }
8674
8675         return cnt;
8676 }
8677
8678 static int __devinit count_1g_ports(struct phy_probe_info *p, int *lowest)
8679 {
8680         *lowest = 32;
8681         if (p->cur[PHY_TYPE_MII])
8682                 *lowest = p->phy_port[PHY_TYPE_MII][0];
8683
8684         return p->cur[PHY_TYPE_MII];
8685 }
8686
8687 static void __devinit niu_n2_divide_channels(struct niu_parent *parent)
8688 {
8689         int num_ports = parent->num_ports;
8690         int i;
8691
8692         for (i = 0; i < num_ports; i++) {
8693                 parent->rxchan_per_port[i] = (16 / num_ports);
8694                 parent->txchan_per_port[i] = (16 / num_ports);
8695
8696                 pr_info(PFX "niu%d: Port %u [%u RX chans] "
8697                         "[%u TX chans]\n",
8698                         parent->index, i,
8699                         parent->rxchan_per_port[i],
8700                         parent->txchan_per_port[i]);
8701         }
8702 }
8703
8704 static void __devinit niu_divide_channels(struct niu_parent *parent,
8705                                           int num_10g, int num_1g)
8706 {
8707         int num_ports = parent->num_ports;
8708         int rx_chans_per_10g, rx_chans_per_1g;
8709         int tx_chans_per_10g, tx_chans_per_1g;
8710         int i, tot_rx, tot_tx;
8711
8712         if (!num_10g || !num_1g) {
8713                 rx_chans_per_10g = rx_chans_per_1g =
8714                         (NIU_NUM_RXCHAN / num_ports);
8715                 tx_chans_per_10g = tx_chans_per_1g =
8716                         (NIU_NUM_TXCHAN / num_ports);
8717         } else {
8718                 rx_chans_per_1g = NIU_NUM_RXCHAN / 8;
8719                 rx_chans_per_10g = (NIU_NUM_RXCHAN -
8720                                     (rx_chans_per_1g * num_1g)) /
8721                         num_10g;
8722
8723                 tx_chans_per_1g = NIU_NUM_TXCHAN / 6;
8724                 tx_chans_per_10g = (NIU_NUM_TXCHAN -
8725                                     (tx_chans_per_1g * num_1g)) /
8726                         num_10g;
8727         }
8728
8729         tot_rx = tot_tx = 0;
8730         for (i = 0; i < num_ports; i++) {
8731                 int type = phy_decode(parent->port_phy, i);
8732
8733                 if (type == PORT_TYPE_10G) {
8734                         parent->rxchan_per_port[i] = rx_chans_per_10g;
8735                         parent->txchan_per_port[i] = tx_chans_per_10g;
8736                 } else {
8737                         parent->rxchan_per_port[i] = rx_chans_per_1g;
8738                         parent->txchan_per_port[i] = tx_chans_per_1g;
8739                 }
8740                 pr_info(PFX "niu%d: Port %u [%u RX chans] "
8741                         "[%u TX chans]\n",
8742                         parent->index, i,
8743                         parent->rxchan_per_port[i],
8744                         parent->txchan_per_port[i]);
8745                 tot_rx += parent->rxchan_per_port[i];
8746                 tot_tx += parent->txchan_per_port[i];
8747         }
8748
8749         if (tot_rx > NIU_NUM_RXCHAN) {
8750                 printk(KERN_ERR PFX "niu%d: Too many RX channels (%d), "
8751                        "resetting to one per port.\n",
8752                        parent->index, tot_rx);
8753                 for (i = 0; i < num_ports; i++)
8754                         parent->rxchan_per_port[i] = 1;
8755         }
8756         if (tot_tx > NIU_NUM_TXCHAN) {
8757                 printk(KERN_ERR PFX "niu%d: Too many TX channels (%d), "
8758                        "resetting to one per port.\n",
8759                        parent->index, tot_tx);
8760                 for (i = 0; i < num_ports; i++)
8761                         parent->txchan_per_port[i] = 1;
8762         }
8763         if (tot_rx < NIU_NUM_RXCHAN || tot_tx < NIU_NUM_TXCHAN) {
8764                 printk(KERN_WARNING PFX "niu%d: Driver bug, wasted channels, "
8765                        "RX[%d] TX[%d]\n",
8766                        parent->index, tot_rx, tot_tx);
8767         }
8768 }
8769
8770 static void __devinit niu_divide_rdc_groups(struct niu_parent *parent,
8771                                             int num_10g, int num_1g)
8772 {
8773         int i, num_ports = parent->num_ports;
8774         int rdc_group, rdc_groups_per_port;
8775         int rdc_channel_base;
8776
8777         rdc_group = 0;
8778         rdc_groups_per_port = NIU_NUM_RDC_TABLES / num_ports;
8779
8780         rdc_channel_base = 0;
8781
8782         for (i = 0; i < num_ports; i++) {
8783                 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[i];
8784                 int grp, num_channels = parent->rxchan_per_port[i];
8785                 int this_channel_offset;
8786
8787                 tp->first_table_num = rdc_group;
8788                 tp->num_tables = rdc_groups_per_port;
8789                 this_channel_offset = 0;
8790                 for (grp = 0; grp < tp->num_tables; grp++) {
8791                         struct rdc_table *rt = &tp->tables[grp];
8792                         int slot;
8793
8794                         pr_info(PFX "niu%d: Port %d RDC tbl(%d) [ ",
8795                                 parent->index, i, tp->first_table_num + grp);
8796                         for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++) {
8797                                 rt->rxdma_channel[slot] =
8798                                         rdc_channel_base + this_channel_offset;
8799
8800                                 printk("%d ", rt->rxdma_channel[slot]);
8801
8802                                 if (++this_channel_offset == num_channels)
8803                                         this_channel_offset = 0;
8804                         }
8805                         printk("]\n");
8806                 }
8807
8808                 parent->rdc_default[i] = rdc_channel_base;
8809
8810                 rdc_channel_base += num_channels;
8811                 rdc_group += rdc_groups_per_port;
8812         }
8813 }
8814
8815 static int __devinit fill_phy_probe_info(struct niu *np,
8816                                          struct niu_parent *parent,
8817                                          struct phy_probe_info *info)
8818 {
8819         unsigned long flags;
8820         int port, err;
8821
8822         memset(info, 0, sizeof(*info));
8823
8824         /* Port 0 to 7 are reserved for onboard Serdes, probe the rest.  */
8825         niu_lock_parent(np, flags);
8826         err = 0;
8827         for (port = 8; port < 32; port++) {
8828                 int dev_id_1, dev_id_2;
8829
8830                 dev_id_1 = mdio_read(np, port,
8831                                      NIU_PMA_PMD_DEV_ADDR, MII_PHYSID1);
8832                 dev_id_2 = mdio_read(np, port,
8833                                      NIU_PMA_PMD_DEV_ADDR, MII_PHYSID2);
8834                 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8835                                  PHY_TYPE_PMA_PMD);
8836                 if (err)
8837                         break;
8838                 dev_id_1 = mdio_read(np, port,
8839                                      NIU_PCS_DEV_ADDR, MII_PHYSID1);
8840                 dev_id_2 = mdio_read(np, port,
8841                                      NIU_PCS_DEV_ADDR, MII_PHYSID2);
8842                 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8843                                  PHY_TYPE_PCS);
8844                 if (err)
8845                         break;
8846                 dev_id_1 = mii_read(np, port, MII_PHYSID1);
8847                 dev_id_2 = mii_read(np, port, MII_PHYSID2);
8848                 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8849                                  PHY_TYPE_MII);
8850                 if (err)
8851                         break;
8852         }
8853         niu_unlock_parent(np, flags);
8854
8855         return err;
8856 }
8857
8858 static int __devinit walk_phys(struct niu *np, struct niu_parent *parent)
8859 {
8860         struct phy_probe_info *info = &parent->phy_probe_info;
8861         int lowest_10g, lowest_1g;
8862         int num_10g, num_1g;
8863         u32 val;
8864         int err;
8865
8866         num_10g = num_1g = 0;
8867
8868         if (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR) ||
8869             !strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) {
8870                 num_10g = 0;
8871                 num_1g = 2;
8872                 parent->plat_type = PLAT_TYPE_ATCA_CP3220;
8873                 parent->num_ports = 4;
8874                 val = (phy_encode(PORT_TYPE_1G, 0) |
8875                        phy_encode(PORT_TYPE_1G, 1) |
8876                        phy_encode(PORT_TYPE_1G, 2) |
8877                        phy_encode(PORT_TYPE_1G, 3));
8878         } else if (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) {
8879                 num_10g = 2;
8880                 num_1g = 0;
8881                 parent->num_ports = 2;
8882                 val = (phy_encode(PORT_TYPE_10G, 0) |
8883                        phy_encode(PORT_TYPE_10G, 1));
8884         } else if ((np->flags & NIU_FLAGS_XCVR_SERDES) &&
8885                    (parent->plat_type == PLAT_TYPE_NIU)) {
8886                 /* this is the Monza case */
8887                 if (np->flags & NIU_FLAGS_10G) {
8888                         val = (phy_encode(PORT_TYPE_10G, 0) |
8889                                phy_encode(PORT_TYPE_10G, 1));
8890                 } else {
8891                         val = (phy_encode(PORT_TYPE_1G, 0) |
8892                                phy_encode(PORT_TYPE_1G, 1));
8893                 }
8894         } else {
8895                 err = fill_phy_probe_info(np, parent, info);
8896                 if (err)
8897                         return err;
8898
8899                 num_10g = count_10g_ports(info, &lowest_10g);
8900                 num_1g = count_1g_ports(info, &lowest_1g);
8901
8902                 switch ((num_10g << 4) | num_1g) {
8903                 case 0x24:
8904                         if (lowest_1g == 10)
8905                                 parent->plat_type = PLAT_TYPE_VF_P0;
8906                         else if (lowest_1g == 26)
8907                                 parent->plat_type = PLAT_TYPE_VF_P1;
8908                         else
8909                                 goto unknown_vg_1g_port;
8910
8911                         /* fallthru */
8912                 case 0x22:
8913                         val = (phy_encode(PORT_TYPE_10G, 0) |
8914                                phy_encode(PORT_TYPE_10G, 1) |
8915                                phy_encode(PORT_TYPE_1G, 2) |
8916                                phy_encode(PORT_TYPE_1G, 3));
8917                         break;
8918
8919                 case 0x20:
8920                         val = (phy_encode(PORT_TYPE_10G, 0) |
8921                                phy_encode(PORT_TYPE_10G, 1));
8922                         break;
8923
8924                 case 0x10:
8925                         val = phy_encode(PORT_TYPE_10G, np->port);
8926                         break;
8927
8928                 case 0x14:
8929                         if (lowest_1g == 10)
8930                                 parent->plat_type = PLAT_TYPE_VF_P0;
8931                         else if (lowest_1g == 26)
8932                                 parent->plat_type = PLAT_TYPE_VF_P1;
8933                         else
8934                                 goto unknown_vg_1g_port;
8935
8936                         /* fallthru */
8937                 case 0x13:
8938                         if ((lowest_10g & 0x7) == 0)
8939                                 val = (phy_encode(PORT_TYPE_10G, 0) |
8940                                        phy_encode(PORT_TYPE_1G, 1) |
8941                                        phy_encode(PORT_TYPE_1G, 2) |
8942                                        phy_encode(PORT_TYPE_1G, 3));
8943                         else
8944                                 val = (phy_encode(PORT_TYPE_1G, 0) |
8945                                        phy_encode(PORT_TYPE_10G, 1) |
8946                                        phy_encode(PORT_TYPE_1G, 2) |
8947                                        phy_encode(PORT_TYPE_1G, 3));
8948                         break;
8949
8950                 case 0x04:
8951                         if (lowest_1g == 10)
8952                                 parent->plat_type = PLAT_TYPE_VF_P0;
8953                         else if (lowest_1g == 26)
8954                                 parent->plat_type = PLAT_TYPE_VF_P1;
8955                         else
8956                                 goto unknown_vg_1g_port;
8957
8958                         val = (phy_encode(PORT_TYPE_1G, 0) |
8959                                phy_encode(PORT_TYPE_1G, 1) |
8960                                phy_encode(PORT_TYPE_1G, 2) |
8961                                phy_encode(PORT_TYPE_1G, 3));
8962                         break;
8963
8964                 default:
8965                         printk(KERN_ERR PFX "Unsupported port config "
8966                                "10G[%d] 1G[%d]\n",
8967                                num_10g, num_1g);
8968                         return -EINVAL;
8969                 }
8970         }
8971
8972         parent->port_phy = val;
8973
8974         if (parent->plat_type == PLAT_TYPE_NIU)
8975                 niu_n2_divide_channels(parent);
8976         else
8977                 niu_divide_channels(parent, num_10g, num_1g);
8978
8979         niu_divide_rdc_groups(parent, num_10g, num_1g);
8980
8981         return 0;
8982
8983 unknown_vg_1g_port:
8984         printk(KERN_ERR PFX "Cannot identify platform type, 1gport=%d\n",
8985                lowest_1g);
8986         return -EINVAL;
8987 }
8988
8989 static int __devinit niu_probe_ports(struct niu *np)
8990 {
8991         struct niu_parent *parent = np->parent;
8992         int err, i;
8993
8994         niudbg(PROBE, "niu_probe_ports(): port_phy[%08x]\n",
8995                parent->port_phy);
8996
8997         if (parent->port_phy == PORT_PHY_UNKNOWN) {
8998                 err = walk_phys(np, parent);
8999                 if (err)
9000                         return err;
9001
9002                 niu_set_ldg_timer_res(np, 2);
9003                 for (i = 0; i <= LDN_MAX; i++)
9004                         niu_ldn_irq_enable(np, i, 0);
9005         }
9006
9007         if (parent->port_phy == PORT_PHY_INVALID)
9008                 return -EINVAL;
9009
9010         return 0;
9011 }
9012
9013 static int __devinit niu_classifier_swstate_init(struct niu *np)
9014 {
9015         struct niu_classifier *cp = &np->clas;
9016
9017         niudbg(PROBE, "niu_classifier_swstate_init: num_tcam(%d)\n",
9018                np->parent->tcam_num_entries);
9019
9020         cp->tcam_top = (u16) np->port;
9021         cp->tcam_sz = np->parent->tcam_num_entries / np->parent->num_ports;
9022         cp->h1_init = 0xffffffff;
9023         cp->h2_init = 0xffff;
9024
9025         return fflp_early_init(np);
9026 }
9027
9028 static void __devinit niu_link_config_init(struct niu *np)
9029 {
9030         struct niu_link_config *lp = &np->link_config;
9031
9032         lp->advertising = (ADVERTISED_10baseT_Half |
9033                            ADVERTISED_10baseT_Full |
9034                            ADVERTISED_100baseT_Half |
9035                            ADVERTISED_100baseT_Full |
9036                            ADVERTISED_1000baseT_Half |
9037                            ADVERTISED_1000baseT_Full |
9038                            ADVERTISED_10000baseT_Full |
9039                            ADVERTISED_Autoneg);
9040         lp->speed = lp->active_speed = SPEED_INVALID;
9041         lp->duplex = DUPLEX_FULL;
9042         lp->active_duplex = DUPLEX_INVALID;
9043         lp->autoneg = 1;
9044 #if 0
9045         lp->loopback_mode = LOOPBACK_MAC;
9046         lp->active_speed = SPEED_10000;
9047         lp->active_duplex = DUPLEX_FULL;
9048 #else
9049         lp->loopback_mode = LOOPBACK_DISABLED;
9050 #endif
9051 }
9052
9053 static int __devinit niu_init_mac_ipp_pcs_base(struct niu *np)
9054 {
9055         switch (np->port) {
9056         case 0:
9057                 np->mac_regs = np->regs + XMAC_PORT0_OFF;
9058                 np->ipp_off  = 0x00000;
9059                 np->pcs_off  = 0x04000;
9060                 np->xpcs_off = 0x02000;
9061                 break;
9062
9063         case 1:
9064                 np->mac_regs = np->regs + XMAC_PORT1_OFF;
9065                 np->ipp_off  = 0x08000;
9066                 np->pcs_off  = 0x0a000;
9067                 np->xpcs_off = 0x08000;
9068                 break;
9069
9070         case 2:
9071                 np->mac_regs = np->regs + BMAC_PORT2_OFF;
9072                 np->ipp_off  = 0x04000;
9073                 np->pcs_off  = 0x0e000;
9074                 np->xpcs_off = ~0UL;
9075                 break;
9076
9077         case 3:
9078                 np->mac_regs = np->regs + BMAC_PORT3_OFF;
9079                 np->ipp_off  = 0x0c000;
9080                 np->pcs_off  = 0x12000;
9081                 np->xpcs_off = ~0UL;
9082                 break;
9083
9084         default:
9085                 dev_err(np->device, PFX "Port %u is invalid, cannot "
9086                         "compute MAC block offset.\n", np->port);
9087                 return -EINVAL;
9088         }
9089
9090         return 0;
9091 }
9092
9093 static void __devinit niu_try_msix(struct niu *np, u8 *ldg_num_map)
9094 {
9095         struct msix_entry msi_vec[NIU_NUM_LDG];
9096         struct niu_parent *parent = np->parent;
9097         struct pci_dev *pdev = np->pdev;
9098         int i, num_irqs, err;
9099         u8 first_ldg;
9100
9101         first_ldg = (NIU_NUM_LDG / parent->num_ports) * np->port;
9102         for (i = 0; i < (NIU_NUM_LDG / parent->num_ports); i++)
9103                 ldg_num_map[i] = first_ldg + i;
9104
9105         num_irqs = (parent->rxchan_per_port[np->port] +
9106                     parent->txchan_per_port[np->port] +
9107                     (np->port == 0 ? 3 : 1));
9108         BUG_ON(num_irqs > (NIU_NUM_LDG / parent->num_ports));
9109
9110 retry:
9111         for (i = 0; i < num_irqs; i++) {
9112                 msi_vec[i].vector = 0;
9113                 msi_vec[i].entry = i;
9114         }
9115
9116         err = pci_enable_msix(pdev, msi_vec, num_irqs);
9117         if (err < 0) {
9118                 np->flags &= ~NIU_FLAGS_MSIX;
9119                 return;
9120         }
9121         if (err > 0) {
9122                 num_irqs = err;
9123                 goto retry;
9124         }
9125
9126         np->flags |= NIU_FLAGS_MSIX;
9127         for (i = 0; i < num_irqs; i++)
9128                 np->ldg[i].irq = msi_vec[i].vector;
9129         np->num_ldg = num_irqs;
9130 }
9131
9132 static int __devinit niu_n2_irq_init(struct niu *np, u8 *ldg_num_map)
9133 {
9134 #ifdef CONFIG_SPARC64
9135         struct of_device *op = np->op;
9136         const u32 *int_prop;
9137         int i;
9138
9139         int_prop = of_get_property(op->node, "interrupts", NULL);
9140         if (!int_prop)
9141                 return -ENODEV;
9142
9143         for (i = 0; i < op->num_irqs; i++) {
9144                 ldg_num_map[i] = int_prop[i];
9145                 np->ldg[i].irq = op->irqs[i];
9146         }
9147
9148         np->num_ldg = op->num_irqs;
9149
9150         return 0;
9151 #else
9152         return -EINVAL;
9153 #endif
9154 }
9155
9156 static int __devinit niu_ldg_init(struct niu *np)
9157 {
9158         struct niu_parent *parent = np->parent;
9159         u8 ldg_num_map[NIU_NUM_LDG];
9160         int first_chan, num_chan;
9161         int i, err, ldg_rotor;
9162         u8 port;
9163
9164         np->num_ldg = 1;
9165         np->ldg[0].irq = np->dev->irq;
9166         if (parent->plat_type == PLAT_TYPE_NIU) {
9167                 err = niu_n2_irq_init(np, ldg_num_map);
9168                 if (err)
9169                         return err;
9170         } else
9171                 niu_try_msix(np, ldg_num_map);
9172
9173         port = np->port;
9174         for (i = 0; i < np->num_ldg; i++) {
9175                 struct niu_ldg *lp = &np->ldg[i];
9176
9177                 netif_napi_add(np->dev, &lp->napi, niu_poll, 64);
9178
9179                 lp->np = np;
9180                 lp->ldg_num = ldg_num_map[i];
9181                 lp->timer = 2; /* XXX */
9182
9183                 /* On N2 NIU the firmware has setup the SID mappings so they go
9184                  * to the correct values that will route the LDG to the proper
9185                  * interrupt in the NCU interrupt table.
9186                  */
9187                 if (np->parent->plat_type != PLAT_TYPE_NIU) {
9188                         err = niu_set_ldg_sid(np, lp->ldg_num, port, i);
9189                         if (err)
9190                                 return err;
9191                 }
9192         }
9193
9194         /* We adopt the LDG assignment ordering used by the N2 NIU
9195          * 'interrupt' properties because that simplifies a lot of
9196          * things.  This ordering is:
9197          *
9198          *      MAC
9199          *      MIF     (if port zero)
9200          *      SYSERR  (if port zero)
9201          *      RX channels
9202          *      TX channels
9203          */
9204
9205         ldg_rotor = 0;
9206
9207         err = niu_ldg_assign_ldn(np, parent, ldg_num_map[ldg_rotor],
9208                                   LDN_MAC(port));
9209         if (err)
9210                 return err;
9211
9212         ldg_rotor++;
9213         if (ldg_rotor == np->num_ldg)
9214                 ldg_rotor = 0;
9215
9216         if (port == 0) {
9217                 err = niu_ldg_assign_ldn(np, parent,
9218                                          ldg_num_map[ldg_rotor],
9219                                          LDN_MIF);
9220                 if (err)
9221                         return err;
9222
9223                 ldg_rotor++;
9224                 if (ldg_rotor == np->num_ldg)
9225                         ldg_rotor = 0;
9226
9227                 err = niu_ldg_assign_ldn(np, parent,
9228                                          ldg_num_map[ldg_rotor],
9229                                          LDN_DEVICE_ERROR);
9230                 if (err)
9231                         return err;
9232
9233                 ldg_rotor++;
9234                 if (ldg_rotor == np->num_ldg)
9235                         ldg_rotor = 0;
9236
9237         }
9238
9239         first_chan = 0;
9240         for (i = 0; i < port; i++)
9241                 first_chan += parent->rxchan_per_port[port];
9242         num_chan = parent->rxchan_per_port[port];
9243
9244         for (i = first_chan; i < (first_chan + num_chan); i++) {
9245                 err = niu_ldg_assign_ldn(np, parent,
9246                                          ldg_num_map[ldg_rotor],
9247                                          LDN_RXDMA(i));
9248                 if (err)
9249                         return err;
9250                 ldg_rotor++;
9251                 if (ldg_rotor == np->num_ldg)
9252                         ldg_rotor = 0;
9253         }
9254
9255         first_chan = 0;
9256         for (i = 0; i < port; i++)
9257                 first_chan += parent->txchan_per_port[port];
9258         num_chan = parent->txchan_per_port[port];
9259         for (i = first_chan; i < (first_chan + num_chan); i++) {
9260                 err = niu_ldg_assign_ldn(np, parent,
9261                                          ldg_num_map[ldg_rotor],
9262                                          LDN_TXDMA(i));
9263                 if (err)
9264                         return err;
9265                 ldg_rotor++;
9266                 if (ldg_rotor == np->num_ldg)
9267                         ldg_rotor = 0;
9268         }
9269
9270         return 0;
9271 }
9272
9273 static void __devexit niu_ldg_free(struct niu *np)
9274 {
9275         if (np->flags & NIU_FLAGS_MSIX)
9276                 pci_disable_msix(np->pdev);
9277 }
9278
9279 static int __devinit niu_get_of_props(struct niu *np)
9280 {
9281 #ifdef CONFIG_SPARC64
9282         struct net_device *dev = np->dev;
9283         struct device_node *dp;
9284         const char *phy_type;
9285         const u8 *mac_addr;
9286         const char *model;
9287         int prop_len;
9288
9289         if (np->parent->plat_type == PLAT_TYPE_NIU)
9290                 dp = np->op->node;
9291         else
9292                 dp = pci_device_to_OF_node(np->pdev);
9293
9294         phy_type = of_get_property(dp, "phy-type", &prop_len);
9295         if (!phy_type) {
9296                 dev_err(np->device, PFX "%s: OF node lacks "
9297                         "phy-type property\n",
9298                         dp->full_name);
9299                 return -EINVAL;
9300         }
9301
9302         if (!strcmp(phy_type, "none"))
9303                 return -ENODEV;
9304
9305         strcpy(np->vpd.phy_type, phy_type);
9306
9307         if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) {
9308                 dev_err(np->device, PFX "%s: Illegal phy string [%s].\n",
9309                         dp->full_name, np->vpd.phy_type);
9310                 return -EINVAL;
9311         }
9312
9313         mac_addr = of_get_property(dp, "local-mac-address", &prop_len);
9314         if (!mac_addr) {
9315                 dev_err(np->device, PFX "%s: OF node lacks "
9316                         "local-mac-address property\n",
9317                         dp->full_name);
9318                 return -EINVAL;
9319         }
9320         if (prop_len != dev->addr_len) {
9321                 dev_err(np->device, PFX "%s: OF MAC address prop len (%d) "
9322                         "is wrong.\n",
9323                         dp->full_name, prop_len);
9324         }
9325         memcpy(dev->perm_addr, mac_addr, dev->addr_len);
9326         if (!is_valid_ether_addr(&dev->perm_addr[0])) {
9327                 int i;
9328
9329                 dev_err(np->device, PFX "%s: OF MAC address is invalid\n",
9330                         dp->full_name);
9331                 dev_err(np->device, PFX "%s: [ \n",
9332                         dp->full_name);
9333                 for (i = 0; i < 6; i++)
9334                         printk("%02x ", dev->perm_addr[i]);
9335                 printk("]\n");
9336                 return -EINVAL;
9337         }
9338
9339         memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
9340
9341         model = of_get_property(dp, "model", &prop_len);
9342
9343         if (model)
9344                 strcpy(np->vpd.model, model);
9345
9346         return 0;
9347 #else
9348         return -EINVAL;
9349 #endif
9350 }
9351
9352 static int __devinit niu_get_invariants(struct niu *np)
9353 {
9354         int err, have_props;
9355         u32 offset;
9356
9357         err = niu_get_of_props(np);
9358         if (err == -ENODEV)
9359                 return err;
9360
9361         have_props = !err;
9362
9363         err = niu_init_mac_ipp_pcs_base(np);
9364         if (err)
9365                 return err;
9366
9367         if (have_props) {
9368                 err = niu_get_and_validate_port(np);
9369                 if (err)
9370                         return err;
9371
9372         } else  {
9373                 if (np->parent->plat_type == PLAT_TYPE_NIU)
9374                         return -EINVAL;
9375
9376                 nw64(ESPC_PIO_EN, ESPC_PIO_EN_ENABLE);
9377                 offset = niu_pci_vpd_offset(np);
9378                 niudbg(PROBE, "niu_get_invariants: VPD offset [%08x]\n",
9379                        offset);
9380                 if (offset)
9381                         niu_pci_vpd_fetch(np, offset);
9382                 nw64(ESPC_PIO_EN, 0);
9383
9384                 if (np->flags & NIU_FLAGS_VPD_VALID) {
9385                         niu_pci_vpd_validate(np);
9386                         err = niu_get_and_validate_port(np);
9387                         if (err)
9388                                 return err;
9389                 }
9390
9391                 if (!(np->flags & NIU_FLAGS_VPD_VALID)) {
9392                         err = niu_get_and_validate_port(np);
9393                         if (err)
9394                                 return err;
9395                         err = niu_pci_probe_sprom(np);
9396                         if (err)
9397                                 return err;
9398                 }
9399         }
9400
9401         err = niu_probe_ports(np);
9402         if (err)
9403                 return err;
9404
9405         niu_ldg_init(np);
9406
9407         niu_classifier_swstate_init(np);
9408         niu_link_config_init(np);
9409
9410         err = niu_determine_phy_disposition(np);
9411         if (!err)
9412                 err = niu_init_link(np);
9413
9414         return err;
9415 }
9416
9417 static LIST_HEAD(niu_parent_list);
9418 static DEFINE_MUTEX(niu_parent_lock);
9419 static int niu_parent_index;
9420
9421 static ssize_t show_port_phy(struct device *dev,
9422                              struct device_attribute *attr, char *buf)
9423 {
9424         struct platform_device *plat_dev = to_platform_device(dev);
9425         struct niu_parent *p = plat_dev->dev.platform_data;
9426         u32 port_phy = p->port_phy;
9427         char *orig_buf = buf;
9428         int i;
9429
9430         if (port_phy == PORT_PHY_UNKNOWN ||
9431             port_phy == PORT_PHY_INVALID)
9432                 return 0;
9433
9434         for (i = 0; i < p->num_ports; i++) {
9435                 const char *type_str;
9436                 int type;
9437
9438                 type = phy_decode(port_phy, i);
9439                 if (type == PORT_TYPE_10G)
9440                         type_str = "10G";
9441                 else
9442                         type_str = "1G";
9443                 buf += sprintf(buf,
9444                                (i == 0) ? "%s" : " %s",
9445                                type_str);
9446         }
9447         buf += sprintf(buf, "\n");
9448         return buf - orig_buf;
9449 }
9450
9451 static ssize_t show_plat_type(struct device *dev,
9452                               struct device_attribute *attr, char *buf)
9453 {
9454         struct platform_device *plat_dev = to_platform_device(dev);
9455         struct niu_parent *p = plat_dev->dev.platform_data;
9456         const char *type_str;
9457
9458         switch (p->plat_type) {
9459         case PLAT_TYPE_ATLAS:
9460                 type_str = "atlas";
9461                 break;
9462         case PLAT_TYPE_NIU:
9463                 type_str = "niu";
9464                 break;
9465         case PLAT_TYPE_VF_P0:
9466                 type_str = "vf_p0";
9467                 break;
9468         case PLAT_TYPE_VF_P1:
9469                 type_str = "vf_p1";
9470                 break;
9471         default:
9472                 type_str = "unknown";
9473                 break;
9474         }
9475
9476         return sprintf(buf, "%s\n", type_str);
9477 }
9478
9479 static ssize_t __show_chan_per_port(struct device *dev,
9480                                     struct device_attribute *attr, char *buf,
9481                                     int rx)
9482 {
9483         struct platform_device *plat_dev = to_platform_device(dev);
9484         struct niu_parent *p = plat_dev->dev.platform_data;
9485         char *orig_buf = buf;
9486         u8 *arr;
9487         int i;
9488
9489         arr = (rx ? p->rxchan_per_port : p->txchan_per_port);
9490
9491         for (i = 0; i < p->num_ports; i++) {
9492                 buf += sprintf(buf,
9493                                (i == 0) ? "%d" : " %d",
9494                                arr[i]);
9495         }
9496         buf += sprintf(buf, "\n");
9497
9498         return buf - orig_buf;
9499 }
9500
9501 static ssize_t show_rxchan_per_port(struct device *dev,
9502                                     struct device_attribute *attr, char *buf)
9503 {
9504         return __show_chan_per_port(dev, attr, buf, 1);
9505 }
9506
9507 static ssize_t show_txchan_per_port(struct device *dev,
9508                                     struct device_attribute *attr, char *buf)
9509 {
9510         return __show_chan_per_port(dev, attr, buf, 1);
9511 }
9512
9513 static ssize_t show_num_ports(struct device *dev,
9514                               struct device_attribute *attr, char *buf)
9515 {
9516         struct platform_device *plat_dev = to_platform_device(dev);
9517         struct niu_parent *p = plat_dev->dev.platform_data;
9518
9519         return sprintf(buf, "%d\n", p->num_ports);
9520 }
9521
9522 static struct device_attribute niu_parent_attributes[] = {
9523         __ATTR(port_phy, S_IRUGO, show_port_phy, NULL),
9524         __ATTR(plat_type, S_IRUGO, show_plat_type, NULL),
9525         __ATTR(rxchan_per_port, S_IRUGO, show_rxchan_per_port, NULL),
9526         __ATTR(txchan_per_port, S_IRUGO, show_txchan_per_port, NULL),
9527         __ATTR(num_ports, S_IRUGO, show_num_ports, NULL),
9528         {}
9529 };
9530
9531 static struct niu_parent * __devinit niu_new_parent(struct niu *np,
9532                                                     union niu_parent_id *id,
9533                                                     u8 ptype)
9534 {
9535         struct platform_device *plat_dev;
9536         struct niu_parent *p;
9537         int i;
9538
9539         niudbg(PROBE, "niu_new_parent: Creating new parent.\n");
9540
9541         plat_dev = platform_device_register_simple("niu", niu_parent_index,
9542                                                    NULL, 0);
9543         if (!plat_dev)
9544                 return NULL;
9545
9546         for (i = 0; attr_name(niu_parent_attributes[i]); i++) {
9547                 int err = device_create_file(&plat_dev->dev,
9548                                              &niu_parent_attributes[i]);
9549                 if (err)
9550                         goto fail_unregister;
9551         }
9552
9553         p = kzalloc(sizeof(*p), GFP_KERNEL);
9554         if (!p)
9555                 goto fail_unregister;
9556
9557         p->index = niu_parent_index++;
9558
9559         plat_dev->dev.platform_data = p;
9560         p->plat_dev = plat_dev;
9561
9562         memcpy(&p->id, id, sizeof(*id));
9563         p->plat_type = ptype;
9564         INIT_LIST_HEAD(&p->list);
9565         atomic_set(&p->refcnt, 0);
9566         list_add(&p->list, &niu_parent_list);
9567         spin_lock_init(&p->lock);
9568
9569         p->rxdma_clock_divider = 7500;
9570
9571         p->tcam_num_entries = NIU_PCI_TCAM_ENTRIES;
9572         if (p->plat_type == PLAT_TYPE_NIU)
9573                 p->tcam_num_entries = NIU_NONPCI_TCAM_ENTRIES;
9574
9575         for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) {
9576                 int index = i - CLASS_CODE_USER_PROG1;
9577
9578                 p->tcam_key[index] = TCAM_KEY_TSEL;
9579                 p->flow_key[index] = (FLOW_KEY_IPSA |
9580                                       FLOW_KEY_IPDA |
9581                                       FLOW_KEY_PROTO |
9582                                       (FLOW_KEY_L4_BYTE12 <<
9583                                        FLOW_KEY_L4_0_SHIFT) |
9584                                       (FLOW_KEY_L4_BYTE12 <<
9585                                        FLOW_KEY_L4_1_SHIFT));
9586         }
9587
9588         for (i = 0; i < LDN_MAX + 1; i++)
9589                 p->ldg_map[i] = LDG_INVALID;
9590
9591         return p;
9592
9593 fail_unregister:
9594         platform_device_unregister(plat_dev);
9595         return NULL;
9596 }
9597
9598 static struct niu_parent * __devinit niu_get_parent(struct niu *np,
9599                                                     union niu_parent_id *id,
9600                                                     u8 ptype)
9601 {
9602         struct niu_parent *p, *tmp;
9603         int port = np->port;
9604
9605         niudbg(PROBE, "niu_get_parent: platform_type[%u] port[%u]\n",
9606                ptype, port);
9607
9608         mutex_lock(&niu_parent_lock);
9609         p = NULL;
9610         list_for_each_entry(tmp, &niu_parent_list, list) {
9611                 if (!memcmp(id, &tmp->id, sizeof(*id))) {
9612                         p = tmp;
9613                         break;
9614                 }
9615         }
9616         if (!p)
9617                 p = niu_new_parent(np, id, ptype);
9618
9619         if (p) {
9620                 char port_name[6];
9621                 int err;
9622
9623                 sprintf(port_name, "port%d", port);
9624                 err = sysfs_create_link(&p->plat_dev->dev.kobj,
9625                                         &np->device->kobj,
9626                                         port_name);
9627                 if (!err) {
9628                         p->ports[port] = np;
9629                         atomic_inc(&p->refcnt);
9630                 }
9631         }
9632         mutex_unlock(&niu_parent_lock);
9633
9634         return p;
9635 }
9636
9637 static void niu_put_parent(struct niu *np)
9638 {
9639         struct niu_parent *p = np->parent;
9640         u8 port = np->port;
9641         char port_name[6];
9642
9643         BUG_ON(!p || p->ports[port] != np);
9644
9645         niudbg(PROBE, "niu_put_parent: port[%u]\n", port);
9646
9647         sprintf(port_name, "port%d", port);
9648
9649         mutex_lock(&niu_parent_lock);
9650
9651         sysfs_remove_link(&p->plat_dev->dev.kobj, port_name);
9652
9653         p->ports[port] = NULL;
9654         np->parent = NULL;
9655
9656         if (atomic_dec_and_test(&p->refcnt)) {
9657                 list_del(&p->list);
9658                 platform_device_unregister(p->plat_dev);
9659         }
9660
9661         mutex_unlock(&niu_parent_lock);
9662 }
9663
9664 static void *niu_pci_alloc_coherent(struct device *dev, size_t size,
9665                                     u64 *handle, gfp_t flag)
9666 {
9667         dma_addr_t dh;
9668         void *ret;
9669
9670         ret = dma_alloc_coherent(dev, size, &dh, flag);
9671         if (ret)
9672                 *handle = dh;
9673         return ret;
9674 }
9675
9676 static void niu_pci_free_coherent(struct device *dev, size_t size,
9677                                   void *cpu_addr, u64 handle)
9678 {
9679         dma_free_coherent(dev, size, cpu_addr, handle);
9680 }
9681
9682 static u64 niu_pci_map_page(struct device *dev, struct page *page,
9683                             unsigned long offset, size_t size,
9684                             enum dma_data_direction direction)
9685 {
9686         return dma_map_page(dev, page, offset, size, direction);
9687 }
9688
9689 static void niu_pci_unmap_page(struct device *dev, u64 dma_address,
9690                                size_t size, enum dma_data_direction direction)
9691 {
9692         dma_unmap_page(dev, dma_address, size, direction);
9693 }
9694
9695 static u64 niu_pci_map_single(struct device *dev, void *cpu_addr,
9696                               size_t size,
9697                               enum dma_data_direction direction)
9698 {
9699         return dma_map_single(dev, cpu_addr, size, direction);
9700 }
9701
9702 static void niu_pci_unmap_single(struct device *dev, u64 dma_address,
9703                                  size_t size,
9704                                  enum dma_data_direction direction)
9705 {
9706         dma_unmap_single(dev, dma_address, size, direction);
9707 }
9708
9709 static const struct niu_ops niu_pci_ops = {
9710         .alloc_coherent = niu_pci_alloc_coherent,
9711         .free_coherent  = niu_pci_free_coherent,
9712         .map_page       = niu_pci_map_page,
9713         .unmap_page     = niu_pci_unmap_page,
9714         .map_single     = niu_pci_map_single,
9715         .unmap_single   = niu_pci_unmap_single,
9716 };
9717
9718 static void __devinit niu_driver_version(void)
9719 {
9720         static int niu_version_printed;
9721
9722         if (niu_version_printed++ == 0)
9723                 pr_info("%s", version);
9724 }
9725
9726 static struct net_device * __devinit niu_alloc_and_init(
9727         struct device *gen_dev, struct pci_dev *pdev,
9728         struct of_device *op, const struct niu_ops *ops,
9729         u8 port)
9730 {
9731         struct net_device *dev;
9732         struct niu *np;
9733
9734         dev = alloc_etherdev_mq(sizeof(struct niu), NIU_NUM_TXCHAN);
9735         if (!dev) {
9736                 dev_err(gen_dev, PFX "Etherdev alloc failed, aborting.\n");
9737                 return NULL;
9738         }
9739
9740         SET_NETDEV_DEV(dev, gen_dev);
9741
9742         np = netdev_priv(dev);
9743         np->dev = dev;
9744         np->pdev = pdev;
9745         np->op = op;
9746         np->device = gen_dev;
9747         np->ops = ops;
9748
9749         np->msg_enable = niu_debug;
9750
9751         spin_lock_init(&np->lock);
9752         INIT_WORK(&np->reset_task, niu_reset_task);
9753
9754         np->port = port;
9755
9756         return dev;
9757 }
9758
9759 static const struct net_device_ops niu_netdev_ops = {
9760         .ndo_open               = niu_open,
9761         .ndo_stop               = niu_close,
9762         .ndo_start_xmit         = niu_start_xmit,
9763         .ndo_get_stats          = niu_get_stats,
9764         .ndo_set_multicast_list = niu_set_rx_mode,
9765         .ndo_validate_addr      = eth_validate_addr,
9766         .ndo_set_mac_address    = niu_set_mac_addr,
9767         .ndo_do_ioctl           = niu_ioctl,
9768         .ndo_tx_timeout         = niu_tx_timeout,
9769         .ndo_change_mtu         = niu_change_mtu,
9770 };
9771
9772 static void __devinit niu_assign_netdev_ops(struct net_device *dev)
9773 {
9774         dev->netdev_ops = &niu_netdev_ops;
9775         dev->ethtool_ops = &niu_ethtool_ops;
9776         dev->watchdog_timeo = NIU_TX_TIMEOUT;
9777 }
9778
9779 static void __devinit niu_device_announce(struct niu *np)
9780 {
9781         struct net_device *dev = np->dev;
9782
9783         pr_info("%s: NIU Ethernet %pM\n", dev->name, dev->dev_addr);
9784
9785         if (np->parent->plat_type == PLAT_TYPE_ATCA_CP3220) {
9786                 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
9787                                 dev->name,
9788                                 (np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"),
9789                                 (np->flags & NIU_FLAGS_10G ? "10G" : "1G"),
9790                                 (np->flags & NIU_FLAGS_FIBER ? "RGMII FIBER" : "SERDES"),
9791                                 (np->mac_xcvr == MAC_XCVR_MII ? "MII" :
9792                                  (np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")),
9793                                 np->vpd.phy_type);
9794         } else {
9795                 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
9796                                 dev->name,
9797                                 (np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"),
9798                                 (np->flags & NIU_FLAGS_10G ? "10G" : "1G"),
9799                                 (np->flags & NIU_FLAGS_FIBER ? "FIBER" :
9800                                  (np->flags & NIU_FLAGS_XCVR_SERDES ? "SERDES" :
9801                                   "COPPER")),
9802                                 (np->mac_xcvr == MAC_XCVR_MII ? "MII" :
9803                                  (np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")),
9804                                 np->vpd.phy_type);
9805         }
9806 }
9807
9808 static int __devinit niu_pci_init_one(struct pci_dev *pdev,
9809                                       const struct pci_device_id *ent)
9810 {
9811         union niu_parent_id parent_id;
9812         struct net_device *dev;
9813         struct niu *np;
9814         int err, pos;
9815         u64 dma_mask;
9816         u16 val16;
9817
9818         niu_driver_version();
9819
9820         err = pci_enable_device(pdev);
9821         if (err) {
9822                 dev_err(&pdev->dev, PFX "Cannot enable PCI device, "
9823                         "aborting.\n");
9824                 return err;
9825         }
9826
9827         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) ||
9828             !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
9829                 dev_err(&pdev->dev, PFX "Cannot find proper PCI device "
9830                         "base addresses, aborting.\n");
9831                 err = -ENODEV;
9832                 goto err_out_disable_pdev;
9833         }
9834
9835         err = pci_request_regions(pdev, DRV_MODULE_NAME);
9836         if (err) {
9837                 dev_err(&pdev->dev, PFX "Cannot obtain PCI resources, "
9838                         "aborting.\n");
9839                 goto err_out_disable_pdev;
9840         }
9841
9842         pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
9843         if (pos <= 0) {
9844                 dev_err(&pdev->dev, PFX "Cannot find PCI Express capability, "
9845                         "aborting.\n");
9846                 goto err_out_free_res;
9847         }
9848
9849         dev = niu_alloc_and_init(&pdev->dev, pdev, NULL,
9850                                  &niu_pci_ops, PCI_FUNC(pdev->devfn));
9851         if (!dev) {
9852                 err = -ENOMEM;
9853                 goto err_out_free_res;
9854         }
9855         np = netdev_priv(dev);
9856
9857         memset(&parent_id, 0, sizeof(parent_id));
9858         parent_id.pci.domain = pci_domain_nr(pdev->bus);
9859         parent_id.pci.bus = pdev->bus->number;
9860         parent_id.pci.device = PCI_SLOT(pdev->devfn);
9861
9862         np->parent = niu_get_parent(np, &parent_id,
9863                                     PLAT_TYPE_ATLAS);
9864         if (!np->parent) {
9865                 err = -ENOMEM;
9866                 goto err_out_free_dev;
9867         }
9868
9869         pci_read_config_word(pdev, pos + PCI_EXP_DEVCTL, &val16);
9870         val16 &= ~PCI_EXP_DEVCTL_NOSNOOP_EN;
9871         val16 |= (PCI_EXP_DEVCTL_CERE |
9872                   PCI_EXP_DEVCTL_NFERE |
9873                   PCI_EXP_DEVCTL_FERE |
9874                   PCI_EXP_DEVCTL_URRE |
9875                   PCI_EXP_DEVCTL_RELAX_EN);
9876         pci_write_config_word(pdev, pos + PCI_EXP_DEVCTL, val16);
9877
9878         dma_mask = DMA_44BIT_MASK;
9879         err = pci_set_dma_mask(pdev, dma_mask);
9880         if (!err) {
9881                 dev->features |= NETIF_F_HIGHDMA;
9882                 err = pci_set_consistent_dma_mask(pdev, dma_mask);
9883                 if (err) {
9884                         dev_err(&pdev->dev, PFX "Unable to obtain 44 bit "
9885                                 "DMA for consistent allocations, "
9886                                 "aborting.\n");
9887                         goto err_out_release_parent;
9888                 }
9889         }
9890         if (err || dma_mask == DMA_32BIT_MASK) {
9891                 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
9892                 if (err) {
9893                         dev_err(&pdev->dev, PFX "No usable DMA configuration, "
9894                                 "aborting.\n");
9895                         goto err_out_release_parent;
9896                 }
9897         }
9898
9899         dev->features |= (NETIF_F_SG | NETIF_F_HW_CSUM);
9900
9901         np->regs = pci_ioremap_bar(pdev, 0);
9902         if (!np->regs) {
9903                 dev_err(&pdev->dev, PFX "Cannot map device registers, "
9904                         "aborting.\n");
9905                 err = -ENOMEM;
9906                 goto err_out_release_parent;
9907         }
9908
9909         pci_set_master(pdev);
9910         pci_save_state(pdev);
9911
9912         dev->irq = pdev->irq;
9913
9914         niu_assign_netdev_ops(dev);
9915
9916         err = niu_get_invariants(np);
9917         if (err) {
9918                 if (err != -ENODEV)
9919                         dev_err(&pdev->dev, PFX "Problem fetching invariants "
9920                                 "of chip, aborting.\n");
9921                 goto err_out_iounmap;
9922         }
9923
9924         err = register_netdev(dev);
9925         if (err) {
9926                 dev_err(&pdev->dev, PFX "Cannot register net device, "
9927                         "aborting.\n");
9928                 goto err_out_iounmap;
9929         }
9930
9931         pci_set_drvdata(pdev, dev);
9932
9933         niu_device_announce(np);
9934
9935         return 0;
9936
9937 err_out_iounmap:
9938         if (np->regs) {
9939                 iounmap(np->regs);
9940                 np->regs = NULL;
9941         }
9942
9943 err_out_release_parent:
9944         niu_put_parent(np);
9945
9946 err_out_free_dev:
9947         free_netdev(dev);
9948
9949 err_out_free_res:
9950         pci_release_regions(pdev);
9951
9952 err_out_disable_pdev:
9953         pci_disable_device(pdev);
9954         pci_set_drvdata(pdev, NULL);
9955
9956         return err;
9957 }
9958
9959 static void __devexit niu_pci_remove_one(struct pci_dev *pdev)
9960 {
9961         struct net_device *dev = pci_get_drvdata(pdev);
9962
9963         if (dev) {
9964                 struct niu *np = netdev_priv(dev);
9965
9966                 unregister_netdev(dev);
9967                 if (np->regs) {
9968                         iounmap(np->regs);
9969                         np->regs = NULL;
9970                 }
9971
9972                 niu_ldg_free(np);
9973
9974                 niu_put_parent(np);
9975
9976                 free_netdev(dev);
9977                 pci_release_regions(pdev);
9978                 pci_disable_device(pdev);
9979                 pci_set_drvdata(pdev, NULL);
9980         }
9981 }
9982
9983 static int niu_suspend(struct pci_dev *pdev, pm_message_t state)
9984 {
9985         struct net_device *dev = pci_get_drvdata(pdev);
9986         struct niu *np = netdev_priv(dev);
9987         unsigned long flags;
9988
9989         if (!netif_running(dev))
9990                 return 0;
9991
9992         flush_scheduled_work();
9993         niu_netif_stop(np);
9994
9995         del_timer_sync(&np->timer);
9996
9997         spin_lock_irqsave(&np->lock, flags);
9998         niu_enable_interrupts(np, 0);
9999         spin_unlock_irqrestore(&np->lock, flags);
10000
10001         netif_device_detach(dev);
10002
10003         spin_lock_irqsave(&np->lock, flags);
10004         niu_stop_hw(np);
10005         spin_unlock_irqrestore(&np->lock, flags);
10006
10007         pci_save_state(pdev);
10008
10009         return 0;
10010 }
10011
10012 static int niu_resume(struct pci_dev *pdev)
10013 {
10014         struct net_device *dev = pci_get_drvdata(pdev);
10015         struct niu *np = netdev_priv(dev);
10016         unsigned long flags;
10017         int err;
10018
10019         if (!netif_running(dev))
10020                 return 0;
10021
10022         pci_restore_state(pdev);
10023
10024         netif_device_attach(dev);
10025
10026         spin_lock_irqsave(&np->lock, flags);
10027
10028         err = niu_init_hw(np);
10029         if (!err) {
10030                 np->timer.expires = jiffies + HZ;
10031                 add_timer(&np->timer);
10032                 niu_netif_start(np);
10033         }
10034
10035         spin_unlock_irqrestore(&np->lock, flags);
10036
10037         return err;
10038 }
10039
10040 static struct pci_driver niu_pci_driver = {
10041         .name           = DRV_MODULE_NAME,
10042         .id_table       = niu_pci_tbl,
10043         .probe          = niu_pci_init_one,
10044         .remove         = __devexit_p(niu_pci_remove_one),
10045         .suspend        = niu_suspend,
10046         .resume         = niu_resume,
10047 };
10048
10049 #ifdef CONFIG_SPARC64
10050 static void *niu_phys_alloc_coherent(struct device *dev, size_t size,
10051                                      u64 *dma_addr, gfp_t flag)
10052 {
10053         unsigned long order = get_order(size);
10054         unsigned long page = __get_free_pages(flag, order);
10055
10056         if (page == 0UL)
10057                 return NULL;
10058         memset((char *)page, 0, PAGE_SIZE << order);
10059         *dma_addr = __pa(page);
10060
10061         return (void *) page;
10062 }
10063
10064 static void niu_phys_free_coherent(struct device *dev, size_t size,
10065                                    void *cpu_addr, u64 handle)
10066 {
10067         unsigned long order = get_order(size);
10068
10069         free_pages((unsigned long) cpu_addr, order);
10070 }
10071
10072 static u64 niu_phys_map_page(struct device *dev, struct page *page,
10073                              unsigned long offset, size_t size,
10074                              enum dma_data_direction direction)
10075 {
10076         return page_to_phys(page) + offset;
10077 }
10078
10079 static void niu_phys_unmap_page(struct device *dev, u64 dma_address,
10080                                 size_t size, enum dma_data_direction direction)
10081 {
10082         /* Nothing to do.  */
10083 }
10084
10085 static u64 niu_phys_map_single(struct device *dev, void *cpu_addr,
10086                                size_t size,
10087                                enum dma_data_direction direction)
10088 {
10089         return __pa(cpu_addr);
10090 }
10091
10092 static void niu_phys_unmap_single(struct device *dev, u64 dma_address,
10093                                   size_t size,
10094                                   enum dma_data_direction direction)
10095 {
10096         /* Nothing to do.  */
10097 }
10098
10099 static const struct niu_ops niu_phys_ops = {
10100         .alloc_coherent = niu_phys_alloc_coherent,
10101         .free_coherent  = niu_phys_free_coherent,
10102         .map_page       = niu_phys_map_page,
10103         .unmap_page     = niu_phys_unmap_page,
10104         .map_single     = niu_phys_map_single,
10105         .unmap_single   = niu_phys_unmap_single,
10106 };
10107
10108 static unsigned long res_size(struct resource *r)
10109 {
10110         return r->end - r->start + 1UL;
10111 }
10112
10113 static int __devinit niu_of_probe(struct of_device *op,
10114                                   const struct of_device_id *match)
10115 {
10116         union niu_parent_id parent_id;
10117         struct net_device *dev;
10118         struct niu *np;
10119         const u32 *reg;
10120         int err;
10121
10122         niu_driver_version();
10123
10124         reg = of_get_property(op->node, "reg", NULL);
10125         if (!reg) {
10126                 dev_err(&op->dev, PFX "%s: No 'reg' property, aborting.\n",
10127                         op->node->full_name);
10128                 return -ENODEV;
10129         }
10130
10131         dev = niu_alloc_and_init(&op->dev, NULL, op,
10132                                  &niu_phys_ops, reg[0] & 0x1);
10133         if (!dev) {
10134                 err = -ENOMEM;
10135                 goto err_out;
10136         }
10137         np = netdev_priv(dev);
10138
10139         memset(&parent_id, 0, sizeof(parent_id));
10140         parent_id.of = of_get_parent(op->node);
10141
10142         np->parent = niu_get_parent(np, &parent_id,
10143                                     PLAT_TYPE_NIU);
10144         if (!np->parent) {
10145                 err = -ENOMEM;
10146                 goto err_out_free_dev;
10147         }
10148
10149         dev->features |= (NETIF_F_SG | NETIF_F_HW_CSUM);
10150
10151         np->regs = of_ioremap(&op->resource[1], 0,
10152                               res_size(&op->resource[1]),
10153                               "niu regs");
10154         if (!np->regs) {
10155                 dev_err(&op->dev, PFX "Cannot map device registers, "
10156                         "aborting.\n");
10157                 err = -ENOMEM;
10158                 goto err_out_release_parent;
10159         }
10160
10161         np->vir_regs_1 = of_ioremap(&op->resource[2], 0,
10162                                     res_size(&op->resource[2]),
10163                                     "niu vregs-1");
10164         if (!np->vir_regs_1) {
10165                 dev_err(&op->dev, PFX "Cannot map device vir registers 1, "
10166                         "aborting.\n");
10167                 err = -ENOMEM;
10168                 goto err_out_iounmap;
10169         }
10170
10171         np->vir_regs_2 = of_ioremap(&op->resource[3], 0,
10172                                     res_size(&op->resource[3]),
10173                                     "niu vregs-2");
10174         if (!np->vir_regs_2) {
10175                 dev_err(&op->dev, PFX "Cannot map device vir registers 2, "
10176                         "aborting.\n");
10177                 err = -ENOMEM;
10178                 goto err_out_iounmap;
10179         }
10180
10181         niu_assign_netdev_ops(dev);
10182
10183         err = niu_get_invariants(np);
10184         if (err) {
10185                 if (err != -ENODEV)
10186                         dev_err(&op->dev, PFX "Problem fetching invariants "
10187                                 "of chip, aborting.\n");
10188                 goto err_out_iounmap;
10189         }
10190
10191         err = register_netdev(dev);
10192         if (err) {
10193                 dev_err(&op->dev, PFX "Cannot register net device, "
10194                         "aborting.\n");
10195                 goto err_out_iounmap;
10196         }
10197
10198         dev_set_drvdata(&op->dev, dev);
10199
10200         niu_device_announce(np);
10201
10202         return 0;
10203
10204 err_out_iounmap:
10205         if (np->vir_regs_1) {
10206                 of_iounmap(&op->resource[2], np->vir_regs_1,
10207                            res_size(&op->resource[2]));
10208                 np->vir_regs_1 = NULL;
10209         }
10210
10211         if (np->vir_regs_2) {
10212                 of_iounmap(&op->resource[3], np->vir_regs_2,
10213                            res_size(&op->resource[3]));
10214                 np->vir_regs_2 = NULL;
10215         }
10216
10217         if (np->regs) {
10218                 of_iounmap(&op->resource[1], np->regs,
10219                            res_size(&op->resource[1]));
10220                 np->regs = NULL;
10221         }
10222
10223 err_out_release_parent:
10224         niu_put_parent(np);
10225
10226 err_out_free_dev:
10227         free_netdev(dev);
10228
10229 err_out:
10230         return err;
10231 }
10232
10233 static int __devexit niu_of_remove(struct of_device *op)
10234 {
10235         struct net_device *dev = dev_get_drvdata(&op->dev);
10236
10237         if (dev) {
10238                 struct niu *np = netdev_priv(dev);
10239
10240                 unregister_netdev(dev);
10241
10242                 if (np->vir_regs_1) {
10243                         of_iounmap(&op->resource[2], np->vir_regs_1,
10244                                    res_size(&op->resource[2]));
10245                         np->vir_regs_1 = NULL;
10246                 }
10247
10248                 if (np->vir_regs_2) {
10249                         of_iounmap(&op->resource[3], np->vir_regs_2,
10250                                    res_size(&op->resource[3]));
10251                         np->vir_regs_2 = NULL;
10252                 }
10253
10254                 if (np->regs) {
10255                         of_iounmap(&op->resource[1], np->regs,
10256                                    res_size(&op->resource[1]));
10257                         np->regs = NULL;
10258                 }
10259
10260                 niu_ldg_free(np);
10261
10262                 niu_put_parent(np);
10263
10264                 free_netdev(dev);
10265                 dev_set_drvdata(&op->dev, NULL);
10266         }
10267         return 0;
10268 }
10269
10270 static const struct of_device_id niu_match[] = {
10271         {
10272                 .name = "network",
10273                 .compatible = "SUNW,niusl",
10274         },
10275         {},
10276 };
10277 MODULE_DEVICE_TABLE(of, niu_match);
10278
10279 static struct of_platform_driver niu_of_driver = {
10280         .name           = "niu",
10281         .match_table    = niu_match,
10282         .probe          = niu_of_probe,
10283         .remove         = __devexit_p(niu_of_remove),
10284 };
10285
10286 #endif /* CONFIG_SPARC64 */
10287
10288 static int __init niu_init(void)
10289 {
10290         int err = 0;
10291
10292         BUILD_BUG_ON(PAGE_SIZE < 4 * 1024);
10293
10294         niu_debug = netif_msg_init(debug, NIU_MSG_DEFAULT);
10295
10296 #ifdef CONFIG_SPARC64
10297         err = of_register_driver(&niu_of_driver, &of_bus_type);
10298 #endif
10299
10300         if (!err) {
10301                 err = pci_register_driver(&niu_pci_driver);
10302 #ifdef CONFIG_SPARC64
10303                 if (err)
10304                         of_unregister_driver(&niu_of_driver);
10305 #endif
10306         }
10307
10308         return err;
10309 }
10310
10311 static void __exit niu_exit(void)
10312 {
10313         pci_unregister_driver(&niu_pci_driver);
10314 #ifdef CONFIG_SPARC64
10315         of_unregister_driver(&niu_of_driver);
10316 #endif
10317 }
10318
10319 module_init(niu_init);
10320 module_exit(niu_exit);