Merge branch 'linus' into x86/pebs
[linux-2.6] / arch / powerpc / boot / dts / sbc8641d.dts
1 /*
2  * SBC8641D Device Tree Source
3  *
4  * Copyright 2008 Wind River Systems Inc.
5  *
6  * Paul Gortmaker (see MAINTAINERS for contact information)
7  *
8  * Based largely on the mpc8641_hpcn.dts by Freescale Semiconductor Inc.
9  *
10  * This program is free software; you can redistribute  it and/or modify it
11  * under  the terms of  the GNU General  Public License as published by the
12  * Free Software Foundation;  either version 2 of the  License, or (at your
13  * option) any later version.
14  */
15
16 /dts-v1/;
17
18 / {
19         model = "SBC8641D";
20         compatible = "wind,sbc8641";
21         #address-cells = <1>;
22         #size-cells = <1>;
23
24         aliases {
25                 ethernet0 = &enet0;
26                 ethernet1 = &enet1;
27                 ethernet2 = &enet2;
28                 ethernet3 = &enet3;
29                 serial0 = &serial0;
30                 serial1 = &serial1;
31                 pci0 = &pci0;
32                 pci1 = &pci1;
33         };
34
35         cpus {
36                 #address-cells = <1>;
37                 #size-cells = <0>;
38
39                 PowerPC,8641@0 {
40                         device_type = "cpu";
41                         reg = <0>;
42                         d-cache-line-size = <32>;
43                         i-cache-line-size = <32>;
44                         d-cache-size = <32768>;         // L1
45                         i-cache-size = <32768>;         // L1
46                         timebase-frequency = <0>;       // From uboot
47                         bus-frequency = <0>;            // From uboot
48                         clock-frequency = <0>;          // From uboot
49                 };
50                 PowerPC,8641@1 {
51                         device_type = "cpu";
52                         reg = <1>;
53                         d-cache-line-size = <32>;
54                         i-cache-line-size = <32>;
55                         d-cache-size = <32768>;
56                         i-cache-size = <32768>;
57                         timebase-frequency = <0>;       // From uboot
58                         bus-frequency = <0>;            // From uboot
59                         clock-frequency = <0>;          // From uboot
60                 };
61         };
62
63         memory {
64                 device_type = "memory";
65                 reg = <0x00000000 0x20000000>;  // 512M at 0x0
66         };
67
68         localbus@f8005000 {
69                 #address-cells = <2>;
70                 #size-cells = <1>;
71                 compatible = "fsl,mpc8641-localbus", "simple-bus";
72                 reg = <0xf8005000 0x1000>;
73                 interrupts = <19 2>;
74                 interrupt-parent = <&mpic>;
75
76                 ranges = <0 0 0xff000000 0x01000000     // 16MB Boot flash
77                           1 0 0xf0000000 0x00010000     // 64KB EEPROM
78                           2 0 0xf1000000 0x00100000     // EPLD (1MB)
79                           3 0 0xe0000000 0x04000000     // 64MB LB SDRAM (CS3)
80                           4 0 0xe4000000 0x04000000     // 64MB LB SDRAM (CS4)
81                           6 0 0xf4000000 0x00100000     // LCD display (1MB)
82                           7 0 0xe8000000 0x04000000>;   // 64MB OneNAND
83
84                 flash@0,0 {
85                         compatible = "cfi-flash";
86                         reg = <0 0 0x01000000>;
87                         bank-width = <2>;
88                         device-width = <2>;
89                         #address-cells = <1>;
90                         #size-cells = <1>;
91                         partition@0 {
92                                 label = "dtb";
93                                 reg = <0x00000000 0x00100000>;
94                                 read-only;
95                         };
96                         partition@300000 {
97                                 label = "kernel";
98                                 reg = <0x00100000 0x00400000>;
99                                 read-only;
100                         };
101                         partition@400000 {
102                                 label = "fs";
103                                 reg = <0x00500000 0x00a00000>;
104                         };
105                         partition@700000 {
106                                 label = "firmware";
107                                 reg = <0x00f00000 0x00100000>;
108                                 read-only;
109                         };
110                 };
111
112                 epld@2,0 {
113                         compatible = "wrs,epld-localbus";
114                         #address-cells = <2>;
115                         #size-cells = <1>;
116                         reg = <2 0 0x100000>;
117                         ranges = <0 0 5 0 1     // User switches
118                                   1 0 5 1 1     // Board ID/Rev
119                                   3 0 5 3 1>;   // LEDs
120                 };
121         };
122
123         soc@f8000000 {
124                 #address-cells = <1>;
125                 #size-cells = <1>;
126                 device_type = "soc";
127                 compatible = "simple-bus";
128                 ranges = <0x00000000 0xf8000000 0x00100000>;
129                 reg = <0xf8000000 0x00001000>;  // CCSRBAR
130                 bus-frequency = <0>;
131
132                 i2c@3000 {
133                         #address-cells = <1>;
134                         #size-cells = <0>;
135                         cell-index = <0>;
136                         compatible = "fsl-i2c";
137                         reg = <0x3000 0x100>;
138                         interrupts = <43 2>;
139                         interrupt-parent = <&mpic>;
140                         dfsrr;
141                 };
142
143                 i2c@3100 {
144                         #address-cells = <1>;
145                         #size-cells = <0>;
146                         cell-index = <1>;
147                         compatible = "fsl-i2c";
148                         reg = <0x3100 0x100>;
149                         interrupts = <43 2>;
150                         interrupt-parent = <&mpic>;
151                         dfsrr;
152                 };
153
154                 dma@21300 {
155                         #address-cells = <1>;
156                         #size-cells = <1>;
157                         compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma";
158                         reg = <0x21300 0x4>;
159                         ranges = <0x0 0x21100 0x200>;
160                         cell-index = <0>;
161                         dma-channel@0 {
162                                 compatible = "fsl,mpc8641-dma-channel",
163                                                 "fsl,eloplus-dma-channel";
164                                 reg = <0x0 0x80>;
165                                 cell-index = <0>;
166                                 interrupt-parent = <&mpic>;
167                                 interrupts = <20 2>;
168                         };
169                         dma-channel@80 {
170                                 compatible = "fsl,mpc8641-dma-channel",
171                                                 "fsl,eloplus-dma-channel";
172                                 reg = <0x80 0x80>;
173                                 cell-index = <1>;
174                                 interrupt-parent = <&mpic>;
175                                 interrupts = <21 2>;
176                         };
177                         dma-channel@100 {
178                                 compatible = "fsl,mpc8641-dma-channel",
179                                                 "fsl,eloplus-dma-channel";
180                                 reg = <0x100 0x80>;
181                                 cell-index = <2>;
182                                 interrupt-parent = <&mpic>;
183                                 interrupts = <22 2>;
184                         };
185                         dma-channel@180 {
186                                 compatible = "fsl,mpc8641-dma-channel",
187                                                 "fsl,eloplus-dma-channel";
188                                 reg = <0x180 0x80>;
189                                 cell-index = <3>;
190                                 interrupt-parent = <&mpic>;
191                                 interrupts = <23 2>;
192                         };
193                 };
194
195                 mdio@24520 {
196                         #address-cells = <1>;
197                         #size-cells = <0>;
198                         compatible = "fsl,gianfar-mdio";
199                         reg = <0x24520 0x20>;
200
201                         phy0: ethernet-phy@1f {
202                                 interrupt-parent = <&mpic>;
203                                 interrupts = <10 1>;
204                                 reg = <0x1f>;
205                                 device_type = "ethernet-phy";
206                         };
207                         phy1: ethernet-phy@0 {
208                                 interrupt-parent = <&mpic>;
209                                 interrupts = <10 1>;
210                                 reg = <0>;
211                                 device_type = "ethernet-phy";
212                         };
213                         phy2: ethernet-phy@1 {
214                                 interrupt-parent = <&mpic>;
215                                 interrupts = <10 1>;
216                                 reg = <1>;
217                                 device_type = "ethernet-phy";
218                         };
219                         phy3: ethernet-phy@2 {
220                                 interrupt-parent = <&mpic>;
221                                 interrupts = <10 1>;
222                                 reg = <2>;
223                                 device_type = "ethernet-phy";
224                         };
225                 };
226
227                 enet0: ethernet@24000 {
228                         cell-index = <0>;
229                         device_type = "network";
230                         model = "TSEC";
231                         compatible = "gianfar";
232                         reg = <0x24000 0x1000>;
233                         local-mac-address = [ 00 00 00 00 00 00 ];
234                         interrupts = <29 2 30  2 34 2>;
235                         interrupt-parent = <&mpic>;
236                         phy-handle = <&phy0>;
237                         phy-connection-type = "rgmii-id";
238                 };
239
240                 enet1: ethernet@25000 {
241                         cell-index = <1>;
242                         device_type = "network";
243                         model = "TSEC";
244                         compatible = "gianfar";
245                         reg = <0x25000 0x1000>;
246                         local-mac-address = [ 00 00 00 00 00 00 ];
247                         interrupts = <35 2 36 2 40 2>;
248                         interrupt-parent = <&mpic>;
249                         phy-handle = <&phy1>;
250                         phy-connection-type = "rgmii-id";
251                 };
252
253                 enet2: ethernet@26000 {
254                         cell-index = <2>;
255                         device_type = "network";
256                         model = "TSEC";
257                         compatible = "gianfar";
258                         reg = <0x26000 0x1000>;
259                         local-mac-address = [ 00 00 00 00 00 00 ];
260                         interrupts = <31 2 32 2 33 2>;
261                         interrupt-parent = <&mpic>;
262                         phy-handle = <&phy2>;
263                         phy-connection-type = "rgmii-id";
264                 };
265
266                 enet3: ethernet@27000 {
267                         cell-index = <3>;
268                         device_type = "network";
269                         model = "TSEC";
270                         compatible = "gianfar";
271                         reg = <0x27000 0x1000>;
272                         local-mac-address = [ 00 00 00 00 00 00 ];
273                         interrupts = <37 2 38 2 39 2>;
274                         interrupt-parent = <&mpic>;
275                         phy-handle = <&phy3>;
276                         phy-connection-type = "rgmii-id";
277                 };
278
279                 serial0: serial@4500 {
280                         cell-index = <0>;
281                         device_type = "serial";
282                         compatible = "ns16550";
283                         reg = <0x4500 0x100>;
284                         clock-frequency = <0>;
285                         interrupts = <42 2>;
286                         interrupt-parent = <&mpic>;
287                 };
288
289                 serial1: serial@4600 {
290                         cell-index = <1>;
291                         device_type = "serial";
292                         compatible = "ns16550";
293                         reg = <0x4600 0x100>;
294                         clock-frequency = <0>;
295                         interrupts = <28 2>;
296                         interrupt-parent = <&mpic>;
297                 };
298
299                 mpic: pic@40000 {
300                         clock-frequency = <0>;
301                         interrupt-controller;
302                         #address-cells = <0>;
303                         #interrupt-cells = <2>;
304                         reg = <0x40000 0x40000>;
305                         compatible = "chrp,open-pic";
306                         device_type = "open-pic";
307                         big-endian;
308                 };
309
310                 global-utilities@e0000 {
311                         compatible = "fsl,mpc8641-guts";
312                         reg = <0xe0000 0x1000>;
313                         fsl,has-rstcr;
314                 };
315         };
316
317         pci0: pcie@f8008000 {
318                 cell-index = <0>;
319                 compatible = "fsl,mpc8641-pcie";
320                 device_type = "pci";
321                 #interrupt-cells = <1>;
322                 #size-cells = <2>;
323                 #address-cells = <3>;
324                 reg = <0xf8008000 0x1000>;
325                 bus-range = <0x0 0xff>;
326                 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000
327                           0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
328                 clock-frequency = <33333333>;
329                 interrupt-parent = <&mpic>;
330                 interrupts = <24 2>;
331                 interrupt-map-mask = <0xff00 0 0 7>;
332                 interrupt-map = <
333                         /* IDSEL 0x0 */
334                         0x0000 0 0 1 &mpic 0 1
335                         0x0000 0 0 2 &mpic 1 1
336                         0x0000 0 0 3 &mpic 2 1
337                         0x0000 0 0 4 &mpic 3 1
338                         >;
339
340                 pcie@0 {
341                         reg = <0 0 0 0 0>;
342                         #size-cells = <2>;
343                         #address-cells = <3>;
344                         device_type = "pci";
345                         ranges = <0x02000000 0x0 0x80000000
346                                   0x02000000 0x0 0x80000000
347                                   0x0 0x20000000
348
349                                   0x01000000 0x0 0x00000000
350                                   0x01000000 0x0 0x00000000
351                                   0x0 0x00100000>;
352                 };
353
354         };
355
356         pci1: pcie@f8009000 {
357                 cell-index = <1>;
358                 compatible = "fsl,mpc8641-pcie";
359                 device_type = "pci";
360                 #interrupt-cells = <1>;
361                 #size-cells = <2>;
362                 #address-cells = <3>;
363                 reg = <0xf8009000 0x1000>;
364                 bus-range = <0 0xff>;
365                 ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
366                           0x01000000 0x0 0x00000000 0xe3000000 0x0 0x00100000>;
367                 clock-frequency = <33333333>;
368                 interrupt-parent = <&mpic>;
369                 interrupts = <25 2>;
370                 interrupt-map-mask = <0xf800 0 0 7>;
371                 interrupt-map = <
372                         /* IDSEL 0x0 */
373                         0x0000 0 0 1 &mpic 4 1
374                         0x0000 0 0 2 &mpic 5 1
375                         0x0000 0 0 3 &mpic 6 1
376                         0x0000 0 0 4 &mpic 7 1
377                         >;
378
379                 pcie@0 {
380                         reg = <0 0 0 0 0>;
381                         #size-cells = <2>;
382                         #address-cells = <3>;
383                         device_type = "pci";
384                         ranges = <0x02000000 0x0 0xa0000000
385                                   0x02000000 0x0 0xa0000000
386                                   0x0 0x20000000
387
388                                   0x01000000 0x0 0x00000000
389                                   0x01000000 0x0 0x00000000
390                                   0x0 0x00100000>;
391                 };
392         };
393 };