git.oblomov.eu Git - linux-2.6/blob - drivers/video/vermilion/vermilion.h

   1 /*
   2  * Copyright (c) Intel Corp. 2007.
   3  * All Rights Reserved.
   4  *
   5  * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   6  * develop this driver.
   7  *
   8  * This file is part of the Vermilion Range fb driver.
   9  * The Vermilion Range fb driver is free software;
  10  * you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * The Vermilion Range fb driver is distributed
  16  * in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this driver; if not, write to the Free Software
  23  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  24  *
  25  * Authors:
  26  *   Thomas Hellström <thomas-at-tungstengraphics-dot-com>
  27  */
  28
  29 #ifndef _VERMILION_H_
  30 #define _VERMILION_H_
  31
  32 #include <linux/kernel.h>
  33 #include <linux/pci.h>
  34 #include <asm/atomic.h>
  35 #include <linux/mutex.h>
  36
  37 #define VML_DEVICE_GPU 0x5002
  38 #define VML_DEVICE_VDC 0x5009
  39
  40 #define VML_VRAM_AREAS 3
  41 #define VML_MAX_XRES 1024
  42 #define VML_MAX_YRES 768
  43 #define VML_MAX_XRES_VIRTUAL 1040
  44
  45 /*
  46  * Display controller registers:
  47  */
  48
  49 /* Display controller 10-bit color representation */
  50
  51 #define VML_R_MASK                   0x3FF00000
  52 #define VML_R_SHIFT                  20
  53 #define VML_G_MASK                   0x000FFC00
  54 #define VML_G_SHIFT                  10
  55 #define VML_B_MASK                   0x000003FF
  56 #define VML_B_SHIFT                  0
  57
  58 /* Graphics plane control */
  59 #define VML_DSPCCNTR                 0x00072180
  60 #define VML_GFX_ENABLE               0x80000000
  61 #define VML_GFX_GAMMABYPASS          0x40000000
  62 #define VML_GFX_ARGB1555             0x0C000000
  63 #define VML_GFX_RGB0888              0x18000000
  64 #define VML_GFX_ARGB8888             0x1C000000
  65 #define VML_GFX_ALPHACONST           0x02000000
  66 #define VML_GFX_ALPHAMULT            0x01000000
  67 #define VML_GFX_CONST_ALPHA          0x000000FF
  68
  69 /* Graphics plane start address. Pixel aligned. */
  70 #define VML_DSPCADDR                 0x00072184
  71
  72 /* Graphics plane stride register. */
  73 #define VML_DSPCSTRIDE               0x00072188
  74
  75 /* Graphics plane position register. */
  76 #define VML_DSPCPOS                  0x0007218C
  77 #define VML_POS_YMASK                0x0FFF0000
  78 #define VML_POS_YSHIFT               16
  79 #define VML_POS_XMASK                0x00000FFF
  80 #define VML_POS_XSHIFT               0
  81
  82 /* Graphics plane height and width */
  83 #define VML_DSPCSIZE                 0x00072190
  84 #define VML_SIZE_HMASK               0x0FFF0000
  85 #define VML_SIZE_HSHIFT              16
  86 #define VML_SISE_WMASK               0x00000FFF
  87 #define VML_SIZE_WSHIFT              0
  88
  89 /* Graphics plane gamma correction lookup table registers (129 * 32 bits) */
  90 #define VML_DSPCGAMLUT               0x00072200
  91
  92 /* Pixel video output configuration register */
  93 #define VML_PVOCONFIG                0x00061140
  94 #define VML_CONFIG_BASE              0x80000000
  95 #define VML_CONFIG_PIXEL_SWAP        0x04000000
  96 #define VML_CONFIG_DE_INV            0x01000000
  97 #define VML_CONFIG_HREF_INV          0x00400000
  98 #define VML_CONFIG_VREF_INV          0x00100000
  99 #define VML_CONFIG_CLK_INV           0x00040000
 100 #define VML_CONFIG_CLK_DIV2          0x00010000
 101 #define VML_CONFIG_ESTRB_INV         0x00008000
 102
 103 /* Pipe A Horizontal total register */
 104 #define VML_HTOTAL_A                 0x00060000
 105 #define VML_HTOTAL_MASK              0x1FFF0000
 106 #define VML_HTOTAL_SHIFT             16
 107 #define VML_HTOTAL_VAL               8192
 108 #define VML_HACTIVE_MASK             0x000007FF
 109 #define VML_HACTIVE_SHIFT            0
 110 #define VML_HACTIVE_VAL              4096
 111
 112 /* Pipe A Horizontal Blank register */
 113 #define VML_HBLANK_A                 0x00060004
 114 #define VML_HBLANK_END_MASK          0x1FFF0000
 115 #define VML_HBLANK_END_SHIFT         16
 116 #define VML_HBLANK_END_VAL           8192
 117 #define VML_HBLANK_START_MASK        0x00001FFF
 118 #define VML_HBLANK_START_SHIFT       0
 119 #define VML_HBLANK_START_VAL         8192
 120
 121 /* Pipe A Horizontal Sync register */
 122 #define VML_HSYNC_A                  0x00060008
 123 #define VML_HSYNC_END_MASK           0x1FFF0000
 124 #define VML_HSYNC_END_SHIFT          16
 125 #define VML_HSYNC_END_VAL            8192
 126 #define VML_HSYNC_START_MASK         0x00001FFF
 127 #define VML_HSYNC_START_SHIFT        0
 128 #define VML_HSYNC_START_VAL          8192
 129
 130 /* Pipe A Vertical total register */
 131 #define VML_VTOTAL_A                 0x0006000C
 132 #define VML_VTOTAL_MASK              0x1FFF0000
 133 #define VML_VTOTAL_SHIFT             16
 134 #define VML_VTOTAL_VAL               8192
 135 #define VML_VACTIVE_MASK             0x000007FF
 136 #define VML_VACTIVE_SHIFT            0
 137 #define VML_VACTIVE_VAL              4096
 138
 139 /* Pipe A Vertical Blank register */
 140 #define VML_VBLANK_A                 0x00060010
 141 #define VML_VBLANK_END_MASK          0x1FFF0000
 142 #define VML_VBLANK_END_SHIFT         16
 143 #define VML_VBLANK_END_VAL           8192
 144 #define VML_VBLANK_START_MASK        0x00001FFF
 145 #define VML_VBLANK_START_SHIFT       0
 146 #define VML_VBLANK_START_VAL         8192
 147
 148 /* Pipe A Vertical Sync register */
 149 #define VML_VSYNC_A                  0x00060014
 150 #define VML_VSYNC_END_MASK           0x1FFF0000
 151 #define VML_VSYNC_END_SHIFT          16
 152 #define VML_VSYNC_END_VAL            8192
 153 #define VML_VSYNC_START_MASK         0x00001FFF
 154 #define VML_VSYNC_START_SHIFT        0
 155 #define VML_VSYNC_START_VAL          8192
 156
 157 /* Pipe A Source Image size (minus one - equal to active size)
 158  * Programmable while pipe is enabled.
 159  */
 160 #define VML_PIPEASRC                 0x0006001C
 161 #define VML_PIPEASRC_HMASK           0x0FFF0000
 162 #define VML_PIPEASRC_HSHIFT          16
 163 #define VML_PIPEASRC_VMASK           0x00000FFF
 164 #define VML_PIPEASRC_VSHIFT          0
 165
 166 /* Pipe A Border Color Pattern register (10 bit color) */
 167 #define VML_BCLRPAT_A                0x00060020
 168
 169 /* Pipe A Canvas Color register  (10 bit color) */
 170 #define VML_CANVSCLR_A               0x00060024
 171
 172 /* Pipe A Configuration register */
 173 #define VML_PIPEACONF                0x00070008
 174 #define VML_PIPE_BASE                0x00000000
 175 #define VML_PIPE_ENABLE              0x80000000
 176 #define VML_PIPE_FORCE_BORDER        0x02000000
 177 #define VML_PIPE_PLANES_OFF          0x00080000
 178 #define VML_PIPE_ARGB_OUTPUT_MODE    0x00040000
 179
 180 /* Pipe A FIFO setting */
 181 #define VML_DSPARB                   0x00070030
 182 #define VML_FIFO_DEFAULT             0x00001D9C
 183
 184 /* MDVO rcomp status & pads control register */
 185 #define VML_RCOMPSTAT                0x00070048
 186 #define VML_MDVO_VDC_I_RCOMP         0x80000000
 187 #define VML_MDVO_POWERSAVE_OFF       0x00000008
 188 #define VML_MDVO_PAD_ENABLE          0x00000004
 189 #define VML_MDVO_PULLDOWN_ENABLE     0x00000001
 190
 191 struct vml_par {
 192         struct pci_dev *vdc;
 193         u64 vdc_mem_base;
 194         u64 vdc_mem_size;
 195         char __iomem *vdc_mem;
 196
 197         struct pci_dev *gpu;
 198         u64 gpu_mem_base;
 199         u64 gpu_mem_size;
 200         char __iomem *gpu_mem;
 201
 202         atomic_t refcount;
 203 };
 204
 205 struct vram_area {
 206         unsigned long logical;
 207         unsigned long phys;
 208         unsigned long size;
 209         unsigned order;
 210 };
 211
 212 struct vml_info {
 213         struct fb_info info;
 214         struct vml_par *par;
 215         struct list_head head;
 216         struct vram_area vram[VML_VRAM_AREAS];
 217         u64 vram_start;
 218         u64 vram_contig_size;
 219         u32 num_areas;
 220         void __iomem *vram_logical;
 221         u32 pseudo_palette[16];
 222         u32 stride;
 223         u32 bytes_per_pixel;
 224         atomic_t vmas;
 225         int cur_blank_mode;
 226         int pipe_disabled;
 227 };
 228
 229 /*
 230  * Subsystem
 231  */
 232
 233 struct vml_sys {
 234         char *name;
 235
 236         /*
 237          * Save / Restore;
 238          */
 239
 240         int (*save) (struct vml_sys * sys);
 241         int (*restore) (struct vml_sys * sys);
 242
 243         /*
 244          * PLL programming;
 245          */
 246
 247         int (*set_clock) (struct vml_sys * sys, int clock);
 248         int (*nearest_clock) (const struct vml_sys * sys, int clock);
 249 };
 250
 251 extern int vmlfb_register_subsys(struct vml_sys *sys);
 252 extern void vmlfb_unregister_subsys(struct vml_sys *sys);
 253
 254 #define VML_READ32(_par, _offset) \
 255         (ioread32((_par)->vdc_mem + (_offset)))
 256 #define VML_WRITE32(_par, _offset, _value)                              \
 257         iowrite32(_value, (_par)->vdc_mem + (_offset))
 258
 259 #endif