2 * BRIEF MODULE DESCRIPTION
3 * Momentum Computer Ocelot-C and -CS board dependent boot routines
5 * Copyright (C) 1996, 1997, 2001 Ralf Baechle
6 * Copyright (C) 2000 RidgeRun, Inc.
7 * Copyright (C) 2001 Red Hat, Inc.
8 * Copyright (C) 2002 Momentum Computer
10 * Author: Matthew Dharm, Momentum Computer
13 * Louis Hamilton, Red Hat, Inc.
14 * hamilton@redhat.com [MIPS64 modifications]
16 * Author: RidgeRun, Inc.
17 * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
19 * Copyright 2001 MontaVista Software Inc.
20 * Author: jsun@mvista.com or jsun@junsun.net
22 * This program is free software; you can redistribute it and/or modify it
23 * under the terms of the GNU General Public License as published by the
24 * Free Software Foundation; either version 2 of the License, or (at your
25 * option) any later version.
27 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
28 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
29 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
30 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
31 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
32 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
33 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
34 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
36 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 * You should have received a copy of the GNU General Public License along
39 * with this program; if not, write to the Free Software Foundation, Inc.,
40 * 675 Mass Ave, Cambridge, MA 02139, USA.
43 #include <linux/bcd.h>
44 #include <linux/init.h>
45 #include <linux/kernel.h>
46 #include <linux/types.h>
48 #include <linux/swap.h>
49 #include <linux/ioport.h>
50 #include <linux/sched.h>
51 #include <linux/interrupt.h>
52 #include <linux/pci.h>
54 #include <linux/timex.h>
55 #include <linux/vmalloc.h>
56 #include <linux/mv643xx.h>
59 #include <asm/bootinfo.h>
64 #include <asm/processor.h>
65 #include <asm/reboot.h>
66 #include <asm/marvell.h>
67 #include <linux/bootmem.h>
68 #include <linux/blkdev.h>
69 #include "ocelot_c_fpga.h"
71 unsigned long marvell_base;
72 unsigned int cpu_clock;
74 /* These functions are used for rebooting or halting the machine*/
75 extern void momenco_ocelot_restart(char *command);
76 extern void momenco_ocelot_halt(void);
77 extern void momenco_ocelot_power_off(void);
79 void momenco_time_init(void);
81 static char reset_reason;
83 void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1, unsigned long entryhi, unsigned long pagemask);
85 static unsigned long ENTRYLO(unsigned long paddr)
87 return ((paddr & PAGE_MASK) |
88 (_PAGE_PRESENT | __READABLE | __WRITEABLE | _PAGE_GLOBAL |
89 _CACHE_UNCACHED)) >> 6;
92 /* setup code for a handoff from a version 2 PMON 2000 PROM */
93 void PMON_v2_setup(void)
95 /* Some wired TLB entries for the MV64340 and perhiperals. The
96 MV64340 is going to be hit on every IRQ anyway - there's
97 absolutely no point in letting it be a random TLB entry, as
98 it'll just cause needless churning of the TLB. And we use
99 the other half for the serial port, which is just a PITA
102 Device Physical Virtual
103 MV64340 Internal Regs 0xf4000000 0xf4000000
104 Ocelot-C[S] PLD (CS0) 0xfc000000 0xfc000000
105 NVRAM (CS1) 0xfc800000 0xfc800000
106 UARTs (CS2) 0xfd000000 0xfd000000
107 Internal SRAM 0xfe000000 0xfe000000
108 M-Systems DOC (CS3) 0xff000000 0xff000000
110 printk("PMON_v2_setup\n");
113 /* marvell and extra space */
114 add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xf4010000), 0xfffffffff4000000, PM_64K);
115 /* fpga, rtc, and uart */
116 add_wired_entry(ENTRYLO(0xfc000000), ENTRYLO(0xfd000000), 0xfffffffffc000000, PM_16M);
117 /* m-sys and internal SRAM */
118 add_wired_entry(ENTRYLO(0xfe000000), ENTRYLO(0xff000000), 0xfffffffffe000000, PM_16M);
120 marvell_base = 0xfffffffff4000000;
122 /* marvell and extra space */
123 add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xf4010000), 0xf4000000, PM_64K);
124 /* fpga, rtc, and uart */
125 add_wired_entry(ENTRYLO(0xfc000000), ENTRYLO(0xfd000000), 0xfc000000, PM_16M);
126 /* m-sys and internal SRAM */
127 add_wired_entry(ENTRYLO(0xfe000000), ENTRYLO(0xff000000), 0xfe000000, PM_16M);
129 marvell_base = 0xf4000000;
133 unsigned long m48t37y_get_time(void)
136 unsigned char *rtc_base = (unsigned char*)0xfffffffffc800000;
138 unsigned char* rtc_base = (unsigned char*)0xfc800000;
140 unsigned int year, month, day, hour, min, sec;
143 spin_lock_irqsave(&rtc_lock, flags);
144 /* stop the update */
145 rtc_base[0x7ff8] = 0x40;
147 year = BCD2BIN(rtc_base[0x7fff]);
148 year += BCD2BIN(rtc_base[0x7ff1]) * 100;
150 month = BCD2BIN(rtc_base[0x7ffe]);
152 day = BCD2BIN(rtc_base[0x7ffd]);
154 hour = BCD2BIN(rtc_base[0x7ffb]);
155 min = BCD2BIN(rtc_base[0x7ffa]);
156 sec = BCD2BIN(rtc_base[0x7ff9]);
158 /* start the update */
159 rtc_base[0x7ff8] = 0x00;
160 spin_unlock_irqrestore(&rtc_lock, flags);
162 return mktime(year, month, day, hour, min, sec);
165 int m48t37y_set_time(unsigned long sec)
168 unsigned char* rtc_base = (unsigned char*)0xfffffffffc800000;
170 unsigned char* rtc_base = (unsigned char*)0xfc800000;
175 /* convert to a more useful format -- note months count from 0 */
179 spin_lock_irqsave(&rtc_lock, flags);
181 rtc_base[0x7ff8] = 0x80;
184 rtc_base[0x7fff] = BIN2BCD(tm.tm_year % 100);
185 rtc_base[0x7ff1] = BIN2BCD(tm.tm_year / 100);
188 rtc_base[0x7ffe] = BIN2BCD(tm.tm_mon);
191 rtc_base[0x7ffd] = BIN2BCD(tm.tm_mday);
194 rtc_base[0x7ffb] = BIN2BCD(tm.tm_hour);
195 rtc_base[0x7ffa] = BIN2BCD(tm.tm_min);
196 rtc_base[0x7ff9] = BIN2BCD(tm.tm_sec);
198 /* day of week -- not really used, but let's keep it up-to-date */
199 rtc_base[0x7ffc] = BIN2BCD(tm.tm_wday + 1);
201 /* disable writing */
202 rtc_base[0x7ff8] = 0x00;
203 spin_unlock_irqrestore(&rtc_lock, flags);
208 void __init plat_timer_setup(struct irqaction *irq)
213 void momenco_time_init(void)
215 #ifdef CONFIG_CPU_SR71000
216 mips_hpt_frequency = cpu_clock;
217 #elif defined(CONFIG_CPU_RM7000)
218 mips_hpt_frequency = cpu_clock / 2;
220 #error Unknown CPU for this board
222 printk("momenco_time_init cpu_clock=%d\n", cpu_clock);
224 rtc_mips_get_time = m48t37y_get_time;
225 rtc_mips_set_time = m48t37y_set_time;
228 void __init plat_mem_setup(void)
230 unsigned int tmpword;
232 board_time_init = momenco_time_init;
234 _machine_restart = momenco_ocelot_restart;
235 _machine_halt = momenco_ocelot_halt;
236 pm_power_off = momenco_ocelot_power_off;
239 * initrd_start = (unsigned long)ocelot_initrd_start;
240 * initrd_end = (unsigned long)ocelot_initrd_start + (ulong)ocelot_initrd_size;
241 * initrd_below_start_ok = 1;
244 /* do handoff reconfiguration */
247 /* shut down ethernet ports, just to be sure our memory doesn't get
248 * corrupted by random ethernet traffic.
250 MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(0), 0xff << 8);
251 MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(1), 0xff << 8);
252 MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(0), 0xff << 8);
253 MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(1), 0xff << 8);
255 while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(0)) & 0xff);
257 while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(1)) & 0xff);
259 while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(0)) & 0xff);
261 while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(1)) & 0xff);
262 MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(0),
263 MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(0)) & ~1);
264 MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(1),
265 MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(1)) & ~1);
267 /* Turn off the Bit-Error LED */
268 OCELOT_FPGA_WRITE(0x80, CLR);
270 tmpword = OCELOT_FPGA_READ(BOARDREV);
271 #ifdef CONFIG_CPU_SR71000
273 printk("Momenco Ocelot-CS: Board Assembly Rev. %c\n",
276 printk("Momenco Ocelot-CS: Board Assembly Revision #0x%x\n",
280 printk("Momenco Ocelot-C: Board Assembly Rev. %c\n",
283 printk("Momenco Ocelot-C: Board Assembly Revision #0x%x\n",
287 tmpword = OCELOT_FPGA_READ(FPGA_REV);
288 printk("FPGA Rev: %d.%d\n", tmpword>>4, tmpword&15);
289 tmpword = OCELOT_FPGA_READ(RESET_STATUS);
290 printk("Reset reason: 0x%x\n", tmpword);
293 printk(" - Power-up reset\n");
296 printk(" - Push-button reset\n");
299 printk(" - cPCI bus reset\n");
302 printk(" - Watchdog reset\n");
305 printk(" - Software reset\n");
308 printk(" - Unknown reset cause\n");
310 reset_reason = tmpword;
311 OCELOT_FPGA_WRITE(0xff, RESET_STATUS);
313 tmpword = OCELOT_FPGA_READ(CPCI_ID);
314 printk("cPCI ID register: 0x%02x\n", tmpword);
315 printk(" - Slot number: %d\n", tmpword & 0x1f);
316 printk(" - PCI bus present: %s\n", tmpword & 0x40 ? "yes" : "no");
317 printk(" - System Slot: %s\n", tmpword & 0x20 ? "yes" : "no");
319 tmpword = OCELOT_FPGA_READ(BOARD_STATUS);
320 printk("Board Status register: 0x%02x\n", tmpword);
321 printk(" - User jumper: %s\n", (tmpword & 0x80)?"installed":"absent");
322 printk(" - Boot flash write jumper: %s\n", (tmpword&0x40)?"installed":"absent");
323 printk(" - L3 Cache size: %d MiB\n", (1<<((tmpword&12) >> 2))&~1);
324 printk(" - SDRAM size: %d MiB\n", 1<<(6+(tmpword&3)));
329 add_memory_region(0x0, 0x200<<20, BOOT_MEM_RAM);
333 add_memory_region(0x0, 0x100<<20, BOOT_MEM_RAM);
337 add_memory_region(0x0, 0x80<<20, BOOT_MEM_RAM);
340 /* 1GiB -- needs CONFIG_HIGHMEM */
341 add_memory_region(0x0, 0x400<<20, BOOT_MEM_RAM);
347 * This needs to be one of the first initcalls, because no I/O port access
348 * can work before this
350 static int io_base_ioremap(void)
352 void __iomem * io_remap_range = ioremap(0xc0000000UL, 0x10000);
355 panic("Could not ioremap I/O port range");
357 set_io_port_base((unsigned long) io_remap_range);
362 module_init(io_base_ioremap);