git.oblomov.eu Git - linux-2.6/blob - arch/mips/dec/kn02-irq.c

   1 /*
   2  *      linux/arch/mips/dec/kn02-irq.c
   3  *
   4  *      DECstation 5000/200 (KN02) Control and Status Register
   5  *      interrupts.
   6  *
   7  *      Copyright (c) 2002, 2003  Maciej W. Rozycki
   8  *
   9  *      This program is free software; you can redistribute it and/or
  10  *      modify it under the terms of the GNU General Public License
  11  *      as published by the Free Software Foundation; either version
  12  *      2 of the License, or (at your option) any later version.
  13  */
  14
  15 #include <linux/init.h>
  16 #include <linux/irq.h>
  17 #include <linux/spinlock.h>
  18 #include <linux/types.h>
  19
  20 #include <asm/dec/kn02.h>
  21
  22
  23 /*
  24  * Bits 7:0 of the Control Register are write-only -- the
  25  * corresponding bits of the Status Register have a different
  26  * meaning.  Hence we use a cache.  It speeds up things a bit
  27  * as well.
  28  *
  29  * There is no default value -- it has to be initialized.
  30  */
  31 u32 cached_kn02_csr;
  32 DEFINE_SPINLOCK(kn02_lock);
  33
  34
  35 static int kn02_irq_base;
  36
  37
  38 static inline void unmask_kn02_irq(unsigned int irq)
  39 {
  40         volatile u32 *csr = (volatile u32 *)KN02_CSR_BASE;
  41
  42         cached_kn02_csr |= (1 << (irq - kn02_irq_base + 16));
  43         *csr = cached_kn02_csr;
  44 }
  45
  46 static inline void mask_kn02_irq(unsigned int irq)
  47 {
  48         volatile u32 *csr = (volatile u32 *)KN02_CSR_BASE;
  49
  50         cached_kn02_csr &= ~(1 << (irq - kn02_irq_base + 16));
  51         *csr = cached_kn02_csr;
  52 }
  53
  54 static inline void enable_kn02_irq(unsigned int irq)
  55 {
  56         unsigned long flags;
  57
  58         spin_lock_irqsave(&kn02_lock, flags);
  59         unmask_kn02_irq(irq);
  60         spin_unlock_irqrestore(&kn02_lock, flags);
  61 }
  62
  63 static inline void disable_kn02_irq(unsigned int irq)
  64 {
  65         unsigned long flags;
  66
  67         spin_lock_irqsave(&kn02_lock, flags);
  68         mask_kn02_irq(irq);
  69         spin_unlock_irqrestore(&kn02_lock, flags);
  70 }
  71
  72
  73 static unsigned int startup_kn02_irq(unsigned int irq)
  74 {
  75         enable_kn02_irq(irq);
  76         return 0;
  77 }
  78
  79 #define shutdown_kn02_irq disable_kn02_irq
  80
  81 static void ack_kn02_irq(unsigned int irq)
  82 {
  83         spin_lock(&kn02_lock);
  84         mask_kn02_irq(irq);
  85         spin_unlock(&kn02_lock);
  86         iob();
  87 }
  88
  89 static void end_kn02_irq(unsigned int irq)
  90 {
  91         if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
  92                 enable_kn02_irq(irq);
  93 }
  94
  95 static struct hw_interrupt_type kn02_irq_type = {
  96         .typename = "KN02-CSR",
  97         .startup = startup_kn02_irq,
  98         .shutdown = shutdown_kn02_irq,
  99         .enable = enable_kn02_irq,
 100         .disable = disable_kn02_irq,
 101         .ack = ack_kn02_irq,
 102         .end = end_kn02_irq,
 103 };
 104
 105
 106 void __init init_kn02_irqs(int base)
 107 {
 108         volatile u32 *csr = (volatile u32 *)KN02_CSR_BASE;
 109         unsigned long flags;
 110         int i;
 111
 112         /* Mask interrupts. */
 113         spin_lock_irqsave(&kn02_lock, flags);
 114         cached_kn02_csr &= ~KN03_CSR_IOINTEN;
 115         *csr = cached_kn02_csr;
 116         iob();
 117         spin_unlock_irqrestore(&kn02_lock, flags);
 118
 119         for (i = base; i < base + KN02_IRQ_LINES; i++) {
 120                 irq_desc[i].status = IRQ_DISABLED;
 121                 irq_desc[i].action = 0;
 122                 irq_desc[i].depth = 1;
 123                 irq_desc[i].handler = &kn02_irq_type;
 124         }
 125
 126         kn02_irq_base = base;
 127 }