1 /****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2007-2008 Solarflare Communications Inc.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published
7 * by the Free Software Foundation, incorporated herein by reference.
10 #include <linux/delay.h>
11 #include <linux/rtnetlink.h>
12 #include <linux/seq_file.h>
17 #include "falcon_hwdefs.h"
19 #include "workarounds.h"
22 /* We expect these MMDs to be in the package. SFT9001 also has a
23 * clause 22 extension MMD, but since it doesn't have all the generic
24 * MMD registers it is pointless to include it here.
26 #define TENXPRESS_REQUIRED_DEVS (MDIO_MMDREG_DEVS_PMAPMD | \
27 MDIO_MMDREG_DEVS_PCS | \
28 MDIO_MMDREG_DEVS_PHYXS | \
31 #define SFX7101_LOOPBACKS ((1 << LOOPBACK_PHYXS) | \
32 (1 << LOOPBACK_PCS) | \
33 (1 << LOOPBACK_PMAPMD) | \
34 (1 << LOOPBACK_NETWORK))
36 #define SFT9001_LOOPBACKS ((1 << LOOPBACK_GPHY) | \
37 (1 << LOOPBACK_PHYXS) | \
38 (1 << LOOPBACK_PCS) | \
39 (1 << LOOPBACK_PMAPMD) | \
40 (1 << LOOPBACK_NETWORK))
42 /* We complain if we fail to see the link partner as 10G capable this many
43 * times in a row (must be > 1 as sampling the autoneg. registers is racy)
45 #define MAX_BAD_LP_TRIES (5)
48 #define PMA_PMD_LASI_CTRL 36866
49 #define PMA_PMD_LASI_STATUS 36869
50 #define PMA_PMD_LS_ALARM_LBN 0
51 #define PMA_PMD_LS_ALARM_WIDTH 1
52 #define PMA_PMD_TX_ALARM_LBN 1
53 #define PMA_PMD_TX_ALARM_WIDTH 1
54 #define PMA_PMD_RX_ALARM_LBN 2
55 #define PMA_PMD_RX_ALARM_WIDTH 1
56 #define PMA_PMD_AN_ALARM_LBN 3
57 #define PMA_PMD_AN_ALARM_WIDTH 1
59 /* Extended control register */
60 #define PMA_PMD_XCONTROL_REG 49152
61 #define PMA_PMD_EXT_GMII_EN_LBN 1
62 #define PMA_PMD_EXT_GMII_EN_WIDTH 1
63 #define PMA_PMD_EXT_CLK_OUT_LBN 2
64 #define PMA_PMD_EXT_CLK_OUT_WIDTH 1
65 #define PMA_PMD_LNPGA_POWERDOWN_LBN 8 /* SFX7101 only */
66 #define PMA_PMD_LNPGA_POWERDOWN_WIDTH 1
67 #define PMA_PMD_EXT_CLK312_LBN 8 /* SFT9001 only */
68 #define PMA_PMD_EXT_CLK312_WIDTH 1
69 #define PMA_PMD_EXT_LPOWER_LBN 12
70 #define PMA_PMD_EXT_LPOWER_WIDTH 1
71 #define PMA_PMD_EXT_ROBUST_LBN 14
72 #define PMA_PMD_EXT_ROBUST_WIDTH 1
73 #define PMA_PMD_EXT_SSR_LBN 15
74 #define PMA_PMD_EXT_SSR_WIDTH 1
76 /* extended status register */
77 #define PMA_PMD_XSTATUS_REG 49153
78 #define PMA_PMD_XSTAT_FLP_LBN (12)
80 /* LED control register */
81 #define PMA_PMD_LED_CTRL_REG 49159
82 #define PMA_PMA_LED_ACTIVITY_LBN (3)
84 /* LED function override register */
85 #define PMA_PMD_LED_OVERR_REG 49161
86 /* Bit positions for different LEDs (there are more but not wired on SFE4001)*/
87 #define PMA_PMD_LED_LINK_LBN (0)
88 #define PMA_PMD_LED_SPEED_LBN (2)
89 #define PMA_PMD_LED_TX_LBN (4)
90 #define PMA_PMD_LED_RX_LBN (6)
91 /* Override settings */
92 #define PMA_PMD_LED_AUTO (0) /* H/W control */
93 #define PMA_PMD_LED_ON (1)
94 #define PMA_PMD_LED_OFF (2)
95 #define PMA_PMD_LED_FLASH (3)
96 #define PMA_PMD_LED_MASK 3
97 /* All LEDs under hardware control */
98 #define PMA_PMD_LED_FULL_AUTO (0)
99 /* Green and Amber under hardware control, Red off */
100 #define PMA_PMD_LED_DEFAULT (PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN)
102 #define PMA_PMD_SPEED_ENABLE_REG 49192
103 #define PMA_PMD_100TX_ADV_LBN 1
104 #define PMA_PMD_100TX_ADV_WIDTH 1
105 #define PMA_PMD_1000T_ADV_LBN 2
106 #define PMA_PMD_1000T_ADV_WIDTH 1
107 #define PMA_PMD_10000T_ADV_LBN 3
108 #define PMA_PMD_10000T_ADV_WIDTH 1
109 #define PMA_PMD_SPEED_LBN 4
110 #define PMA_PMD_SPEED_WIDTH 4
112 /* Cable diagnostics - SFT9001 only */
113 #define PMA_PMD_CDIAG_CTRL_REG 49213
114 #define CDIAG_CTRL_IMMED_LBN 15
115 #define CDIAG_CTRL_BRK_LINK_LBN 12
116 #define CDIAG_CTRL_IN_PROG_LBN 11
117 #define CDIAG_CTRL_LEN_UNIT_LBN 10
118 #define CDIAG_CTRL_LEN_METRES 1
119 #define PMA_PMD_CDIAG_RES_REG 49174
120 #define CDIAG_RES_A_LBN 12
121 #define CDIAG_RES_B_LBN 8
122 #define CDIAG_RES_C_LBN 4
123 #define CDIAG_RES_D_LBN 0
124 #define CDIAG_RES_WIDTH 4
125 #define CDIAG_RES_OPEN 2
126 #define CDIAG_RES_OK 1
127 #define CDIAG_RES_INVALID 0
128 /* Set of 4 registers for pairs A-D */
129 #define PMA_PMD_CDIAG_LEN_REG 49175
131 /* Serdes control registers - SFT9001 only */
132 #define PMA_PMD_CSERDES_CTRL_REG 64258
133 /* Set the 156.25 MHz output to 312.5 MHz to drive Falcon's XMAC */
134 #define PMA_PMD_CSERDES_DEFAULT 0x000f
136 /* Misc register defines - SFX7101 only */
137 #define PCS_CLOCK_CTRL_REG 55297
138 #define PLL312_RST_N_LBN 2
140 #define PCS_SOFT_RST2_REG 55302
141 #define SERDES_RST_N_LBN 13
142 #define XGXS_RST_N_LBN 12
144 #define PCS_TEST_SELECT_REG 55303 /* PRM 10.5.8 */
145 #define CLK312_EN_LBN 3
147 /* PHYXS registers */
148 #define PHYXS_XCONTROL_REG 49152
149 #define PHYXS_RESET_LBN 15
150 #define PHYXS_RESET_WIDTH 1
152 #define PHYXS_TEST1 (49162)
153 #define LOOPBACK_NEAR_LBN (8)
154 #define LOOPBACK_NEAR_WIDTH (1)
156 #define PCS_10GBASET_STAT1 32
157 #define PCS_10GBASET_BLKLK_LBN 0
158 #define PCS_10GBASET_BLKLK_WIDTH 1
160 /* Boot status register */
161 #define PCS_BOOT_STATUS_REG 53248
162 #define PCS_BOOT_FATAL_ERR_LBN (0)
163 #define PCS_BOOT_PROGRESS_LBN (1)
164 #define PCS_BOOT_PROGRESS_WIDTH (2)
165 #define PCS_BOOT_COMPLETE_LBN (3)
167 #define PCS_BOOT_MAX_DELAY (100)
168 #define PCS_BOOT_POLL_DELAY (10)
170 /* 100M/1G PHY registers */
171 #define GPHY_XCONTROL_REG 49152
172 #define GPHY_ISOLATE_LBN 10
173 #define GPHY_ISOLATE_WIDTH 1
174 #define GPHY_DUPLEX_LBN 8
175 #define GPHY_DUPLEX_WIDTH 1
176 #define GPHY_LOOPBACK_NEAR_LBN 14
177 #define GPHY_LOOPBACK_NEAR_WIDTH 1
179 #define C22EXT_STATUS_REG 49153
180 #define C22EXT_STATUS_LINK_LBN 2
181 #define C22EXT_STATUS_LINK_WIDTH 1
183 #define C22EXT_MSTSLV_CTRL 49161
184 #define C22EXT_MSTSLV_CTRL_ADV_1000_HD_LBN 8
185 #define C22EXT_MSTSLV_CTRL_ADV_1000_FD_LBN 9
187 #define C22EXT_MSTSLV_STATUS 49162
188 #define C22EXT_MSTSLV_STATUS_LP_1000_HD_LBN 10
189 #define C22EXT_MSTSLV_STATUS_LP_1000_FD_LBN 11
191 /* Time to wait between powering down the LNPGA and turning off the power
193 #define LNPGA_PDOWN_WAIT (HZ / 5)
195 struct tenxpress_phy_data {
196 enum efx_loopback_mode loopback_mode;
197 enum efx_phy_mode phy_mode;
201 static ssize_t show_phy_short_reach(struct device *dev,
202 struct device_attribute *attr, char *buf)
204 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
207 reg = mdio_clause45_read(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD,
208 MDIO_PMAPMD_10GBT_TXPWR);
209 return sprintf(buf, "%d\n",
210 !!(reg & (1 << MDIO_PMAPMD_10GBT_TXPWR_SHORT_LBN)));
213 static ssize_t set_phy_short_reach(struct device *dev,
214 struct device_attribute *attr,
215 const char *buf, size_t count)
217 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
220 mdio_clause45_set_flag(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD,
221 MDIO_PMAPMD_10GBT_TXPWR,
222 MDIO_PMAPMD_10GBT_TXPWR_SHORT_LBN,
223 count != 0 && *buf != '0');
224 efx_reconfigure_port(efx);
230 static DEVICE_ATTR(phy_short_reach, 0644, show_phy_short_reach,
231 set_phy_short_reach);
233 /* Check that the C166 has booted successfully */
234 static int tenxpress_phy_check(struct efx_nic *efx)
236 int phy_id = efx->mii.phy_id;
237 int count = PCS_BOOT_MAX_DELAY / PCS_BOOT_POLL_DELAY;
240 /* Wait for the boot to complete (or not) */
242 boot_stat = mdio_clause45_read(efx, phy_id,
244 PCS_BOOT_STATUS_REG);
245 if (boot_stat & (1 << PCS_BOOT_COMPLETE_LBN))
248 udelay(PCS_BOOT_POLL_DELAY);
252 EFX_ERR(efx, "%s: PHY boot timed out. Last status "
254 (boot_stat >> PCS_BOOT_PROGRESS_LBN) &
255 ((1 << PCS_BOOT_PROGRESS_WIDTH) - 1));
262 static int tenxpress_init(struct efx_nic *efx)
264 int phy_id = efx->mii.phy_id;
268 if (efx->phy_type == PHY_TYPE_SFX7101) {
269 /* Enable 312.5 MHz clock */
270 mdio_clause45_write(efx, phy_id,
271 MDIO_MMD_PCS, PCS_TEST_SELECT_REG,
274 /* Enable 312.5 MHz clock and GMII */
275 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_PMAPMD,
276 PMA_PMD_XCONTROL_REG);
277 reg |= ((1 << PMA_PMD_EXT_GMII_EN_LBN) |
278 (1 << PMA_PMD_EXT_CLK_OUT_LBN) |
279 (1 << PMA_PMD_EXT_CLK312_LBN) |
280 (1 << PMA_PMD_EXT_ROBUST_LBN));
282 mdio_clause45_write(efx, phy_id, MDIO_MMD_PMAPMD,
283 PMA_PMD_XCONTROL_REG, reg);
284 mdio_clause45_set_flag(efx, phy_id, MDIO_MMD_C22EXT,
285 GPHY_XCONTROL_REG, GPHY_ISOLATE_LBN,
289 rc = tenxpress_phy_check(efx);
293 /* Set the LEDs up as: Green = Link, Amber = Link/Act, Red = Off */
294 if (efx->phy_type == PHY_TYPE_SFX7101) {
295 mdio_clause45_set_flag(efx, phy_id, MDIO_MMD_PMAPMD,
296 PMA_PMD_LED_CTRL_REG,
297 PMA_PMA_LED_ACTIVITY_LBN,
299 mdio_clause45_write(efx, phy_id, MDIO_MMD_PMAPMD,
300 PMA_PMD_LED_OVERR_REG, PMA_PMD_LED_DEFAULT);
306 static int tenxpress_phy_init(struct efx_nic *efx)
308 struct tenxpress_phy_data *phy_data;
311 phy_data = kzalloc(sizeof(*phy_data), GFP_KERNEL);
314 efx->phy_data = phy_data;
315 phy_data->phy_mode = efx->phy_mode;
317 if (!(efx->phy_mode & PHY_MODE_SPECIAL)) {
318 if (efx->phy_type == PHY_TYPE_SFT9001A) {
320 reg = mdio_clause45_read(efx, efx->mii.phy_id,
322 PMA_PMD_XCONTROL_REG);
323 reg |= (1 << PMA_PMD_EXT_SSR_LBN);
324 mdio_clause45_write(efx, efx->mii.phy_id,
326 PMA_PMD_XCONTROL_REG, reg);
330 rc = mdio_clause45_wait_reset_mmds(efx,
331 TENXPRESS_REQUIRED_DEVS);
335 rc = mdio_clause45_check_mmds(efx, TENXPRESS_REQUIRED_DEVS, 0);
340 rc = tenxpress_init(efx);
343 mdio_clause45_set_pause(efx);
345 if (efx->phy_type == PHY_TYPE_SFT9001B) {
346 rc = device_create_file(&efx->pci_dev->dev,
347 &dev_attr_phy_short_reach);
352 schedule_timeout_uninterruptible(HZ / 5); /* 200ms */
354 /* Let XGXS and SerDes out of reset */
355 falcon_reset_xaui(efx);
360 kfree(efx->phy_data);
361 efx->phy_data = NULL;
365 /* Perform a "special software reset" on the PHY. The caller is
366 * responsible for saving and restoring the PHY hardware registers
367 * properly, and masking/unmasking LASI */
368 static int tenxpress_special_reset(struct efx_nic *efx)
372 /* The XGMAC clock is driven from the SFC7101/SFT9001 312MHz clock, so
373 * a special software reset can glitch the XGMAC sufficiently for stats
374 * requests to fail. */
375 efx_stats_disable(efx);
378 reg = mdio_clause45_read(efx, efx->mii.phy_id,
379 MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG);
380 reg |= (1 << PMA_PMD_EXT_SSR_LBN);
381 mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD,
382 PMA_PMD_XCONTROL_REG, reg);
386 /* Wait for the blocks to come out of reset */
387 rc = mdio_clause45_wait_reset_mmds(efx,
388 TENXPRESS_REQUIRED_DEVS);
392 /* Try and reconfigure the device */
393 rc = tenxpress_init(efx);
397 /* Wait for the XGXS state machine to churn */
400 efx_stats_enable(efx);
404 static void sfx7101_check_bad_lp(struct efx_nic *efx, bool link_ok)
406 struct tenxpress_phy_data *pd = efx->phy_data;
407 int phy_id = efx->mii.phy_id;
414 /* Check that AN has started but not completed. */
415 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_AN,
417 if (!(reg & (1 << MDIO_AN_STATUS_LP_AN_CAP_LBN)))
418 return; /* LP status is unknown */
419 bad_lp = !(reg & (1 << MDIO_AN_STATUS_AN_DONE_LBN));
424 /* Nothing to do if all is well and was previously so. */
425 if (!pd->bad_lp_tries)
428 /* Use the RX (red) LED as an error indicator once we've seen AN
429 * failure several times in a row, and also log a message. */
430 if (!bad_lp || pd->bad_lp_tries == MAX_BAD_LP_TRIES) {
431 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_PMAPMD,
432 PMA_PMD_LED_OVERR_REG);
433 reg &= ~(PMA_PMD_LED_MASK << PMA_PMD_LED_RX_LBN);
435 reg |= PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN;
437 reg |= PMA_PMD_LED_FLASH << PMA_PMD_LED_RX_LBN;
438 EFX_ERR(efx, "appears to be plugged into a port"
439 " that is not 10GBASE-T capable. The PHY"
440 " supports 10GBASE-T ONLY, so no link can"
441 " be established\n");
443 mdio_clause45_write(efx, phy_id, MDIO_MMD_PMAPMD,
444 PMA_PMD_LED_OVERR_REG, reg);
445 pd->bad_lp_tries = bad_lp;
449 static bool sfx7101_link_ok(struct efx_nic *efx)
451 return mdio_clause45_links_ok(efx,
452 MDIO_MMDREG_DEVS_PMAPMD |
453 MDIO_MMDREG_DEVS_PCS |
454 MDIO_MMDREG_DEVS_PHYXS);
457 static bool sft9001_link_ok(struct efx_nic *efx, struct ethtool_cmd *ecmd)
459 int phy_id = efx->mii.phy_id;
462 if (efx_phy_mode_disabled(efx->phy_mode))
464 else if (efx->loopback_mode == LOOPBACK_GPHY)
466 else if (efx->loopback_mode)
467 return mdio_clause45_links_ok(efx,
468 MDIO_MMDREG_DEVS_PMAPMD |
469 MDIO_MMDREG_DEVS_PHYXS);
471 /* We must use the same definition of link state as LASI,
472 * otherwise we can miss a link state transition
474 if (ecmd->speed == 10000) {
475 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_PCS,
477 return reg & (1 << PCS_10GBASET_BLKLK_LBN);
479 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_C22EXT,
481 return reg & (1 << C22EXT_STATUS_LINK_LBN);
485 static void tenxpress_ext_loopback(struct efx_nic *efx)
487 int phy_id = efx->mii.phy_id;
489 mdio_clause45_set_flag(efx, phy_id, MDIO_MMD_PHYXS,
490 PHYXS_TEST1, LOOPBACK_NEAR_LBN,
491 efx->loopback_mode == LOOPBACK_PHYXS);
492 if (efx->phy_type != PHY_TYPE_SFX7101)
493 mdio_clause45_set_flag(efx, phy_id, MDIO_MMD_C22EXT,
495 GPHY_LOOPBACK_NEAR_LBN,
496 efx->loopback_mode == LOOPBACK_GPHY);
499 static void tenxpress_low_power(struct efx_nic *efx)
501 int phy_id = efx->mii.phy_id;
503 if (efx->phy_type == PHY_TYPE_SFX7101)
504 mdio_clause45_set_mmds_lpower(
505 efx, !!(efx->phy_mode & PHY_MODE_LOW_POWER),
506 TENXPRESS_REQUIRED_DEVS);
508 mdio_clause45_set_flag(
509 efx, phy_id, MDIO_MMD_PMAPMD,
510 PMA_PMD_XCONTROL_REG, PMA_PMD_EXT_LPOWER_LBN,
511 !!(efx->phy_mode & PHY_MODE_LOW_POWER));
514 static void tenxpress_phy_reconfigure(struct efx_nic *efx)
516 struct tenxpress_phy_data *phy_data = efx->phy_data;
517 struct ethtool_cmd ecmd;
518 bool phy_mode_change, loop_reset;
520 if (efx->phy_mode & (PHY_MODE_OFF | PHY_MODE_SPECIAL)) {
521 phy_data->phy_mode = efx->phy_mode;
525 tenxpress_low_power(efx);
527 phy_mode_change = (efx->phy_mode == PHY_MODE_NORMAL &&
528 phy_data->phy_mode != PHY_MODE_NORMAL);
529 loop_reset = (LOOPBACK_OUT_OF(phy_data, efx, efx->phy_op->loopbacks) ||
530 LOOPBACK_CHANGED(phy_data, efx, 1 << LOOPBACK_GPHY));
532 if (loop_reset || phy_mode_change) {
535 efx->phy_op->get_settings(efx, &ecmd);
537 if (loop_reset || phy_mode_change) {
538 tenxpress_special_reset(efx);
540 /* Reset XAUI if we were in 10G, and are staying
541 * in 10G. If we're moving into and out of 10G
542 * then xaui will be reset anyway */
544 falcon_reset_xaui(efx);
547 rc = efx->phy_op->set_settings(efx, &ecmd);
551 mdio_clause45_transmit_disable(efx);
552 mdio_clause45_phy_reconfigure(efx);
553 tenxpress_ext_loopback(efx);
555 phy_data->loopback_mode = efx->loopback_mode;
556 phy_data->phy_mode = efx->phy_mode;
558 if (efx->phy_type == PHY_TYPE_SFX7101) {
559 efx->link_speed = 10000;
561 efx->link_up = sfx7101_link_ok(efx);
563 efx->phy_op->get_settings(efx, &ecmd);
564 efx->link_speed = ecmd.speed;
565 efx->link_fd = ecmd.duplex == DUPLEX_FULL;
566 efx->link_up = sft9001_link_ok(efx, &ecmd);
568 efx->link_fc = mdio_clause45_get_pause(efx);
571 /* Poll PHY for interrupt */
572 static void tenxpress_phy_poll(struct efx_nic *efx)
574 struct tenxpress_phy_data *phy_data = efx->phy_data;
575 bool change = false, link_ok;
578 if (efx->phy_type == PHY_TYPE_SFX7101) {
579 link_ok = sfx7101_link_ok(efx);
580 if (link_ok != efx->link_up) {
583 link_fc = mdio_clause45_get_pause(efx);
584 if (link_fc != efx->link_fc)
587 sfx7101_check_bad_lp(efx, link_ok);
588 } else if (efx->loopback_mode) {
589 bool link_ok = sft9001_link_ok(efx, NULL);
590 if (link_ok != efx->link_up)
593 u32 status = mdio_clause45_read(efx, efx->mii.phy_id,
595 PMA_PMD_LASI_STATUS);
596 if (status & (1 << PMA_PMD_LS_ALARM_LBN))
601 falcon_sim_phy_event(efx);
603 if (phy_data->phy_mode != PHY_MODE_NORMAL)
607 static void tenxpress_phy_fini(struct efx_nic *efx)
611 if (efx->phy_type == PHY_TYPE_SFT9001B)
612 device_remove_file(&efx->pci_dev->dev,
613 &dev_attr_phy_short_reach);
615 if (efx->phy_type == PHY_TYPE_SFX7101) {
616 /* Power down the LNPGA */
617 reg = (1 << PMA_PMD_LNPGA_POWERDOWN_LBN);
618 mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD,
619 PMA_PMD_XCONTROL_REG, reg);
621 /* Waiting here ensures that the board fini, which can turn
622 * off the power to the PHY, won't get run until the LNPGA
623 * powerdown has been given long enough to complete. */
624 schedule_timeout_uninterruptible(LNPGA_PDOWN_WAIT); /* 200 ms */
627 kfree(efx->phy_data);
628 efx->phy_data = NULL;
632 /* Set the RX and TX LEDs and Link LED flashing. The other LEDs
633 * (which probably aren't wired anyway) are left in AUTO mode */
634 void tenxpress_phy_blink(struct efx_nic *efx, bool blink)
639 reg = (PMA_PMD_LED_FLASH << PMA_PMD_LED_TX_LBN) |
640 (PMA_PMD_LED_FLASH << PMA_PMD_LED_RX_LBN) |
641 (PMA_PMD_LED_FLASH << PMA_PMD_LED_LINK_LBN);
643 reg = PMA_PMD_LED_DEFAULT;
645 mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD,
646 PMA_PMD_LED_OVERR_REG, reg);
649 static const char *const sfx7101_test_names[] = {
654 sfx7101_run_tests(struct efx_nic *efx, int *results, unsigned flags)
658 if (!(flags & ETH_TEST_FL_OFFLINE))
661 /* BIST is automatically run after a special software reset */
662 rc = tenxpress_special_reset(efx);
663 results[0] = rc ? -1 : 1;
667 static const char *const sft9001_test_names[] = {
669 "cable.pairA.status",
670 "cable.pairB.status",
671 "cable.pairC.status",
672 "cable.pairD.status",
673 "cable.pairA.length",
674 "cable.pairB.length",
675 "cable.pairC.length",
676 "cable.pairD.length",
679 static int sft9001_run_tests(struct efx_nic *efx, int *results, unsigned flags)
681 struct ethtool_cmd ecmd;
682 int phy_id = efx->mii.phy_id;
683 int rc = 0, rc2, i, res_reg;
685 if (!(flags & ETH_TEST_FL_OFFLINE))
688 efx->phy_op->get_settings(efx, &ecmd);
690 /* Initialise cable diagnostic results to unknown failure */
691 for (i = 1; i < 9; ++i)
694 /* Run cable diagnostics; wait up to 5 seconds for them to complete.
695 * A cable fault is not a self-test failure, but a timeout is. */
696 mdio_clause45_write(efx, phy_id, MDIO_MMD_PMAPMD,
697 PMA_PMD_CDIAG_CTRL_REG,
698 (1 << CDIAG_CTRL_IMMED_LBN) |
699 (1 << CDIAG_CTRL_BRK_LINK_LBN) |
700 (CDIAG_CTRL_LEN_METRES << CDIAG_CTRL_LEN_UNIT_LBN));
702 while (mdio_clause45_read(efx, phy_id, MDIO_MMD_PMAPMD,
703 PMA_PMD_CDIAG_CTRL_REG) &
704 (1 << CDIAG_CTRL_IN_PROG_LBN)) {
711 res_reg = mdio_clause45_read(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD,
712 PMA_PMD_CDIAG_RES_REG);
713 for (i = 0; i < 4; i++) {
715 (res_reg >> (CDIAG_RES_A_LBN - i * CDIAG_RES_WIDTH))
716 & ((1 << CDIAG_RES_WIDTH) - 1);
717 int len_reg = mdio_clause45_read(efx, efx->mii.phy_id,
719 PMA_PMD_CDIAG_LEN_REG + i);
720 if (pair_res == CDIAG_RES_OK)
722 else if (pair_res == CDIAG_RES_INVALID)
725 results[1 + i] = -pair_res;
726 if (pair_res != CDIAG_RES_INVALID &&
727 pair_res != CDIAG_RES_OPEN &&
729 results[5 + i] = len_reg;
732 /* We must reset to exit cable diagnostic mode. The BIST will
733 * also run when we do this. */
735 rc2 = tenxpress_special_reset(efx);
736 results[0] = rc2 ? -1 : 1;
740 rc2 = efx->phy_op->set_settings(efx, &ecmd);
748 tenxpress_get_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd)
750 int phy_id = efx->mii.phy_id;
751 u32 adv = 0, lpa = 0;
754 if (efx->phy_type != PHY_TYPE_SFX7101) {
755 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_C22EXT,
757 if (reg & (1 << C22EXT_MSTSLV_CTRL_ADV_1000_FD_LBN))
758 adv |= ADVERTISED_1000baseT_Full;
759 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_C22EXT,
760 C22EXT_MSTSLV_STATUS);
761 if (reg & (1 << C22EXT_MSTSLV_STATUS_LP_1000_HD_LBN))
762 lpa |= ADVERTISED_1000baseT_Half;
763 if (reg & (1 << C22EXT_MSTSLV_STATUS_LP_1000_FD_LBN))
764 lpa |= ADVERTISED_1000baseT_Full;
766 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_AN,
768 if (reg & (1 << MDIO_AN_10GBT_CTRL_ADV_10G_LBN))
769 adv |= ADVERTISED_10000baseT_Full;
770 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_AN,
771 MDIO_AN_10GBT_STATUS);
772 if (reg & (1 << MDIO_AN_10GBT_STATUS_LP_10G_LBN))
773 lpa |= ADVERTISED_10000baseT_Full;
775 mdio_clause45_get_settings_ext(efx, ecmd, adv, lpa);
777 if (efx->phy_type != PHY_TYPE_SFX7101)
778 ecmd->supported |= (SUPPORTED_100baseT_Full |
779 SUPPORTED_1000baseT_Full);
781 /* In loopback, the PHY automatically brings up the correct interface,
782 * but doesn't advertise the correct speed. So override it */
783 if (efx->loopback_mode == LOOPBACK_GPHY)
784 ecmd->speed = SPEED_1000;
785 else if (LOOPBACK_MASK(efx) & efx->phy_op->loopbacks)
786 ecmd->speed = SPEED_10000;
789 static int tenxpress_set_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd)
794 return mdio_clause45_set_settings(efx, ecmd);
797 static void sfx7101_set_npage_adv(struct efx_nic *efx, u32 advertising)
799 mdio_clause45_set_flag(efx, efx->mii.phy_id, MDIO_MMD_AN,
801 MDIO_AN_10GBT_CTRL_ADV_10G_LBN,
802 advertising & ADVERTISED_10000baseT_Full);
805 static void sft9001_set_npage_adv(struct efx_nic *efx, u32 advertising)
807 int phy_id = efx->mii.phy_id;
809 mdio_clause45_set_flag(efx, phy_id, MDIO_MMD_C22EXT,
811 C22EXT_MSTSLV_CTRL_ADV_1000_FD_LBN,
812 advertising & ADVERTISED_1000baseT_Full);
813 mdio_clause45_set_flag(efx, phy_id, MDIO_MMD_AN,
815 MDIO_AN_10GBT_CTRL_ADV_10G_LBN,
816 advertising & ADVERTISED_10000baseT_Full);
819 struct efx_phy_operations falcon_sfx7101_phy_ops = {
821 .init = tenxpress_phy_init,
822 .reconfigure = tenxpress_phy_reconfigure,
823 .poll = tenxpress_phy_poll,
824 .fini = tenxpress_phy_fini,
825 .clear_interrupt = efx_port_dummy_op_void,
826 .get_settings = tenxpress_get_settings,
827 .set_settings = tenxpress_set_settings,
828 .set_npage_adv = sfx7101_set_npage_adv,
829 .num_tests = ARRAY_SIZE(sfx7101_test_names),
830 .test_names = sfx7101_test_names,
831 .run_tests = sfx7101_run_tests,
832 .mmds = TENXPRESS_REQUIRED_DEVS,
833 .loopbacks = SFX7101_LOOPBACKS,
836 struct efx_phy_operations falcon_sft9001_phy_ops = {
837 .macs = EFX_GMAC | EFX_XMAC,
838 .init = tenxpress_phy_init,
839 .reconfigure = tenxpress_phy_reconfigure,
840 .poll = tenxpress_phy_poll,
841 .fini = tenxpress_phy_fini,
842 .clear_interrupt = efx_port_dummy_op_void,
843 .get_settings = tenxpress_get_settings,
844 .set_settings = tenxpress_set_settings,
845 .set_npage_adv = sft9001_set_npage_adv,
846 .num_tests = ARRAY_SIZE(sft9001_test_names),
847 .test_names = sft9001_test_names,
848 .run_tests = sft9001_run_tests,
849 .mmds = TENXPRESS_REQUIRED_DEVS,
850 .loopbacks = SFT9001_LOOPBACKS,