git.oblomov.eu Git - linux-2.6/blob - arch/ppc/syslib/mv64x60_win.c

   1 /*
   2  * arch/ppc/syslib/mv64x60_win.c
   3  *
   4  * Tables with info on how to manipulate the 32 & 64 bit windows on the
   5  * various types of Marvell bridge chips.
   6  *
   7  * Author: Mark A. Greer <mgreer@mvista.com>
   8  *
   9  * 2004 (c) MontaVista, Software, Inc.  This file is licensed under
  10  * the terms of the GNU General Public License version 2.  This program
  11  * is licensed "as is" without any warranty of any kind, whether express
  12  * or implied.
  13  */
  14 #include <linux/kernel.h>
  15 #include <linux/init.h>
  16 #include <linux/pci.h>
  17 #include <linux/slab.h>
  18 #include <linux/module.h>
  19 #include <linux/string.h>
  20 #include <linux/mv643xx.h>
  21
  22 #include <asm/byteorder.h>
  23 #include <asm/io.h>
  24 #include <asm/irq.h>
  25 #include <asm/uaccess.h>
  26 #include <asm/machdep.h>
  27 #include <asm/pci-bridge.h>
  28 #include <asm/delay.h>
  29 #include <asm/mv64x60.h>
  30
  31
  32 /*
  33  *****************************************************************************
  34  *
  35  *      Tables describing how to set up windows on each type of bridge
  36  *
  37  *****************************************************************************
  38  */
  39 struct mv64x60_32bit_window
  40         gt64260_32bit_windows[MV64x60_32BIT_WIN_COUNT] __initdata = {
  41         /* CPU->MEM Windows */
  42         [MV64x60_CPU2MEM_0_WIN] = {
  43                 .base_reg               = MV64x60_CPU2MEM_0_BASE,
  44                 .size_reg               = MV64x60_CPU2MEM_0_SIZE,
  45                 .base_bits              = 12,
  46                 .size_bits              = 12,
  47                 .get_from_field         = mv64x60_shift_left,
  48                 .map_to_field           = mv64x60_shift_right,
  49                 .extra                  = 0 },
  50         [MV64x60_CPU2MEM_1_WIN] = {
  51                 .base_reg               = MV64x60_CPU2MEM_1_BASE,
  52                 .size_reg               = MV64x60_CPU2MEM_1_SIZE,
  53                 .base_bits              = 12,
  54                 .size_bits              = 12,
  55                 .get_from_field         = mv64x60_shift_left,
  56                 .map_to_field           = mv64x60_shift_right,
  57                 .extra                  = 0 },
  58         [MV64x60_CPU2MEM_2_WIN] = {
  59                 .base_reg               = MV64x60_CPU2MEM_2_BASE,
  60                 .size_reg               = MV64x60_CPU2MEM_2_SIZE,
  61                 .base_bits              = 12,
  62                 .size_bits              = 12,
  63                 .get_from_field         = mv64x60_shift_left,
  64                 .map_to_field           = mv64x60_shift_right,
  65                 .extra                  = 0 },
  66         [MV64x60_CPU2MEM_3_WIN] = {
  67                 .base_reg               = MV64x60_CPU2MEM_3_BASE,
  68                 .size_reg               = MV64x60_CPU2MEM_3_SIZE,
  69                 .base_bits              = 12,
  70                 .size_bits              = 12,
  71                 .get_from_field         = mv64x60_shift_left,
  72                 .map_to_field           = mv64x60_shift_right,
  73                 .extra                  = 0 },
  74         /* CPU->Device Windows */
  75         [MV64x60_CPU2DEV_0_WIN] = {
  76                 .base_reg               = MV64x60_CPU2DEV_0_BASE,
  77                 .size_reg               = MV64x60_CPU2DEV_0_SIZE,
  78                 .base_bits              = 12,
  79                 .size_bits              = 12,
  80                 .get_from_field         = mv64x60_shift_left,
  81                 .map_to_field           = mv64x60_shift_right,
  82                 .extra                  = 0 },
  83         [MV64x60_CPU2DEV_1_WIN] = {
  84                 .base_reg               = MV64x60_CPU2DEV_1_BASE,
  85                 .size_reg               = MV64x60_CPU2DEV_1_SIZE,
  86                 .base_bits              = 12,
  87                 .size_bits              = 12,
  88                 .get_from_field         = mv64x60_shift_left,
  89                 .map_to_field           = mv64x60_shift_right,
  90                 .extra                  = 0 },
  91         [MV64x60_CPU2DEV_2_WIN] = {
  92                 .base_reg               = MV64x60_CPU2DEV_2_BASE,
  93                 .size_reg               = MV64x60_CPU2DEV_2_SIZE,
  94                 .base_bits              = 12,
  95                 .size_bits              = 12,
  96                 .get_from_field         = mv64x60_shift_left,
  97                 .map_to_field           = mv64x60_shift_right,
  98                 .extra                  = 0 },
  99         [MV64x60_CPU2DEV_3_WIN] = {
 100                 .base_reg               = MV64x60_CPU2DEV_3_BASE,
 101                 .size_reg               = MV64x60_CPU2DEV_3_SIZE,
 102                 .base_bits              = 12,
 103                 .size_bits              = 12,
 104                 .get_from_field         = mv64x60_shift_left,
 105                 .map_to_field           = mv64x60_shift_right,
 106                 .extra                  = 0 },
 107         /* CPU->Boot Window */
 108         [MV64x60_CPU2BOOT_WIN] = {
 109                 .base_reg               = MV64x60_CPU2BOOT_0_BASE,
 110                 .size_reg               = MV64x60_CPU2BOOT_0_SIZE,
 111                 .base_bits              = 12,
 112                 .size_bits              = 12,
 113                 .get_from_field         = mv64x60_shift_left,
 114                 .map_to_field           = mv64x60_shift_right,
 115                 .extra                  = 0 },
 116         /* CPU->PCI 0 Windows */
 117         [MV64x60_CPU2PCI0_IO_WIN] = {
 118                 .base_reg               = MV64x60_CPU2PCI0_IO_BASE,
 119                 .size_reg               = MV64x60_CPU2PCI0_IO_SIZE,
 120                 .base_bits              = 12,
 121                 .size_bits              = 12,
 122                 .get_from_field         = mv64x60_shift_left,
 123                 .map_to_field           = mv64x60_shift_right,
 124                 .extra                  = 0 },
 125         [MV64x60_CPU2PCI0_MEM_0_WIN] = {
 126                 .base_reg               = MV64x60_CPU2PCI0_MEM_0_BASE,
 127                 .size_reg               = MV64x60_CPU2PCI0_MEM_0_SIZE,
 128                 .base_bits              = 12,
 129                 .size_bits              = 12,
 130                 .get_from_field         = mv64x60_shift_left,
 131                 .map_to_field           = mv64x60_shift_right,
 132                 .extra                  = 0 },
 133         [MV64x60_CPU2PCI0_MEM_1_WIN] = {
 134                 .base_reg               = MV64x60_CPU2PCI0_MEM_1_BASE,
 135                 .size_reg               = MV64x60_CPU2PCI0_MEM_1_SIZE,
 136                 .base_bits              = 12,
 137                 .size_bits              = 12,
 138                 .get_from_field         = mv64x60_shift_left,
 139                 .map_to_field           = mv64x60_shift_right,
 140                 .extra                  = 0 },
 141         [MV64x60_CPU2PCI0_MEM_2_WIN] = {
 142                 .base_reg               = MV64x60_CPU2PCI0_MEM_2_BASE,
 143                 .size_reg               = MV64x60_CPU2PCI0_MEM_2_SIZE,
 144                 .base_bits              = 12,
 145                 .size_bits              = 12,
 146                 .get_from_field         = mv64x60_shift_left,
 147                 .map_to_field           = mv64x60_shift_right,
 148                 .extra                  = 0 },
 149         [MV64x60_CPU2PCI0_MEM_3_WIN] = {
 150                 .base_reg               = MV64x60_CPU2PCI0_MEM_3_BASE,
 151                 .size_reg               = MV64x60_CPU2PCI0_MEM_3_SIZE,
 152                 .base_bits              = 12,
 153                 .size_bits              = 12,
 154                 .get_from_field         = mv64x60_shift_left,
 155                 .map_to_field           = mv64x60_shift_right,
 156                 .extra                  = 0 },
 157         /* CPU->PCI 1 Windows */
 158         [MV64x60_CPU2PCI1_IO_WIN] = {
 159                 .base_reg               = MV64x60_CPU2PCI1_IO_BASE,
 160                 .size_reg               = MV64x60_CPU2PCI1_IO_SIZE,
 161                 .base_bits              = 12,
 162                 .size_bits              = 12,
 163                 .get_from_field         = mv64x60_shift_left,
 164                 .map_to_field           = mv64x60_shift_right,
 165                 .extra                  = 0 },
 166         [MV64x60_CPU2PCI1_MEM_0_WIN] = {
 167                 .base_reg               = MV64x60_CPU2PCI1_MEM_0_BASE,
 168                 .size_reg               = MV64x60_CPU2PCI1_MEM_0_SIZE,
 169                 .base_bits              = 12,
 170                 .size_bits              = 12,
 171                 .get_from_field         = mv64x60_shift_left,
 172                 .map_to_field           = mv64x60_shift_right,
 173                 .extra                  = 0 },
 174         [MV64x60_CPU2PCI1_MEM_1_WIN] = {
 175                 .base_reg               = MV64x60_CPU2PCI1_MEM_1_BASE,
 176                 .size_reg               = MV64x60_CPU2PCI1_MEM_1_SIZE,
 177                 .base_bits              = 12,
 178                 .size_bits              = 12,
 179                 .get_from_field         = mv64x60_shift_left,
 180                 .map_to_field           = mv64x60_shift_right,
 181                 .extra                  = 0 },
 182         [MV64x60_CPU2PCI1_MEM_2_WIN] = {
 183                 .base_reg               = MV64x60_CPU2PCI1_MEM_2_BASE,
 184                 .size_reg               = MV64x60_CPU2PCI1_MEM_2_SIZE,
 185                 .base_bits              = 12,
 186                 .size_bits              = 12,
 187                 .get_from_field         = mv64x60_shift_left,
 188                 .map_to_field           = mv64x60_shift_right,
 189                 .extra                  = 0 },
 190         [MV64x60_CPU2PCI1_MEM_3_WIN] = {
 191                 .base_reg               = MV64x60_CPU2PCI1_MEM_3_BASE,
 192                 .size_reg               = MV64x60_CPU2PCI1_MEM_3_SIZE,
 193                 .base_bits              = 12,
 194                 .size_bits              = 12,
 195                 .get_from_field         = mv64x60_shift_left,
 196                 .map_to_field           = mv64x60_shift_right,
 197                 .extra                  = 0 },
 198         /* CPU->SRAM Window (64260 has no integrated SRAM) */
 199         /* CPU->PCI 0 Remap I/O Window */
 200         [MV64x60_CPU2PCI0_IO_REMAP_WIN] = {
 201                 .base_reg               = MV64x60_CPU2PCI0_IO_REMAP,
 202                 .size_reg               = 0,
 203                 .base_bits              = 12,
 204                 .size_bits              = 0,
 205                 .get_from_field         = mv64x60_shift_left,
 206                 .map_to_field           = mv64x60_shift_right,
 207                 .extra                  = 0 },
 208         /* CPU->PCI 1 Remap I/O Window */
 209         [MV64x60_CPU2PCI1_IO_REMAP_WIN] = {
 210                 .base_reg               = MV64x60_CPU2PCI1_IO_REMAP,
 211                 .size_reg               = 0,
 212                 .base_bits              = 12,
 213                 .size_bits              = 0,
 214                 .get_from_field         = mv64x60_shift_left,
 215                 .map_to_field           = mv64x60_shift_right,
 216                 .extra                  = 0 },
 217         /* CPU Memory Protection Windows */
 218         [MV64x60_CPU_PROT_0_WIN] = {
 219                 .base_reg               = MV64x60_CPU_PROT_BASE_0,
 220                 .size_reg               = MV64x60_CPU_PROT_SIZE_0,
 221                 .base_bits              = 12,
 222                 .size_bits              = 12,
 223                 .get_from_field         = mv64x60_shift_left,
 224                 .map_to_field           = mv64x60_shift_right,
 225                 .extra                  = 0 },
 226         [MV64x60_CPU_PROT_1_WIN] = {
 227                 .base_reg               = MV64x60_CPU_PROT_BASE_1,
 228                 .size_reg               = MV64x60_CPU_PROT_SIZE_1,
 229                 .base_bits              = 12,
 230                 .size_bits              = 12,
 231                 .get_from_field         = mv64x60_shift_left,
 232                 .map_to_field           = mv64x60_shift_right,
 233                 .extra                  = 0 },
 234         [MV64x60_CPU_PROT_2_WIN] = {
 235                 .base_reg               = MV64x60_CPU_PROT_BASE_2,
 236                 .size_reg               = MV64x60_CPU_PROT_SIZE_2,
 237                 .base_bits              = 12,
 238                 .size_bits              = 12,
 239                 .get_from_field         = mv64x60_shift_left,
 240                 .map_to_field           = mv64x60_shift_right,
 241                 .extra                  = 0 },
 242         [MV64x60_CPU_PROT_3_WIN] = {
 243                 .base_reg               = MV64x60_CPU_PROT_BASE_3,
 244                 .size_reg               = MV64x60_CPU_PROT_SIZE_3,
 245                 .base_bits              = 12,
 246                 .size_bits              = 12,
 247                 .get_from_field         = mv64x60_shift_left,
 248                 .map_to_field           = mv64x60_shift_right,
 249                 .extra                  = 0 },
 250         /* CPU Snoop Windows */
 251         [MV64x60_CPU_SNOOP_0_WIN] = {
 252                 .base_reg               = GT64260_CPU_SNOOP_BASE_0,
 253                 .size_reg               = GT64260_CPU_SNOOP_SIZE_0,
 254                 .base_bits              = 12,
 255                 .size_bits              = 12,
 256                 .get_from_field         = mv64x60_shift_left,
 257                 .map_to_field           = mv64x60_shift_right,
 258                 .extra                  = 0 },
 259         [MV64x60_CPU_SNOOP_1_WIN] = {
 260                 .base_reg               = GT64260_CPU_SNOOP_BASE_1,
 261                 .size_reg               = GT64260_CPU_SNOOP_SIZE_1,
 262                 .base_bits              = 12,
 263                 .size_bits              = 12,
 264                 .get_from_field         = mv64x60_shift_left,
 265                 .map_to_field           = mv64x60_shift_right,
 266                 .extra                  = 0 },
 267         [MV64x60_CPU_SNOOP_2_WIN] = {
 268                 .base_reg               = GT64260_CPU_SNOOP_BASE_2,
 269                 .size_reg               = GT64260_CPU_SNOOP_SIZE_2,
 270                 .base_bits              = 12,
 271                 .size_bits              = 12,
 272                 .get_from_field         = mv64x60_shift_left,
 273                 .map_to_field           = mv64x60_shift_right,
 274                 .extra                  = 0 },
 275         [MV64x60_CPU_SNOOP_3_WIN] = {
 276                 .base_reg               = GT64260_CPU_SNOOP_BASE_3,
 277                 .size_reg               = GT64260_CPU_SNOOP_SIZE_3,
 278                 .base_bits              = 12,
 279                 .size_bits              = 12,
 280                 .get_from_field         = mv64x60_shift_left,
 281                 .map_to_field           = mv64x60_shift_right,
 282                 .extra                  = 0 },
 283         /* PCI 0->System Memory Remap Windows */
 284         [MV64x60_PCI02MEM_REMAP_0_WIN] = {
 285                 .base_reg               = MV64x60_PCI0_SLAVE_MEM_0_REMAP,
 286                 .size_reg               = 0,
 287                 .base_bits              = 20,
 288                 .size_bits              = 0,
 289                 .get_from_field         = mv64x60_mask,
 290                 .map_to_field           = mv64x60_mask,
 291                 .extra                  = 0 },
 292         [MV64x60_PCI02MEM_REMAP_1_WIN] = {
 293                 .base_reg               = MV64x60_PCI0_SLAVE_MEM_1_REMAP,
 294                 .size_reg               = 0,
 295                 .base_bits              = 20,
 296                 .size_bits              = 0,
 297                 .get_from_field         = mv64x60_mask,
 298                 .map_to_field           = mv64x60_mask,
 299                 .extra                  = 0 },
 300         [MV64x60_PCI02MEM_REMAP_2_WIN] = {
 301                 .base_reg               = MV64x60_PCI0_SLAVE_MEM_1_REMAP,
 302                 .size_reg               = 0,
 303                 .base_bits              = 20,
 304                 .size_bits              = 0,
 305                 .get_from_field         = mv64x60_mask,
 306                 .map_to_field           = mv64x60_mask,
 307                 .extra                  = 0 },
 308         [MV64x60_PCI02MEM_REMAP_3_WIN] = {
 309                 .base_reg               = MV64x60_PCI0_SLAVE_MEM_1_REMAP,
 310                 .size_reg               = 0,
 311                 .base_bits              = 20,
 312                 .size_bits              = 0,
 313                 .get_from_field         = mv64x60_mask,
 314                 .map_to_field           = mv64x60_mask,
 315                 .extra                  = 0 },
 316         /* PCI 1->System Memory Remap Windows */
 317         [MV64x60_PCI12MEM_REMAP_0_WIN] = {
 318                 .base_reg               = MV64x60_PCI1_SLAVE_MEM_0_REMAP,
 319                 .size_reg               = 0,
 320                 .base_bits              = 20,
 321                 .size_bits              = 0,
 322                 .get_from_field         = mv64x60_mask,
 323                 .map_to_field           = mv64x60_mask,
 324                 .extra                  = 0 },
 325         [MV64x60_PCI12MEM_REMAP_1_WIN] = {
 326                 .base_reg               = MV64x60_PCI1_SLAVE_MEM_1_REMAP,
 327                 .size_reg               = 0,
 328                 .base_bits              = 20,
 329                 .size_bits              = 0,
 330                 .get_from_field         = mv64x60_mask,
 331                 .map_to_field           = mv64x60_mask,
 332                 .extra                  = 0 },
 333         [MV64x60_PCI12MEM_REMAP_2_WIN] = {
 334                 .base_reg               = MV64x60_PCI1_SLAVE_MEM_1_REMAP,
 335                 .size_reg               = 0,
 336                 .base_bits              = 20,
 337                 .size_bits              = 0,
 338                 .get_from_field         = mv64x60_mask,
 339                 .map_to_field           = mv64x60_mask,
 340                 .extra                  = 0 },
 341         [MV64x60_PCI12MEM_REMAP_3_WIN] = {
 342                 .base_reg               = MV64x60_PCI1_SLAVE_MEM_1_REMAP,
 343                 .size_reg               = 0,
 344                 .base_bits              = 20,
 345                 .size_bits              = 0,
 346                 .get_from_field         = mv64x60_mask,
 347                 .map_to_field           = mv64x60_mask,
 348                 .extra                  = 0 },
 349         /* ENET->SRAM Window (64260 doesn't have separate windows) */
 350         /* MPSC->SRAM Window (64260 doesn't have separate windows) */
 351         /* IDMA->SRAM Window (64260 doesn't have separate windows) */
 352 };
 353
 354 struct mv64x60_64bit_window
 355         gt64260_64bit_windows[MV64x60_64BIT_WIN_COUNT] __initdata = {
 356         /* CPU->PCI 0 MEM Remap Windows */
 357         [MV64x60_CPU2PCI0_MEM_0_REMAP_WIN] = {
 358                 .base_hi_reg            = MV64x60_CPU2PCI0_MEM_0_REMAP_HI,
 359                 .base_lo_reg            = MV64x60_CPU2PCI0_MEM_0_REMAP_LO,
 360                 .size_reg               = 0,
 361                 .base_lo_bits           = 12,
 362                 .size_bits              = 0,
 363                 .get_from_field         = mv64x60_shift_left,
 364                 .map_to_field           = mv64x60_shift_right,
 365                 .extra                  = 0 },
 366         [MV64x60_CPU2PCI0_MEM_1_REMAP_WIN] = {
 367                 .base_hi_reg            = MV64x60_CPU2PCI0_MEM_1_REMAP_HI,
 368                 .base_lo_reg            = MV64x60_CPU2PCI0_MEM_1_REMAP_LO,
 369                 .size_reg               = 0,
 370                 .base_lo_bits           = 12,
 371                 .size_bits              = 0,
 372                 .get_from_field         = mv64x60_shift_left,
 373                 .map_to_field           = mv64x60_shift_right,
 374                 .extra                  = 0 },
 375         [MV64x60_CPU2PCI0_MEM_2_REMAP_WIN] = {
 376                 .base_hi_reg            = MV64x60_CPU2PCI0_MEM_2_REMAP_HI,
 377                 .base_lo_reg            = MV64x60_CPU2PCI0_MEM_2_REMAP_LO,
 378                 .size_reg               = 0,
 379                 .base_lo_bits           = 12,
 380                 .size_bits              = 0,
 381                 .get_from_field         = mv64x60_shift_left,
 382                 .map_to_field           = mv64x60_shift_right,
 383                 .extra                  = 0 },
 384         [MV64x60_CPU2PCI0_MEM_3_REMAP_WIN] = {
 385                 .base_hi_reg            = MV64x60_CPU2PCI0_MEM_3_REMAP_HI,
 386                 .base_lo_reg            = MV64x60_CPU2PCI0_MEM_3_REMAP_LO,
 387                 .size_reg               = 0,
 388                 .base_lo_bits           = 12,
 389                 .size_bits              = 0,
 390                 .get_from_field         = mv64x60_shift_left,
 391                 .map_to_field           = mv64x60_shift_right,
 392                 .extra                  = 0 },
 393         /* CPU->PCI 1 MEM Remap Windows */
 394         [MV64x60_CPU2PCI1_MEM_0_REMAP_WIN] = {
 395                 .base_hi_reg            = MV64x60_CPU2PCI1_MEM_0_REMAP_HI,
 396                 .base_lo_reg            = MV64x60_CPU2PCI1_MEM_0_REMAP_LO,
 397                 .size_reg               = 0,
 398                 .base_lo_bits           = 12,
 399                 .size_bits              = 0,
 400                 .get_from_field         = mv64x60_shift_left,
 401                 .map_to_field           = mv64x60_shift_right,
 402                 .extra                  = 0 },
 403         [MV64x60_CPU2PCI1_MEM_1_REMAP_WIN] = {
 404                 .base_hi_reg            = MV64x60_CPU2PCI1_MEM_1_REMAP_HI,
 405                 .base_lo_reg            = MV64x60_CPU2PCI1_MEM_1_REMAP_LO,
 406                 .size_reg               = 0,
 407                 .base_lo_bits           = 12,
 408                 .size_bits              = 0,
 409                 .get_from_field         = mv64x60_shift_left,
 410                 .map_to_field           = mv64x60_shift_right,
 411                 .extra                  = 0 },
 412         [MV64x60_CPU2PCI1_MEM_2_REMAP_WIN] = {
 413                 .base_hi_reg            = MV64x60_CPU2PCI1_MEM_2_REMAP_HI,
 414                 .base_lo_reg            = MV64x60_CPU2PCI1_MEM_2_REMAP_LO,
 415                 .size_reg               = 0,
 416                 .base_lo_bits           = 12,
 417                 .size_bits              = 0,
 418                 .get_from_field         = mv64x60_shift_left,
 419                 .map_to_field           = mv64x60_shift_right,
 420                 .extra                  = 0 },
 421         [MV64x60_CPU2PCI1_MEM_3_REMAP_WIN] = {
 422                 .base_hi_reg            = MV64x60_CPU2PCI1_MEM_3_REMAP_HI,
 423                 .base_lo_reg            = MV64x60_CPU2PCI1_MEM_3_REMAP_LO,
 424                 .size_reg               = 0,
 425                 .base_lo_bits           = 12,
 426                 .size_bits              = 0,
 427                 .get_from_field         = mv64x60_shift_left,
 428                 .map_to_field           = mv64x60_shift_right,
 429                 .extra                  = 0 },
 430         /* PCI 0->MEM Access Control Windows */
 431         [MV64x60_PCI02MEM_ACC_CNTL_0_WIN] = {
 432                 .base_hi_reg            = MV64x60_PCI0_ACC_CNTL_0_BASE_HI,
 433                 .base_lo_reg            = MV64x60_PCI0_ACC_CNTL_0_BASE_LO,
 434                 .size_reg               = MV64x60_PCI0_ACC_CNTL_0_SIZE,
 435                 .base_lo_bits           = 12,
 436                 .size_bits              = 12,
 437                 .get_from_field         = mv64x60_shift_left,
 438                 .map_to_field           = mv64x60_shift_right,
 439                 .extra                  = 0 },
 440         [MV64x60_PCI02MEM_ACC_CNTL_1_WIN] = {
 441                 .base_hi_reg            = MV64x60_PCI0_ACC_CNTL_1_BASE_HI,
 442                 .base_lo_reg            = MV64x60_PCI0_ACC_CNTL_1_BASE_LO,
 443                 .size_reg               = MV64x60_PCI0_ACC_CNTL_1_SIZE,
 444                 .base_lo_bits           = 12,
 445                 .size_bits              = 12,
 446                 .get_from_field         = mv64x60_shift_left,
 447                 .map_to_field           = mv64x60_shift_right,
 448                 .extra                  = 0 },
 449         [MV64x60_PCI02MEM_ACC_CNTL_2_WIN] = {
 450                 .base_hi_reg            = MV64x60_PCI0_ACC_CNTL_2_BASE_HI,
 451                 .base_lo_reg            = MV64x60_PCI0_ACC_CNTL_2_BASE_LO,
 452                 .size_reg               = MV64x60_PCI0_ACC_CNTL_2_SIZE,
 453                 .base_lo_bits           = 12,
 454                 .size_bits              = 12,
 455                 .get_from_field         = mv64x60_shift_left,
 456                 .map_to_field           = mv64x60_shift_right,
 457                 .extra                  = 0 },
 458         [MV64x60_PCI02MEM_ACC_CNTL_3_WIN] = {
 459                 .base_hi_reg            = MV64x60_PCI0_ACC_CNTL_3_BASE_HI,
 460                 .base_lo_reg            = MV64x60_PCI0_ACC_CNTL_3_BASE_LO,
 461                 .size_reg               = MV64x60_PCI0_ACC_CNTL_3_SIZE,
 462                 .base_lo_bits           = 12,
 463                 .size_bits              = 12,
 464                 .get_from_field         = mv64x60_shift_left,
 465                 .map_to_field           = mv64x60_shift_right,
 466                 .extra                  = 0 },
 467         /* PCI 1->MEM Access Control Windows */
 468         [MV64x60_PCI12MEM_ACC_CNTL_0_WIN] = {
 469                 .base_hi_reg            = MV64x60_PCI1_ACC_CNTL_0_BASE_HI,
 470                 .base_lo_reg            = MV64x60_PCI1_ACC_CNTL_0_BASE_LO,
 471                 .size_reg               = MV64x60_PCI1_ACC_CNTL_0_SIZE,
 472                 .base_lo_bits           = 12,
 473                 .size_bits              = 12,
 474                 .get_from_field         = mv64x60_shift_left,
 475                 .map_to_field           = mv64x60_shift_right,
 476                 .extra                  = 0 },
 477         [MV64x60_PCI12MEM_ACC_CNTL_1_WIN] = {
 478                 .base_hi_reg            = MV64x60_PCI1_ACC_CNTL_1_BASE_HI,
 479                 .base_lo_reg            = MV64x60_PCI1_ACC_CNTL_1_BASE_LO,
 480                 .size_reg               = MV64x60_PCI1_ACC_CNTL_1_SIZE,
 481                 .base_lo_bits           = 12,
 482                 .size_bits              = 12,
 483                 .get_from_field         = mv64x60_shift_left,
 484                 .map_to_field           = mv64x60_shift_right,
 485                 .extra                  = 0 },
 486         [MV64x60_PCI12MEM_ACC_CNTL_2_WIN] = {
 487                 .base_hi_reg            = MV64x60_PCI1_ACC_CNTL_2_BASE_HI,
 488                 .base_lo_reg            = MV64x60_PCI1_ACC_CNTL_2_BASE_LO,
 489                 .size_reg               = MV64x60_PCI1_ACC_CNTL_2_SIZE,
 490                 .base_lo_bits           = 12,
 491                 .size_bits              = 12,
 492                 .get_from_field         = mv64x60_shift_left,
 493                 .map_to_field           = mv64x60_shift_right,
 494                 .extra                  = 0 },
 495         [MV64x60_PCI12MEM_ACC_CNTL_3_WIN] = {
 496                 .base_hi_reg            = MV64x60_PCI1_ACC_CNTL_3_BASE_HI,
 497                 .base_lo_reg            = MV64x60_PCI1_ACC_CNTL_3_BASE_LO,
 498                 .size_reg               = MV64x60_PCI1_ACC_CNTL_3_SIZE,
 499                 .base_lo_bits           = 12,
 500                 .size_bits              = 12,
 501                 .get_from_field         = mv64x60_shift_left,
 502                 .map_to_field           = mv64x60_shift_right,
 503                 .extra                  = 0 },
 504         /* PCI 0->MEM Snoop Windows */
 505         [MV64x60_PCI02MEM_SNOOP_0_WIN] = {
 506                 .base_hi_reg            = GT64260_PCI0_SNOOP_0_BASE_HI,
 507                 .base_lo_reg            = GT64260_PCI0_SNOOP_0_BASE_LO,
 508                 .size_reg               = GT64260_PCI0_SNOOP_0_SIZE,
 509                 .base_lo_bits           = 12,
 510                 .size_bits              = 12,
 511                 .get_from_field         = mv64x60_shift_left,
 512                 .map_to_field           = mv64x60_shift_right,
 513                 .extra                  = 0 },
 514         [MV64x60_PCI02MEM_SNOOP_1_WIN] = {
 515                 .base_hi_reg            = GT64260_PCI0_SNOOP_1_BASE_HI,
 516                 .base_lo_reg            = GT64260_PCI0_SNOOP_1_BASE_LO,
 517                 .size_reg               = GT64260_PCI0_SNOOP_1_SIZE,
 518                 .base_lo_bits           = 12,
 519                 .size_bits              = 12,
 520                 .get_from_field         = mv64x60_shift_left,
 521                 .map_to_field           = mv64x60_shift_right,
 522                 .extra                  = 0 },
 523         [MV64x60_PCI02MEM_SNOOP_2_WIN] = {
 524                 .base_hi_reg            = GT64260_PCI0_SNOOP_2_BASE_HI,
 525                 .base_lo_reg            = GT64260_PCI0_SNOOP_2_BASE_LO,
 526                 .size_reg               = GT64260_PCI0_SNOOP_2_SIZE,
 527                 .base_lo_bits           = 12,
 528                 .size_bits              = 12,
 529                 .get_from_field         = mv64x60_shift_left,
 530                 .map_to_field           = mv64x60_shift_right,
 531                 .extra                  = 0 },
 532         [MV64x60_PCI02MEM_SNOOP_3_WIN] = {
 533                 .base_hi_reg            = GT64260_PCI0_SNOOP_3_BASE_HI,
 534                 .base_lo_reg            = GT64260_PCI0_SNOOP_3_BASE_LO,
 535                 .size_reg               = GT64260_PCI0_SNOOP_3_SIZE,
 536                 .base_lo_bits           = 12,
 537                 .size_bits              = 12,
 538                 .get_from_field         = mv64x60_shift_left,
 539                 .map_to_field           = mv64x60_shift_right,
 540                 .extra                  = 0 },
 541         /* PCI 1->MEM Snoop Windows */
 542         [MV64x60_PCI12MEM_SNOOP_0_WIN] = {
 543                 .base_hi_reg            = GT64260_PCI1_SNOOP_0_BASE_HI,
 544                 .base_lo_reg            = GT64260_PCI1_SNOOP_0_BASE_LO,
 545                 .size_reg               = GT64260_PCI1_SNOOP_0_SIZE,
 546                 .base_lo_bits           = 12,
 547                 .size_bits              = 12,
 548                 .get_from_field         = mv64x60_shift_left,
 549                 .map_to_field           = mv64x60_shift_right,
 550                 .extra                  = 0 },
 551         [MV64x60_PCI12MEM_SNOOP_1_WIN] = {
 552                 .base_hi_reg            = GT64260_PCI1_SNOOP_1_BASE_HI,
 553                 .base_lo_reg            = GT64260_PCI1_SNOOP_1_BASE_LO,
 554                 .size_reg               = GT64260_PCI1_SNOOP_1_SIZE,
 555                 .base_lo_bits           = 12,
 556                 .size_bits              = 12,
 557                 .get_from_field         = mv64x60_shift_left,
 558                 .map_to_field           = mv64x60_shift_right,
 559                 .extra                  = 0 },
 560         [MV64x60_PCI12MEM_SNOOP_2_WIN] = {
 561                 .base_hi_reg            = GT64260_PCI1_SNOOP_2_BASE_HI,
 562                 .base_lo_reg            = GT64260_PCI1_SNOOP_2_BASE_LO,
 563                 .size_reg               = GT64260_PCI1_SNOOP_2_SIZE,
 564                 .base_lo_bits           = 12,
 565                 .size_bits              = 12,
 566                 .get_from_field         = mv64x60_shift_left,
 567                 .map_to_field           = mv64x60_shift_right,
 568                 .extra                  = 0 },
 569         [MV64x60_PCI12MEM_SNOOP_3_WIN] = {
 570                 .base_hi_reg            = GT64260_PCI1_SNOOP_3_BASE_HI,
 571                 .base_lo_reg            = GT64260_PCI1_SNOOP_3_BASE_LO,
 572                 .size_reg               = GT64260_PCI1_SNOOP_3_SIZE,
 573                 .base_lo_bits           = 12,
 574                 .size_bits              = 12,
 575                 .get_from_field         = mv64x60_shift_left,
 576                 .map_to_field           = mv64x60_shift_right,
 577                 .extra                  = 0 },
 578 };
 579
 580 struct mv64x60_32bit_window
 581         mv64360_32bit_windows[MV64x60_32BIT_WIN_COUNT] __initdata = {
 582         /* CPU->MEM Windows */
 583         [MV64x60_CPU2MEM_0_WIN] = {
 584                 .base_reg               = MV64x60_CPU2MEM_0_BASE,
 585                 .size_reg               = MV64x60_CPU2MEM_0_SIZE,
 586                 .base_bits              = 16,
 587                 .size_bits              = 16,
 588                 .get_from_field         = mv64x60_shift_left,
 589                 .map_to_field           = mv64x60_shift_right,
 590                 .extra                  = MV64x60_EXTRA_CPUWIN_ENAB | 0 },
 591         [MV64x60_CPU2MEM_1_WIN] = {
 592                 .base_reg               = MV64x60_CPU2MEM_1_BASE,
 593                 .size_reg               = MV64x60_CPU2MEM_1_SIZE,
 594                 .base_bits              = 16,
 595                 .size_bits              = 16,
 596                 .get_from_field         = mv64x60_shift_left,
 597                 .map_to_field           = mv64x60_shift_right,
 598                 .extra                  = MV64x60_EXTRA_CPUWIN_ENAB | 1 },
 599         [MV64x60_CPU2MEM_2_WIN] = {
 600                 .base_reg               = MV64x60_CPU2MEM_2_BASE,
 601                 .size_reg               = MV64x60_CPU2MEM_2_SIZE,
 602                 .base_bits              = 16,
 603                 .size_bits              = 16,
 604                 .get_from_field         = mv64x60_shift_left,
 605                 .map_to_field           = mv64x60_shift_right,
 606                 .extra                  = MV64x60_EXTRA_CPUWIN_ENAB | 2 },
 607         [MV64x60_CPU2MEM_3_WIN] = {
 608                 .base_reg               = MV64x60_CPU2MEM_3_BASE,
 609                 .size_reg               = MV64x60_CPU2MEM_3_SIZE,
 610                 .base_bits              = 16,
 611                 .size_bits              = 16,
 612                 .get_from_field         = mv64x60_shift_left,
 613                 .map_to_field           = mv64x60_shift_right,
 614                 .extra                  = MV64x60_EXTRA_CPUWIN_ENAB | 3 },
 615         /* CPU->Device Windows */
 616         [MV64x60_CPU2DEV_0_WIN] = {
 617                 .base_reg               = MV64x60_CPU2DEV_0_BASE,
 618                 .size_reg               = MV64x60_CPU2DEV_0_SIZE,
 619                 .base_bits              = 16,
 620                 .size_bits              = 16,
 621                 .get_from_field         = mv64x60_shift_left,
 622                 .map_to_field           = mv64x60_shift_right,
 623                 .extra                  = MV64x60_EXTRA_CPUWIN_ENAB | 4 },
 624         [MV64x60_CPU2DEV_1_WIN] = {
 625                 .base_reg               = MV64x60_CPU2DEV_1_BASE,
 626                 .size_reg               = MV64x60_CPU2DEV_1_SIZE,
 627                 .base_bits              = 16,
 628                 .size_bits              = 16,
 629                 .get_from_field         = mv64x60_shift_left,
 630                 .map_to_field           = mv64x60_shift_right,
 631                 .extra                  = MV64x60_EXTRA_CPUWIN_ENAB | 5 },
 632         [MV64x60_CPU2DEV_2_WIN] = {
 633                 .base_reg               = MV64x60_CPU2DEV_2_BASE,
 634                 .size_reg               = MV64x60_CPU2DEV_2_SIZE,
 635                 .base_bits              = 16,
 636                 .size_bits              = 16,
 637                 .get_from_field         = mv64x60_shift_left,
 638                 .map_to_field           = mv64x60_shift_right,
 639                 .extra                  = MV64x60_EXTRA_CPUWIN_ENAB | 6 },
 640         [MV64x60_CPU2DEV_3_WIN] = {
 641                 .base_reg               = MV64x60_CPU2DEV_3_BASE,
 642                 .size_reg               = MV64x60_CPU2DEV_3_SIZE,
 643                 .base_bits              = 16,
 644                 .size_bits              = 16,
 645                 .get_from_field         = mv64x60_shift_left,
 646                 .map_to_field           = mv64x60_shift_right,
 647                 .extra                  = MV64x60_EXTRA_CPUWIN_ENAB | 7 },
 648         /* CPU->Boot Window */
 649         [MV64x60_CPU2BOOT_WIN] = {
 650                 .base_reg               = MV64x60_CPU2BOOT_0_BASE,
 651                 .size_reg               = MV64x60_CPU2BOOT_0_SIZE,
 652                 .base_bits              = 16,
 653                 .size_bits              = 16,
 654                 .get_from_field         = mv64x60_shift_left,
 655                 .map_to_field           = mv64x60_shift_right,
 656                 .extra                  = MV64x60_EXTRA_CPUWIN_ENAB | 8 },
 657         /* CPU->PCI 0 Windows */
 658         [MV64x60_CPU2PCI0_IO_WIN] = {
 659                 .base_reg               = MV64x60_CPU2PCI0_IO_BASE,
 660                 .size_reg               = MV64x60_CPU2PCI0_IO_SIZE,
 661                 .base_bits              = 16,
 662                 .size_bits              = 16,
 663                 .get_from_field         = mv64x60_shift_left,
 664                 .map_to_field           = mv64x60_shift_right,
 665                 .extra                  = MV64x60_EXTRA_CPUWIN_ENAB | 9 },
 666         [MV64x60_CPU2PCI0_MEM_0_WIN] = {
 667                 .base_reg               = MV64x60_CPU2PCI0_MEM_0_BASE,
 668                 .size_reg               = MV64x60_CPU2PCI0_MEM_0_SIZE,
 669                 .base_bits              = 16,
 670                 .size_bits              = 16,
 671                 .get_from_field         = mv64x60_shift_left,
 672                 .map_to_field           = mv64x60_shift_right,
 673                 .extra                  = MV64x60_EXTRA_CPUWIN_ENAB | 10 },
 674         [MV64x60_CPU2PCI0_MEM_1_WIN] = {
 675                 .base_reg               = MV64x60_CPU2PCI0_MEM_1_BASE,
 676                 .size_reg               = MV64x60_CPU2PCI0_MEM_1_SIZE,
 677                 .base_bits              = 16,
 678                 .size_bits              = 16,
 679                 .get_from_field         = mv64x60_shift_left,
 680                 .map_to_field           = mv64x60_shift_right,
 681                 .extra                  = MV64x60_EXTRA_CPUWIN_ENAB | 11 },
 682         [MV64x60_CPU2PCI0_MEM_2_WIN] = {
 683                 .base_reg               = MV64x60_CPU2PCI0_MEM_2_BASE,
 684                 .size_reg               = MV64x60_CPU2PCI0_MEM_2_SIZE,
 685                 .base_bits              = 16,
 686                 .size_bits              = 16,
 687                 .get_from_field         = mv64x60_shift_left,
 688                 .map_to_field           = mv64x60_shift_right,
 689                 .extra                  = MV64x60_EXTRA_CPUWIN_ENAB | 12 },
 690         [MV64x60_CPU2PCI0_MEM_3_WIN] = {
 691                 .base_reg               = MV64x60_CPU2PCI0_MEM_3_BASE,
 692                 .size_reg               = MV64x60_CPU2PCI0_MEM_3_SIZE,
 693                 .base_bits              = 16,
 694                 .size_bits              = 16,
 695                 .get_from_field         = mv64x60_shift_left,
 696                 .map_to_field           = mv64x60_shift_right,
 697                 .extra                  = MV64x60_EXTRA_CPUWIN_ENAB | 13 },
 698         /* CPU->PCI 1 Windows */
 699         [MV64x60_CPU2PCI1_IO_WIN] = {
 700                 .base_reg               = MV64x60_CPU2PCI1_IO_BASE,
 701                 .size_reg               = MV64x60_CPU2PCI1_IO_SIZE,
 702                 .base_bits              = 16,
 703                 .size_bits              = 16,
 704                 .get_from_field         = mv64x60_shift_left,
 705                 .map_to_field           = mv64x60_shift_right,
 706                 .extra                  = MV64x60_EXTRA_CPUWIN_ENAB | 14 },
 707         [MV64x60_CPU2PCI1_MEM_0_WIN] = {
 708                 .base_reg               = MV64x60_CPU2PCI1_MEM_0_BASE,
 709                 .size_reg               = MV64x60_CPU2PCI1_MEM_0_SIZE,
 710                 .base_bits              = 16,
 711                 .size_bits              = 16,
 712                 .get_from_field         = mv64x60_shift_left,
 713                 .map_to_field           = mv64x60_shift_right,
 714                 .extra                  = MV64x60_EXTRA_CPUWIN_ENAB | 15 },
 715         [MV64x60_CPU2PCI1_MEM_1_WIN] = {
 716                 .base_reg               = MV64x60_CPU2PCI1_MEM_1_BASE,
 717                 .size_reg               = MV64x60_CPU2PCI1_MEM_1_SIZE,
 718                 .base_bits              = 16,
 719                 .size_bits              = 16,
 720                 .get_from_field         = mv64x60_shift_left,
 721                 .map_to_field           = mv64x60_shift_right,
 722                 .extra                  = MV64x60_EXTRA_CPUWIN_ENAB | 16 },
 723         [MV64x60_CPU2PCI1_MEM_2_WIN] = {
 724                 .base_reg               = MV64x60_CPU2PCI1_MEM_2_BASE,
 725                 .size_reg               = MV64x60_CPU2PCI1_MEM_2_SIZE,
 726                 .base_bits              = 16,
 727                 .size_bits              = 16,
 728                 .get_from_field         = mv64x60_shift_left,
 729                 .map_to_field           = mv64x60_shift_right,
 730                 .extra                  = MV64x60_EXTRA_CPUWIN_ENAB | 17 },
 731         [MV64x60_CPU2PCI1_MEM_3_WIN] = {
 732                 .base_reg               = MV64x60_CPU2PCI1_MEM_3_BASE,
 733                 .size_reg               = MV64x60_CPU2PCI1_MEM_3_SIZE,
 734                 .base_bits              = 16,
 735                 .size_bits              = 16,
 736                 .get_from_field         = mv64x60_shift_left,
 737                 .map_to_field           = mv64x60_shift_right,
 738                 .extra                  = MV64x60_EXTRA_CPUWIN_ENAB | 18 },
 739         /* CPU->SRAM Window */
 740         [MV64x60_CPU2SRAM_WIN] = {
 741                 .base_reg               = MV64360_CPU2SRAM_BASE,
 742                 .size_reg               = 0,
 743                 .base_bits              = 16,
 744                 .size_bits              = 0,
 745                 .get_from_field         = mv64x60_shift_left,
 746                 .map_to_field           = mv64x60_shift_right,
 747                 .extra                  = MV64x60_EXTRA_CPUWIN_ENAB | 19 },
 748         /* CPU->PCI 0 Remap I/O Window */
 749         [MV64x60_CPU2PCI0_IO_REMAP_WIN] = {
 750                 .base_reg               = MV64x60_CPU2PCI0_IO_REMAP,
 751                 .size_reg               = 0,
 752                 .base_bits              = 16,
 753                 .size_bits              = 0,
 754                 .get_from_field         = mv64x60_shift_left,
 755                 .map_to_field           = mv64x60_shift_right,
 756                 .extra                  = 0 },
 757         /* CPU->PCI 1 Remap I/O Window */
 758         [MV64x60_CPU2PCI1_IO_REMAP_WIN] = {
 759                 .base_reg               = MV64x60_CPU2PCI1_IO_REMAP,
 760                 .size_reg               = 0,
 761                 .base_bits              = 16,
 762                 .size_bits              = 0,
 763                 .get_from_field         = mv64x60_shift_left,
 764                 .map_to_field           = mv64x60_shift_right,
 765                 .extra                  = 0 },
 766         /* CPU Memory Protection Windows */
 767         [MV64x60_CPU_PROT_0_WIN] = {
 768                 .base_reg               = MV64x60_CPU_PROT_BASE_0,
 769                 .size_reg               = MV64x60_CPU_PROT_SIZE_0,
 770                 .base_bits              = 16,
 771                 .size_bits              = 16,
 772                 .get_from_field         = mv64x60_shift_left,
 773                 .map_to_field           = mv64x60_shift_right,
 774                 .extra                  = MV64x60_EXTRA_CPUPROT_ENAB | 31 },
 775         [MV64x60_CPU_PROT_1_WIN] = {
 776                 .base_reg               = MV64x60_CPU_PROT_BASE_1,
 777                 .size_reg               = MV64x60_CPU_PROT_SIZE_1,
 778                 .base_bits              = 16,
 779                 .size_bits              = 16,
 780                 .get_from_field         = mv64x60_shift_left,
 781                 .map_to_field           = mv64x60_shift_right,
 782                 .extra                  = MV64x60_EXTRA_CPUPROT_ENAB | 31 },
 783         [MV64x60_CPU_PROT_2_WIN] = {
 784                 .base_reg               = MV64x60_CPU_PROT_BASE_2,
 785                 .size_reg               = MV64x60_CPU_PROT_SIZE_2,
 786                 .base_bits              = 16,
 787                 .size_bits              = 16,
 788                 .get_from_field         = mv64x60_shift_left,
 789                 .map_to_field           = mv64x60_shift_right,
 790                 .extra                  = MV64x60_EXTRA_CPUPROT_ENAB | 31 },
 791         [MV64x60_CPU_PROT_3_WIN] = {
 792                 .base_reg               = MV64x60_CPU_PROT_BASE_3,
 793                 .size_reg               = MV64x60_CPU_PROT_SIZE_3,
 794                 .base_bits              = 16,
 795                 .size_bits              = 16,
 796                 .get_from_field         = mv64x60_shift_left,
 797                 .map_to_field           = mv64x60_shift_right,
 798                 .extra                  = MV64x60_EXTRA_CPUPROT_ENAB | 31 },
 799         /* CPU Snoop Windows -- don't exist on 64360 */
 800         /* PCI 0->System Memory Remap Windows */
 801         [MV64x60_PCI02MEM_REMAP_0_WIN] = {
 802                 .base_reg               = MV64x60_PCI0_SLAVE_MEM_0_REMAP,
 803                 .size_reg               = 0,
 804                 .base_bits              = 20,
 805                 .size_bits              = 0,
 806                 .get_from_field         = mv64x60_mask,
 807                 .map_to_field           = mv64x60_mask,
 808                 .extra                  = 0 },
 809         [MV64x60_PCI02MEM_REMAP_1_WIN] = {
 810                 .base_reg               = MV64x60_PCI0_SLAVE_MEM_1_REMAP,
 811                 .size_reg               = 0,
 812                 .base_bits              = 20,
 813                 .size_bits              = 0,
 814                 .get_from_field         = mv64x60_mask,
 815                 .map_to_field           = mv64x60_mask,
 816                 .extra                  = 0 },
 817         [MV64x60_PCI02MEM_REMAP_2_WIN] = {
 818                 .base_reg               = MV64x60_PCI0_SLAVE_MEM_1_REMAP,
 819                 .size_reg               = 0,
 820                 .base_bits              = 20,
 821                 .size_bits              = 0,
 822                 .get_from_field         = mv64x60_mask,
 823                 .map_to_field           = mv64x60_mask,
 824                 .extra                  = 0 },
 825         [MV64x60_PCI02MEM_REMAP_3_WIN] = {
 826                 .base_reg               = MV64x60_PCI0_SLAVE_MEM_1_REMAP,
 827                 .size_reg               = 0,
 828                 .base_bits              = 20,
 829                 .size_bits              = 0,
 830                 .get_from_field         = mv64x60_mask,
 831                 .map_to_field           = mv64x60_mask,
 832                 .extra                  = 0 },
 833         /* PCI 1->System Memory Remap Windows */
 834         [MV64x60_PCI12MEM_REMAP_0_WIN] = {
 835                 .base_reg               = MV64x60_PCI1_SLAVE_MEM_0_REMAP,
 836                 .size_reg               = 0,
 837                 .base_bits              = 20,
 838                 .size_bits              = 0,
 839                 .get_from_field         = mv64x60_mask,
 840                 .map_to_field           = mv64x60_mask,
 841                 .extra                  = 0 },
 842         [MV64x60_PCI12MEM_REMAP_1_WIN] = {
 843                 .base_reg               = MV64x60_PCI1_SLAVE_MEM_1_REMAP,
 844                 .size_reg               = 0,
 845                 .base_bits              = 20,
 846                 .size_bits              = 0,
 847                 .get_from_field         = mv64x60_mask,
 848                 .map_to_field           = mv64x60_mask,
 849                 .extra                  = 0 },
 850         [MV64x60_PCI12MEM_REMAP_2_WIN] = {
 851                 .base_reg               = MV64x60_PCI1_SLAVE_MEM_1_REMAP,
 852                 .size_reg               = 0,
 853                 .base_bits              = 20,
 854                 .size_bits              = 0,
 855                 .get_from_field         = mv64x60_mask,
 856                 .map_to_field           = mv64x60_mask,
 857                 .extra                  = 0 },
 858         [MV64x60_PCI12MEM_REMAP_3_WIN] = {
 859                 .base_reg               = MV64x60_PCI1_SLAVE_MEM_1_REMAP,
 860                 .size_reg               = 0,
 861                 .base_bits              = 20,
 862                 .size_bits              = 0,
 863                 .get_from_field         = mv64x60_mask,
 864                 .map_to_field           = mv64x60_mask,
 865                 .extra                  = 0 },
 866         /* ENET->System Memory Windows */
 867         [MV64x60_ENET2MEM_0_WIN] = {
 868                 .base_reg               = MV64360_ENET2MEM_0_BASE,
 869                 .size_reg               = MV64360_ENET2MEM_0_SIZE,
 870                 .base_bits              = 16,
 871                 .size_bits              = 16,
 872                 .get_from_field         = mv64x60_mask,
 873                 .map_to_field           = mv64x60_mask,
 874                 .extra                  = MV64x60_EXTRA_ENET_ENAB | 0 },
 875         [MV64x60_ENET2MEM_1_WIN] = {
 876                 .base_reg               = MV64360_ENET2MEM_1_BASE,
 877                 .size_reg               = MV64360_ENET2MEM_1_SIZE,
 878                 .base_bits              = 16,
 879                 .size_bits              = 16,
 880                 .get_from_field         = mv64x60_mask,
 881                 .map_to_field           = mv64x60_mask,
 882                 .extra                  = MV64x60_EXTRA_ENET_ENAB | 1 },
 883         [MV64x60_ENET2MEM_2_WIN] = {
 884                 .base_reg               = MV64360_ENET2MEM_2_BASE,
 885                 .size_reg               = MV64360_ENET2MEM_2_SIZE,
 886                 .base_bits              = 16,
 887                 .size_bits              = 16,
 888                 .get_from_field         = mv64x60_mask,
 889                 .map_to_field           = mv64x60_mask,
 890                 .extra                  = MV64x60_EXTRA_ENET_ENAB | 2 },
 891         [MV64x60_ENET2MEM_3_WIN] = {
 892                 .base_reg               = MV64360_ENET2MEM_3_BASE,
 893                 .size_reg               = MV64360_ENET2MEM_3_SIZE,
 894                 .base_bits              = 16,
 895                 .size_bits              = 16,
 896                 .get_from_field         = mv64x60_mask,
 897                 .map_to_field           = mv64x60_mask,
 898                 .extra                  = MV64x60_EXTRA_ENET_ENAB | 3 },
 899         [MV64x60_ENET2MEM_4_WIN] = {
 900                 .base_reg               = MV64360_ENET2MEM_4_BASE,
 901                 .size_reg               = MV64360_ENET2MEM_4_SIZE,
 902                 .base_bits              = 16,
 903                 .size_bits              = 16,
 904                 .get_from_field         = mv64x60_mask,
 905                 .map_to_field           = mv64x60_mask,
 906                 .extra                  = MV64x60_EXTRA_ENET_ENAB | 4 },
 907         [MV64x60_ENET2MEM_5_WIN] = {
 908                 .base_reg               = MV64360_ENET2MEM_5_BASE,
 909                 .size_reg               = MV64360_ENET2MEM_5_SIZE,
 910                 .base_bits              = 16,
 911                 .size_bits              = 16,
 912                 .get_from_field         = mv64x60_mask,
 913                 .map_to_field           = mv64x60_mask,
 914                 .extra                  = MV64x60_EXTRA_ENET_ENAB | 5 },
 915         /* MPSC->System Memory Windows */
 916         [MV64x60_MPSC2MEM_0_WIN] = {
 917                 .base_reg               = MV64360_MPSC2MEM_0_BASE,
 918                 .size_reg               = MV64360_MPSC2MEM_0_SIZE,
 919                 .base_bits              = 16,
 920                 .size_bits              = 16,
 921                 .get_from_field         = mv64x60_mask,
 922                 .map_to_field           = mv64x60_mask,
 923                 .extra                  = MV64x60_EXTRA_MPSC_ENAB | 0 },
 924         [MV64x60_MPSC2MEM_1_WIN] = {
 925                 .base_reg               = MV64360_MPSC2MEM_1_BASE,
 926                 .size_reg               = MV64360_MPSC2MEM_1_SIZE,
 927                 .base_bits              = 16,
 928                 .size_bits              = 16,
 929                 .get_from_field         = mv64x60_mask,
 930                 .map_to_field           = mv64x60_mask,
 931                 .extra                  = MV64x60_EXTRA_MPSC_ENAB | 1 },
 932         [MV64x60_MPSC2MEM_2_WIN] = {
 933                 .base_reg               = MV64360_MPSC2MEM_2_BASE,
 934                 .size_reg               = MV64360_MPSC2MEM_2_SIZE,
 935                 .base_bits              = 16,
 936                 .size_bits              = 16,
 937                 .get_from_field         = mv64x60_mask,
 938                 .map_to_field           = mv64x60_mask,
 939                 .extra                  = MV64x60_EXTRA_MPSC_ENAB | 2 },
 940         [MV64x60_MPSC2MEM_3_WIN] = {
 941                 .base_reg               = MV64360_MPSC2MEM_3_BASE,
 942                 .size_reg               = MV64360_MPSC2MEM_3_SIZE,
 943                 .base_bits              = 16,
 944                 .size_bits              = 16,
 945                 .get_from_field         = mv64x60_mask,
 946                 .map_to_field           = mv64x60_mask,
 947                 .extra                  = MV64x60_EXTRA_MPSC_ENAB | 3 },
 948         /* IDMA->System Memory Windows */
 949         [MV64x60_IDMA2MEM_0_WIN] = {
 950                 .base_reg               = MV64360_IDMA2MEM_0_BASE,
 951                 .size_reg               = MV64360_IDMA2MEM_0_SIZE,
 952                 .base_bits              = 16,
 953                 .size_bits              = 16,
 954                 .get_from_field         = mv64x60_mask,
 955                 .map_to_field           = mv64x60_mask,
 956                 .extra                  = MV64x60_EXTRA_IDMA_ENAB | 0 },
 957         [MV64x60_IDMA2MEM_1_WIN] = {
 958                 .base_reg               = MV64360_IDMA2MEM_1_BASE,
 959                 .size_reg               = MV64360_IDMA2MEM_1_SIZE,
 960                 .base_bits              = 16,
 961                 .size_bits              = 16,
 962                 .get_from_field         = mv64x60_mask,
 963                 .map_to_field           = mv64x60_mask,
 964                 .extra                  = MV64x60_EXTRA_IDMA_ENAB | 1 },
 965         [MV64x60_IDMA2MEM_2_WIN] = {
 966                 .base_reg               = MV64360_IDMA2MEM_2_BASE,
 967                 .size_reg               = MV64360_IDMA2MEM_2_SIZE,
 968                 .base_bits              = 16,
 969                 .size_bits              = 16,
 970                 .get_from_field         = mv64x60_mask,
 971                 .map_to_field           = mv64x60_mask,
 972                 .extra                  = MV64x60_EXTRA_IDMA_ENAB | 2 },
 973         [MV64x60_IDMA2MEM_3_WIN] = {
 974                 .base_reg               = MV64360_IDMA2MEM_3_BASE,
 975                 .size_reg               = MV64360_IDMA2MEM_3_SIZE,
 976                 .base_bits              = 16,
 977                 .size_bits              = 16,
 978                 .get_from_field         = mv64x60_mask,
 979                 .map_to_field           = mv64x60_mask,
 980                 .extra                  = MV64x60_EXTRA_IDMA_ENAB | 3 },
 981         [MV64x60_IDMA2MEM_4_WIN] = {
 982                 .base_reg               = MV64360_IDMA2MEM_4_BASE,
 983                 .size_reg               = MV64360_IDMA2MEM_4_SIZE,
 984                 .base_bits              = 16,
 985                 .size_bits              = 16,
 986                 .get_from_field         = mv64x60_mask,
 987                 .map_to_field           = mv64x60_mask,
 988                 .extra                  = MV64x60_EXTRA_IDMA_ENAB | 4 },
 989         [MV64x60_IDMA2MEM_5_WIN] = {
 990                 .base_reg               = MV64360_IDMA2MEM_5_BASE,
 991                 .size_reg               = MV64360_IDMA2MEM_5_SIZE,
 992                 .base_bits              = 16,
 993                 .size_bits              = 16,
 994                 .get_from_field         = mv64x60_mask,
 995                 .map_to_field           = mv64x60_mask,
 996                 .extra                  = MV64x60_EXTRA_IDMA_ENAB | 5 },
 997         [MV64x60_IDMA2MEM_6_WIN] = {
 998                 .base_reg               = MV64360_IDMA2MEM_6_BASE,
 999                 .size_reg               = MV64360_IDMA2MEM_6_SIZE,
1000                 .base_bits              = 16,
1001                 .size_bits              = 16,
1002                 .get_from_field         = mv64x60_mask,
1003                 .map_to_field           = mv64x60_mask,
1004                 .extra                  = MV64x60_EXTRA_IDMA_ENAB | 6 },
1005         [MV64x60_IDMA2MEM_7_WIN] = {
1006                 .base_reg               = MV64360_IDMA2MEM_7_BASE,
1007                 .size_reg               = MV64360_IDMA2MEM_7_SIZE,
1008                 .base_bits              = 16,
1009                 .size_bits              = 16,
1010                 .get_from_field         = mv64x60_mask,
1011                 .map_to_field           = mv64x60_mask,
1012                 .extra                  = MV64x60_EXTRA_IDMA_ENAB | 7 },
1013 };
1014
1015 struct mv64x60_64bit_window
1016         mv64360_64bit_windows[MV64x60_64BIT_WIN_COUNT] __initdata = {
1017         /* CPU->PCI 0 MEM Remap Windows */
1018         [MV64x60_CPU2PCI0_MEM_0_REMAP_WIN] = {
1019                 .base_hi_reg            = MV64x60_CPU2PCI0_MEM_0_REMAP_HI,
1020                 .base_lo_reg            = MV64x60_CPU2PCI0_MEM_0_REMAP_LO,
1021                 .size_reg               = 0,
1022                 .base_lo_bits           = 16,
1023                 .size_bits              = 0,
1024                 .get_from_field         = mv64x60_shift_left,
1025                 .map_to_field           = mv64x60_shift_right,
1026                 .extra                  = 0 },
1027         [MV64x60_CPU2PCI0_MEM_1_REMAP_WIN] = {
1028                 .base_hi_reg            = MV64x60_CPU2PCI0_MEM_1_REMAP_HI,
1029                 .base_lo_reg            = MV64x60_CPU2PCI0_MEM_1_REMAP_LO,
1030                 .size_reg               = 0,
1031                 .base_lo_bits           = 16,
1032                 .size_bits              = 0,
1033                 .get_from_field         = mv64x60_shift_left,
1034                 .map_to_field           = mv64x60_shift_right,
1035                 .extra                  = 0 },
1036         [MV64x60_CPU2PCI0_MEM_2_REMAP_WIN] = {
1037                 .base_hi_reg            = MV64x60_CPU2PCI0_MEM_2_REMAP_HI,
1038                 .base_lo_reg            = MV64x60_CPU2PCI0_MEM_2_REMAP_LO,
1039                 .size_reg               = 0,
1040                 .base_lo_bits           = 16,
1041                 .size_bits              = 0,
1042                 .get_from_field         = mv64x60_shift_left,
1043                 .map_to_field           = mv64x60_shift_right,
1044                 .extra                  = 0 },
1045         [MV64x60_CPU2PCI0_MEM_3_REMAP_WIN] = {
1046                 .base_hi_reg            = MV64x60_CPU2PCI0_MEM_3_REMAP_HI,
1047                 .base_lo_reg            = MV64x60_CPU2PCI0_MEM_3_REMAP_LO,
1048                 .size_reg               = 0,
1049                 .base_lo_bits           = 16,
1050                 .size_bits              = 0,
1051                 .get_from_field         = mv64x60_shift_left,
1052                 .map_to_field           = mv64x60_shift_right,
1053                 .extra                  = 0 },
1054         /* CPU->PCI 1 MEM Remap Windows */
1055         [MV64x60_CPU2PCI1_MEM_0_REMAP_WIN] = {
1056                 .base_hi_reg            = MV64x60_CPU2PCI1_MEM_0_REMAP_HI,
1057                 .base_lo_reg            = MV64x60_CPU2PCI1_MEM_0_REMAP_LO,
1058                 .size_reg               = 0,
1059                 .base_lo_bits           = 16,
1060                 .size_bits              = 0,
1061                 .get_from_field         = mv64x60_shift_left,
1062                 .map_to_field           = mv64x60_shift_right,
1063                 .extra                  = 0 },
1064         [MV64x60_CPU2PCI1_MEM_1_REMAP_WIN] = {
1065                 .base_hi_reg            = MV64x60_CPU2PCI1_MEM_1_REMAP_HI,
1066                 .base_lo_reg            = MV64x60_CPU2PCI1_MEM_1_REMAP_LO,
1067                 .size_reg               = 0,
1068                 .base_lo_bits           = 16,
1069                 .size_bits              = 0,
1070                 .get_from_field         = mv64x60_shift_left,
1071                 .map_to_field           = mv64x60_shift_right,
1072                 .extra                  = 0 },
1073         [MV64x60_CPU2PCI1_MEM_2_REMAP_WIN] = {
1074                 .base_hi_reg            = MV64x60_CPU2PCI1_MEM_2_REMAP_HI,
1075                 .base_lo_reg            = MV64x60_CPU2PCI1_MEM_2_REMAP_LO,
1076                 .size_reg               = 0,
1077                 .base_lo_bits           = 16,
1078                 .size_bits              = 0,
1079                 .get_from_field         = mv64x60_shift_left,
1080                 .map_to_field           = mv64x60_shift_right,
1081                 .extra                  = 0 },
1082         [MV64x60_CPU2PCI1_MEM_3_REMAP_WIN] = {
1083                 .base_hi_reg            = MV64x60_CPU2PCI1_MEM_3_REMAP_HI,
1084                 .base_lo_reg            = MV64x60_CPU2PCI1_MEM_3_REMAP_LO,
1085                 .size_reg               = 0,
1086                 .base_lo_bits           = 16,
1087                 .size_bits              = 0,
1088                 .get_from_field         = mv64x60_shift_left,
1089                 .map_to_field           = mv64x60_shift_right,
1090                 .extra                  = 0 },
1091         /* PCI 0->MEM Access Control Windows */
1092         [MV64x60_PCI02MEM_ACC_CNTL_0_WIN] = {
1093                 .base_hi_reg            = MV64x60_PCI0_ACC_CNTL_0_BASE_HI,
1094                 .base_lo_reg            = MV64x60_PCI0_ACC_CNTL_0_BASE_LO,
1095                 .size_reg               = MV64x60_PCI0_ACC_CNTL_0_SIZE,
1096                 .base_lo_bits           = 20,
1097                 .size_bits              = 20,
1098                 .get_from_field         = mv64x60_mask,
1099                 .map_to_field           = mv64x60_mask,
1100                 .extra                  = MV64x60_EXTRA_PCIACC_ENAB | 0 },
1101         [MV64x60_PCI02MEM_ACC_CNTL_1_WIN] = {
1102                 .base_hi_reg            = MV64x60_PCI0_ACC_CNTL_1_BASE_HI,
1103                 .base_lo_reg            = MV64x60_PCI0_ACC_CNTL_1_BASE_LO,
1104                 .size_reg               = MV64x60_PCI0_ACC_CNTL_1_SIZE,
1105                 .base_lo_bits           = 20,
1106                 .size_bits              = 20,
1107                 .get_from_field         = mv64x60_mask,
1108                 .map_to_field           = mv64x60_mask,
1109                 .extra                  = MV64x60_EXTRA_PCIACC_ENAB | 0 },
1110         [MV64x60_PCI02MEM_ACC_CNTL_2_WIN] = {
1111                 .base_hi_reg            = MV64x60_PCI0_ACC_CNTL_2_BASE_HI,
1112                 .base_lo_reg            = MV64x60_PCI0_ACC_CNTL_2_BASE_LO,
1113                 .size_reg               = MV64x60_PCI0_ACC_CNTL_2_SIZE,
1114                 .base_lo_bits           = 20,
1115                 .size_bits              = 20,
1116                 .get_from_field         = mv64x60_mask,
1117                 .map_to_field           = mv64x60_mask,
1118                 .extra                  = MV64x60_EXTRA_PCIACC_ENAB | 0 },
1119         [MV64x60_PCI02MEM_ACC_CNTL_3_WIN] = {
1120                 .base_hi_reg            = MV64x60_PCI0_ACC_CNTL_3_BASE_HI,
1121                 .base_lo_reg            = MV64x60_PCI0_ACC_CNTL_3_BASE_LO,
1122                 .size_reg               = MV64x60_PCI0_ACC_CNTL_3_SIZE,
1123                 .base_lo_bits           = 20,
1124                 .size_bits              = 20,
1125                 .get_from_field         = mv64x60_mask,
1126                 .map_to_field           = mv64x60_mask,
1127                 .extra                  = MV64x60_EXTRA_PCIACC_ENAB | 0 },
1128         /* PCI 1->MEM Access Control Windows */
1129         [MV64x60_PCI12MEM_ACC_CNTL_0_WIN] = {
1130                 .base_hi_reg            = MV64x60_PCI1_ACC_CNTL_0_BASE_HI,
1131                 .base_lo_reg            = MV64x60_PCI1_ACC_CNTL_0_BASE_LO,
1132                 .size_reg               = MV64x60_PCI1_ACC_CNTL_0_SIZE,
1133                 .base_lo_bits           = 20,
1134                 .size_bits              = 20,
1135                 .get_from_field         = mv64x60_mask,
1136                 .map_to_field           = mv64x60_mask,
1137                 .extra                  = MV64x60_EXTRA_PCIACC_ENAB | 0 },
1138         [MV64x60_PCI12MEM_ACC_CNTL_1_WIN] = {
1139                 .base_hi_reg            = MV64x60_PCI1_ACC_CNTL_1_BASE_HI,
1140                 .base_lo_reg            = MV64x60_PCI1_ACC_CNTL_1_BASE_LO,
1141                 .size_reg               = MV64x60_PCI1_ACC_CNTL_1_SIZE,
1142                 .base_lo_bits           = 20,
1143                 .size_bits              = 20,
1144                 .get_from_field         = mv64x60_mask,
1145                 .map_to_field           = mv64x60_mask,
1146                 .extra                  = MV64x60_EXTRA_PCIACC_ENAB | 0 },
1147         [MV64x60_PCI12MEM_ACC_CNTL_2_WIN] = {
1148                 .base_hi_reg            = MV64x60_PCI1_ACC_CNTL_2_BASE_HI,
1149                 .base_lo_reg            = MV64x60_PCI1_ACC_CNTL_2_BASE_LO,
1150                 .size_reg               = MV64x60_PCI1_ACC_CNTL_2_SIZE,
1151                 .base_lo_bits           = 20,
1152                 .size_bits              = 20,
1153                 .get_from_field         = mv64x60_mask,
1154                 .map_to_field           = mv64x60_mask,
1155                 .extra                  = MV64x60_EXTRA_PCIACC_ENAB | 0 },
1156         [MV64x60_PCI12MEM_ACC_CNTL_3_WIN] = {
1157                 .base_hi_reg            = MV64x60_PCI1_ACC_CNTL_3_BASE_HI,
1158                 .base_lo_reg            = MV64x60_PCI1_ACC_CNTL_3_BASE_LO,
1159                 .size_reg               = MV64x60_PCI1_ACC_CNTL_3_SIZE,
1160                 .base_lo_bits           = 20,
1161                 .size_bits              = 20,
1162                 .get_from_field         = mv64x60_mask,
1163                 .map_to_field           = mv64x60_mask,
1164                 .extra                  = MV64x60_EXTRA_PCIACC_ENAB | 0 },
1165         /* PCI 0->MEM Snoop Windows -- don't exist on 64360 */
1166         /* PCI 1->MEM Snoop Windows -- don't exist on 64360 */
1167 };