Merge branch 'pxa-plat' into devel
[linux-2.6] / arch / arm / mach-at91 / at91sam9rl_devices.c
1 /*
2  *  Copyright (C) 2007 Atmel Corporation
3  *
4  * This file is subject to the terms and conditions of the GNU General Public
5  * License.  See the file COPYING in the main directory of this archive for
6  * more details.
7  */
8
9 #include <asm/mach/arch.h>
10 #include <asm/mach/map.h>
11
12 #include <linux/dma-mapping.h>
13 #include <linux/platform_device.h>
14 #include <linux/i2c-gpio.h>
15
16 #include <linux/fb.h>
17 #include <video/atmel_lcdc.h>
18
19 #include <asm/arch/board.h>
20 #include <asm/arch/gpio.h>
21 #include <asm/arch/at91sam9rl.h>
22 #include <asm/arch/at91sam9rl_matrix.h>
23 #include <asm/arch/at91sam926x_mc.h>
24
25 #include "generic.h"
26
27
28 /* --------------------------------------------------------------------
29  *  MMC / SD
30  * -------------------------------------------------------------------- */
31
32 #if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
33 static u64 mmc_dmamask = DMA_BIT_MASK(32);
34 static struct at91_mmc_data mmc_data;
35
36 static struct resource mmc_resources[] = {
37         [0] = {
38                 .start  = AT91SAM9RL_BASE_MCI,
39                 .end    = AT91SAM9RL_BASE_MCI + SZ_16K - 1,
40                 .flags  = IORESOURCE_MEM,
41         },
42         [1] = {
43                 .start  = AT91SAM9RL_ID_MCI,
44                 .end    = AT91SAM9RL_ID_MCI,
45                 .flags  = IORESOURCE_IRQ,
46         },
47 };
48
49 static struct platform_device at91sam9rl_mmc_device = {
50         .name           = "at91_mci",
51         .id             = -1,
52         .dev            = {
53                                 .dma_mask               = &mmc_dmamask,
54                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
55                                 .platform_data          = &mmc_data,
56         },
57         .resource       = mmc_resources,
58         .num_resources  = ARRAY_SIZE(mmc_resources),
59 };
60
61 void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
62 {
63         if (!data)
64                 return;
65
66         /* input/irq */
67         if (data->det_pin) {
68                 at91_set_gpio_input(data->det_pin, 1);
69                 at91_set_deglitch(data->det_pin, 1);
70         }
71         if (data->wp_pin)
72                 at91_set_gpio_input(data->wp_pin, 1);
73         if (data->vcc_pin)
74                 at91_set_gpio_output(data->vcc_pin, 0);
75
76         /* CLK */
77         at91_set_A_periph(AT91_PIN_PA2, 0);
78
79         /* CMD */
80         at91_set_A_periph(AT91_PIN_PA1, 1);
81
82         /* DAT0, maybe DAT1..DAT3 */
83         at91_set_A_periph(AT91_PIN_PA0, 1);
84         if (data->wire4) {
85                 at91_set_A_periph(AT91_PIN_PA3, 1);
86                 at91_set_A_periph(AT91_PIN_PA4, 1);
87                 at91_set_A_periph(AT91_PIN_PA5, 1);
88         }
89
90         mmc_data = *data;
91         platform_device_register(&at91sam9rl_mmc_device);
92 }
93 #else
94 void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
95 #endif
96
97
98 /* --------------------------------------------------------------------
99  *  NAND / SmartMedia
100  * -------------------------------------------------------------------- */
101
102 #if defined(CONFIG_MTD_NAND_AT91) || defined(CONFIG_MTD_NAND_AT91_MODULE)
103 static struct at91_nand_data nand_data;
104
105 #define NAND_BASE       AT91_CHIPSELECT_3
106
107 static struct resource nand_resources[] = {
108         {
109                 .start  = NAND_BASE,
110                 .end    = NAND_BASE + SZ_256M - 1,
111                 .flags  = IORESOURCE_MEM,
112         }
113 };
114
115 static struct platform_device at91_nand_device = {
116         .name           = "at91_nand",
117         .id             = -1,
118         .dev            = {
119                                 .platform_data  = &nand_data,
120         },
121         .resource       = nand_resources,
122         .num_resources  = ARRAY_SIZE(nand_resources),
123 };
124
125 void __init at91_add_device_nand(struct at91_nand_data *data)
126 {
127         unsigned long csa;
128
129         if (!data)
130                 return;
131
132         csa = at91_sys_read(AT91_MATRIX_EBICSA);
133         at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
134
135         /* set the bus interface characteristics */
136         at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0)
137                         | AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
138
139         at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(2) | AT91_SMC_NCS_WRPULSE_(5)
140                         | AT91_SMC_NRDPULSE_(2) | AT91_SMC_NCS_RDPULSE_(5));
141
142         at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(7));
143
144         at91_sys_write(AT91_SMC_MODE(3), AT91_SMC_DBW_8 | AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_TDF_(1));
145
146         /* enable pin */
147         if (data->enable_pin)
148                 at91_set_gpio_output(data->enable_pin, 1);
149
150         /* ready/busy pin */
151         if (data->rdy_pin)
152                 at91_set_gpio_input(data->rdy_pin, 1);
153
154         /* card detect pin */
155         if (data->det_pin)
156                 at91_set_gpio_input(data->det_pin, 1);
157
158         at91_set_A_periph(AT91_PIN_PB4, 0);             /* NANDOE */
159         at91_set_A_periph(AT91_PIN_PB5, 0);             /* NANDWE */
160
161         nand_data = *data;
162         platform_device_register(&at91_nand_device);
163 }
164
165 #else
166 void __init at91_add_device_nand(struct at91_nand_data *data) {}
167 #endif
168
169
170 /* --------------------------------------------------------------------
171  *  TWI (i2c)
172  * -------------------------------------------------------------------- */
173
174 /*
175  * Prefer the GPIO code since the TWI controller isn't robust
176  * (gets overruns and underruns under load) and can only issue
177  * repeated STARTs in one scenario (the driver doesn't yet handle them).
178  */
179 #if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
180
181 static struct i2c_gpio_platform_data pdata = {
182         .sda_pin                = AT91_PIN_PA23,
183         .sda_is_open_drain      = 1,
184         .scl_pin                = AT91_PIN_PA24,
185         .scl_is_open_drain      = 1,
186         .udelay                 = 2,            /* ~100 kHz */
187 };
188
189 static struct platform_device at91sam9rl_twi_device = {
190         .name                   = "i2c-gpio",
191         .id                     = -1,
192         .dev.platform_data      = &pdata,
193 };
194
195 void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
196 {
197         at91_set_GPIO_periph(AT91_PIN_PA23, 1);         /* TWD (SDA) */
198         at91_set_multi_drive(AT91_PIN_PA23, 1);
199
200         at91_set_GPIO_periph(AT91_PIN_PA24, 1);         /* TWCK (SCL) */
201         at91_set_multi_drive(AT91_PIN_PA24, 1);
202
203         i2c_register_board_info(0, devices, nr_devices);
204         platform_device_register(&at91sam9rl_twi_device);
205 }
206
207 #elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
208
209 static struct resource twi_resources[] = {
210         [0] = {
211                 .start  = AT91SAM9RL_BASE_TWI0,
212                 .end    = AT91SAM9RL_BASE_TWI0 + SZ_16K - 1,
213                 .flags  = IORESOURCE_MEM,
214         },
215         [1] = {
216                 .start  = AT91SAM9RL_ID_TWI0,
217                 .end    = AT91SAM9RL_ID_TWI0,
218                 .flags  = IORESOURCE_IRQ,
219         },
220 };
221
222 static struct platform_device at91sam9rl_twi_device = {
223         .name           = "at91_i2c",
224         .id             = -1,
225         .resource       = twi_resources,
226         .num_resources  = ARRAY_SIZE(twi_resources),
227 };
228
229 void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
230 {
231         /* pins used for TWI interface */
232         at91_set_A_periph(AT91_PIN_PA23, 0);            /* TWD */
233         at91_set_multi_drive(AT91_PIN_PA23, 1);
234
235         at91_set_A_periph(AT91_PIN_PA24, 0);            /* TWCK */
236         at91_set_multi_drive(AT91_PIN_PA24, 1);
237
238         i2c_register_board_info(0, devices, nr_devices);
239         platform_device_register(&at91sam9rl_twi_device);
240 }
241 #else
242 void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) {}
243 #endif
244
245
246 /* --------------------------------------------------------------------
247  *  SPI
248  * -------------------------------------------------------------------- */
249
250 #if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
251 static u64 spi_dmamask = DMA_BIT_MASK(32);
252
253 static struct resource spi_resources[] = {
254         [0] = {
255                 .start  = AT91SAM9RL_BASE_SPI,
256                 .end    = AT91SAM9RL_BASE_SPI + SZ_16K - 1,
257                 .flags  = IORESOURCE_MEM,
258         },
259         [1] = {
260                 .start  = AT91SAM9RL_ID_SPI,
261                 .end    = AT91SAM9RL_ID_SPI,
262                 .flags  = IORESOURCE_IRQ,
263         },
264 };
265
266 static struct platform_device at91sam9rl_spi_device = {
267         .name           = "atmel_spi",
268         .id             = 0,
269         .dev            = {
270                                 .dma_mask               = &spi_dmamask,
271                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
272         },
273         .resource       = spi_resources,
274         .num_resources  = ARRAY_SIZE(spi_resources),
275 };
276
277 static const unsigned spi_standard_cs[4] = { AT91_PIN_PA28, AT91_PIN_PB7, AT91_PIN_PD8, AT91_PIN_PD9 };
278
279
280 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
281 {
282         int i;
283         unsigned long cs_pin;
284
285         at91_set_A_periph(AT91_PIN_PA25, 0);    /* MISO */
286         at91_set_A_periph(AT91_PIN_PA26, 0);    /* MOSI */
287         at91_set_A_periph(AT91_PIN_PA27, 0);    /* SPCK */
288
289         /* Enable SPI chip-selects */
290         for (i = 0; i < nr_devices; i++) {
291                 if (devices[i].controller_data)
292                         cs_pin = (unsigned long) devices[i].controller_data;
293                 else
294                         cs_pin = spi_standard_cs[devices[i].chip_select];
295
296                 /* enable chip-select pin */
297                 at91_set_gpio_output(cs_pin, 1);
298
299                 /* pass chip-select pin to driver */
300                 devices[i].controller_data = (void *) cs_pin;
301         }
302
303         spi_register_board_info(devices, nr_devices);
304         platform_device_register(&at91sam9rl_spi_device);
305 }
306 #else
307 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
308 #endif
309
310
311 /* --------------------------------------------------------------------
312  *  LCD Controller
313  * -------------------------------------------------------------------- */
314
315 #if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
316 static u64 lcdc_dmamask = DMA_BIT_MASK(32);
317 static struct atmel_lcdfb_info lcdc_data;
318
319 static struct resource lcdc_resources[] = {
320         [0] = {
321                 .start  = AT91SAM9RL_LCDC_BASE,
322                 .end    = AT91SAM9RL_LCDC_BASE + SZ_4K - 1,
323                 .flags  = IORESOURCE_MEM,
324         },
325         [1] = {
326                 .start  = AT91SAM9RL_ID_LCDC,
327                 .end    = AT91SAM9RL_ID_LCDC,
328                 .flags  = IORESOURCE_IRQ,
329         },
330 #if defined(CONFIG_FB_INTSRAM)
331         [2] = {
332                 .start  = AT91SAM9RL_SRAM_BASE,
333                 .end    = AT91SAM9RL_SRAM_BASE + AT91SAM9RL_SRAM_SIZE - 1,
334                 .flags  = IORESOURCE_MEM,
335         },
336 #endif
337 };
338
339 static struct platform_device at91_lcdc_device = {
340         .name           = "atmel_lcdfb",
341         .id             = 0,
342         .dev            = {
343                                 .dma_mask               = &lcdc_dmamask,
344                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
345                                 .platform_data          = &lcdc_data,
346         },
347         .resource       = lcdc_resources,
348         .num_resources  = ARRAY_SIZE(lcdc_resources),
349 };
350
351 void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
352 {
353         if (!data) {
354                 return;
355         }
356
357         at91_set_B_periph(AT91_PIN_PC1, 0);     /* LCDPWR */
358         at91_set_A_periph(AT91_PIN_PC5, 0);     /* LCDHSYNC */
359         at91_set_A_periph(AT91_PIN_PC6, 0);     /* LCDDOTCK */
360         at91_set_A_periph(AT91_PIN_PC7, 0);     /* LCDDEN */
361         at91_set_A_periph(AT91_PIN_PC3, 0);     /* LCDCC */
362         at91_set_B_periph(AT91_PIN_PC9, 0);     /* LCDD3 */
363         at91_set_B_periph(AT91_PIN_PC10, 0);    /* LCDD4 */
364         at91_set_B_periph(AT91_PIN_PC11, 0);    /* LCDD5 */
365         at91_set_B_periph(AT91_PIN_PC12, 0);    /* LCDD6 */
366         at91_set_B_periph(AT91_PIN_PC13, 0);    /* LCDD7 */
367         at91_set_B_periph(AT91_PIN_PC15, 0);    /* LCDD11 */
368         at91_set_B_periph(AT91_PIN_PC16, 0);    /* LCDD12 */
369         at91_set_B_periph(AT91_PIN_PC17, 0);    /* LCDD13 */
370         at91_set_B_periph(AT91_PIN_PC18, 0);    /* LCDD14 */
371         at91_set_B_periph(AT91_PIN_PC19, 0);    /* LCDD15 */
372         at91_set_B_periph(AT91_PIN_PC20, 0);    /* LCDD18 */
373         at91_set_B_periph(AT91_PIN_PC21, 0);    /* LCDD19 */
374         at91_set_B_periph(AT91_PIN_PC22, 0);    /* LCDD20 */
375         at91_set_B_periph(AT91_PIN_PC23, 0);    /* LCDD21 */
376         at91_set_B_periph(AT91_PIN_PC24, 0);    /* LCDD22 */
377         at91_set_B_periph(AT91_PIN_PC25, 0);    /* LCDD23 */
378
379         lcdc_data = *data;
380         platform_device_register(&at91_lcdc_device);
381 }
382 #else
383 void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
384 #endif
385
386
387 /* --------------------------------------------------------------------
388  *  RTC
389  * -------------------------------------------------------------------- */
390
391 #if defined(CONFIG_RTC_DRV_AT91RM9200) || defined(CONFIG_RTC_DRV_AT91RM9200_MODULE)
392 static struct platform_device at91sam9rl_rtc_device = {
393         .name           = "at91_rtc",
394         .id             = -1,
395         .num_resources  = 0,
396 };
397
398 static void __init at91_add_device_rtc(void)
399 {
400         platform_device_register(&at91sam9rl_rtc_device);
401 }
402 #else
403 static void __init at91_add_device_rtc(void) {}
404 #endif
405
406
407 /* --------------------------------------------------------------------
408  *  RTT
409  * -------------------------------------------------------------------- */
410
411 static struct resource rtt_resources[] = {
412         {
413                 .start  = AT91_BASE_SYS + AT91_RTT,
414                 .end    = AT91_BASE_SYS + AT91_RTT + SZ_16 - 1,
415                 .flags  = IORESOURCE_MEM,
416         }
417 };
418
419 static struct platform_device at91sam9rl_rtt_device = {
420         .name           = "at91_rtt",
421         .id             = -1,
422         .resource       = rtt_resources,
423         .num_resources  = ARRAY_SIZE(rtt_resources),
424 };
425
426 static void __init at91_add_device_rtt(void)
427 {
428         platform_device_register(&at91sam9rl_rtt_device);
429 }
430
431
432 /* --------------------------------------------------------------------
433  *  Watchdog
434  * -------------------------------------------------------------------- */
435
436 #if defined(CONFIG_AT91SAM9_WATCHDOG) || defined(CONFIG_AT91SAM9_WATCHDOG_MODULE)
437 static struct platform_device at91sam9rl_wdt_device = {
438         .name           = "at91_wdt",
439         .id             = -1,
440         .num_resources  = 0,
441 };
442
443 static void __init at91_add_device_watchdog(void)
444 {
445         platform_device_register(&at91sam9rl_wdt_device);
446 }
447 #else
448 static void __init at91_add_device_watchdog(void) {}
449 #endif
450
451
452 /* --------------------------------------------------------------------
453  *  SSC -- Synchronous Serial Controller
454  * -------------------------------------------------------------------- */
455
456 #if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
457 static u64 ssc0_dmamask = DMA_BIT_MASK(32);
458
459 static struct resource ssc0_resources[] = {
460         [0] = {
461                 .start  = AT91SAM9RL_BASE_SSC0,
462                 .end    = AT91SAM9RL_BASE_SSC0 + SZ_16K - 1,
463                 .flags  = IORESOURCE_MEM,
464         },
465         [1] = {
466                 .start  = AT91SAM9RL_ID_SSC0,
467                 .end    = AT91SAM9RL_ID_SSC0,
468                 .flags  = IORESOURCE_IRQ,
469         },
470 };
471
472 static struct platform_device at91sam9rl_ssc0_device = {
473         .name   = "ssc",
474         .id     = 0,
475         .dev    = {
476                 .dma_mask               = &ssc0_dmamask,
477                 .coherent_dma_mask      = DMA_BIT_MASK(32),
478         },
479         .resource       = ssc0_resources,
480         .num_resources  = ARRAY_SIZE(ssc0_resources),
481 };
482
483 static inline void configure_ssc0_pins(unsigned pins)
484 {
485         if (pins & ATMEL_SSC_TF)
486                 at91_set_A_periph(AT91_PIN_PC0, 1);
487         if (pins & ATMEL_SSC_TK)
488                 at91_set_A_periph(AT91_PIN_PC1, 1);
489         if (pins & ATMEL_SSC_TD)
490                 at91_set_A_periph(AT91_PIN_PA15, 1);
491         if (pins & ATMEL_SSC_RD)
492                 at91_set_A_periph(AT91_PIN_PA16, 1);
493         if (pins & ATMEL_SSC_RK)
494                 at91_set_B_periph(AT91_PIN_PA10, 1);
495         if (pins & ATMEL_SSC_RF)
496                 at91_set_B_periph(AT91_PIN_PA22, 1);
497 }
498
499 static u64 ssc1_dmamask = DMA_BIT_MASK(32);
500
501 static struct resource ssc1_resources[] = {
502         [0] = {
503                 .start  = AT91SAM9RL_BASE_SSC1,
504                 .end    = AT91SAM9RL_BASE_SSC1 + SZ_16K - 1,
505                 .flags  = IORESOURCE_MEM,
506         },
507         [1] = {
508                 .start  = AT91SAM9RL_ID_SSC1,
509                 .end    = AT91SAM9RL_ID_SSC1,
510                 .flags  = IORESOURCE_IRQ,
511         },
512 };
513
514 static struct platform_device at91sam9rl_ssc1_device = {
515         .name   = "ssc",
516         .id     = 1,
517         .dev    = {
518                 .dma_mask               = &ssc1_dmamask,
519                 .coherent_dma_mask      = DMA_BIT_MASK(32),
520         },
521         .resource       = ssc1_resources,
522         .num_resources  = ARRAY_SIZE(ssc1_resources),
523 };
524
525 static inline void configure_ssc1_pins(unsigned pins)
526 {
527         if (pins & ATMEL_SSC_TF)
528                 at91_set_B_periph(AT91_PIN_PA29, 1);
529         if (pins & ATMEL_SSC_TK)
530                 at91_set_B_periph(AT91_PIN_PA30, 1);
531         if (pins & ATMEL_SSC_TD)
532                 at91_set_B_periph(AT91_PIN_PA13, 1);
533         if (pins & ATMEL_SSC_RD)
534                 at91_set_B_periph(AT91_PIN_PA14, 1);
535         if (pins & ATMEL_SSC_RK)
536                 at91_set_B_periph(AT91_PIN_PA9, 1);
537         if (pins & ATMEL_SSC_RF)
538                 at91_set_B_periph(AT91_PIN_PA8, 1);
539 }
540
541 /*
542  * Return the device node so that board init code can use it as the
543  * parent for the device node reflecting how it's used on this board.
544  *
545  * SSC controllers are accessed through library code, instead of any
546  * kind of all-singing/all-dancing driver.  For example one could be
547  * used by a particular I2S audio codec's driver, while another one
548  * on the same system might be used by a custom data capture driver.
549  */
550 void __init at91_add_device_ssc(unsigned id, unsigned pins)
551 {
552         struct platform_device *pdev;
553
554         /*
555          * NOTE: caller is responsible for passing information matching
556          * "pins" to whatever will be using each particular controller.
557          */
558         switch (id) {
559         case AT91SAM9RL_ID_SSC0:
560                 pdev = &at91sam9rl_ssc0_device;
561                 configure_ssc0_pins(pins);
562                 at91_clock_associate("ssc0_clk", &pdev->dev, "pclk");
563                 break;
564         case AT91SAM9RL_ID_SSC1:
565                 pdev = &at91sam9rl_ssc1_device;
566                 configure_ssc1_pins(pins);
567                 at91_clock_associate("ssc1_clk", &pdev->dev, "pclk");
568                 break;
569         default:
570                 return;
571         }
572
573         platform_device_register(pdev);
574 }
575
576 #else
577 void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
578 #endif
579
580
581 /* --------------------------------------------------------------------
582  *  UART
583  * -------------------------------------------------------------------- */
584
585 #if defined(CONFIG_SERIAL_ATMEL)
586 static struct resource dbgu_resources[] = {
587         [0] = {
588                 .start  = AT91_VA_BASE_SYS + AT91_DBGU,
589                 .end    = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1,
590                 .flags  = IORESOURCE_MEM,
591         },
592         [1] = {
593                 .start  = AT91_ID_SYS,
594                 .end    = AT91_ID_SYS,
595                 .flags  = IORESOURCE_IRQ,
596         },
597 };
598
599 static struct atmel_uart_data dbgu_data = {
600         .use_dma_tx     = 0,
601         .use_dma_rx     = 0,            /* DBGU not capable of receive DMA */
602         .regs           = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU),
603 };
604
605 static u64 dbgu_dmamask = DMA_BIT_MASK(32);
606
607 static struct platform_device at91sam9rl_dbgu_device = {
608         .name           = "atmel_usart",
609         .id             = 0,
610         .dev            = {
611                                 .dma_mask               = &dbgu_dmamask,
612                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
613                                 .platform_data          = &dbgu_data,
614         },
615         .resource       = dbgu_resources,
616         .num_resources  = ARRAY_SIZE(dbgu_resources),
617 };
618
619 static inline void configure_dbgu_pins(void)
620 {
621         at91_set_A_periph(AT91_PIN_PA21, 0);            /* DRXD */
622         at91_set_A_periph(AT91_PIN_PA22, 1);            /* DTXD */
623 }
624
625 static struct resource uart0_resources[] = {
626         [0] = {
627                 .start  = AT91SAM9RL_BASE_US0,
628                 .end    = AT91SAM9RL_BASE_US0 + SZ_16K - 1,
629                 .flags  = IORESOURCE_MEM,
630         },
631         [1] = {
632                 .start  = AT91SAM9RL_ID_US0,
633                 .end    = AT91SAM9RL_ID_US0,
634                 .flags  = IORESOURCE_IRQ,
635         },
636 };
637
638 static struct atmel_uart_data uart0_data = {
639         .use_dma_tx     = 1,
640         .use_dma_rx     = 1,
641 };
642
643 static u64 uart0_dmamask = DMA_BIT_MASK(32);
644
645 static struct platform_device at91sam9rl_uart0_device = {
646         .name           = "atmel_usart",
647         .id             = 1,
648         .dev            = {
649                                 .dma_mask               = &uart0_dmamask,
650                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
651                                 .platform_data          = &uart0_data,
652         },
653         .resource       = uart0_resources,
654         .num_resources  = ARRAY_SIZE(uart0_resources),
655 };
656
657 static inline void configure_usart0_pins(unsigned pins)
658 {
659         at91_set_A_periph(AT91_PIN_PA6, 1);             /* TXD0 */
660         at91_set_A_periph(AT91_PIN_PA7, 0);             /* RXD0 */
661
662         if (pins & ATMEL_UART_RTS)
663                 at91_set_A_periph(AT91_PIN_PA9, 0);     /* RTS0 */
664         if (pins & ATMEL_UART_CTS)
665                 at91_set_A_periph(AT91_PIN_PA10, 0);    /* CTS0 */
666         if (pins & ATMEL_UART_DSR)
667                 at91_set_A_periph(AT91_PIN_PD14, 0);    /* DSR0 */
668         if (pins & ATMEL_UART_DTR)
669                 at91_set_A_periph(AT91_PIN_PD15, 0);    /* DTR0 */
670         if (pins & ATMEL_UART_DCD)
671                 at91_set_A_periph(AT91_PIN_PD16, 0);    /* DCD0 */
672         if (pins & ATMEL_UART_RI)
673                 at91_set_A_periph(AT91_PIN_PD17, 0);    /* RI0 */
674 }
675
676 static struct resource uart1_resources[] = {
677         [0] = {
678                 .start  = AT91SAM9RL_BASE_US1,
679                 .end    = AT91SAM9RL_BASE_US1 + SZ_16K - 1,
680                 .flags  = IORESOURCE_MEM,
681         },
682         [1] = {
683                 .start  = AT91SAM9RL_ID_US1,
684                 .end    = AT91SAM9RL_ID_US1,
685                 .flags  = IORESOURCE_IRQ,
686         },
687 };
688
689 static struct atmel_uart_data uart1_data = {
690         .use_dma_tx     = 1,
691         .use_dma_rx     = 1,
692 };
693
694 static u64 uart1_dmamask = DMA_BIT_MASK(32);
695
696 static struct platform_device at91sam9rl_uart1_device = {
697         .name           = "atmel_usart",
698         .id             = 2,
699         .dev            = {
700                                 .dma_mask               = &uart1_dmamask,
701                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
702                                 .platform_data          = &uart1_data,
703         },
704         .resource       = uart1_resources,
705         .num_resources  = ARRAY_SIZE(uart1_resources),
706 };
707
708 static inline void configure_usart1_pins(unsigned pins)
709 {
710         at91_set_A_periph(AT91_PIN_PA11, 1);            /* TXD1 */
711         at91_set_A_periph(AT91_PIN_PA12, 0);            /* RXD1 */
712
713         if (pins & ATMEL_UART_RTS)
714                 at91_set_B_periph(AT91_PIN_PA18, 0);    /* RTS1 */
715         if (pins & ATMEL_UART_CTS)
716                 at91_set_B_periph(AT91_PIN_PA19, 0);    /* CTS1 */
717 }
718
719 static struct resource uart2_resources[] = {
720         [0] = {
721                 .start  = AT91SAM9RL_BASE_US2,
722                 .end    = AT91SAM9RL_BASE_US2 + SZ_16K - 1,
723                 .flags  = IORESOURCE_MEM,
724         },
725         [1] = {
726                 .start  = AT91SAM9RL_ID_US2,
727                 .end    = AT91SAM9RL_ID_US2,
728                 .flags  = IORESOURCE_IRQ,
729         },
730 };
731
732 static struct atmel_uart_data uart2_data = {
733         .use_dma_tx     = 1,
734         .use_dma_rx     = 1,
735 };
736
737 static u64 uart2_dmamask = DMA_BIT_MASK(32);
738
739 static struct platform_device at91sam9rl_uart2_device = {
740         .name           = "atmel_usart",
741         .id             = 3,
742         .dev            = {
743                                 .dma_mask               = &uart2_dmamask,
744                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
745                                 .platform_data          = &uart2_data,
746         },
747         .resource       = uart2_resources,
748         .num_resources  = ARRAY_SIZE(uart2_resources),
749 };
750
751 static inline void configure_usart2_pins(unsigned pins)
752 {
753         at91_set_A_periph(AT91_PIN_PA13, 1);            /* TXD2 */
754         at91_set_A_periph(AT91_PIN_PA14, 0);            /* RXD2 */
755
756         if (pins & ATMEL_UART_RTS)
757                 at91_set_A_periph(AT91_PIN_PA29, 0);    /* RTS2 */
758         if (pins & ATMEL_UART_CTS)
759                 at91_set_A_periph(AT91_PIN_PA30, 0);    /* CTS2 */
760 }
761
762 static struct resource uart3_resources[] = {
763         [0] = {
764                 .start  = AT91SAM9RL_BASE_US3,
765                 .end    = AT91SAM9RL_BASE_US3 + SZ_16K - 1,
766                 .flags  = IORESOURCE_MEM,
767         },
768         [1] = {
769                 .start  = AT91SAM9RL_ID_US3,
770                 .end    = AT91SAM9RL_ID_US3,
771                 .flags  = IORESOURCE_IRQ,
772         },
773 };
774
775 static struct atmel_uart_data uart3_data = {
776         .use_dma_tx     = 1,
777         .use_dma_rx     = 1,
778 };
779
780 static u64 uart3_dmamask = DMA_BIT_MASK(32);
781
782 static struct platform_device at91sam9rl_uart3_device = {
783         .name           = "atmel_usart",
784         .id             = 4,
785         .dev            = {
786                                 .dma_mask               = &uart3_dmamask,
787                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
788                                 .platform_data          = &uart3_data,
789         },
790         .resource       = uart3_resources,
791         .num_resources  = ARRAY_SIZE(uart3_resources),
792 };
793
794 static inline void configure_usart3_pins(unsigned pins)
795 {
796         at91_set_A_periph(AT91_PIN_PB0, 1);             /* TXD3 */
797         at91_set_A_periph(AT91_PIN_PB1, 0);             /* RXD3 */
798
799         if (pins & ATMEL_UART_RTS)
800                 at91_set_B_periph(AT91_PIN_PD4, 0);     /* RTS3 */
801         if (pins & ATMEL_UART_CTS)
802                 at91_set_B_periph(AT91_PIN_PD3, 0);     /* CTS3 */
803 }
804
805 static struct platform_device *at91_uarts[ATMEL_MAX_UART];      /* the UARTs to use */
806 struct platform_device *atmel_default_console_device;   /* the serial console device */
807
808 void __init __deprecated at91_init_serial(struct at91_uart_config *config)
809 {
810         int i;
811
812         /* Fill in list of supported UARTs */
813         for (i = 0; i < config->nr_tty; i++) {
814                 switch (config->tty_map[i]) {
815                         case 0:
816                                 configure_usart0_pins(ATMEL_UART_CTS | ATMEL_UART_RTS);
817                                 at91_uarts[i] = &at91sam9rl_uart0_device;
818                                 at91_clock_associate("usart0_clk", &at91sam9rl_uart0_device.dev, "usart");
819                                 break;
820                         case 1:
821                                 configure_usart1_pins(0);
822                                 at91_uarts[i] = &at91sam9rl_uart1_device;
823                                 at91_clock_associate("usart1_clk", &at91sam9rl_uart1_device.dev, "usart");
824                                 break;
825                         case 2:
826                                 configure_usart2_pins(0);
827                                 at91_uarts[i] = &at91sam9rl_uart2_device;
828                                 at91_clock_associate("usart2_clk", &at91sam9rl_uart2_device.dev, "usart");
829                                 break;
830                         case 3:
831                                 configure_usart3_pins(0);
832                                 at91_uarts[i] = &at91sam9rl_uart3_device;
833                                 at91_clock_associate("usart3_clk", &at91sam9rl_uart3_device.dev, "usart");
834                                 break;
835                         case 4:
836                                 configure_dbgu_pins();
837                                 at91_uarts[i] = &at91sam9rl_dbgu_device;
838                                 at91_clock_associate("mck", &at91sam9rl_dbgu_device.dev, "usart");
839                                 break;
840                         default:
841                                 continue;
842                 }
843                 at91_uarts[i]->id = i;          /* update ID number to mapped ID */
844         }
845
846         /* Set serial console device */
847         if (config->console_tty < ATMEL_MAX_UART)
848                 atmel_default_console_device = at91_uarts[config->console_tty];
849         if (!atmel_default_console_device)
850                 printk(KERN_INFO "AT91: No default serial console defined.\n");
851 }
852
853 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
854 {
855         struct platform_device *pdev;
856
857         switch (id) {
858                 case 0:         /* DBGU */
859                         pdev = &at91sam9rl_dbgu_device;
860                         configure_dbgu_pins();
861                         at91_clock_associate("mck", &pdev->dev, "usart");
862                         break;
863                 case AT91SAM9RL_ID_US0:
864                         pdev = &at91sam9rl_uart0_device;
865                         configure_usart0_pins(pins);
866                         at91_clock_associate("usart0_clk", &pdev->dev, "usart");
867                         break;
868                 case AT91SAM9RL_ID_US1:
869                         pdev = &at91sam9rl_uart1_device;
870                         configure_usart1_pins(pins);
871                         at91_clock_associate("usart1_clk", &pdev->dev, "usart");
872                         break;
873                 case AT91SAM9RL_ID_US2:
874                         pdev = &at91sam9rl_uart2_device;
875                         configure_usart2_pins(pins);
876                         at91_clock_associate("usart2_clk", &pdev->dev, "usart");
877                         break;
878                 case AT91SAM9RL_ID_US3:
879                         pdev = &at91sam9rl_uart3_device;
880                         configure_usart3_pins(pins);
881                         at91_clock_associate("usart3_clk", &pdev->dev, "usart");
882                         break;
883                 default:
884                         return;
885         }
886         pdev->id = portnr;              /* update to mapped ID */
887
888         if (portnr < ATMEL_MAX_UART)
889                 at91_uarts[portnr] = pdev;
890 }
891
892 void __init at91_set_serial_console(unsigned portnr)
893 {
894         if (portnr < ATMEL_MAX_UART)
895                 atmel_default_console_device = at91_uarts[portnr];
896         if (!atmel_default_console_device)
897                 printk(KERN_INFO "AT91: No default serial console defined.\n");
898 }
899
900 void __init at91_add_device_serial(void)
901 {
902         int i;
903
904         for (i = 0; i < ATMEL_MAX_UART; i++) {
905                 if (at91_uarts[i])
906                         platform_device_register(at91_uarts[i]);
907         }
908 }
909 #else
910 void __init __deprecated at91_init_serial(struct at91_uart_config *config) {}
911 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
912 void __init at91_set_serial_console(unsigned portnr) {}
913 void __init at91_add_device_serial(void) {}
914 #endif
915
916
917 /* -------------------------------------------------------------------- */
918
919 /*
920  * These devices are always present and don't need any board-specific
921  * setup.
922  */
923 static int __init at91_add_standard_devices(void)
924 {
925         at91_add_device_rtc();
926         at91_add_device_rtt();
927         at91_add_device_watchdog();
928         return 0;
929 }
930
931 arch_initcall(at91_add_standard_devices);