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   1 /* bnx2.c: Broadcom NX2 network driver.
   2  *
   3  * Copyright (c) 2004-2008 Broadcom Corporation
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation.
   8  *
   9  * Written by: Michael Chan  (mchan@broadcom.com)
  10  */
  11
  12
  13 #include <linux/module.h>
  14 #include <linux/moduleparam.h>
  15
  16 #include <linux/kernel.h>
  17 #include <linux/timer.h>
  18 #include <linux/errno.h>
  19 #include <linux/ioport.h>
  20 #include <linux/slab.h>
  21 #include <linux/vmalloc.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/pci.h>
  24 #include <linux/init.h>
  25 #include <linux/netdevice.h>
  26 #include <linux/etherdevice.h>
  27 #include <linux/skbuff.h>
  28 #include <linux/dma-mapping.h>
  29 #include <linux/bitops.h>
  30 #include <asm/io.h>
  31 #include <asm/irq.h>
  32 #include <linux/delay.h>
  33 #include <asm/byteorder.h>
  34 #include <asm/page.h>
  35 #include <linux/time.h>
  36 #include <linux/ethtool.h>
  37 #include <linux/mii.h>
  38 #include <linux/if_vlan.h>
  39 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  40 #define BCM_VLAN 1
  41 #endif
  42 #include <net/ip.h>
  43 #include <net/tcp.h>
  44 #include <net/checksum.h>
  45 #include <linux/workqueue.h>
  46 #include <linux/crc32.h>
  47 #include <linux/prefetch.h>
  48 #include <linux/cache.h>
  49 #include <linux/zlib.h>
  50 #include <linux/log2.h>
  51
  52 #include "bnx2.h"
  53 #include "bnx2_fw.h"
  54 #include "bnx2_fw2.h"
  55
  56 #define FW_BUF_SIZE             0x10000
  57
  58 #define DRV_MODULE_NAME         "bnx2"
  59 #define PFX DRV_MODULE_NAME     ": "
  60 #define DRV_MODULE_VERSION      "1.8.0"
  61 #define DRV_MODULE_RELDATE      "Aug 14, 2008"
  62
  63 #define RUN_AT(x) (jiffies + (x))
  64
  65 /* Time in jiffies before concluding the transmitter is hung. */
  66 #define TX_TIMEOUT  (5*HZ)
  67
  68 static char version[] __devinitdata =
  69         "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  70
  71 MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
  72 MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708/5709 Driver");
  73 MODULE_LICENSE("GPL");
  74 MODULE_VERSION(DRV_MODULE_VERSION);
  75
  76 static int disable_msi = 0;
  77
  78 module_param(disable_msi, int, 0);
  79 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
  80
  81 typedef enum {
  82         BCM5706 = 0,
  83         NC370T,
  84         NC370I,
  85         BCM5706S,
  86         NC370F,
  87         BCM5708,
  88         BCM5708S,
  89         BCM5709,
  90         BCM5709S,
  91         BCM5716,
  92 } board_t;
  93
  94 /* indexed by board_t, above */
  95 static struct {
  96         char *name;
  97 } board_info[] __devinitdata = {
  98         { "Broadcom NetXtreme II BCM5706 1000Base-T" },
  99         { "HP NC370T Multifunction Gigabit Server Adapter" },
 100         { "HP NC370i Multifunction Gigabit Server Adapter" },
 101         { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
 102         { "HP NC370F Multifunction Gigabit Server Adapter" },
 103         { "Broadcom NetXtreme II BCM5708 1000Base-T" },
 104         { "Broadcom NetXtreme II BCM5708 1000Base-SX" },
 105         { "Broadcom NetXtreme II BCM5709 1000Base-T" },
 106         { "Broadcom NetXtreme II BCM5709 1000Base-SX" },
 107         { "Broadcom NetXtreme II BCM5716 1000Base-T" },
 108         };
 109
 110 static DEFINE_PCI_DEVICE_TABLE(bnx2_pci_tbl) = {
 111         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
 112           PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
 113         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
 114           PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
 115         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
 116           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
 117         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708,
 118           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 },
 119         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
 120           PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
 121         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
 122           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
 123         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S,
 124           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
 125         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709,
 126           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709 },
 127         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709S,
 128           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709S },
 129         { PCI_VENDOR_ID_BROADCOM, 0x163b,
 130           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716 },
 131         { 0, }
 132 };
 133
 134 static struct flash_spec flash_table[] =
 135 {
 136 #define BUFFERED_FLAGS          (BNX2_NV_BUFFERED | BNX2_NV_TRANSLATE)
 137 #define NONBUFFERED_FLAGS       (BNX2_NV_WREN)
 138         /* Slow EEPROM */
 139         {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
 140          BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
 141          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
 142          "EEPROM - slow"},
 143         /* Expansion entry 0001 */
 144         {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
 145          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 146          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 147          "Entry 0001"},
 148         /* Saifun SA25F010 (non-buffered flash) */
 149         /* strap, cfg1, & write1 need updates */
 150         {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
 151          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 152          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
 153          "Non-buffered flash (128kB)"},
 154         /* Saifun SA25F020 (non-buffered flash) */
 155         /* strap, cfg1, & write1 need updates */
 156         {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
 157          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 158          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
 159          "Non-buffered flash (256kB)"},
 160         /* Expansion entry 0100 */
 161         {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
 162          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 163          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 164          "Entry 0100"},
 165         /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
 166         {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
 167          NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
 168          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
 169          "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
 170         /* Entry 0110: ST M45PE20 (non-buffered flash)*/
 171         {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
 172          NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
 173          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
 174          "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
 175         /* Saifun SA25F005 (non-buffered flash) */
 176         /* strap, cfg1, & write1 need updates */
 177         {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
 178          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 179          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
 180          "Non-buffered flash (64kB)"},
 181         /* Fast EEPROM */
 182         {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
 183          BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
 184          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
 185          "EEPROM - fast"},
 186         /* Expansion entry 1001 */
 187         {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
 188          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 189          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 190          "Entry 1001"},
 191         /* Expansion entry 1010 */
 192         {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
 193          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 194          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 195          "Entry 1010"},
 196         /* ATMEL AT45DB011B (buffered flash) */
 197         {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
 198          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 199          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
 200          "Buffered flash (128kB)"},
 201         /* Expansion entry 1100 */
 202         {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
 203          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 204          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 205          "Entry 1100"},
 206         /* Expansion entry 1101 */
 207         {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
 208          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 209          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 210          "Entry 1101"},
 211         /* Ateml Expansion entry 1110 */
 212         {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
 213          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 214          BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
 215          "Entry 1110 (Atmel)"},
 216         /* ATMEL AT45DB021B (buffered flash) */
 217         {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
 218          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 219          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
 220          "Buffered flash (256kB)"},
 221 };
 222
 223 static struct flash_spec flash_5709 = {
 224         .flags          = BNX2_NV_BUFFERED,
 225         .page_bits      = BCM5709_FLASH_PAGE_BITS,
 226         .page_size      = BCM5709_FLASH_PAGE_SIZE,
 227         .addr_mask      = BCM5709_FLASH_BYTE_ADDR_MASK,
 228         .total_size     = BUFFERED_FLASH_TOTAL_SIZE*2,
 229         .name           = "5709 Buffered flash (256kB)",
 230 };
 231
 232 MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
 233
 234 static inline u32 bnx2_tx_avail(struct bnx2 *bp, struct bnx2_tx_ring_info *txr)
 235 {
 236         u32 diff;
 237
 238         smp_mb();
 239
 240         /* The ring uses 256 indices for 255 entries, one of them
 241          * needs to be skipped.
 242          */
 243         diff = txr->tx_prod - txr->tx_cons;
 244         if (unlikely(diff >= TX_DESC_CNT)) {
 245                 diff &= 0xffff;
 246                 if (diff == TX_DESC_CNT)
 247                         diff = MAX_TX_DESC_CNT;
 248         }
 249         return (bp->tx_ring_size - diff);
 250 }
 251
 252 static u32
 253 bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
 254 {
 255         u32 val;
 256
 257         spin_lock_bh(&bp->indirect_lock);
 258         REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
 259         val = REG_RD(bp, BNX2_PCICFG_REG_WINDOW);
 260         spin_unlock_bh(&bp->indirect_lock);
 261         return val;
 262 }
 263
 264 static void
 265 bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
 266 {
 267         spin_lock_bh(&bp->indirect_lock);
 268         REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
 269         REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
 270         spin_unlock_bh(&bp->indirect_lock);
 271 }
 272
 273 static void
 274 bnx2_shmem_wr(struct bnx2 *bp, u32 offset, u32 val)
 275 {
 276         bnx2_reg_wr_ind(bp, bp->shmem_base + offset, val);
 277 }
 278
 279 static u32
 280 bnx2_shmem_rd(struct bnx2 *bp, u32 offset)
 281 {
 282         return (bnx2_reg_rd_ind(bp, bp->shmem_base + offset));
 283 }
 284
 285 static void
 286 bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
 287 {
 288         offset += cid_addr;
 289         spin_lock_bh(&bp->indirect_lock);
 290         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
 291                 int i;
 292
 293                 REG_WR(bp, BNX2_CTX_CTX_DATA, val);
 294                 REG_WR(bp, BNX2_CTX_CTX_CTRL,
 295                        offset | BNX2_CTX_CTX_CTRL_WRITE_REQ);
 296                 for (i = 0; i < 5; i++) {
 297                         val = REG_RD(bp, BNX2_CTX_CTX_CTRL);
 298                         if ((val & BNX2_CTX_CTX_CTRL_WRITE_REQ) == 0)
 299                                 break;
 300                         udelay(5);
 301                 }
 302         } else {
 303                 REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
 304                 REG_WR(bp, BNX2_CTX_DATA, val);
 305         }
 306         spin_unlock_bh(&bp->indirect_lock);
 307 }
 308
 309 static int
 310 bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
 311 {
 312         u32 val1;
 313         int i, ret;
 314
 315         if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
 316                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 317                 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
 318
 319                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
 320                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 321
 322                 udelay(40);
 323         }
 324
 325         val1 = (bp->phy_addr << 21) | (reg << 16) |
 326                 BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
 327                 BNX2_EMAC_MDIO_COMM_START_BUSY;
 328         REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
 329
 330         for (i = 0; i < 50; i++) {
 331                 udelay(10);
 332
 333                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
 334                 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
 335                         udelay(5);
 336
 337                         val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
 338                         val1 &= BNX2_EMAC_MDIO_COMM_DATA;
 339
 340                         break;
 341                 }
 342         }
 343
 344         if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
 345                 *val = 0x0;
 346                 ret = -EBUSY;
 347         }
 348         else {
 349                 *val = val1;
 350                 ret = 0;
 351         }
 352
 353         if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
 354                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 355                 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
 356
 357                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
 358                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 359
 360                 udelay(40);
 361         }
 362
 363         return ret;
 364 }
 365
 366 static int
 367 bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
 368 {
 369         u32 val1;
 370         int i, ret;
 371
 372         if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
 373                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 374                 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
 375
 376                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
 377                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 378
 379                 udelay(40);
 380         }
 381
 382         val1 = (bp->phy_addr << 21) | (reg << 16) | val |
 383                 BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
 384                 BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
 385         REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
 386
 387         for (i = 0; i < 50; i++) {
 388                 udelay(10);
 389
 390                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
 391                 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
 392                         udelay(5);
 393                         break;
 394                 }
 395         }
 396
 397         if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
 398                 ret = -EBUSY;
 399         else
 400                 ret = 0;
 401
 402         if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
 403                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 404                 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
 405
 406                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
 407                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 408
 409                 udelay(40);
 410         }
 411
 412         return ret;
 413 }
 414
 415 static void
 416 bnx2_disable_int(struct bnx2 *bp)
 417 {
 418         int i;
 419         struct bnx2_napi *bnapi;
 420
 421         for (i = 0; i < bp->irq_nvecs; i++) {
 422                 bnapi = &bp->bnx2_napi[i];
 423                 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
 424                        BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
 425         }
 426         REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
 427 }
 428
 429 static void
 430 bnx2_enable_int(struct bnx2 *bp)
 431 {
 432         int i;
 433         struct bnx2_napi *bnapi;
 434
 435         for (i = 0; i < bp->irq_nvecs; i++) {
 436                 bnapi = &bp->bnx2_napi[i];
 437
 438                 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
 439                        BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
 440                        BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
 441                        bnapi->last_status_idx);
 442
 443                 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
 444                        BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
 445                        bnapi->last_status_idx);
 446         }
 447         REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
 448 }
 449
 450 static void
 451 bnx2_disable_int_sync(struct bnx2 *bp)
 452 {
 453         int i;
 454
 455         atomic_inc(&bp->intr_sem);
 456         bnx2_disable_int(bp);
 457         for (i = 0; i < bp->irq_nvecs; i++)
 458                 synchronize_irq(bp->irq_tbl[i].vector);
 459 }
 460
 461 static void
 462 bnx2_napi_disable(struct bnx2 *bp)
 463 {
 464         int i;
 465
 466         for (i = 0; i < bp->irq_nvecs; i++)
 467                 napi_disable(&bp->bnx2_napi[i].napi);
 468 }
 469
 470 static void
 471 bnx2_napi_enable(struct bnx2 *bp)
 472 {
 473         int i;
 474
 475         for (i = 0; i < bp->irq_nvecs; i++)
 476                 napi_enable(&bp->bnx2_napi[i].napi);
 477 }
 478
 479 static void
 480 bnx2_netif_stop(struct bnx2 *bp)
 481 {
 482         bnx2_disable_int_sync(bp);
 483         if (netif_running(bp->dev)) {
 484                 bnx2_napi_disable(bp);
 485                 netif_tx_disable(bp->dev);
 486                 bp->dev->trans_start = jiffies; /* prevent tx timeout */
 487         }
 488 }
 489
 490 static void
 491 bnx2_netif_start(struct bnx2 *bp)
 492 {
 493         if (atomic_dec_and_test(&bp->intr_sem)) {
 494                 if (netif_running(bp->dev)) {
 495                         netif_tx_wake_all_queues(bp->dev);
 496                         bnx2_napi_enable(bp);
 497                         bnx2_enable_int(bp);
 498                 }
 499         }
 500 }
 501
 502 static void
 503 bnx2_free_tx_mem(struct bnx2 *bp)
 504 {
 505         int i;
 506
 507         for (i = 0; i < bp->num_tx_rings; i++) {
 508                 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
 509                 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
 510
 511                 if (txr->tx_desc_ring) {
 512                         pci_free_consistent(bp->pdev, TXBD_RING_SIZE,
 513                                             txr->tx_desc_ring,
 514                                             txr->tx_desc_mapping);
 515                         txr->tx_desc_ring = NULL;
 516                 }
 517                 kfree(txr->tx_buf_ring);
 518                 txr->tx_buf_ring = NULL;
 519         }
 520 }
 521
 522 static void
 523 bnx2_free_rx_mem(struct bnx2 *bp)
 524 {
 525         int i;
 526
 527         for (i = 0; i < bp->num_rx_rings; i++) {
 528                 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
 529                 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
 530                 int j;
 531
 532                 for (j = 0; j < bp->rx_max_ring; j++) {
 533                         if (rxr->rx_desc_ring[j])
 534                                 pci_free_consistent(bp->pdev, RXBD_RING_SIZE,
 535                                                     rxr->rx_desc_ring[j],
 536                                                     rxr->rx_desc_mapping[j]);
 537                         rxr->rx_desc_ring[j] = NULL;
 538                 }
 539                 if (rxr->rx_buf_ring)
 540                         vfree(rxr->rx_buf_ring);
 541                 rxr->rx_buf_ring = NULL;
 542
 543                 for (j = 0; j < bp->rx_max_pg_ring; j++) {
 544                         if (rxr->rx_pg_desc_ring[j])
 545                                 pci_free_consistent(bp->pdev, RXBD_RING_SIZE,
 546                                                     rxr->rx_pg_desc_ring[i],
 547                                                     rxr->rx_pg_desc_mapping[i]);
 548                         rxr->rx_pg_desc_ring[i] = NULL;
 549                 }
 550                 if (rxr->rx_pg_ring)
 551                         vfree(rxr->rx_pg_ring);
 552                 rxr->rx_pg_ring = NULL;
 553         }
 554 }
 555
 556 static int
 557 bnx2_alloc_tx_mem(struct bnx2 *bp)
 558 {
 559         int i;
 560
 561         for (i = 0; i < bp->num_tx_rings; i++) {
 562                 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
 563                 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
 564
 565                 txr->tx_buf_ring = kzalloc(SW_TXBD_RING_SIZE, GFP_KERNEL);
 566                 if (txr->tx_buf_ring == NULL)
 567                         return -ENOMEM;
 568
 569                 txr->tx_desc_ring =
 570                         pci_alloc_consistent(bp->pdev, TXBD_RING_SIZE,
 571                                              &txr->tx_desc_mapping);
 572                 if (txr->tx_desc_ring == NULL)
 573                         return -ENOMEM;
 574         }
 575         return 0;
 576 }
 577
 578 static int
 579 bnx2_alloc_rx_mem(struct bnx2 *bp)
 580 {
 581         int i;
 582
 583         for (i = 0; i < bp->num_rx_rings; i++) {
 584                 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
 585                 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
 586                 int j;
 587
 588                 rxr->rx_buf_ring =
 589                         vmalloc(SW_RXBD_RING_SIZE * bp->rx_max_ring);
 590                 if (rxr->rx_buf_ring == NULL)
 591                         return -ENOMEM;
 592
 593                 memset(rxr->rx_buf_ring, 0,
 594                        SW_RXBD_RING_SIZE * bp->rx_max_ring);
 595
 596                 for (j = 0; j < bp->rx_max_ring; j++) {
 597                         rxr->rx_desc_ring[j] =
 598                                 pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE,
 599                                                      &rxr->rx_desc_mapping[j]);
 600                         if (rxr->rx_desc_ring[j] == NULL)
 601                                 return -ENOMEM;
 602
 603                 }
 604
 605                 if (bp->rx_pg_ring_size) {
 606                         rxr->rx_pg_ring = vmalloc(SW_RXPG_RING_SIZE *
 607                                                   bp->rx_max_pg_ring);
 608                         if (rxr->rx_pg_ring == NULL)
 609                                 return -ENOMEM;
 610
 611                         memset(rxr->rx_pg_ring, 0, SW_RXPG_RING_SIZE *
 612                                bp->rx_max_pg_ring);
 613                 }
 614
 615                 for (j = 0; j < bp->rx_max_pg_ring; j++) {
 616                         rxr->rx_pg_desc_ring[j] =
 617                                 pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE,
 618                                                 &rxr->rx_pg_desc_mapping[j]);
 619                         if (rxr->rx_pg_desc_ring[j] == NULL)
 620                                 return -ENOMEM;
 621
 622                 }
 623         }
 624         return 0;
 625 }
 626
 627 static void
 628 bnx2_free_mem(struct bnx2 *bp)
 629 {
 630         int i;
 631         struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
 632
 633         bnx2_free_tx_mem(bp);
 634         bnx2_free_rx_mem(bp);
 635
 636         for (i = 0; i < bp->ctx_pages; i++) {
 637                 if (bp->ctx_blk[i]) {
 638                         pci_free_consistent(bp->pdev, BCM_PAGE_SIZE,
 639                                             bp->ctx_blk[i],
 640                                             bp->ctx_blk_mapping[i]);
 641                         bp->ctx_blk[i] = NULL;
 642                 }
 643         }
 644         if (bnapi->status_blk.msi) {
 645                 pci_free_consistent(bp->pdev, bp->status_stats_size,
 646                                     bnapi->status_blk.msi,
 647                                     bp->status_blk_mapping);
 648                 bnapi->status_blk.msi = NULL;
 649                 bp->stats_blk = NULL;
 650         }
 651 }
 652
 653 static int
 654 bnx2_alloc_mem(struct bnx2 *bp)
 655 {
 656         int i, status_blk_size, err;
 657         struct bnx2_napi *bnapi;
 658         void *status_blk;
 659
 660         /* Combine status and statistics blocks into one allocation. */
 661         status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block));
 662         if (bp->flags & BNX2_FLAG_MSIX_CAP)
 663                 status_blk_size = L1_CACHE_ALIGN(BNX2_MAX_MSIX_HW_VEC *
 664                                                  BNX2_SBLK_MSIX_ALIGN_SIZE);
 665         bp->status_stats_size = status_blk_size +
 666                                 sizeof(struct statistics_block);
 667
 668         status_blk = pci_alloc_consistent(bp->pdev, bp->status_stats_size,
 669                                           &bp->status_blk_mapping);
 670         if (status_blk == NULL)
 671                 goto alloc_mem_err;
 672
 673         memset(status_blk, 0, bp->status_stats_size);
 674
 675         bnapi = &bp->bnx2_napi[0];
 676         bnapi->status_blk.msi = status_blk;
 677         bnapi->hw_tx_cons_ptr =
 678                 &bnapi->status_blk.msi->status_tx_quick_consumer_index0;
 679         bnapi->hw_rx_cons_ptr =
 680                 &bnapi->status_blk.msi->status_rx_quick_consumer_index0;
 681         if (bp->flags & BNX2_FLAG_MSIX_CAP) {
 682                 for (i = 1; i < BNX2_MAX_MSIX_VEC; i++) {
 683                         struct status_block_msix *sblk;
 684
 685                         bnapi = &bp->bnx2_napi[i];
 686
 687                         sblk = (void *) (status_blk +
 688                                          BNX2_SBLK_MSIX_ALIGN_SIZE * i);
 689                         bnapi->status_blk.msix = sblk;
 690                         bnapi->hw_tx_cons_ptr =
 691                                 &sblk->status_tx_quick_consumer_index;
 692                         bnapi->hw_rx_cons_ptr =
 693                                 &sblk->status_rx_quick_consumer_index;
 694                         bnapi->int_num = i << 24;
 695                 }
 696         }
 697
 698         bp->stats_blk = status_blk + status_blk_size;
 699
 700         bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size;
 701
 702         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
 703                 bp->ctx_pages = 0x2000 / BCM_PAGE_SIZE;
 704                 if (bp->ctx_pages == 0)
 705                         bp->ctx_pages = 1;
 706                 for (i = 0; i < bp->ctx_pages; i++) {
 707                         bp->ctx_blk[i] = pci_alloc_consistent(bp->pdev,
 708                                                 BCM_PAGE_SIZE,
 709                                                 &bp->ctx_blk_mapping[i]);
 710                         if (bp->ctx_blk[i] == NULL)
 711                                 goto alloc_mem_err;
 712                 }
 713         }
 714
 715         err = bnx2_alloc_rx_mem(bp);
 716         if (err)
 717                 goto alloc_mem_err;
 718
 719         err = bnx2_alloc_tx_mem(bp);
 720         if (err)
 721                 goto alloc_mem_err;
 722
 723         return 0;
 724
 725 alloc_mem_err:
 726         bnx2_free_mem(bp);
 727         return -ENOMEM;
 728 }
 729
 730 static void
 731 bnx2_report_fw_link(struct bnx2 *bp)
 732 {
 733         u32 fw_link_status = 0;
 734
 735         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
 736                 return;
 737
 738         if (bp->link_up) {
 739                 u32 bmsr;
 740
 741                 switch (bp->line_speed) {
 742                 case SPEED_10:
 743                         if (bp->duplex == DUPLEX_HALF)
 744                                 fw_link_status = BNX2_LINK_STATUS_10HALF;
 745                         else
 746                                 fw_link_status = BNX2_LINK_STATUS_10FULL;
 747                         break;
 748                 case SPEED_100:
 749                         if (bp->duplex == DUPLEX_HALF)
 750                                 fw_link_status = BNX2_LINK_STATUS_100HALF;
 751                         else
 752                                 fw_link_status = BNX2_LINK_STATUS_100FULL;
 753                         break;
 754                 case SPEED_1000:
 755                         if (bp->duplex == DUPLEX_HALF)
 756                                 fw_link_status = BNX2_LINK_STATUS_1000HALF;
 757                         else
 758                                 fw_link_status = BNX2_LINK_STATUS_1000FULL;
 759                         break;
 760                 case SPEED_2500:
 761                         if (bp->duplex == DUPLEX_HALF)
 762                                 fw_link_status = BNX2_LINK_STATUS_2500HALF;
 763                         else
 764                                 fw_link_status = BNX2_LINK_STATUS_2500FULL;
 765                         break;
 766                 }
 767
 768                 fw_link_status |= BNX2_LINK_STATUS_LINK_UP;
 769
 770                 if (bp->autoneg) {
 771                         fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED;
 772
 773                         bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
 774                         bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
 775
 776                         if (!(bmsr & BMSR_ANEGCOMPLETE) ||
 777                             bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)
 778                                 fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET;
 779                         else
 780                                 fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE;
 781                 }
 782         }
 783         else
 784                 fw_link_status = BNX2_LINK_STATUS_LINK_DOWN;
 785
 786         bnx2_shmem_wr(bp, BNX2_LINK_STATUS, fw_link_status);
 787 }
 788
 789 static char *
 790 bnx2_xceiver_str(struct bnx2 *bp)
 791 {
 792         return ((bp->phy_port == PORT_FIBRE) ? "SerDes" :
 793                 ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) ? "Remote Copper" :
 794                  "Copper"));
 795 }
 796
 797 static void
 798 bnx2_report_link(struct bnx2 *bp)
 799 {
 800         if (bp->link_up) {
 801                 netif_carrier_on(bp->dev);
 802                 printk(KERN_INFO PFX "%s NIC %s Link is Up, ", bp->dev->name,
 803                        bnx2_xceiver_str(bp));
 804
 805                 printk("%d Mbps ", bp->line_speed);
 806
 807                 if (bp->duplex == DUPLEX_FULL)
 808                         printk("full duplex");
 809                 else
 810                         printk("half duplex");
 811
 812                 if (bp->flow_ctrl) {
 813                         if (bp->flow_ctrl & FLOW_CTRL_RX) {
 814                                 printk(", receive ");
 815                                 if (bp->flow_ctrl & FLOW_CTRL_TX)
 816                                         printk("& transmit ");
 817                         }
 818                         else {
 819                                 printk(", transmit ");
 820                         }
 821                         printk("flow control ON");
 822                 }
 823                 printk("\n");
 824         }
 825         else {
 826                 netif_carrier_off(bp->dev);
 827                 printk(KERN_ERR PFX "%s NIC %s Link is Down\n", bp->dev->name,
 828                        bnx2_xceiver_str(bp));
 829         }
 830
 831         bnx2_report_fw_link(bp);
 832 }
 833
 834 static void
 835 bnx2_resolve_flow_ctrl(struct bnx2 *bp)
 836 {
 837         u32 local_adv, remote_adv;
 838
 839         bp->flow_ctrl = 0;
 840         if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
 841                 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
 842
 843                 if (bp->duplex == DUPLEX_FULL) {
 844                         bp->flow_ctrl = bp->req_flow_ctrl;
 845                 }
 846                 return;
 847         }
 848
 849         if (bp->duplex != DUPLEX_FULL) {
 850                 return;
 851         }
 852
 853         if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
 854             (CHIP_NUM(bp) == CHIP_NUM_5708)) {
 855                 u32 val;
 856
 857                 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
 858                 if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
 859                         bp->flow_ctrl |= FLOW_CTRL_TX;
 860                 if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
 861                         bp->flow_ctrl |= FLOW_CTRL_RX;
 862                 return;
 863         }
 864
 865         bnx2_read_phy(bp, bp->mii_adv, &local_adv);
 866         bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
 867
 868         if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
 869                 u32 new_local_adv = 0;
 870                 u32 new_remote_adv = 0;
 871
 872                 if (local_adv & ADVERTISE_1000XPAUSE)
 873                         new_local_adv |= ADVERTISE_PAUSE_CAP;
 874                 if (local_adv & ADVERTISE_1000XPSE_ASYM)
 875                         new_local_adv |= ADVERTISE_PAUSE_ASYM;
 876                 if (remote_adv & ADVERTISE_1000XPAUSE)
 877                         new_remote_adv |= ADVERTISE_PAUSE_CAP;
 878                 if (remote_adv & ADVERTISE_1000XPSE_ASYM)
 879                         new_remote_adv |= ADVERTISE_PAUSE_ASYM;
 880
 881                 local_adv = new_local_adv;
 882                 remote_adv = new_remote_adv;
 883         }
 884
 885         /* See Table 28B-3 of 802.3ab-1999 spec. */
 886         if (local_adv & ADVERTISE_PAUSE_CAP) {
 887                 if(local_adv & ADVERTISE_PAUSE_ASYM) {
 888                         if (remote_adv & ADVERTISE_PAUSE_CAP) {
 889                                 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
 890                         }
 891                         else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
 892                                 bp->flow_ctrl = FLOW_CTRL_RX;
 893                         }
 894                 }
 895                 else {
 896                         if (remote_adv & ADVERTISE_PAUSE_CAP) {
 897                                 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
 898                         }
 899                 }
 900         }
 901         else if (local_adv & ADVERTISE_PAUSE_ASYM) {
 902                 if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
 903                         (remote_adv & ADVERTISE_PAUSE_ASYM)) {
 904
 905                         bp->flow_ctrl = FLOW_CTRL_TX;
 906                 }
 907         }
 908 }
 909
 910 static int
 911 bnx2_5709s_linkup(struct bnx2 *bp)
 912 {
 913         u32 val, speed;
 914
 915         bp->link_up = 1;
 916
 917         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_GP_STATUS);
 918         bnx2_read_phy(bp, MII_BNX2_GP_TOP_AN_STATUS1, &val);
 919         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
 920
 921         if ((bp->autoneg & AUTONEG_SPEED) == 0) {
 922                 bp->line_speed = bp->req_line_speed;
 923                 bp->duplex = bp->req_duplex;
 924                 return 0;
 925         }
 926         speed = val & MII_BNX2_GP_TOP_AN_SPEED_MSK;
 927         switch (speed) {
 928                 case MII_BNX2_GP_TOP_AN_SPEED_10:
 929                         bp->line_speed = SPEED_10;
 930                         break;
 931                 case MII_BNX2_GP_TOP_AN_SPEED_100:
 932                         bp->line_speed = SPEED_100;
 933                         break;
 934                 case MII_BNX2_GP_TOP_AN_SPEED_1G:
 935                 case MII_BNX2_GP_TOP_AN_SPEED_1GKV:
 936                         bp->line_speed = SPEED_1000;
 937                         break;
 938                 case MII_BNX2_GP_TOP_AN_SPEED_2_5G:
 939                         bp->line_speed = SPEED_2500;
 940                         break;
 941         }
 942         if (val & MII_BNX2_GP_TOP_AN_FD)
 943                 bp->duplex = DUPLEX_FULL;
 944         else
 945                 bp->duplex = DUPLEX_HALF;
 946         return 0;
 947 }
 948
 949 static int
 950 bnx2_5708s_linkup(struct bnx2 *bp)
 951 {
 952         u32 val;
 953
 954         bp->link_up = 1;
 955         bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
 956         switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
 957                 case BCM5708S_1000X_STAT1_SPEED_10:
 958                         bp->line_speed = SPEED_10;
 959                         break;
 960                 case BCM5708S_1000X_STAT1_SPEED_100:
 961                         bp->line_speed = SPEED_100;
 962                         break;
 963                 case BCM5708S_1000X_STAT1_SPEED_1G:
 964                         bp->line_speed = SPEED_1000;
 965                         break;
 966                 case BCM5708S_1000X_STAT1_SPEED_2G5:
 967                         bp->line_speed = SPEED_2500;
 968                         break;
 969         }
 970         if (val & BCM5708S_1000X_STAT1_FD)
 971                 bp->duplex = DUPLEX_FULL;
 972         else
 973                 bp->duplex = DUPLEX_HALF;
 974
 975         return 0;
 976 }
 977
 978 static int
 979 bnx2_5706s_linkup(struct bnx2 *bp)
 980 {
 981         u32 bmcr, local_adv, remote_adv, common;
 982
 983         bp->link_up = 1;
 984         bp->line_speed = SPEED_1000;
 985
 986         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
 987         if (bmcr & BMCR_FULLDPLX) {
 988                 bp->duplex = DUPLEX_FULL;
 989         }
 990         else {
 991                 bp->duplex = DUPLEX_HALF;
 992         }
 993
 994         if (!(bmcr & BMCR_ANENABLE)) {
 995                 return 0;
 996         }
 997
 998         bnx2_read_phy(bp, bp->mii_adv, &local_adv);
 999         bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
1000
1001         common = local_adv & remote_adv;
1002         if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
1003
1004                 if (common & ADVERTISE_1000XFULL) {
1005                         bp->duplex = DUPLEX_FULL;
1006                 }
1007                 else {
1008                         bp->duplex = DUPLEX_HALF;
1009                 }
1010         }
1011
1012         return 0;
1013 }
1014
1015 static int
1016 bnx2_copper_linkup(struct bnx2 *bp)
1017 {
1018         u32 bmcr;
1019
1020         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1021         if (bmcr & BMCR_ANENABLE) {
1022                 u32 local_adv, remote_adv, common;
1023
1024                 bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
1025                 bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
1026
1027                 common = local_adv & (remote_adv >> 2);
1028                 if (common & ADVERTISE_1000FULL) {
1029                         bp->line_speed = SPEED_1000;
1030                         bp->duplex = DUPLEX_FULL;
1031                 }
1032                 else if (common & ADVERTISE_1000HALF) {
1033                         bp->line_speed = SPEED_1000;
1034                         bp->duplex = DUPLEX_HALF;
1035                 }
1036                 else {
1037                         bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1038                         bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
1039
1040                         common = local_adv & remote_adv;
1041                         if (common & ADVERTISE_100FULL) {
1042                                 bp->line_speed = SPEED_100;
1043                                 bp->duplex = DUPLEX_FULL;
1044                         }
1045                         else if (common & ADVERTISE_100HALF) {
1046                                 bp->line_speed = SPEED_100;
1047                                 bp->duplex = DUPLEX_HALF;
1048                         }
1049                         else if (common & ADVERTISE_10FULL) {
1050                                 bp->line_speed = SPEED_10;
1051                                 bp->duplex = DUPLEX_FULL;
1052                         }
1053                         else if (common & ADVERTISE_10HALF) {
1054                                 bp->line_speed = SPEED_10;
1055                                 bp->duplex = DUPLEX_HALF;
1056                         }
1057                         else {
1058                                 bp->line_speed = 0;
1059                                 bp->link_up = 0;
1060                         }
1061                 }
1062         }
1063         else {
1064                 if (bmcr & BMCR_SPEED100) {
1065                         bp->line_speed = SPEED_100;
1066                 }
1067                 else {
1068                         bp->line_speed = SPEED_10;
1069                 }
1070                 if (bmcr & BMCR_FULLDPLX) {
1071                         bp->duplex = DUPLEX_FULL;
1072                 }
1073                 else {
1074                         bp->duplex = DUPLEX_HALF;
1075                 }
1076         }
1077
1078         return 0;
1079 }
1080
1081 static void
1082 bnx2_init_rx_context(struct bnx2 *bp, u32 cid)
1083 {
1084         u32 val, rx_cid_addr = GET_CID_ADDR(cid);
1085
1086         val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
1087         val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
1088         val |= 0x02 << 8;
1089
1090         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1091                 u32 lo_water, hi_water;
1092
1093                 if (bp->flow_ctrl & FLOW_CTRL_TX)
1094                         lo_water = BNX2_L2CTX_LO_WATER_MARK_DEFAULT;
1095                 else
1096                         lo_water = BNX2_L2CTX_LO_WATER_MARK_DIS;
1097                 if (lo_water >= bp->rx_ring_size)
1098                         lo_water = 0;
1099
1100                 hi_water = bp->rx_ring_size / 4;
1101
1102                 if (hi_water <= lo_water)
1103                         lo_water = 0;
1104
1105                 hi_water /= BNX2_L2CTX_HI_WATER_MARK_SCALE;
1106                 lo_water /= BNX2_L2CTX_LO_WATER_MARK_SCALE;
1107
1108                 if (hi_water > 0xf)
1109                         hi_water = 0xf;
1110                 else if (hi_water == 0)
1111                         lo_water = 0;
1112                 val |= lo_water | (hi_water << BNX2_L2CTX_HI_WATER_MARK_SHIFT);
1113         }
1114         bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val);
1115 }
1116
1117 static void
1118 bnx2_init_all_rx_contexts(struct bnx2 *bp)
1119 {
1120         int i;
1121         u32 cid;
1122
1123         for (i = 0, cid = RX_CID; i < bp->num_rx_rings; i++, cid++) {
1124                 if (i == 1)
1125                         cid = RX_RSS_CID;
1126                 bnx2_init_rx_context(bp, cid);
1127         }
1128 }
1129
1130 static int
1131 bnx2_set_mac_link(struct bnx2 *bp)
1132 {
1133         u32 val;
1134
1135         REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
1136         if (bp->link_up && (bp->line_speed == SPEED_1000) &&
1137                 (bp->duplex == DUPLEX_HALF)) {
1138                 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
1139         }
1140
1141         /* Configure the EMAC mode register. */
1142         val = REG_RD(bp, BNX2_EMAC_MODE);
1143
1144         val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
1145                 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
1146                 BNX2_EMAC_MODE_25G_MODE);
1147
1148         if (bp->link_up) {
1149                 switch (bp->line_speed) {
1150                         case SPEED_10:
1151                                 if (CHIP_NUM(bp) != CHIP_NUM_5706) {
1152                                         val |= BNX2_EMAC_MODE_PORT_MII_10M;
1153                                         break;
1154                                 }
1155                                 /* fall through */
1156                         case SPEED_100:
1157                                 val |= BNX2_EMAC_MODE_PORT_MII;
1158                                 break;
1159                         case SPEED_2500:
1160                                 val |= BNX2_EMAC_MODE_25G_MODE;
1161                                 /* fall through */
1162                         case SPEED_1000:
1163                                 val |= BNX2_EMAC_MODE_PORT_GMII;
1164                                 break;
1165                 }
1166         }
1167         else {
1168                 val |= BNX2_EMAC_MODE_PORT_GMII;
1169         }
1170
1171         /* Set the MAC to operate in the appropriate duplex mode. */
1172         if (bp->duplex == DUPLEX_HALF)
1173                 val |= BNX2_EMAC_MODE_HALF_DUPLEX;
1174         REG_WR(bp, BNX2_EMAC_MODE, val);
1175
1176         /* Enable/disable rx PAUSE. */
1177         bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
1178
1179         if (bp->flow_ctrl & FLOW_CTRL_RX)
1180                 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
1181         REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
1182
1183         /* Enable/disable tx PAUSE. */
1184         val = REG_RD(bp, BNX2_EMAC_TX_MODE);
1185         val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
1186
1187         if (bp->flow_ctrl & FLOW_CTRL_TX)
1188                 val |= BNX2_EMAC_TX_MODE_FLOW_EN;
1189         REG_WR(bp, BNX2_EMAC_TX_MODE, val);
1190
1191         /* Acknowledge the interrupt. */
1192         REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
1193
1194         if (CHIP_NUM(bp) == CHIP_NUM_5709)
1195                 bnx2_init_all_rx_contexts(bp);
1196
1197         return 0;
1198 }
1199
1200 static void
1201 bnx2_enable_bmsr1(struct bnx2 *bp)
1202 {
1203         if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1204             (CHIP_NUM(bp) == CHIP_NUM_5709))
1205                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1206                                MII_BNX2_BLK_ADDR_GP_STATUS);
1207 }
1208
1209 static void
1210 bnx2_disable_bmsr1(struct bnx2 *bp)
1211 {
1212         if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1213             (CHIP_NUM(bp) == CHIP_NUM_5709))
1214                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1215                                MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1216 }
1217
1218 static int
1219 bnx2_test_and_enable_2g5(struct bnx2 *bp)
1220 {
1221         u32 up1;
1222         int ret = 1;
1223
1224         if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1225                 return 0;
1226
1227         if (bp->autoneg & AUTONEG_SPEED)
1228                 bp->advertising |= ADVERTISED_2500baseX_Full;
1229
1230         if (CHIP_NUM(bp) == CHIP_NUM_5709)
1231                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1232
1233         bnx2_read_phy(bp, bp->mii_up1, &up1);
1234         if (!(up1 & BCM5708S_UP1_2G5)) {
1235                 up1 |= BCM5708S_UP1_2G5;
1236                 bnx2_write_phy(bp, bp->mii_up1, up1);
1237                 ret = 0;
1238         }
1239
1240         if (CHIP_NUM(bp) == CHIP_NUM_5709)
1241                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1242                                MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1243
1244         return ret;
1245 }
1246
1247 static int
1248 bnx2_test_and_disable_2g5(struct bnx2 *bp)
1249 {
1250         u32 up1;
1251         int ret = 0;
1252
1253         if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1254                 return 0;
1255
1256         if (CHIP_NUM(bp) == CHIP_NUM_5709)
1257                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1258
1259         bnx2_read_phy(bp, bp->mii_up1, &up1);
1260         if (up1 & BCM5708S_UP1_2G5) {
1261                 up1 &= ~BCM5708S_UP1_2G5;
1262                 bnx2_write_phy(bp, bp->mii_up1, up1);
1263                 ret = 1;
1264         }
1265
1266         if (CHIP_NUM(bp) == CHIP_NUM_5709)
1267                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1268                                MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1269
1270         return ret;
1271 }
1272
1273 static void
1274 bnx2_enable_forced_2g5(struct bnx2 *bp)
1275 {
1276         u32 bmcr;
1277
1278         if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1279                 return;
1280
1281         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1282                 u32 val;
1283
1284                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1285                                MII_BNX2_BLK_ADDR_SERDES_DIG);
1286                 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
1287                 val &= ~MII_BNX2_SD_MISC1_FORCE_MSK;
1288                 val |= MII_BNX2_SD_MISC1_FORCE | MII_BNX2_SD_MISC1_FORCE_2_5G;
1289                 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1290
1291                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1292                                MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1293                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1294
1295         } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1296                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1297                 bmcr |= BCM5708S_BMCR_FORCE_2500;
1298         }
1299
1300         if (bp->autoneg & AUTONEG_SPEED) {
1301                 bmcr &= ~BMCR_ANENABLE;
1302                 if (bp->req_duplex == DUPLEX_FULL)
1303                         bmcr |= BMCR_FULLDPLX;
1304         }
1305         bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1306 }
1307
1308 static void
1309 bnx2_disable_forced_2g5(struct bnx2 *bp)
1310 {
1311         u32 bmcr;
1312
1313         if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1314                 return;
1315
1316         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1317                 u32 val;
1318
1319                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1320                                MII_BNX2_BLK_ADDR_SERDES_DIG);
1321                 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
1322                 val &= ~MII_BNX2_SD_MISC1_FORCE;
1323                 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1324
1325                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1326                                MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1327                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1328
1329         } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1330                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1331                 bmcr &= ~BCM5708S_BMCR_FORCE_2500;
1332         }
1333
1334         if (bp->autoneg & AUTONEG_SPEED)
1335                 bmcr |= BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_ANRESTART;
1336         bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1337 }
1338
1339 static void
1340 bnx2_5706s_force_link_dn(struct bnx2 *bp, int start)
1341 {
1342         u32 val;
1343
1344         bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_SERDES_CTL);
1345         bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
1346         if (start)
1347                 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val & 0xff0f);
1348         else
1349                 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val | 0xc0);
1350 }
1351
1352 static int
1353 bnx2_set_link(struct bnx2 *bp)
1354 {
1355         u32 bmsr;
1356         u8 link_up;
1357
1358         if (bp->loopback == MAC_LOOPBACK || bp->loopback == PHY_LOOPBACK) {
1359                 bp->link_up = 1;
1360                 return 0;
1361         }
1362
1363         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
1364                 return 0;
1365
1366         link_up = bp->link_up;
1367
1368         bnx2_enable_bmsr1(bp);
1369         bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1370         bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1371         bnx2_disable_bmsr1(bp);
1372
1373         if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1374             (CHIP_NUM(bp) == CHIP_NUM_5706)) {
1375                 u32 val, an_dbg;
1376
1377                 if (bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN) {
1378                         bnx2_5706s_force_link_dn(bp, 0);
1379                         bp->phy_flags &= ~BNX2_PHY_FLAG_FORCED_DOWN;
1380                 }
1381                 val = REG_RD(bp, BNX2_EMAC_STATUS);
1382
1383                 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
1384                 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1385                 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1386
1387                 if ((val & BNX2_EMAC_STATUS_LINK) &&
1388                     !(an_dbg & MISC_SHDW_AN_DBG_NOSYNC))
1389                         bmsr |= BMSR_LSTATUS;
1390                 else
1391                         bmsr &= ~BMSR_LSTATUS;
1392         }
1393
1394         if (bmsr & BMSR_LSTATUS) {
1395                 bp->link_up = 1;
1396
1397                 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1398                         if (CHIP_NUM(bp) == CHIP_NUM_5706)
1399                                 bnx2_5706s_linkup(bp);
1400                         else if (CHIP_NUM(bp) == CHIP_NUM_5708)
1401                                 bnx2_5708s_linkup(bp);
1402                         else if (CHIP_NUM(bp) == CHIP_NUM_5709)
1403                                 bnx2_5709s_linkup(bp);
1404                 }
1405                 else {
1406                         bnx2_copper_linkup(bp);
1407                 }
1408                 bnx2_resolve_flow_ctrl(bp);
1409         }
1410         else {
1411                 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1412                     (bp->autoneg & AUTONEG_SPEED))
1413                         bnx2_disable_forced_2g5(bp);
1414
1415                 if (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT) {
1416                         u32 bmcr;
1417
1418                         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1419                         bmcr |= BMCR_ANENABLE;
1420                         bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1421
1422                         bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
1423                 }
1424                 bp->link_up = 0;
1425         }
1426
1427         if (bp->link_up != link_up) {
1428                 bnx2_report_link(bp);
1429         }
1430
1431         bnx2_set_mac_link(bp);
1432
1433         return 0;
1434 }
1435
1436 static int
1437 bnx2_reset_phy(struct bnx2 *bp)
1438 {
1439         int i;
1440         u32 reg;
1441
1442         bnx2_write_phy(bp, bp->mii_bmcr, BMCR_RESET);
1443
1444 #define PHY_RESET_MAX_WAIT 100
1445         for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
1446                 udelay(10);
1447
1448                 bnx2_read_phy(bp, bp->mii_bmcr, &reg);
1449                 if (!(reg & BMCR_RESET)) {
1450                         udelay(20);
1451                         break;
1452                 }
1453         }
1454         if (i == PHY_RESET_MAX_WAIT) {
1455                 return -EBUSY;
1456         }
1457         return 0;
1458 }
1459
1460 static u32
1461 bnx2_phy_get_pause_adv(struct bnx2 *bp)
1462 {
1463         u32 adv = 0;
1464
1465         if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
1466                 (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
1467
1468                 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1469                         adv = ADVERTISE_1000XPAUSE;
1470                 }
1471                 else {
1472                         adv = ADVERTISE_PAUSE_CAP;
1473                 }
1474         }
1475         else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
1476                 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1477                         adv = ADVERTISE_1000XPSE_ASYM;
1478                 }
1479                 else {
1480                         adv = ADVERTISE_PAUSE_ASYM;
1481                 }
1482         }
1483         else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
1484                 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1485                         adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1486                 }
1487                 else {
1488                         adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1489                 }
1490         }
1491         return adv;
1492 }
1493
1494 static int bnx2_fw_sync(struct bnx2 *, u32, int, int);
1495
1496 static int
1497 bnx2_setup_remote_phy(struct bnx2 *bp, u8 port)
1498 {
1499         u32 speed_arg = 0, pause_adv;
1500
1501         pause_adv = bnx2_phy_get_pause_adv(bp);
1502
1503         if (bp->autoneg & AUTONEG_SPEED) {
1504                 speed_arg |= BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG;
1505                 if (bp->advertising & ADVERTISED_10baseT_Half)
1506                         speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1507                 if (bp->advertising & ADVERTISED_10baseT_Full)
1508                         speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1509                 if (bp->advertising & ADVERTISED_100baseT_Half)
1510                         speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1511                 if (bp->advertising & ADVERTISED_100baseT_Full)
1512                         speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1513                 if (bp->advertising & ADVERTISED_1000baseT_Full)
1514                         speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1515                 if (bp->advertising & ADVERTISED_2500baseX_Full)
1516                         speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1517         } else {
1518                 if (bp->req_line_speed == SPEED_2500)
1519                         speed_arg = BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1520                 else if (bp->req_line_speed == SPEED_1000)
1521                         speed_arg = BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1522                 else if (bp->req_line_speed == SPEED_100) {
1523                         if (bp->req_duplex == DUPLEX_FULL)
1524                                 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1525                         else
1526                                 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1527                 } else if (bp->req_line_speed == SPEED_10) {
1528                         if (bp->req_duplex == DUPLEX_FULL)
1529                                 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1530                         else
1531                                 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1532                 }
1533         }
1534
1535         if (pause_adv & (ADVERTISE_1000XPAUSE | ADVERTISE_PAUSE_CAP))
1536                 speed_arg |= BNX2_NETLINK_SET_LINK_FC_SYM_PAUSE;
1537         if (pause_adv & (ADVERTISE_1000XPSE_ASYM | ADVERTISE_PAUSE_ASYM))
1538                 speed_arg |= BNX2_NETLINK_SET_LINK_FC_ASYM_PAUSE;
1539
1540         if (port == PORT_TP)
1541                 speed_arg |= BNX2_NETLINK_SET_LINK_PHY_APP_REMOTE |
1542                              BNX2_NETLINK_SET_LINK_ETH_AT_WIRESPEED;
1543
1544         bnx2_shmem_wr(bp, BNX2_DRV_MB_ARG0, speed_arg);
1545
1546         spin_unlock_bh(&bp->phy_lock);
1547         bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_CMD_SET_LINK, 1, 0);
1548         spin_lock_bh(&bp->phy_lock);
1549
1550         return 0;
1551 }
1552
1553 static int
1554 bnx2_setup_serdes_phy(struct bnx2 *bp, u8 port)
1555 {
1556         u32 adv, bmcr;
1557         u32 new_adv = 0;
1558
1559         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
1560                 return (bnx2_setup_remote_phy(bp, port));
1561
1562         if (!(bp->autoneg & AUTONEG_SPEED)) {
1563                 u32 new_bmcr;
1564                 int force_link_down = 0;
1565
1566                 if (bp->req_line_speed == SPEED_2500) {
1567                         if (!bnx2_test_and_enable_2g5(bp))
1568                                 force_link_down = 1;
1569                 } else if (bp->req_line_speed == SPEED_1000) {
1570                         if (bnx2_test_and_disable_2g5(bp))
1571                                 force_link_down = 1;
1572                 }
1573                 bnx2_read_phy(bp, bp->mii_adv, &adv);
1574                 adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
1575
1576                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1577                 new_bmcr = bmcr & ~BMCR_ANENABLE;
1578                 new_bmcr |= BMCR_SPEED1000;
1579
1580                 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1581                         if (bp->req_line_speed == SPEED_2500)
1582                                 bnx2_enable_forced_2g5(bp);
1583                         else if (bp->req_line_speed == SPEED_1000) {
1584                                 bnx2_disable_forced_2g5(bp);
1585                                 new_bmcr &= ~0x2000;
1586                         }
1587
1588                 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1589                         if (bp->req_line_speed == SPEED_2500)
1590                                 new_bmcr |= BCM5708S_BMCR_FORCE_2500;
1591                         else
1592                                 new_bmcr = bmcr & ~BCM5708S_BMCR_FORCE_2500;
1593                 }
1594
1595                 if (bp->req_duplex == DUPLEX_FULL) {
1596                         adv |= ADVERTISE_1000XFULL;
1597                         new_bmcr |= BMCR_FULLDPLX;
1598                 }
1599                 else {
1600                         adv |= ADVERTISE_1000XHALF;
1601                         new_bmcr &= ~BMCR_FULLDPLX;
1602                 }
1603                 if ((new_bmcr != bmcr) || (force_link_down)) {
1604                         /* Force a link down visible on the other side */
1605                         if (bp->link_up) {
1606                                 bnx2_write_phy(bp, bp->mii_adv, adv &
1607                                                ~(ADVERTISE_1000XFULL |
1608                                                  ADVERTISE_1000XHALF));
1609                                 bnx2_write_phy(bp, bp->mii_bmcr, bmcr |
1610                                         BMCR_ANRESTART | BMCR_ANENABLE);
1611
1612                                 bp->link_up = 0;
1613                                 netif_carrier_off(bp->dev);
1614                                 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1615                                 bnx2_report_link(bp);
1616                         }
1617                         bnx2_write_phy(bp, bp->mii_adv, adv);
1618                         bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1619                 } else {
1620                         bnx2_resolve_flow_ctrl(bp);
1621                         bnx2_set_mac_link(bp);
1622                 }
1623                 return 0;
1624         }
1625
1626         bnx2_test_and_enable_2g5(bp);
1627
1628         if (bp->advertising & ADVERTISED_1000baseT_Full)
1629                 new_adv |= ADVERTISE_1000XFULL;
1630
1631         new_adv |= bnx2_phy_get_pause_adv(bp);
1632
1633         bnx2_read_phy(bp, bp->mii_adv, &adv);
1634         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1635
1636         bp->serdes_an_pending = 0;
1637         if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
1638                 /* Force a link down visible on the other side */
1639                 if (bp->link_up) {
1640                         bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
1641                         spin_unlock_bh(&bp->phy_lock);
1642                         msleep(20);
1643                         spin_lock_bh(&bp->phy_lock);
1644                 }
1645
1646                 bnx2_write_phy(bp, bp->mii_adv, new_adv);
1647                 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART |
1648                         BMCR_ANENABLE);
1649                 /* Speed up link-up time when the link partner
1650                  * does not autonegotiate which is very common
1651                  * in blade servers. Some blade servers use
1652                  * IPMI for kerboard input and it's important
1653                  * to minimize link disruptions. Autoneg. involves
1654                  * exchanging base pages plus 3 next pages and
1655                  * normally completes in about 120 msec.
1656                  */
1657                 bp->current_interval = SERDES_AN_TIMEOUT;
1658                 bp->serdes_an_pending = 1;
1659                 mod_timer(&bp->timer, jiffies + bp->current_interval);
1660         } else {
1661                 bnx2_resolve_flow_ctrl(bp);
1662                 bnx2_set_mac_link(bp);
1663         }
1664
1665         return 0;
1666 }
1667
1668 #define ETHTOOL_ALL_FIBRE_SPEED                                         \
1669         (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ?                  \
1670                 (ADVERTISED_2500baseX_Full | ADVERTISED_1000baseT_Full) :\
1671                 (ADVERTISED_1000baseT_Full)
1672
1673 #define ETHTOOL_ALL_COPPER_SPEED                                        \
1674         (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |            \
1675         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |           \
1676         ADVERTISED_1000baseT_Full)
1677
1678 #define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
1679         ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
1680
1681 #define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
1682
1683 static void
1684 bnx2_set_default_remote_link(struct bnx2 *bp)
1685 {
1686         u32 link;
1687
1688         if (bp->phy_port == PORT_TP)
1689                 link = bnx2_shmem_rd(bp, BNX2_RPHY_COPPER_LINK);
1690         else
1691                 link = bnx2_shmem_rd(bp, BNX2_RPHY_SERDES_LINK);
1692
1693         if (link & BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG) {
1694                 bp->req_line_speed = 0;
1695                 bp->autoneg |= AUTONEG_SPEED;
1696                 bp->advertising = ADVERTISED_Autoneg;
1697                 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1698                         bp->advertising |= ADVERTISED_10baseT_Half;
1699                 if (link & BNX2_NETLINK_SET_LINK_SPEED_10FULL)
1700                         bp->advertising |= ADVERTISED_10baseT_Full;
1701                 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1702                         bp->advertising |= ADVERTISED_100baseT_Half;
1703                 if (link & BNX2_NETLINK_SET_LINK_SPEED_100FULL)
1704                         bp->advertising |= ADVERTISED_100baseT_Full;
1705                 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1706                         bp->advertising |= ADVERTISED_1000baseT_Full;
1707                 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1708                         bp->advertising |= ADVERTISED_2500baseX_Full;
1709         } else {
1710                 bp->autoneg = 0;
1711                 bp->advertising = 0;
1712                 bp->req_duplex = DUPLEX_FULL;
1713                 if (link & BNX2_NETLINK_SET_LINK_SPEED_10) {
1714                         bp->req_line_speed = SPEED_10;
1715                         if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1716                                 bp->req_duplex = DUPLEX_HALF;
1717                 }
1718                 if (link & BNX2_NETLINK_SET_LINK_SPEED_100) {
1719                         bp->req_line_speed = SPEED_100;
1720                         if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1721                                 bp->req_duplex = DUPLEX_HALF;
1722                 }
1723                 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1724                         bp->req_line_speed = SPEED_1000;
1725                 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1726                         bp->req_line_speed = SPEED_2500;
1727         }
1728 }
1729
1730 static void
1731 bnx2_set_default_link(struct bnx2 *bp)
1732 {
1733         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
1734                 bnx2_set_default_remote_link(bp);
1735                 return;
1736         }
1737
1738         bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
1739         bp->req_line_speed = 0;
1740         if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1741                 u32 reg;
1742
1743                 bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
1744
1745                 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG);
1746                 reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
1747                 if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
1748                         bp->autoneg = 0;
1749                         bp->req_line_speed = bp->line_speed = SPEED_1000;
1750                         bp->req_duplex = DUPLEX_FULL;
1751                 }
1752         } else
1753                 bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
1754 }
1755
1756 static void
1757 bnx2_send_heart_beat(struct bnx2 *bp)
1758 {
1759         u32 msg;
1760         u32 addr;
1761
1762         spin_lock(&bp->indirect_lock);
1763         msg = (u32) (++bp->fw_drv_pulse_wr_seq & BNX2_DRV_PULSE_SEQ_MASK);
1764         addr = bp->shmem_base + BNX2_DRV_PULSE_MB;
1765         REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, addr);
1766         REG_WR(bp, BNX2_PCICFG_REG_WINDOW, msg);
1767         spin_unlock(&bp->indirect_lock);
1768 }
1769
1770 static void
1771 bnx2_remote_phy_event(struct bnx2 *bp)
1772 {
1773         u32 msg;
1774         u8 link_up = bp->link_up;
1775         u8 old_port;
1776
1777         msg = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
1778
1779         if (msg & BNX2_LINK_STATUS_HEART_BEAT_EXPIRED)
1780                 bnx2_send_heart_beat(bp);
1781
1782         msg &= ~BNX2_LINK_STATUS_HEART_BEAT_EXPIRED;
1783
1784         if ((msg & BNX2_LINK_STATUS_LINK_UP) == BNX2_LINK_STATUS_LINK_DOWN)
1785                 bp->link_up = 0;
1786         else {
1787                 u32 speed;
1788
1789                 bp->link_up = 1;
1790                 speed = msg & BNX2_LINK_STATUS_SPEED_MASK;
1791                 bp->duplex = DUPLEX_FULL;
1792                 switch (speed) {
1793                         case BNX2_LINK_STATUS_10HALF:
1794                                 bp->duplex = DUPLEX_HALF;
1795                         case BNX2_LINK_STATUS_10FULL:
1796                                 bp->line_speed = SPEED_10;
1797                                 break;
1798                         case BNX2_LINK_STATUS_100HALF:
1799                                 bp->duplex = DUPLEX_HALF;
1800                         case BNX2_LINK_STATUS_100BASE_T4:
1801                         case BNX2_LINK_STATUS_100FULL:
1802                                 bp->line_speed = SPEED_100;
1803                                 break;
1804                         case BNX2_LINK_STATUS_1000HALF:
1805                                 bp->duplex = DUPLEX_HALF;
1806                         case BNX2_LINK_STATUS_1000FULL:
1807                                 bp->line_speed = SPEED_1000;
1808                                 break;
1809                         case BNX2_LINK_STATUS_2500HALF:
1810                                 bp->duplex = DUPLEX_HALF;
1811                         case BNX2_LINK_STATUS_2500FULL:
1812                                 bp->line_speed = SPEED_2500;
1813                                 break;
1814                         default:
1815                                 bp->line_speed = 0;
1816                                 break;
1817                 }
1818
1819                 bp->flow_ctrl = 0;
1820                 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
1821                     (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
1822                         if (bp->duplex == DUPLEX_FULL)
1823                                 bp->flow_ctrl = bp->req_flow_ctrl;
1824                 } else {
1825                         if (msg & BNX2_LINK_STATUS_TX_FC_ENABLED)
1826                                 bp->flow_ctrl |= FLOW_CTRL_TX;
1827                         if (msg & BNX2_LINK_STATUS_RX_FC_ENABLED)
1828                                 bp->flow_ctrl |= FLOW_CTRL_RX;
1829                 }
1830
1831                 old_port = bp->phy_port;
1832                 if (msg & BNX2_LINK_STATUS_SERDES_LINK)
1833                         bp->phy_port = PORT_FIBRE;
1834                 else
1835                         bp->phy_port = PORT_TP;
1836
1837                 if (old_port != bp->phy_port)
1838                         bnx2_set_default_link(bp);
1839
1840         }
1841         if (bp->link_up != link_up)
1842                 bnx2_report_link(bp);
1843
1844         bnx2_set_mac_link(bp);
1845 }
1846
1847 static int
1848 bnx2_set_remote_link(struct bnx2 *bp)
1849 {
1850         u32 evt_code;
1851
1852         evt_code = bnx2_shmem_rd(bp, BNX2_FW_EVT_CODE_MB);
1853         switch (evt_code) {
1854                 case BNX2_FW_EVT_CODE_LINK_EVENT:
1855                         bnx2_remote_phy_event(bp);
1856                         break;
1857                 case BNX2_FW_EVT_CODE_SW_TIMER_EXPIRATION_EVENT:
1858                 default:
1859                         bnx2_send_heart_beat(bp);
1860                         break;
1861         }
1862         return 0;
1863 }
1864
1865 static int
1866 bnx2_setup_copper_phy(struct bnx2 *bp)
1867 {
1868         u32 bmcr;
1869         u32 new_bmcr;
1870
1871         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1872
1873         if (bp->autoneg & AUTONEG_SPEED) {
1874                 u32 adv_reg, adv1000_reg;
1875                 u32 new_adv_reg = 0;
1876                 u32 new_adv1000_reg = 0;
1877
1878                 bnx2_read_phy(bp, bp->mii_adv, &adv_reg);
1879                 adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
1880                         ADVERTISE_PAUSE_ASYM);
1881
1882                 bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
1883                 adv1000_reg &= PHY_ALL_1000_SPEED;
1884
1885                 if (bp->advertising & ADVERTISED_10baseT_Half)
1886                         new_adv_reg |= ADVERTISE_10HALF;
1887                 if (bp->advertising & ADVERTISED_10baseT_Full)
1888                         new_adv_reg |= ADVERTISE_10FULL;
1889                 if (bp->advertising & ADVERTISED_100baseT_Half)
1890                         new_adv_reg |= ADVERTISE_100HALF;
1891                 if (bp->advertising & ADVERTISED_100baseT_Full)
1892                         new_adv_reg |= ADVERTISE_100FULL;
1893                 if (bp->advertising & ADVERTISED_1000baseT_Full)
1894                         new_adv1000_reg |= ADVERTISE_1000FULL;
1895
1896                 new_adv_reg |= ADVERTISE_CSMA;
1897
1898                 new_adv_reg |= bnx2_phy_get_pause_adv(bp);
1899
1900                 if ((adv1000_reg != new_adv1000_reg) ||
1901                         (adv_reg != new_adv_reg) ||
1902                         ((bmcr & BMCR_ANENABLE) == 0)) {
1903
1904                         bnx2_write_phy(bp, bp->mii_adv, new_adv_reg);
1905                         bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg);
1906                         bnx2_write_phy(bp, bp->mii_bmcr, BMCR_ANRESTART |
1907                                 BMCR_ANENABLE);
1908                 }
1909                 else if (bp->link_up) {
1910                         /* Flow ctrl may have changed from auto to forced */
1911                         /* or vice-versa. */
1912
1913                         bnx2_resolve_flow_ctrl(bp);
1914                         bnx2_set_mac_link(bp);
1915                 }
1916                 return 0;
1917         }
1918
1919         new_bmcr = 0;
1920         if (bp->req_line_speed == SPEED_100) {
1921                 new_bmcr |= BMCR_SPEED100;
1922         }
1923         if (bp->req_duplex == DUPLEX_FULL) {
1924                 new_bmcr |= BMCR_FULLDPLX;
1925         }
1926         if (new_bmcr != bmcr) {
1927                 u32 bmsr;
1928
1929                 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1930                 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1931
1932                 if (bmsr & BMSR_LSTATUS) {
1933                         /* Force link down */
1934                         bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
1935                         spin_unlock_bh(&bp->phy_lock);
1936                         msleep(50);
1937                         spin_lock_bh(&bp->phy_lock);
1938
1939                         bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1940                         bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1941                 }
1942
1943                 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1944
1945                 /* Normally, the new speed is setup after the link has
1946                  * gone down and up again. In some cases, link will not go
1947                  * down so we need to set up the new speed here.
1948                  */
1949                 if (bmsr & BMSR_LSTATUS) {
1950                         bp->line_speed = bp->req_line_speed;
1951                         bp->duplex = bp->req_duplex;
1952                         bnx2_resolve_flow_ctrl(bp);
1953                         bnx2_set_mac_link(bp);
1954                 }
1955         } else {
1956                 bnx2_resolve_flow_ctrl(bp);
1957                 bnx2_set_mac_link(bp);
1958         }
1959         return 0;
1960 }
1961
1962 static int
1963 bnx2_setup_phy(struct bnx2 *bp, u8 port)
1964 {
1965         if (bp->loopback == MAC_LOOPBACK)
1966                 return 0;
1967
1968         if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1969                 return (bnx2_setup_serdes_phy(bp, port));
1970         }
1971         else {
1972                 return (bnx2_setup_copper_phy(bp));
1973         }
1974 }
1975
1976 static int
1977 bnx2_init_5709s_phy(struct bnx2 *bp, int reset_phy)
1978 {
1979         u32 val;
1980
1981         bp->mii_bmcr = MII_BMCR + 0x10;
1982         bp->mii_bmsr = MII_BMSR + 0x10;
1983         bp->mii_bmsr1 = MII_BNX2_GP_TOP_AN_STATUS1;
1984         bp->mii_adv = MII_ADVERTISE + 0x10;
1985         bp->mii_lpa = MII_LPA + 0x10;
1986         bp->mii_up1 = MII_BNX2_OVER1G_UP1;
1987
1988         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_AER);
1989         bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD);
1990
1991         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1992         if (reset_phy)
1993                 bnx2_reset_phy(bp);
1994
1995         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG);
1996
1997         bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, &val);
1998         val &= ~MII_BNX2_SD_1000XCTL1_AUTODET;
1999         val |= MII_BNX2_SD_1000XCTL1_FIBER;
2000         bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val);
2001
2002         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
2003         bnx2_read_phy(bp, MII_BNX2_OVER1G_UP1, &val);
2004         if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
2005                 val |= BCM5708S_UP1_2G5;
2006         else
2007                 val &= ~BCM5708S_UP1_2G5;
2008         bnx2_write_phy(bp, MII_BNX2_OVER1G_UP1, val);
2009
2010         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_BAM_NXTPG);
2011         bnx2_read_phy(bp, MII_BNX2_BAM_NXTPG_CTL, &val);
2012         val |= MII_BNX2_NXTPG_CTL_T2 | MII_BNX2_NXTPG_CTL_BAM;
2013         bnx2_write_phy(bp, MII_BNX2_BAM_NXTPG_CTL, val);
2014
2015         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_CL73_USERB0);
2016
2017         val = MII_BNX2_CL73_BAM_EN | MII_BNX2_CL73_BAM_STA_MGR_EN |
2018               MII_BNX2_CL73_BAM_NP_AFT_BP_EN;
2019         bnx2_write_phy(bp, MII_BNX2_CL73_BAM_CTL1, val);
2020
2021         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
2022
2023         return 0;
2024 }
2025
2026 static int
2027 bnx2_init_5708s_phy(struct bnx2 *bp, int reset_phy)
2028 {
2029         u32 val;
2030
2031         if (reset_phy)
2032                 bnx2_reset_phy(bp);
2033
2034         bp->mii_up1 = BCM5708S_UP1;
2035
2036         bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
2037         bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
2038         bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
2039
2040         bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
2041         val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
2042         bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
2043
2044         bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
2045         val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
2046         bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
2047
2048         if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) {
2049                 bnx2_read_phy(bp, BCM5708S_UP1, &val);
2050                 val |= BCM5708S_UP1_2G5;
2051                 bnx2_write_phy(bp, BCM5708S_UP1, val);
2052         }
2053
2054         if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
2055             (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
2056             (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
2057                 /* increase tx signal amplitude */
2058                 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2059                                BCM5708S_BLK_ADDR_TX_MISC);
2060                 bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
2061                 val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
2062                 bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
2063                 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
2064         }
2065
2066         val = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG) &
2067               BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
2068
2069         if (val) {
2070                 u32 is_backplane;
2071
2072                 is_backplane = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
2073                 if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
2074                         bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2075                                        BCM5708S_BLK_ADDR_TX_MISC);
2076                         bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
2077                         bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2078                                        BCM5708S_BLK_ADDR_DIG);
2079                 }
2080         }
2081         return 0;
2082 }
2083
2084 static int
2085 bnx2_init_5706s_phy(struct bnx2 *bp, int reset_phy)
2086 {
2087         if (reset_phy)
2088                 bnx2_reset_phy(bp);
2089
2090         bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
2091
2092         if (CHIP_NUM(bp) == CHIP_NUM_5706)
2093                 REG_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300);
2094
2095         if (bp->dev->mtu > 1500) {
2096                 u32 val;
2097
2098                 /* Set extended packet length bit */
2099                 bnx2_write_phy(bp, 0x18, 0x7);
2100                 bnx2_read_phy(bp, 0x18, &val);
2101                 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
2102
2103                 bnx2_write_phy(bp, 0x1c, 0x6c00);
2104                 bnx2_read_phy(bp, 0x1c, &val);
2105                 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
2106         }
2107         else {
2108                 u32 val;
2109
2110                 bnx2_write_phy(bp, 0x18, 0x7);
2111                 bnx2_read_phy(bp, 0x18, &val);
2112                 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2113
2114                 bnx2_write_phy(bp, 0x1c, 0x6c00);
2115                 bnx2_read_phy(bp, 0x1c, &val);
2116                 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
2117         }
2118
2119         return 0;
2120 }
2121
2122 static int
2123 bnx2_init_copper_phy(struct bnx2 *bp, int reset_phy)
2124 {
2125         u32 val;
2126
2127         if (reset_phy)
2128                 bnx2_reset_phy(bp);
2129
2130         if (bp->phy_flags & BNX2_PHY_FLAG_CRC_FIX) {
2131                 bnx2_write_phy(bp, 0x18, 0x0c00);
2132                 bnx2_write_phy(bp, 0x17, 0x000a);
2133                 bnx2_write_phy(bp, 0x15, 0x310b);
2134                 bnx2_write_phy(bp, 0x17, 0x201f);
2135                 bnx2_write_phy(bp, 0x15, 0x9506);
2136                 bnx2_write_phy(bp, 0x17, 0x401f);
2137                 bnx2_write_phy(bp, 0x15, 0x14e2);
2138                 bnx2_write_phy(bp, 0x18, 0x0400);
2139         }
2140
2141         if (bp->phy_flags & BNX2_PHY_FLAG_DIS_EARLY_DAC) {
2142                 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS,
2143                                MII_BNX2_DSP_EXPAND_REG | 0x8);
2144                 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
2145                 val &= ~(1 << 8);
2146                 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val);
2147         }
2148
2149         if (bp->dev->mtu > 1500) {
2150                 /* Set extended packet length bit */
2151                 bnx2_write_phy(bp, 0x18, 0x7);
2152                 bnx2_read_phy(bp, 0x18, &val);
2153                 bnx2_write_phy(bp, 0x18, val | 0x4000);
2154
2155                 bnx2_read_phy(bp, 0x10, &val);
2156                 bnx2_write_phy(bp, 0x10, val | 0x1);
2157         }
2158         else {
2159                 bnx2_write_phy(bp, 0x18, 0x7);
2160                 bnx2_read_phy(bp, 0x18, &val);
2161                 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2162
2163                 bnx2_read_phy(bp, 0x10, &val);
2164                 bnx2_write_phy(bp, 0x10, val & ~0x1);
2165         }
2166
2167         /* ethernet@wirespeed */
2168         bnx2_write_phy(bp, 0x18, 0x7007);
2169         bnx2_read_phy(bp, 0x18, &val);
2170         bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4));
2171         return 0;
2172 }
2173
2174
2175 static int
2176 bnx2_init_phy(struct bnx2 *bp, int reset_phy)
2177 {
2178         u32 val;
2179         int rc = 0;
2180
2181         bp->phy_flags &= ~BNX2_PHY_FLAG_INT_MODE_MASK;
2182         bp->phy_flags |= BNX2_PHY_FLAG_INT_MODE_LINK_READY;
2183
2184         bp->mii_bmcr = MII_BMCR;
2185         bp->mii_bmsr = MII_BMSR;
2186         bp->mii_bmsr1 = MII_BMSR;
2187         bp->mii_adv = MII_ADVERTISE;
2188         bp->mii_lpa = MII_LPA;
2189
2190         REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
2191
2192         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
2193                 goto setup_phy;
2194
2195         bnx2_read_phy(bp, MII_PHYSID1, &val);
2196         bp->phy_id = val << 16;
2197         bnx2_read_phy(bp, MII_PHYSID2, &val);
2198         bp->phy_id |= val & 0xffff;
2199
2200         if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
2201                 if (CHIP_NUM(bp) == CHIP_NUM_5706)
2202                         rc = bnx2_init_5706s_phy(bp, reset_phy);
2203                 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
2204                         rc = bnx2_init_5708s_phy(bp, reset_phy);
2205                 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
2206                         rc = bnx2_init_5709s_phy(bp, reset_phy);
2207         }
2208         else {
2209                 rc = bnx2_init_copper_phy(bp, reset_phy);
2210         }
2211
2212 setup_phy:
2213         if (!rc)
2214                 rc = bnx2_setup_phy(bp, bp->phy_port);
2215
2216         return rc;
2217 }
2218
2219 static int
2220 bnx2_set_mac_loopback(struct bnx2 *bp)
2221 {
2222         u32 mac_mode;
2223
2224         mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2225         mac_mode &= ~BNX2_EMAC_MODE_PORT;
2226         mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
2227         REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2228         bp->link_up = 1;
2229         return 0;
2230 }
2231
2232 static int bnx2_test_link(struct bnx2 *);
2233
2234 static int
2235 bnx2_set_phy_loopback(struct bnx2 *bp)
2236 {
2237         u32 mac_mode;
2238         int rc, i;
2239
2240         spin_lock_bh(&bp->phy_lock);
2241         rc = bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK | BMCR_FULLDPLX |
2242                             BMCR_SPEED1000);
2243         spin_unlock_bh(&bp->phy_lock);
2244         if (rc)
2245                 return rc;
2246
2247         for (i = 0; i < 10; i++) {
2248                 if (bnx2_test_link(bp) == 0)
2249                         break;
2250                 msleep(100);
2251         }
2252
2253         mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2254         mac_mode &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
2255                       BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
2256                       BNX2_EMAC_MODE_25G_MODE);
2257
2258         mac_mode |= BNX2_EMAC_MODE_PORT_GMII;
2259         REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2260         bp->link_up = 1;
2261         return 0;
2262 }
2263
2264 static int
2265 bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int ack, int silent)
2266 {
2267         int i;
2268         u32 val;
2269
2270         bp->fw_wr_seq++;
2271         msg_data |= bp->fw_wr_seq;
2272
2273         bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
2274
2275         if (!ack)
2276                 return 0;
2277
2278         /* wait for an acknowledgement. */
2279         for (i = 0; i < (FW_ACK_TIME_OUT_MS / 10); i++) {
2280                 msleep(10);
2281
2282                 val = bnx2_shmem_rd(bp, BNX2_FW_MB);
2283
2284                 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
2285                         break;
2286         }
2287         if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0)
2288                 return 0;
2289
2290         /* If we timed out, inform the firmware that this is the case. */
2291         if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) {
2292                 if (!silent)
2293                         printk(KERN_ERR PFX "fw sync timeout, reset code = "
2294                                             "%x\n", msg_data);
2295
2296                 msg_data &= ~BNX2_DRV_MSG_CODE;
2297                 msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
2298
2299                 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
2300
2301                 return -EBUSY;
2302         }
2303
2304         if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK)
2305                 return -EIO;
2306
2307         return 0;
2308 }
2309
2310 static int
2311 bnx2_init_5709_context(struct bnx2 *bp)
2312 {
2313         int i, ret = 0;
2314         u32 val;
2315
2316         val = BNX2_CTX_COMMAND_ENABLED | BNX2_CTX_COMMAND_MEM_INIT | (1 << 12);
2317         val |= (BCM_PAGE_BITS - 8) << 16;
2318         REG_WR(bp, BNX2_CTX_COMMAND, val);
2319         for (i = 0; i < 10; i++) {
2320                 val = REG_RD(bp, BNX2_CTX_COMMAND);
2321                 if (!(val & BNX2_CTX_COMMAND_MEM_INIT))
2322                         break;
2323                 udelay(2);
2324         }
2325         if (val & BNX2_CTX_COMMAND_MEM_INIT)
2326                 return -EBUSY;
2327
2328         for (i = 0; i < bp->ctx_pages; i++) {
2329                 int j;
2330
2331                 if (bp->ctx_blk[i])
2332                         memset(bp->ctx_blk[i], 0, BCM_PAGE_SIZE);
2333                 else
2334                         return -ENOMEM;
2335
2336                 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0,
2337                        (bp->ctx_blk_mapping[i] & 0xffffffff) |
2338                        BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID);
2339                 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1,
2340                        (u64) bp->ctx_blk_mapping[i] >> 32);
2341                 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i |
2342                        BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
2343                 for (j = 0; j < 10; j++) {
2344
2345                         val = REG_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL);
2346                         if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
2347                                 break;
2348                         udelay(5);
2349                 }
2350                 if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
2351                         ret = -EBUSY;
2352                         break;
2353                 }
2354         }
2355         return ret;
2356 }
2357
2358 static void
2359 bnx2_init_context(struct bnx2 *bp)
2360 {
2361         u32 vcid;
2362
2363         vcid = 96;
2364         while (vcid) {
2365                 u32 vcid_addr, pcid_addr, offset;
2366                 int i;
2367
2368                 vcid--;
2369
2370                 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
2371                         u32 new_vcid;
2372
2373                         vcid_addr = GET_PCID_ADDR(vcid);
2374                         if (vcid & 0x8) {
2375                                 new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
2376                         }
2377                         else {
2378                                 new_vcid = vcid;
2379                         }
2380                         pcid_addr = GET_PCID_ADDR(new_vcid);
2381                 }
2382                 else {
2383                         vcid_addr = GET_CID_ADDR(vcid);
2384                         pcid_addr = vcid_addr;
2385                 }
2386
2387                 for (i = 0; i < (CTX_SIZE / PHY_CTX_SIZE); i++) {
2388                         vcid_addr += (i << PHY_CTX_SHIFT);
2389                         pcid_addr += (i << PHY_CTX_SHIFT);
2390
2391                         REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
2392                         REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
2393
2394                         /* Zero out the context. */
2395                         for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
2396                                 bnx2_ctx_wr(bp, vcid_addr, offset, 0);
2397                 }
2398         }
2399 }
2400
2401 static int
2402 bnx2_alloc_bad_rbuf(struct bnx2 *bp)
2403 {
2404         u16 *good_mbuf;
2405         u32 good_mbuf_cnt;
2406         u32 val;
2407
2408         good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL);
2409         if (good_mbuf == NULL) {
2410                 printk(KERN_ERR PFX "Failed to allocate memory in "
2411                                     "bnx2_alloc_bad_rbuf\n");
2412                 return -ENOMEM;
2413         }
2414
2415         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2416                 BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
2417
2418         good_mbuf_cnt = 0;
2419
2420         /* Allocate a bunch of mbufs and save the good ones in an array. */
2421         val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
2422         while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
2423                 bnx2_reg_wr_ind(bp, BNX2_RBUF_COMMAND,
2424                                 BNX2_RBUF_COMMAND_ALLOC_REQ);
2425
2426                 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_FW_BUF_ALLOC);
2427
2428                 val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
2429
2430                 /* The addresses with Bit 9 set are bad memory blocks. */
2431                 if (!(val & (1 << 9))) {
2432                         good_mbuf[good_mbuf_cnt] = (u16) val;
2433                         good_mbuf_cnt++;
2434                 }
2435
2436                 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
2437         }
2438
2439         /* Free the good ones back to the mbuf pool thus discarding
2440          * all the bad ones. */
2441         while (good_mbuf_cnt) {
2442                 good_mbuf_cnt--;
2443
2444                 val = good_mbuf[good_mbuf_cnt];
2445                 val = (val << 9) | val | 1;
2446
2447                 bnx2_reg_wr_ind(bp, BNX2_RBUF_FW_BUF_FREE, val);
2448         }
2449         kfree(good_mbuf);
2450         return 0;
2451 }
2452
2453 static void
2454 bnx2_set_mac_addr(struct bnx2 *bp, u8 *mac_addr, u32 pos)
2455 {
2456         u32 val;
2457
2458         val = (mac_addr[0] << 8) | mac_addr[1];
2459
2460         REG_WR(bp, BNX2_EMAC_MAC_MATCH0 + (pos * 8), val);
2461
2462         val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
2463                 (mac_addr[4] << 8) | mac_addr[5];
2464
2465         REG_WR(bp, BNX2_EMAC_MAC_MATCH1 + (pos * 8), val);
2466 }
2467
2468 static inline int
2469 bnx2_alloc_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
2470 {
2471         dma_addr_t mapping;
2472         struct sw_pg *rx_pg = &rxr->rx_pg_ring[index];
2473         struct rx_bd *rxbd =
2474                 &rxr->rx_pg_desc_ring[RX_RING(index)][RX_IDX(index)];
2475         struct page *page = alloc_page(GFP_ATOMIC);
2476
2477         if (!page)
2478                 return -ENOMEM;
2479         mapping = pci_map_page(bp->pdev, page, 0, PAGE_SIZE,
2480                                PCI_DMA_FROMDEVICE);
2481         rx_pg->page = page;
2482         pci_unmap_addr_set(rx_pg, mapping, mapping);
2483         rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2484         rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2485         return 0;
2486 }
2487
2488 static void
2489 bnx2_free_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
2490 {
2491         struct sw_pg *rx_pg = &rxr->rx_pg_ring[index];
2492         struct page *page = rx_pg->page;
2493
2494         if (!page)
2495                 return;
2496
2497         pci_unmap_page(bp->pdev, pci_unmap_addr(rx_pg, mapping), PAGE_SIZE,
2498                        PCI_DMA_FROMDEVICE);
2499
2500         __free_page(page);
2501         rx_pg->page = NULL;
2502 }
2503
2504 static inline int
2505 bnx2_alloc_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
2506 {
2507         struct sk_buff *skb;
2508         struct sw_bd *rx_buf = &rxr->rx_buf_ring[index];
2509         dma_addr_t mapping;
2510         struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(index)][RX_IDX(index)];
2511         unsigned long align;
2512
2513         skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
2514         if (skb == NULL) {
2515                 return -ENOMEM;
2516         }
2517
2518         if (unlikely((align = (unsigned long) skb->data & (BNX2_RX_ALIGN - 1))))
2519                 skb_reserve(skb, BNX2_RX_ALIGN - align);
2520
2521         mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size,
2522                 PCI_DMA_FROMDEVICE);
2523
2524         rx_buf->skb = skb;
2525         pci_unmap_addr_set(rx_buf, mapping, mapping);
2526
2527         rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2528         rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2529
2530         rxr->rx_prod_bseq += bp->rx_buf_use_size;
2531
2532         return 0;
2533 }
2534
2535 static int
2536 bnx2_phy_event_is_set(struct bnx2 *bp, struct bnx2_napi *bnapi, u32 event)
2537 {
2538         struct status_block *sblk = bnapi->status_blk.msi;
2539         u32 new_link_state, old_link_state;
2540         int is_set = 1;
2541
2542         new_link_state = sblk->status_attn_bits & event;
2543         old_link_state = sblk->status_attn_bits_ack & event;
2544         if (new_link_state != old_link_state) {
2545                 if (new_link_state)
2546                         REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, event);
2547                 else
2548                         REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, event);
2549         } else
2550                 is_set = 0;
2551
2552         return is_set;
2553 }
2554
2555 static void
2556 bnx2_phy_int(struct bnx2 *bp, struct bnx2_napi *bnapi)
2557 {
2558         spin_lock(&bp->phy_lock);
2559
2560         if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_LINK_STATE))
2561                 bnx2_set_link(bp);
2562         if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_TIMER_ABORT))
2563                 bnx2_set_remote_link(bp);
2564
2565         spin_unlock(&bp->phy_lock);
2566
2567 }
2568
2569 static inline u16
2570 bnx2_get_hw_tx_cons(struct bnx2_napi *bnapi)
2571 {
2572         u16 cons;
2573
2574         /* Tell compiler that status block fields can change. */
2575         barrier();
2576         cons = *bnapi->hw_tx_cons_ptr;
2577         if (unlikely((cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT))
2578                 cons++;
2579         return cons;
2580 }
2581
2582 static int
2583 bnx2_tx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
2584 {
2585         struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
2586         u16 hw_cons, sw_cons, sw_ring_cons;
2587         int tx_pkt = 0, index;
2588         struct netdev_queue *txq;
2589
2590         index = (bnapi - bp->bnx2_napi);
2591         txq = netdev_get_tx_queue(bp->dev, index);
2592
2593         hw_cons = bnx2_get_hw_tx_cons(bnapi);
2594         sw_cons = txr->tx_cons;
2595
2596         while (sw_cons != hw_cons) {
2597                 struct sw_bd *tx_buf;
2598                 struct sk_buff *skb;
2599                 int i, last;
2600
2601                 sw_ring_cons = TX_RING_IDX(sw_cons);
2602
2603                 tx_buf = &txr->tx_buf_ring[sw_ring_cons];
2604                 skb = tx_buf->skb;
2605
2606                 /* partial BD completions possible with TSO packets */
2607                 if (skb_is_gso(skb)) {
2608                         u16 last_idx, last_ring_idx;
2609
2610                         last_idx = sw_cons +
2611                                 skb_shinfo(skb)->nr_frags + 1;
2612                         last_ring_idx = sw_ring_cons +
2613                                 skb_shinfo(skb)->nr_frags + 1;
2614                         if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) {
2615                                 last_idx++;
2616                         }
2617                         if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
2618                                 break;
2619                         }
2620                 }
2621
2622                 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
2623                         skb_headlen(skb), PCI_DMA_TODEVICE);
2624
2625                 tx_buf->skb = NULL;
2626                 last = skb_shinfo(skb)->nr_frags;
2627
2628                 for (i = 0; i < last; i++) {
2629                         sw_cons = NEXT_TX_BD(sw_cons);
2630
2631                         pci_unmap_page(bp->pdev,
2632                                 pci_unmap_addr(
2633                                         &txr->tx_buf_ring[TX_RING_IDX(sw_cons)],
2634                                         mapping),
2635                                 skb_shinfo(skb)->frags[i].size,
2636                                 PCI_DMA_TODEVICE);
2637                 }
2638
2639                 sw_cons = NEXT_TX_BD(sw_cons);
2640
2641                 dev_kfree_skb(skb);
2642                 tx_pkt++;
2643                 if (tx_pkt == budget)
2644                         break;
2645
2646                 hw_cons = bnx2_get_hw_tx_cons(bnapi);
2647         }
2648
2649         txr->hw_tx_cons = hw_cons;
2650         txr->tx_cons = sw_cons;
2651
2652         /* Need to make the tx_cons update visible to bnx2_start_xmit()
2653          * before checking for netif_tx_queue_stopped().  Without the
2654          * memory barrier, there is a small possibility that bnx2_start_xmit()
2655          * will miss it and cause the queue to be stopped forever.
2656          */
2657         smp_mb();
2658
2659         if (unlikely(netif_tx_queue_stopped(txq)) &&
2660                      (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
2661                 __netif_tx_lock(txq, smp_processor_id());
2662                 if ((netif_tx_queue_stopped(txq)) &&
2663                     (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh))
2664                         netif_tx_wake_queue(txq);
2665                 __netif_tx_unlock(txq);
2666         }
2667
2668         return tx_pkt;
2669 }
2670
2671 static void
2672 bnx2_reuse_rx_skb_pages(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
2673                         struct sk_buff *skb, int count)
2674 {
2675         struct sw_pg *cons_rx_pg, *prod_rx_pg;
2676         struct rx_bd *cons_bd, *prod_bd;
2677         dma_addr_t mapping;
2678         int i;
2679         u16 hw_prod = rxr->rx_pg_prod, prod;
2680         u16 cons = rxr->rx_pg_cons;
2681
2682         for (i = 0; i < count; i++) {
2683                 prod = RX_PG_RING_IDX(hw_prod);
2684
2685                 prod_rx_pg = &rxr->rx_pg_ring[prod];
2686                 cons_rx_pg = &rxr->rx_pg_ring[cons];
2687                 cons_bd = &rxr->rx_pg_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2688                 prod_bd = &rxr->rx_pg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
2689
2690                 if (i == 0 && skb) {
2691                         struct page *page;
2692                         struct skb_shared_info *shinfo;
2693
2694                         shinfo = skb_shinfo(skb);
2695                         shinfo->nr_frags--;
2696                         page = shinfo->frags[shinfo->nr_frags].page;
2697                         shinfo->frags[shinfo->nr_frags].page = NULL;
2698                         mapping = pci_map_page(bp->pdev, page, 0, PAGE_SIZE,
2699                                                PCI_DMA_FROMDEVICE);
2700                         cons_rx_pg->page = page;
2701                         pci_unmap_addr_set(cons_rx_pg, mapping, mapping);
2702                         dev_kfree_skb(skb);
2703                 }
2704                 if (prod != cons) {
2705                         prod_rx_pg->page = cons_rx_pg->page;
2706                         cons_rx_pg->page = NULL;
2707                         pci_unmap_addr_set(prod_rx_pg, mapping,
2708                                 pci_unmap_addr(cons_rx_pg, mapping));
2709
2710                         prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2711                         prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2712
2713                 }
2714                 cons = RX_PG_RING_IDX(NEXT_RX_BD(cons));
2715                 hw_prod = NEXT_RX_BD(hw_prod);
2716         }
2717         rxr->rx_pg_prod = hw_prod;
2718         rxr->rx_pg_cons = cons;
2719 }
2720
2721 static inline void
2722 bnx2_reuse_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
2723                   struct sk_buff *skb, u16 cons, u16 prod)
2724 {
2725         struct sw_bd *cons_rx_buf, *prod_rx_buf;
2726         struct rx_bd *cons_bd, *prod_bd;
2727
2728         cons_rx_buf = &rxr->rx_buf_ring[cons];
2729         prod_rx_buf = &rxr->rx_buf_ring[prod];
2730
2731         pci_dma_sync_single_for_device(bp->pdev,
2732                 pci_unmap_addr(cons_rx_buf, mapping),
2733                 BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
2734
2735         rxr->rx_prod_bseq += bp->rx_buf_use_size;
2736
2737         prod_rx_buf->skb = skb;
2738
2739         if (cons == prod)
2740                 return;
2741
2742         pci_unmap_addr_set(prod_rx_buf, mapping,
2743                         pci_unmap_addr(cons_rx_buf, mapping));
2744
2745         cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2746         prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
2747         prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2748         prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2749 }
2750
2751 static int
2752 bnx2_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, struct sk_buff *skb,
2753             unsigned int len, unsigned int hdr_len, dma_addr_t dma_addr,
2754             u32 ring_idx)
2755 {
2756         int err;
2757         u16 prod = ring_idx & 0xffff;
2758
2759         err = bnx2_alloc_rx_skb(bp, rxr, prod);
2760         if (unlikely(err)) {
2761                 bnx2_reuse_rx_skb(bp, rxr, skb, (u16) (ring_idx >> 16), prod);
2762                 if (hdr_len) {
2763                         unsigned int raw_len = len + 4;
2764                         int pages = PAGE_ALIGN(raw_len - hdr_len) >> PAGE_SHIFT;
2765
2766                         bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);
2767                 }
2768                 return err;
2769         }
2770
2771         skb_reserve(skb, BNX2_RX_OFFSET);
2772         pci_unmap_single(bp->pdev, dma_addr, bp->rx_buf_use_size,
2773                          PCI_DMA_FROMDEVICE);
2774
2775         if (hdr_len == 0) {
2776                 skb_put(skb, len);
2777                 return 0;
2778         } else {
2779                 unsigned int i, frag_len, frag_size, pages;
2780                 struct sw_pg *rx_pg;
2781                 u16 pg_cons = rxr->rx_pg_cons;
2782                 u16 pg_prod = rxr->rx_pg_prod;
2783
2784                 frag_size = len + 4 - hdr_len;
2785                 pages = PAGE_ALIGN(frag_size) >> PAGE_SHIFT;
2786                 skb_put(skb, hdr_len);
2787
2788                 for (i = 0; i < pages; i++) {
2789                         frag_len = min(frag_size, (unsigned int) PAGE_SIZE);
2790                         if (unlikely(frag_len <= 4)) {
2791                                 unsigned int tail = 4 - frag_len;
2792
2793                                 rxr->rx_pg_cons = pg_cons;
2794                                 rxr->rx_pg_prod = pg_prod;
2795                                 bnx2_reuse_rx_skb_pages(bp, rxr, NULL,
2796                                                         pages - i);
2797                                 skb->len -= tail;
2798                                 if (i == 0) {
2799                                         skb->tail -= tail;
2800                                 } else {
2801                                         skb_frag_t *frag =
2802                                                 &skb_shinfo(skb)->frags[i - 1];
2803                                         frag->size -= tail;
2804                                         skb->data_len -= tail;
2805                                         skb->truesize -= tail;
2806                                 }
2807                                 return 0;
2808                         }
2809                         rx_pg = &rxr->rx_pg_ring[pg_cons];
2810
2811                         pci_unmap_page(bp->pdev, pci_unmap_addr(rx_pg, mapping),
2812                                        PAGE_SIZE, PCI_DMA_FROMDEVICE);
2813
2814                         if (i == pages - 1)
2815                                 frag_len -= 4;
2816
2817                         skb_fill_page_desc(skb, i, rx_pg->page, 0, frag_len);
2818                         rx_pg->page = NULL;
2819
2820                         err = bnx2_alloc_rx_page(bp, rxr,
2821                                                  RX_PG_RING_IDX(pg_prod));
2822                         if (unlikely(err)) {
2823                                 rxr->rx_pg_cons = pg_cons;
2824                                 rxr->rx_pg_prod = pg_prod;
2825                                 bnx2_reuse_rx_skb_pages(bp, rxr, skb,
2826                                                         pages - i);
2827                                 return err;
2828                         }
2829
2830                         frag_size -= frag_len;
2831                         skb->data_len += frag_len;
2832                         skb->truesize += frag_len;
2833                         skb->len += frag_len;
2834
2835                         pg_prod = NEXT_RX_BD(pg_prod);
2836                         pg_cons = RX_PG_RING_IDX(NEXT_RX_BD(pg_cons));
2837                 }
2838                 rxr->rx_pg_prod = pg_prod;
2839                 rxr->rx_pg_cons = pg_cons;
2840         }
2841         return 0;
2842 }
2843
2844 static inline u16
2845 bnx2_get_hw_rx_cons(struct bnx2_napi *bnapi)
2846 {
2847         u16 cons;
2848
2849         /* Tell compiler that status block fields can change. */
2850         barrier();
2851         cons = *bnapi->hw_rx_cons_ptr;
2852         if (unlikely((cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT))
2853                 cons++;
2854         return cons;
2855 }
2856
2857 static int
2858 bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
2859 {
2860         struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
2861         u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
2862         struct l2_fhdr *rx_hdr;
2863         int rx_pkt = 0, pg_ring_used = 0;
2864
2865         hw_cons = bnx2_get_hw_rx_cons(bnapi);
2866         sw_cons = rxr->rx_cons;
2867         sw_prod = rxr->rx_prod;
2868
2869         /* Memory barrier necessary as speculative reads of the rx
2870          * buffer can be ahead of the index in the status block
2871          */
2872         rmb();
2873         while (sw_cons != hw_cons) {
2874                 unsigned int len, hdr_len;
2875                 u32 status;
2876                 struct sw_bd *rx_buf;
2877                 struct sk_buff *skb;
2878                 dma_addr_t dma_addr;
2879                 u16 vtag = 0;
2880                 int hw_vlan __maybe_unused = 0;
2881
2882                 sw_ring_cons = RX_RING_IDX(sw_cons);
2883                 sw_ring_prod = RX_RING_IDX(sw_prod);
2884
2885                 rx_buf = &rxr->rx_buf_ring[sw_ring_cons];
2886                 skb = rx_buf->skb;
2887
2888                 rx_buf->skb = NULL;
2889
2890                 dma_addr = pci_unmap_addr(rx_buf, mapping);
2891
2892                 pci_dma_sync_single_for_cpu(bp->pdev, dma_addr,
2893                         BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH,
2894                         PCI_DMA_FROMDEVICE);
2895
2896                 rx_hdr = (struct l2_fhdr *) skb->data;
2897                 len = rx_hdr->l2_fhdr_pkt_len;
2898
2899                 if ((status = rx_hdr->l2_fhdr_status) &
2900                         (L2_FHDR_ERRORS_BAD_CRC |
2901                         L2_FHDR_ERRORS_PHY_DECODE |
2902                         L2_FHDR_ERRORS_ALIGNMENT |
2903                         L2_FHDR_ERRORS_TOO_SHORT |
2904                         L2_FHDR_ERRORS_GIANT_FRAME)) {
2905
2906                         bnx2_reuse_rx_skb(bp, rxr, skb, sw_ring_cons,
2907                                           sw_ring_prod);
2908                         goto next_rx;
2909                 }
2910                 hdr_len = 0;
2911                 if (status & L2_FHDR_STATUS_SPLIT) {
2912                         hdr_len = rx_hdr->l2_fhdr_ip_xsum;
2913                         pg_ring_used = 1;
2914                 } else if (len > bp->rx_jumbo_thresh) {
2915                         hdr_len = bp->rx_jumbo_thresh;
2916                         pg_ring_used = 1;
2917                 }
2918
2919                 len -= 4;
2920
2921                 if (len <= bp->rx_copy_thresh) {
2922                         struct sk_buff *new_skb;
2923
2924                         new_skb = netdev_alloc_skb(bp->dev, len + 6);
2925                         if (new_skb == NULL) {
2926                                 bnx2_reuse_rx_skb(bp, rxr, skb, sw_ring_cons,
2927                                                   sw_ring_prod);
2928                                 goto next_rx;
2929                         }
2930
2931                         /* aligned copy */
2932                         skb_copy_from_linear_data_offset(skb,
2933                                                          BNX2_RX_OFFSET - 6,
2934                                       new_skb->data, len + 6);
2935                         skb_reserve(new_skb, 6);
2936                         skb_put(new_skb, len);
2937
2938                         bnx2_reuse_rx_skb(bp, rxr, skb,
2939                                 sw_ring_cons, sw_ring_prod);
2940
2941                         skb = new_skb;
2942                 } else if (unlikely(bnx2_rx_skb(bp, rxr, skb, len, hdr_len,
2943                            dma_addr, (sw_ring_cons << 16) | sw_ring_prod)))
2944                         goto next_rx;
2945
2946                 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) &&
2947                     !(bp->rx_mode & BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG)) {
2948                         vtag = rx_hdr->l2_fhdr_vlan_tag;
2949 #ifdef BCM_VLAN
2950                         if (bp->vlgrp)
2951                                 hw_vlan = 1;
2952                         else
2953 #endif
2954                         {
2955                                 struct vlan_ethhdr *ve = (struct vlan_ethhdr *)
2956                                         __skb_push(skb, 4);
2957
2958                                 memmove(ve, skb->data + 4, ETH_ALEN * 2);
2959                                 ve->h_vlan_proto = htons(ETH_P_8021Q);
2960                                 ve->h_vlan_TCI = htons(vtag);
2961                                 len += 4;
2962                         }
2963                 }
2964
2965                 skb->protocol = eth_type_trans(skb, bp->dev);
2966
2967                 if ((len > (bp->dev->mtu + ETH_HLEN)) &&
2968                         (ntohs(skb->protocol) != 0x8100)) {
2969
2970                         dev_kfree_skb(skb);
2971                         goto next_rx;
2972
2973                 }
2974
2975                 skb->ip_summed = CHECKSUM_NONE;
2976                 if (bp->rx_csum &&
2977                         (status & (L2_FHDR_STATUS_TCP_SEGMENT |
2978                         L2_FHDR_STATUS_UDP_DATAGRAM))) {
2979
2980                         if (likely((status & (L2_FHDR_ERRORS_TCP_XSUM |
2981                                               L2_FHDR_ERRORS_UDP_XSUM)) == 0))
2982                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2983                 }
2984
2985 #ifdef BCM_VLAN
2986                 if (hw_vlan)
2987                         vlan_hwaccel_receive_skb(skb, bp->vlgrp, vtag);
2988                 else
2989 #endif
2990                         netif_receive_skb(skb);
2991
2992                 bp->dev->last_rx = jiffies;
2993                 rx_pkt++;
2994
2995 next_rx:
2996                 sw_cons = NEXT_RX_BD(sw_cons);
2997                 sw_prod = NEXT_RX_BD(sw_prod);
2998
2999                 if ((rx_pkt == budget))
3000                         break;
3001
3002                 /* Refresh hw_cons to see if there is new work */
3003                 if (sw_cons == hw_cons) {
3004                         hw_cons = bnx2_get_hw_rx_cons(bnapi);
3005                         rmb();
3006                 }
3007         }
3008         rxr->rx_cons = sw_cons;
3009         rxr->rx_prod = sw_prod;
3010
3011         if (pg_ring_used)
3012                 REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
3013
3014         REG_WR16(bp, rxr->rx_bidx_addr, sw_prod);
3015
3016         REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
3017
3018         mmiowb();
3019
3020         return rx_pkt;
3021
3022 }
3023
3024 /* MSI ISR - The only difference between this and the INTx ISR
3025  * is that the MSI interrupt is always serviced.
3026  */
3027 static irqreturn_t
3028 bnx2_msi(int irq, void *dev_instance)
3029 {
3030         struct bnx2_napi *bnapi = dev_instance;
3031         struct bnx2 *bp = bnapi->bp;
3032         struct net_device *dev = bp->dev;
3033
3034         prefetch(bnapi->status_blk.msi);
3035         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3036                 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
3037                 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3038
3039         /* Return here if interrupt is disabled. */
3040         if (unlikely(atomic_read(&bp->intr_sem) != 0))
3041                 return IRQ_HANDLED;
3042
3043         netif_rx_schedule(dev, &bnapi->napi);
3044
3045         return IRQ_HANDLED;
3046 }
3047
3048 static irqreturn_t
3049 bnx2_msi_1shot(int irq, void *dev_instance)
3050 {
3051         struct bnx2_napi *bnapi = dev_instance;
3052         struct bnx2 *bp = bnapi->bp;
3053         struct net_device *dev = bp->dev;
3054
3055         prefetch(bnapi->status_blk.msi);
3056
3057         /* Return here if interrupt is disabled. */
3058         if (unlikely(atomic_read(&bp->intr_sem) != 0))
3059                 return IRQ_HANDLED;
3060
3061         netif_rx_schedule(dev, &bnapi->napi);
3062
3063         return IRQ_HANDLED;
3064 }
3065
3066 static irqreturn_t
3067 bnx2_interrupt(int irq, void *dev_instance)
3068 {
3069         struct bnx2_napi *bnapi = dev_instance;
3070         struct bnx2 *bp = bnapi->bp;
3071         struct net_device *dev = bp->dev;
3072         struct status_block *sblk = bnapi->status_blk.msi;
3073
3074         /* When using INTx, it is possible for the interrupt to arrive
3075          * at the CPU before the status block posted prior to the
3076          * interrupt. Reading a register will flush the status block.
3077          * When using MSI, the MSI message will always complete after
3078          * the status block write.
3079          */
3080         if ((sblk->status_idx == bnapi->last_status_idx) &&
3081             (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
3082              BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
3083                 return IRQ_NONE;
3084
3085         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3086                 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
3087                 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3088
3089         /* Read back to deassert IRQ immediately to avoid too many
3090          * spurious interrupts.
3091          */
3092         REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
3093
3094         /* Return here if interrupt is shared and is disabled. */
3095         if (unlikely(atomic_read(&bp->intr_sem) != 0))
3096                 return IRQ_HANDLED;
3097
3098         if (netif_rx_schedule_prep(dev, &bnapi->napi)) {
3099                 bnapi->last_status_idx = sblk->status_idx;
3100                 __netif_rx_schedule(dev, &bnapi->napi);
3101         }
3102
3103         return IRQ_HANDLED;
3104 }
3105
3106 static inline int
3107 bnx2_has_fast_work(struct bnx2_napi *bnapi)
3108 {
3109         struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
3110         struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
3111
3112         if ((bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons) ||
3113             (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons))
3114                 return 1;
3115         return 0;
3116 }
3117
3118 #define STATUS_ATTN_EVENTS      (STATUS_ATTN_BITS_LINK_STATE | \
3119                                  STATUS_ATTN_BITS_TIMER_ABORT)
3120
3121 static inline int
3122 bnx2_has_work(struct bnx2_napi *bnapi)
3123 {
3124         struct status_block *sblk = bnapi->status_blk.msi;
3125
3126         if (bnx2_has_fast_work(bnapi))
3127                 return 1;
3128
3129         if ((sblk->status_attn_bits & STATUS_ATTN_EVENTS) !=
3130             (sblk->status_attn_bits_ack & STATUS_ATTN_EVENTS))
3131                 return 1;
3132
3133         return 0;
3134 }
3135
3136 static void bnx2_poll_link(struct bnx2 *bp, struct bnx2_napi *bnapi)
3137 {
3138         struct status_block *sblk = bnapi->status_blk.msi;
3139         u32 status_attn_bits = sblk->status_attn_bits;
3140         u32 status_attn_bits_ack = sblk->status_attn_bits_ack;
3141
3142         if ((status_attn_bits & STATUS_ATTN_EVENTS) !=
3143             (status_attn_bits_ack & STATUS_ATTN_EVENTS)) {
3144
3145                 bnx2_phy_int(bp, bnapi);
3146
3147                 /* This is needed to take care of transient status
3148                  * during link changes.
3149                  */
3150                 REG_WR(bp, BNX2_HC_COMMAND,
3151                        bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3152                 REG_RD(bp, BNX2_HC_COMMAND);
3153         }
3154 }
3155
3156 static int bnx2_poll_work(struct bnx2 *bp, struct bnx2_napi *bnapi,
3157                           int work_done, int budget)
3158 {
3159         struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
3160         struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
3161
3162         if (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons)
3163                 bnx2_tx_int(bp, bnapi, 0);
3164
3165         if (bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons)
3166                 work_done += bnx2_rx_int(bp, bnapi, budget - work_done);
3167
3168         return work_done;
3169 }
3170
3171 static int bnx2_poll_msix(struct napi_struct *napi, int budget)
3172 {
3173         struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3174         struct bnx2 *bp = bnapi->bp;
3175         int work_done = 0;
3176         struct status_block_msix *sblk = bnapi->status_blk.msix;
3177
3178         while (1) {
3179                 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
3180                 if (unlikely(work_done >= budget))
3181                         break;
3182
3183                 bnapi->last_status_idx = sblk->status_idx;
3184                 /* status idx must be read before checking for more work. */
3185                 rmb();
3186                 if (likely(!bnx2_has_fast_work(bnapi))) {
3187
3188                         netif_rx_complete(bp->dev, napi);
3189                         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
3190                                BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3191                                bnapi->last_status_idx);
3192                         break;
3193                 }
3194         }
3195         return work_done;
3196 }
3197
3198 static int bnx2_poll(struct napi_struct *napi, int budget)
3199 {
3200         struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3201         struct bnx2 *bp = bnapi->bp;
3202         int work_done = 0;
3203         struct status_block *sblk = bnapi->status_blk.msi;
3204
3205         while (1) {
3206                 bnx2_poll_link(bp, bnapi);
3207
3208                 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
3209
3210                 if (unlikely(work_done >= budget))
3211                         break;
3212
3213                 /* bnapi->last_status_idx is used below to tell the hw how
3214                  * much work has been processed, so we must read it before
3215                  * checking for more work.
3216                  */
3217                 bnapi->last_status_idx = sblk->status_idx;
3218                 rmb();
3219                 if (likely(!bnx2_has_work(bnapi))) {
3220                         netif_rx_complete(bp->dev, napi);
3221                         if (likely(bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)) {
3222                                 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3223                                        BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3224                                        bnapi->last_status_idx);
3225                                 break;
3226                         }
3227                         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3228                                BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3229                                BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
3230                                bnapi->last_status_idx);
3231
3232                         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3233                                BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3234                                bnapi->last_status_idx);
3235                         break;
3236                 }
3237         }
3238
3239         return work_done;
3240 }
3241
3242 /* Called with rtnl_lock from vlan functions and also netif_tx_lock
3243  * from set_multicast.
3244  */
3245 static void
3246 bnx2_set_rx_mode(struct net_device *dev)
3247 {
3248         struct bnx2 *bp = netdev_priv(dev);
3249         u32 rx_mode, sort_mode;
3250         struct dev_addr_list *uc_ptr;
3251         int i;
3252
3253         spin_lock_bh(&bp->phy_lock);
3254
3255         rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
3256                                   BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
3257         sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
3258 #ifdef BCM_VLAN
3259         if (!bp->vlgrp && (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN))
3260                 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
3261 #else
3262         if (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN)
3263                 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
3264 #endif
3265         if (dev->flags & IFF_PROMISC) {
3266                 /* Promiscuous mode. */
3267                 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
3268                 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3269                              BNX2_RPM_SORT_USER0_PROM_VLAN;
3270         }
3271         else if (dev->flags & IFF_ALLMULTI) {
3272                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3273                         REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3274                                0xffffffff);
3275                 }
3276                 sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
3277         }
3278         else {
3279                 /* Accept one or more multicast(s). */
3280                 struct dev_mc_list *mclist;
3281                 u32 mc_filter[NUM_MC_HASH_REGISTERS];
3282                 u32 regidx;
3283                 u32 bit;
3284                 u32 crc;
3285
3286                 memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);
3287
3288                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
3289                      i++, mclist = mclist->next) {
3290
3291                         crc = ether_crc_le(ETH_ALEN, mclist->dmi_addr);
3292                         bit = crc & 0xff;
3293                         regidx = (bit & 0xe0) >> 5;
3294                         bit &= 0x1f;
3295                         mc_filter[regidx] |= (1 << bit);
3296                 }
3297
3298                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3299                         REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3300                                mc_filter[i]);
3301                 }
3302
3303                 sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
3304         }
3305
3306         uc_ptr = NULL;
3307         if (dev->uc_count > BNX2_MAX_UNICAST_ADDRESSES) {
3308                 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
3309                 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3310                              BNX2_RPM_SORT_USER0_PROM_VLAN;
3311         } else if (!(dev->flags & IFF_PROMISC)) {
3312                 uc_ptr = dev->uc_list;
3313
3314                 /* Add all entries into to the match filter list */
3315                 for (i = 0; i < dev->uc_count; i++) {
3316                         bnx2_set_mac_addr(bp, uc_ptr->da_addr,
3317                                           i + BNX2_START_UNICAST_ADDRESS_INDEX);
3318                         sort_mode |= (1 <<
3319                                       (i + BNX2_START_UNICAST_ADDRESS_INDEX));
3320                         uc_ptr = uc_ptr->next;
3321                 }
3322
3323         }
3324
3325         if (rx_mode != bp->rx_mode) {
3326                 bp->rx_mode = rx_mode;
3327                 REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
3328         }
3329
3330         REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3331         REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
3332         REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
3333
3334         spin_unlock_bh(&bp->phy_lock);
3335 }
3336
3337 static void
3338 load_rv2p_fw(struct bnx2 *bp, __le32 *rv2p_code, u32 rv2p_code_len,
3339         u32 rv2p_proc)
3340 {
3341         int i;
3342         u32 val;
3343
3344         if (rv2p_proc == RV2P_PROC2 && CHIP_NUM(bp) == CHIP_NUM_5709) {
3345                 val = le32_to_cpu(rv2p_code[XI_RV2P_PROC2_MAX_BD_PAGE_LOC]);
3346                 val &= ~XI_RV2P_PROC2_BD_PAGE_SIZE_MSK;
3347                 val |= XI_RV2P_PROC2_BD_PAGE_SIZE;
3348                 rv2p_code[XI_RV2P_PROC2_MAX_BD_PAGE_LOC] = cpu_to_le32(val);
3349         }
3350
3351         for (i = 0; i < rv2p_code_len; i += 8) {
3352                 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, le32_to_cpu(*rv2p_code));
3353                 rv2p_code++;
3354                 REG_WR(bp, BNX2_RV2P_INSTR_LOW, le32_to_cpu(*rv2p_code));
3355                 rv2p_code++;
3356
3357                 if (rv2p_proc == RV2P_PROC1) {
3358                         val = (i / 8) | BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
3359                         REG_WR(bp, BNX2_RV2P_PROC1_ADDR_CMD, val);
3360                 }
3361                 else {
3362                         val = (i / 8) | BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
3363                         REG_WR(bp, BNX2_RV2P_PROC2_ADDR_CMD, val);
3364                 }
3365         }
3366
3367         /* Reset the processor, un-stall is done later. */
3368         if (rv2p_proc == RV2P_PROC1) {
3369                 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
3370         }
3371         else {
3372                 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
3373         }
3374 }
3375
3376 static int
3377 load_cpu_fw(struct bnx2 *bp, const struct cpu_reg *cpu_reg, struct fw_info *fw)
3378 {
3379         u32 offset;
3380         u32 val;
3381         int rc;
3382
3383         /* Halt the CPU. */
3384         val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
3385         val |= cpu_reg->mode_value_halt;
3386         bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
3387         bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
3388
3389         /* Load the Text area. */
3390         offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
3391         if (fw->gz_text) {
3392                 int j;
3393
3394                 rc = zlib_inflate_blob(fw->text, FW_BUF_SIZE, fw->gz_text,
3395                                        fw->gz_text_len);
3396                 if (rc < 0)
3397                         return rc;
3398
3399                 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) {
3400                         bnx2_reg_wr_ind(bp, offset, le32_to_cpu(fw->text[j]));
3401                 }
3402         }
3403
3404         /* Load the Data area. */
3405         offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
3406         if (fw->data) {
3407                 int j;
3408
3409                 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) {
3410                         bnx2_reg_wr_ind(bp, offset, fw->data[j]);
3411                 }
3412         }
3413
3414         /* Load the SBSS area. */
3415         offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
3416         if (fw->sbss_len) {
3417                 int j;
3418
3419                 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) {
3420                         bnx2_reg_wr_ind(bp, offset, 0);
3421                 }
3422         }
3423
3424         /* Load the BSS area. */
3425         offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
3426         if (fw->bss_len) {
3427                 int j;
3428
3429                 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) {
3430                         bnx2_reg_wr_ind(bp, offset, 0);
3431                 }
3432         }
3433
3434         /* Load the Read-Only area. */
3435         offset = cpu_reg->spad_base +
3436                 (fw->rodata_addr - cpu_reg->mips_view_base);
3437         if (fw->rodata) {
3438                 int j;
3439
3440                 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) {
3441                         bnx2_reg_wr_ind(bp, offset, fw->rodata[j]);
3442                 }
3443         }
3444
3445         /* Clear the pre-fetch instruction. */
3446         bnx2_reg_wr_ind(bp, cpu_reg->inst, 0);
3447         bnx2_reg_wr_ind(bp, cpu_reg->pc, fw->start_addr);
3448
3449         /* Start the CPU. */
3450         val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
3451         val &= ~cpu_reg->mode_value_halt;
3452         bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
3453         bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
3454
3455         return 0;
3456 }
3457
3458 static int
3459 bnx2_init_cpus(struct bnx2 *bp)
3460 {
3461         struct fw_info *fw;
3462         int rc, rv2p_len;
3463         void *text, *rv2p;
3464
3465         /* Initialize the RV2P processor. */
3466         text = vmalloc(FW_BUF_SIZE);
3467         if (!text)
3468                 return -ENOMEM;
3469         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3470                 rv2p = bnx2_xi_rv2p_proc1;
3471                 rv2p_len = sizeof(bnx2_xi_rv2p_proc1);
3472         } else {
3473                 rv2p = bnx2_rv2p_proc1;
3474                 rv2p_len = sizeof(bnx2_rv2p_proc1);
3475         }
3476         rc = zlib_inflate_blob(text, FW_BUF_SIZE, rv2p, rv2p_len);
3477         if (rc < 0)
3478                 goto init_cpu_err;
3479
3480         load_rv2p_fw(bp, text, rc /* == len */, RV2P_PROC1);
3481
3482         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3483                 rv2p = bnx2_xi_rv2p_proc2;
3484                 rv2p_len = sizeof(bnx2_xi_rv2p_proc2);
3485         } else {
3486                 rv2p = bnx2_rv2p_proc2;
3487                 rv2p_len = sizeof(bnx2_rv2p_proc2);
3488         }
3489         rc = zlib_inflate_blob(text, FW_BUF_SIZE, rv2p, rv2p_len);
3490         if (rc < 0)
3491                 goto init_cpu_err;
3492
3493         load_rv2p_fw(bp, text, rc /* == len */, RV2P_PROC2);
3494
3495         /* Initialize the RX Processor. */
3496         if (CHIP_NUM(bp) == CHIP_NUM_5709)
3497                 fw = &bnx2_rxp_fw_09;
3498         else
3499                 fw = &bnx2_rxp_fw_06;
3500
3501         fw->text = text;
3502         rc = load_cpu_fw(bp, &cpu_reg_rxp, fw);
3503         if (rc)
3504                 goto init_cpu_err;
3505
3506         /* Initialize the TX Processor. */
3507         if (CHIP_NUM(bp) == CHIP_NUM_5709)
3508                 fw = &bnx2_txp_fw_09;
3509         else
3510                 fw = &bnx2_txp_fw_06;
3511
3512         fw->text = text;
3513         rc = load_cpu_fw(bp, &cpu_reg_txp, fw);
3514         if (rc)
3515                 goto init_cpu_err;
3516
3517         /* Initialize the TX Patch-up Processor. */
3518         if (CHIP_NUM(bp) == CHIP_NUM_5709)
3519                 fw = &bnx2_tpat_fw_09;
3520         else
3521                 fw = &bnx2_tpat_fw_06;
3522
3523         fw->text = text;
3524         rc = load_cpu_fw(bp, &cpu_reg_tpat, fw);
3525         if (rc)
3526                 goto init_cpu_err;
3527
3528         /* Initialize the Completion Processor. */
3529         if (CHIP_NUM(bp) == CHIP_NUM_5709)
3530                 fw = &bnx2_com_fw_09;
3531         else
3532                 fw = &bnx2_com_fw_06;
3533
3534         fw->text = text;
3535         rc = load_cpu_fw(bp, &cpu_reg_com, fw);
3536         if (rc)
3537                 goto init_cpu_err;
3538
3539         /* Initialize the Command Processor. */
3540         if (CHIP_NUM(bp) == CHIP_NUM_5709)
3541                 fw = &bnx2_cp_fw_09;
3542         else
3543                 fw = &bnx2_cp_fw_06;
3544
3545         fw->text = text;
3546         rc = load_cpu_fw(bp, &cpu_reg_cp, fw);
3547
3548 init_cpu_err:
3549         vfree(text);
3550         return rc;
3551 }
3552
3553 static int
3554 bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
3555 {
3556         u16 pmcsr;
3557
3558         pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
3559
3560         switch (state) {
3561         case PCI_D0: {
3562                 u32 val;
3563
3564                 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3565                         (pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
3566                         PCI_PM_CTRL_PME_STATUS);
3567
3568                 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
3569                         /* delay required during transition out of D3hot */
3570                         msleep(20);
3571
3572                 val = REG_RD(bp, BNX2_EMAC_MODE);
3573                 val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
3574                 val &= ~BNX2_EMAC_MODE_MPKT;
3575                 REG_WR(bp, BNX2_EMAC_MODE, val);
3576
3577                 val = REG_RD(bp, BNX2_RPM_CONFIG);
3578                 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3579                 REG_WR(bp, BNX2_RPM_CONFIG, val);
3580                 break;
3581         }
3582         case PCI_D3hot: {
3583                 int i;
3584                 u32 val, wol_msg;
3585
3586                 if (bp->wol) {
3587                         u32 advertising;
3588                         u8 autoneg;
3589
3590                         autoneg = bp->autoneg;
3591                         advertising = bp->advertising;
3592
3593                         if (bp->phy_port == PORT_TP) {
3594                                 bp->autoneg = AUTONEG_SPEED;
3595                                 bp->advertising = ADVERTISED_10baseT_Half |
3596                                         ADVERTISED_10baseT_Full |
3597                                         ADVERTISED_100baseT_Half |
3598                                         ADVERTISED_100baseT_Full |
3599                                         ADVERTISED_Autoneg;
3600                         }
3601
3602                         spin_lock_bh(&bp->phy_lock);
3603                         bnx2_setup_phy(bp, bp->phy_port);
3604                         spin_unlock_bh(&bp->phy_lock);
3605
3606                         bp->autoneg = autoneg;
3607                         bp->advertising = advertising;
3608
3609                         bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
3610
3611                         val = REG_RD(bp, BNX2_EMAC_MODE);
3612
3613                         /* Enable port mode. */
3614                         val &= ~BNX2_EMAC_MODE_PORT;
3615                         val |= BNX2_EMAC_MODE_MPKT_RCVD |
3616                                BNX2_EMAC_MODE_ACPI_RCVD |
3617                                BNX2_EMAC_MODE_MPKT;
3618                         if (bp->phy_port == PORT_TP)
3619                                 val |= BNX2_EMAC_MODE_PORT_MII;
3620                         else {
3621                                 val |= BNX2_EMAC_MODE_PORT_GMII;
3622                                 if (bp->line_speed == SPEED_2500)
3623                                         val |= BNX2_EMAC_MODE_25G_MODE;
3624                         }
3625
3626                         REG_WR(bp, BNX2_EMAC_MODE, val);
3627
3628                         /* receive all multicast */
3629                         for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3630                                 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3631                                        0xffffffff);
3632                         }
3633                         REG_WR(bp, BNX2_EMAC_RX_MODE,
3634                                BNX2_EMAC_RX_MODE_SORT_MODE);
3635
3636                         val = 1 | BNX2_RPM_SORT_USER0_BC_EN |
3637                               BNX2_RPM_SORT_USER0_MC_EN;
3638                         REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3639                         REG_WR(bp, BNX2_RPM_SORT_USER0, val);
3640                         REG_WR(bp, BNX2_RPM_SORT_USER0, val |
3641                                BNX2_RPM_SORT_USER0_ENA);
3642
3643                         /* Need to enable EMAC and RPM for WOL. */
3644                         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
3645                                BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
3646                                BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
3647                                BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);
3648
3649                         val = REG_RD(bp, BNX2_RPM_CONFIG);
3650                         val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3651                         REG_WR(bp, BNX2_RPM_CONFIG, val);
3652
3653                         wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
3654                 }
3655                 else {
3656                         wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
3657                 }
3658
3659                 if (!(bp->flags & BNX2_FLAG_NO_WOL))
3660                         bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg,
3661                                      1, 0);
3662
3663                 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
3664                 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
3665                     (CHIP_ID(bp) == CHIP_ID_5706_A1)) {
3666
3667                         if (bp->wol)
3668                                 pmcsr |= 3;
3669                 }
3670                 else {
3671                         pmcsr |= 3;
3672                 }
3673                 if (bp->wol) {
3674                         pmcsr |= PCI_PM_CTRL_PME_ENABLE;
3675                 }
3676                 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3677                                       pmcsr);
3678
3679                 /* No more memory access after this point until
3680                  * device is brought back to D0.
3681                  */
3682                 udelay(50);
3683                 break;
3684         }
3685         default:
3686                 return -EINVAL;
3687         }
3688         return 0;
3689 }
3690
3691 static int
3692 bnx2_acquire_nvram_lock(struct bnx2 *bp)
3693 {
3694         u32 val;
3695         int j;
3696
3697         /* Request access to the flash interface. */
3698         REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
3699         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3700                 val = REG_RD(bp, BNX2_NVM_SW_ARB);
3701                 if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
3702                         break;
3703
3704                 udelay(5);
3705         }
3706
3707         if (j >= NVRAM_TIMEOUT_COUNT)
3708                 return -EBUSY;
3709
3710         return 0;
3711 }
3712
3713 static int
3714 bnx2_release_nvram_lock(struct bnx2 *bp)
3715 {
3716         int j;
3717         u32 val;
3718
3719         /* Relinquish nvram interface. */
3720         REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
3721
3722         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3723                 val = REG_RD(bp, BNX2_NVM_SW_ARB);
3724                 if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
3725                         break;
3726
3727                 udelay(5);
3728         }
3729
3730         if (j >= NVRAM_TIMEOUT_COUNT)
3731                 return -EBUSY;
3732
3733         return 0;
3734 }
3735
3736
3737 static int
3738 bnx2_enable_nvram_write(struct bnx2 *bp)
3739 {
3740         u32 val;
3741
3742         val = REG_RD(bp, BNX2_MISC_CFG);
3743         REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
3744
3745         if (bp->flash_info->flags & BNX2_NV_WREN) {
3746                 int j;
3747
3748                 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3749                 REG_WR(bp, BNX2_NVM_COMMAND,
3750                        BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);
3751
3752                 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3753                         udelay(5);
3754
3755                         val = REG_RD(bp, BNX2_NVM_COMMAND);
3756                         if (val & BNX2_NVM_COMMAND_DONE)
3757                                 break;
3758                 }
3759
3760                 if (j >= NVRAM_TIMEOUT_COUNT)
3761                         return -EBUSY;
3762         }
3763         return 0;
3764 }
3765
3766 static void
3767 bnx2_disable_nvram_write(struct bnx2 *bp)
3768 {
3769         u32 val;
3770
3771         val = REG_RD(bp, BNX2_MISC_CFG);
3772         REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
3773 }
3774
3775
3776 static void
3777 bnx2_enable_nvram_access(struct bnx2 *bp)
3778 {
3779         u32 val;
3780
3781         val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
3782         /* Enable both bits, even on read. */
3783         REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
3784                val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
3785 }
3786
3787 static void
3788 bnx2_disable_nvram_access(struct bnx2 *bp)
3789 {
3790         u32 val;
3791
3792         val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
3793         /* Disable both bits, even after read. */
3794         REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
3795                 val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
3796                         BNX2_NVM_ACCESS_ENABLE_WR_EN));
3797 }
3798
3799 static int
3800 bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
3801 {
3802         u32 cmd;
3803         int j;
3804
3805         if (bp->flash_info->flags & BNX2_NV_BUFFERED)
3806                 /* Buffered flash, no erase needed */
3807                 return 0;
3808
3809         /* Build an erase command */
3810         cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR |
3811               BNX2_NVM_COMMAND_DOIT;
3812
3813         /* Need to clear DONE bit separately. */
3814         REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3815
3816         /* Address of the NVRAM to read from. */
3817         REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3818
3819         /* Issue an erase command. */
3820         REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3821
3822         /* Wait for completion. */
3823         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3824                 u32 val;
3825
3826                 udelay(5);
3827
3828                 val = REG_RD(bp, BNX2_NVM_COMMAND);
3829                 if (val & BNX2_NVM_COMMAND_DONE)
3830                         break;
3831         }
3832
3833         if (j >= NVRAM_TIMEOUT_COUNT)
3834                 return -EBUSY;
3835
3836         return 0;
3837 }
3838
3839 static int
3840 bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
3841 {
3842         u32 cmd;
3843         int j;
3844
3845         /* Build the command word. */
3846         cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags;
3847
3848         /* Calculate an offset of a buffered flash, not needed for 5709. */
3849         if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
3850                 offset = ((offset / bp->flash_info->page_size) <<
3851                            bp->flash_info->page_bits) +
3852                           (offset % bp->flash_info->page_size);
3853         }
3854
3855         /* Need to clear DONE bit separately. */
3856         REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3857
3858         /* Address of the NVRAM to read from. */
3859         REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3860
3861         /* Issue a read command. */
3862         REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3863
3864         /* Wait for completion. */
3865         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3866                 u32 val;
3867
3868                 udelay(5);
3869
3870                 val = REG_RD(bp, BNX2_NVM_COMMAND);
3871                 if (val & BNX2_NVM_COMMAND_DONE) {
3872                         __be32 v = cpu_to_be32(REG_RD(bp, BNX2_NVM_READ));
3873                         memcpy(ret_val, &v, 4);
3874                         break;
3875                 }
3876         }
3877         if (j >= NVRAM_TIMEOUT_COUNT)
3878                 return -EBUSY;
3879
3880         return 0;
3881 }
3882
3883
3884 static int
3885 bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
3886 {
3887         u32 cmd;
3888         __be32 val32;
3889         int j;
3890
3891         /* Build the command word. */
3892         cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags;
3893
3894         /* Calculate an offset of a buffered flash, not needed for 5709. */
3895         if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
3896                 offset = ((offset / bp->flash_info->page_size) <<
3897                           bp->flash_info->page_bits) +
3898                          (offset % bp->flash_info->page_size);
3899         }
3900
3901         /* Need to clear DONE bit separately. */
3902         REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3903
3904         memcpy(&val32, val, 4);
3905
3906         /* Write the data. */
3907         REG_WR(bp, BNX2_NVM_WRITE, be32_to_cpu(val32));
3908
3909         /* Address of the NVRAM to write to. */
3910         REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3911
3912         /* Issue the write command. */
3913         REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3914
3915         /* Wait for completion. */
3916         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3917                 udelay(5);
3918
3919                 if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
3920                         break;
3921         }
3922         if (j >= NVRAM_TIMEOUT_COUNT)
3923                 return -EBUSY;
3924
3925         return 0;
3926 }
3927
3928 static int
3929 bnx2_init_nvram(struct bnx2 *bp)
3930 {
3931         u32 val;
3932         int j, entry_count, rc = 0;
3933         struct flash_spec *flash;
3934
3935         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3936                 bp->flash_info = &flash_5709;
3937                 goto get_flash_size;
3938         }
3939
3940         /* Determine the selected interface. */
3941         val = REG_RD(bp, BNX2_NVM_CFG1);
3942
3943         entry_count = ARRAY_SIZE(flash_table);
3944
3945         if (val & 0x40000000) {
3946
3947                 /* Flash interface has been reconfigured */
3948                 for (j = 0, flash = &flash_table[0]; j < entry_count;
3949                      j++, flash++) {
3950                         if ((val & FLASH_BACKUP_STRAP_MASK) ==
3951                             (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
3952                                 bp->flash_info = flash;
3953                                 break;
3954                         }
3955                 }
3956         }
3957         else {
3958                 u32 mask;
3959                 /* Not yet been reconfigured */
3960
3961                 if (val & (1 << 23))
3962                         mask = FLASH_BACKUP_STRAP_MASK;
3963                 else
3964                         mask = FLASH_STRAP_MASK;
3965
3966                 for (j = 0, flash = &flash_table[0]; j < entry_count;
3967                         j++, flash++) {
3968
3969                         if ((val & mask) == (flash->strapping & mask)) {
3970                                 bp->flash_info = flash;
3971
3972                                 /* Request access to the flash interface. */
3973                                 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
3974                                         return rc;
3975
3976                                 /* Enable access to flash interface */
3977                                 bnx2_enable_nvram_access(bp);
3978
3979                                 /* Reconfigure the flash interface */
3980                                 REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
3981                                 REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
3982                                 REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
3983                                 REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);
3984
3985                                 /* Disable access to flash interface */
3986                                 bnx2_disable_nvram_access(bp);
3987                                 bnx2_release_nvram_lock(bp);
3988
3989                                 break;
3990                         }
3991                 }
3992         } /* if (val & 0x40000000) */
3993
3994         if (j == entry_count) {
3995                 bp->flash_info = NULL;
3996                 printk(KERN_ALERT PFX "Unknown flash/EEPROM type.\n");
3997                 return -ENODEV;
3998         }
3999
4000 get_flash_size:
4001         val = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG2);
4002         val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK;
4003         if (val)
4004                 bp->flash_size = val;
4005         else
4006                 bp->flash_size = bp->flash_info->total_size;
4007
4008         return rc;
4009 }
4010
4011 static int
4012 bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
4013                 int buf_size)
4014 {
4015         int rc = 0;
4016         u32 cmd_flags, offset32, len32, extra;
4017
4018         if (buf_size == 0)
4019                 return 0;
4020
4021         /* Request access to the flash interface. */
4022         if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4023                 return rc;
4024
4025         /* Enable access to flash interface */
4026         bnx2_enable_nvram_access(bp);
4027
4028         len32 = buf_size;
4029         offset32 = offset;
4030         extra = 0;
4031
4032         cmd_flags = 0;
4033
4034         if (offset32 & 3) {
4035                 u8 buf[4];
4036                 u32 pre_len;
4037
4038                 offset32 &= ~3;
4039                 pre_len = 4 - (offset & 3);
4040
4041                 if (pre_len >= len32) {
4042                         pre_len = len32;
4043                         cmd_flags = BNX2_NVM_COMMAND_FIRST |
4044                                     BNX2_NVM_COMMAND_LAST;
4045                 }
4046                 else {
4047                         cmd_flags = BNX2_NVM_COMMAND_FIRST;
4048                 }
4049
4050                 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4051
4052                 if (rc)
4053                         return rc;
4054
4055                 memcpy(ret_buf, buf + (offset & 3), pre_len);
4056
4057                 offset32 += 4;
4058                 ret_buf += pre_len;
4059                 len32 -= pre_len;
4060         }
4061         if (len32 & 3) {
4062                 extra = 4 - (len32 & 3);
4063                 len32 = (len32 + 4) & ~3;
4064         }
4065
4066         if (len32 == 4) {
4067                 u8 buf[4];
4068
4069                 if (cmd_flags)
4070                         cmd_flags = BNX2_NVM_COMMAND_LAST;
4071                 else
4072                         cmd_flags = BNX2_NVM_COMMAND_FIRST |
4073                                     BNX2_NVM_COMMAND_LAST;
4074
4075                 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4076
4077                 memcpy(ret_buf, buf, 4 - extra);
4078         }
4079         else if (len32 > 0) {
4080                 u8 buf[4];
4081
4082                 /* Read the first word. */
4083                 if (cmd_flags)
4084                         cmd_flags = 0;
4085                 else
4086                         cmd_flags = BNX2_NVM_COMMAND_FIRST;
4087
4088                 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);
4089
4090                 /* Advance to the next dword. */
4091                 offset32 += 4;
4092                 ret_buf += 4;
4093                 len32 -= 4;
4094
4095                 while (len32 > 4 && rc == 0) {
4096                         rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);
4097
4098                         /* Advance to the next dword. */
4099                         offset32 += 4;
4100                         ret_buf += 4;
4101                         len32 -= 4;
4102                 }
4103
4104                 if (rc)
4105                         return rc;
4106
4107                 cmd_flags = BNX2_NVM_COMMAND_LAST;
4108                 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4109
4110                 memcpy(ret_buf, buf, 4 - extra);
4111         }
4112
4113         /* Disable access to flash interface */
4114         bnx2_disable_nvram_access(bp);
4115
4116         bnx2_release_nvram_lock(bp);
4117
4118         return rc;
4119 }
4120
4121 static int
4122 bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
4123                 int buf_size)
4124 {
4125         u32 written, offset32, len32;
4126         u8 *buf, start[4], end[4], *align_buf = NULL, *flash_buffer = NULL;
4127         int rc = 0;
4128         int align_start, align_end;
4129
4130         buf = data_buf;
4131         offset32 = offset;
4132         len32 = buf_size;
4133         align_start = align_end = 0;
4134
4135         if ((align_start = (offset32 & 3))) {
4136                 offset32 &= ~3;
4137                 len32 += align_start;
4138                 if (len32 < 4)
4139                         len32 = 4;
4140                 if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
4141                         return rc;
4142         }
4143
4144         if (len32 & 3) {
4145                 align_end = 4 - (len32 & 3);
4146                 len32 += align_end;
4147                 if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4, end, 4)))
4148                         return rc;
4149         }
4150
4151         if (align_start || align_end) {
4152                 align_buf = kmalloc(len32, GFP_KERNEL);
4153                 if (align_buf == NULL)
4154                         return -ENOMEM;
4155                 if (align_start) {
4156                         memcpy(align_buf, start, 4);
4157                 }
4158                 if (align_end) {
4159                         memcpy(align_buf + len32 - 4, end, 4);
4160                 }
4161                 memcpy(align_buf + align_start, data_buf, buf_size);
4162                 buf = align_buf;
4163         }
4164
4165         if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4166                 flash_buffer = kmalloc(264, GFP_KERNEL);
4167                 if (flash_buffer == NULL) {
4168                         rc = -ENOMEM;
4169                         goto nvram_write_end;
4170                 }
4171         }
4172
4173         written = 0;
4174         while ((written < len32) && (rc == 0)) {
4175                 u32 page_start, page_end, data_start, data_end;
4176                 u32 addr, cmd_flags;
4177                 int i;
4178
4179                 /* Find the page_start addr */
4180                 page_start = offset32 + written;
4181                 page_start -= (page_start % bp->flash_info->page_size);
4182                 /* Find the page_end addr */
4183                 page_end = page_start + bp->flash_info->page_size;
4184                 /* Find the data_start addr */
4185                 data_start = (written == 0) ? offset32 : page_start;
4186                 /* Find the data_end addr */
4187                 data_end = (page_end > offset32 + len32) ?
4188                         (offset32 + len32) : page_end;
4189
4190                 /* Request access to the flash interface. */
4191                 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4192                         goto nvram_write_end;
4193
4194                 /* Enable access to flash interface */
4195                 bnx2_enable_nvram_access(bp);
4196
4197                 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4198                 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4199                         int j;
4200
4201                         /* Read the whole page into the buffer
4202                          * (non-buffer flash only) */
4203                         for (j = 0; j < bp->flash_info->page_size; j += 4) {
4204                                 if (j == (bp->flash_info->page_size - 4)) {
4205                                         cmd_flags |= BNX2_NVM_COMMAND_LAST;
4206                                 }
4207                                 rc = bnx2_nvram_read_dword(bp,
4208                                         page_start + j,
4209                                         &flash_buffer[j],
4210                                         cmd_flags);
4211
4212                                 if (rc)
4213                                         goto nvram_write_end;
4214
4215                                 cmd_flags = 0;
4216                         }
4217                 }
4218
4219                 /* Enable writes to flash interface (unlock write-protect) */
4220                 if ((rc = bnx2_enable_nvram_write(bp)) != 0)
4221                         goto nvram_write_end;
4222
4223                 /* Loop to write back the buffer data from page_start to
4224                  * data_start */
4225                 i = 0;
4226                 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4227                         /* Erase the page */
4228                         if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
4229                                 goto nvram_write_end;
4230
4231                         /* Re-enable the write again for the actual write */
4232                         bnx2_enable_nvram_write(bp);
4233
4234                         for (addr = page_start; addr < data_start;
4235                                 addr += 4, i += 4) {
4236
4237                                 rc = bnx2_nvram_write_dword(bp, addr,
4238                                         &flash_buffer[i], cmd_flags);
4239
4240                                 if (rc != 0)
4241                                         goto nvram_write_end;
4242
4243                                 cmd_flags = 0;
4244                         }
4245                 }
4246
4247                 /* Loop to write the new data from data_start to data_end */
4248                 for (addr = data_start; addr < data_end; addr += 4, i += 4) {
4249                         if ((addr == page_end - 4) ||
4250                                 ((bp->flash_info->flags & BNX2_NV_BUFFERED) &&
4251                                  (addr == data_end - 4))) {
4252
4253                                 cmd_flags |= BNX2_NVM_COMMAND_LAST;
4254                         }
4255                         rc = bnx2_nvram_write_dword(bp, addr, buf,
4256                                 cmd_flags);
4257
4258                         if (rc != 0)
4259                                 goto nvram_write_end;
4260
4261                         cmd_flags = 0;
4262                         buf += 4;
4263                 }
4264
4265                 /* Loop to write back the buffer data from data_end
4266                  * to page_end */
4267                 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4268                         for (addr = data_end; addr < page_end;
4269                                 addr += 4, i += 4) {
4270
4271                                 if (addr == page_end-4) {
4272                                         cmd_flags = BNX2_NVM_COMMAND_LAST;
4273                                 }
4274                                 rc = bnx2_nvram_write_dword(bp, addr,
4275                                         &flash_buffer[i], cmd_flags);
4276
4277                                 if (rc != 0)
4278                                         goto nvram_write_end;
4279
4280                                 cmd_flags = 0;
4281                         }
4282                 }
4283
4284                 /* Disable writes to flash interface (lock write-protect) */
4285                 bnx2_disable_nvram_write(bp);
4286
4287                 /* Disable access to flash interface */
4288                 bnx2_disable_nvram_access(bp);
4289                 bnx2_release_nvram_lock(bp);
4290
4291                 /* Increment written */
4292                 written += data_end - data_start;
4293         }
4294
4295 nvram_write_end:
4296         kfree(flash_buffer);
4297         kfree(align_buf);
4298         return rc;
4299 }
4300
4301 static void
4302 bnx2_init_fw_cap(struct bnx2 *bp)
4303 {
4304         u32 val, sig = 0;
4305
4306         bp->phy_flags &= ~BNX2_PHY_FLAG_REMOTE_PHY_CAP;
4307         bp->flags &= ~BNX2_FLAG_CAN_KEEP_VLAN;
4308
4309         if (!(bp->flags & BNX2_FLAG_ASF_ENABLE))
4310                 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
4311
4312         val = bnx2_shmem_rd(bp, BNX2_FW_CAP_MB);
4313         if ((val & BNX2_FW_CAP_SIGNATURE_MASK) != BNX2_FW_CAP_SIGNATURE)
4314                 return;
4315
4316         if ((val & BNX2_FW_CAP_CAN_KEEP_VLAN) == BNX2_FW_CAP_CAN_KEEP_VLAN) {
4317                 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
4318                 sig |= BNX2_DRV_ACK_CAP_SIGNATURE | BNX2_FW_CAP_CAN_KEEP_VLAN;
4319         }
4320
4321         if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
4322             (val & BNX2_FW_CAP_REMOTE_PHY_CAPABLE)) {
4323                 u32 link;
4324
4325                 bp->phy_flags |= BNX2_PHY_FLAG_REMOTE_PHY_CAP;
4326
4327                 link = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
4328                 if (link & BNX2_LINK_STATUS_SERDES_LINK)
4329                         bp->phy_port = PORT_FIBRE;
4330                 else
4331                         bp->phy_port = PORT_TP;
4332
4333                 sig |= BNX2_DRV_ACK_CAP_SIGNATURE |
4334                        BNX2_FW_CAP_REMOTE_PHY_CAPABLE;
4335         }
4336
4337         if (netif_running(bp->dev) && sig)
4338                 bnx2_shmem_wr(bp, BNX2_DRV_ACK_CAP_MB, sig);
4339 }
4340
4341 static void
4342 bnx2_setup_msix_tbl(struct bnx2 *bp)
4343 {
4344         REG_WR(bp, BNX2_PCI_GRC_WINDOW_ADDR, BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN);
4345
4346         REG_WR(bp, BNX2_PCI_GRC_WINDOW2_ADDR, BNX2_MSIX_TABLE_ADDR);
4347         REG_WR(bp, BNX2_PCI_GRC_WINDOW3_ADDR, BNX2_MSIX_PBA_ADDR);
4348 }
4349
4350 static int
4351 bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
4352 {
4353         u32 val;
4354         int i, rc = 0;
4355         u8 old_port;
4356
4357         /* Wait for the current PCI transaction to complete before
4358          * issuing a reset. */
4359         REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
4360                BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
4361                BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
4362                BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
4363                BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
4364         val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
4365         udelay(5);
4366
4367         /* Wait for the firmware to tell us it is ok to issue a reset. */
4368         bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1, 1);
4369
4370         /* Deposit a driver reset signature so the firmware knows that
4371          * this is a soft reset. */
4372         bnx2_shmem_wr(bp, BNX2_DRV_RESET_SIGNATURE,
4373                       BNX2_DRV_RESET_SIGNATURE_MAGIC);
4374
4375         /* Do a dummy read to force the chip to complete all current transaction
4376          * before we issue a reset. */
4377         val = REG_RD(bp, BNX2_MISC_ID);
4378
4379         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4380                 REG_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET);
4381                 REG_RD(bp, BNX2_MISC_COMMAND);
4382                 udelay(5);
4383
4384                 val = BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4385                       BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4386
4387                 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, val);
4388
4389         } else {
4390                 val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4391                       BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4392                       BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4393
4394                 /* Chip reset. */
4395                 REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
4396
4397                 /* Reading back any register after chip reset will hang the
4398                  * bus on 5706 A0 and A1.  The msleep below provides plenty
4399                  * of margin for write posting.
4400                  */
4401                 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
4402                     (CHIP_ID(bp) == CHIP_ID_5706_A1))
4403                         msleep(20);
4404
4405                 /* Reset takes approximate 30 usec */
4406                 for (i = 0; i < 10; i++) {
4407                         val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
4408                         if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4409                                     BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
4410                                 break;
4411                         udelay(10);
4412                 }
4413
4414                 if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4415                            BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
4416                         printk(KERN_ERR PFX "Chip reset did not complete\n");
4417                         return -EBUSY;
4418                 }
4419         }
4420
4421         /* Make sure byte swapping is properly configured. */
4422         val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0);
4423         if (val != 0x01020304) {
4424                 printk(KERN_ERR PFX "Chip not in correct endian mode\n");
4425                 return -ENODEV;
4426         }
4427
4428         /* Wait for the firmware to finish its initialization. */
4429         rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 1, 0);
4430         if (rc)
4431                 return rc;
4432
4433         spin_lock_bh(&bp->phy_lock);
4434         old_port = bp->phy_port;
4435         bnx2_init_fw_cap(bp);
4436         if ((bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) &&
4437             old_port != bp->phy_port)
4438                 bnx2_set_default_remote_link(bp);
4439         spin_unlock_bh(&bp->phy_lock);
4440
4441         if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4442                 /* Adjust the voltage regular to two steps lower.  The default
4443                  * of this register is 0x0000000e. */
4444                 REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
4445
4446                 /* Remove bad rbuf memory from the free pool. */
4447                 rc = bnx2_alloc_bad_rbuf(bp);
4448         }
4449
4450         if (bp->flags & BNX2_FLAG_USING_MSIX)
4451                 bnx2_setup_msix_tbl(bp);
4452
4453         return rc;
4454 }
4455
4456 static int
4457 bnx2_init_chip(struct bnx2 *bp)
4458 {
4459         u32 val;
4460         int rc, i;
4461
4462         /* Make sure the interrupt is not active. */
4463         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
4464
4465         val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
4466               BNX2_DMA_CONFIG_DATA_WORD_SWAP |
4467 #ifdef __BIG_ENDIAN
4468               BNX2_DMA_CONFIG_CNTL_BYTE_SWAP |
4469 #endif
4470               BNX2_DMA_CONFIG_CNTL_WORD_SWAP |
4471               DMA_READ_CHANS << 12 |
4472               DMA_WRITE_CHANS << 16;
4473
4474         val |= (0x2 << 20) | (1 << 11);
4475
4476         if ((bp->flags & BNX2_FLAG_PCIX) && (bp->bus_speed_mhz == 133))
4477                 val |= (1 << 23);
4478
4479         if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
4480             (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & BNX2_FLAG_PCIX))
4481                 val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
4482
4483         REG_WR(bp, BNX2_DMA_CONFIG, val);
4484
4485         if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4486                 val = REG_RD(bp, BNX2_TDMA_CONFIG);
4487                 val |= BNX2_TDMA_CONFIG_ONE_DMA;
4488                 REG_WR(bp, BNX2_TDMA_CONFIG, val);
4489         }
4490
4491         if (bp->flags & BNX2_FLAG_PCIX) {
4492                 u16 val16;
4493
4494                 pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4495                                      &val16);
4496                 pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4497                                       val16 & ~PCI_X_CMD_ERO);
4498         }
4499
4500         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
4501                BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
4502                BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
4503                BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
4504
4505         /* Initialize context mapping and zero out the quick contexts.  The
4506          * context block must have already been enabled. */
4507         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4508                 rc = bnx2_init_5709_context(bp);
4509                 if (rc)
4510                         return rc;
4511         } else
4512                 bnx2_init_context(bp);
4513
4514         if ((rc = bnx2_init_cpus(bp)) != 0)
4515                 return rc;
4516
4517         bnx2_init_nvram(bp);
4518
4519         bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
4520
4521         val = REG_RD(bp, BNX2_MQ_CONFIG);
4522         val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
4523         val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
4524         if (CHIP_ID(bp) == CHIP_ID_5709_A0 || CHIP_ID(bp) == CHIP_ID_5709_A1)
4525                 val |= BNX2_MQ_CONFIG_HALT_DIS;
4526
4527         REG_WR(bp, BNX2_MQ_CONFIG, val);
4528
4529         val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
4530         REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
4531         REG_WR(bp, BNX2_MQ_KNL_WIND_END, val);
4532
4533         val = (BCM_PAGE_BITS - 8) << 24;
4534         REG_WR(bp, BNX2_RV2P_CONFIG, val);
4535
4536         /* Configure page size. */
4537         val = REG_RD(bp, BNX2_TBDR_CONFIG);
4538         val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
4539         val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
4540         REG_WR(bp, BNX2_TBDR_CONFIG, val);
4541
4542         val = bp->mac_addr[0] +
4543               (bp->mac_addr[1] << 8) +
4544               (bp->mac_addr[2] << 16) +
4545               bp->mac_addr[3] +
4546               (bp->mac_addr[4] << 8) +
4547               (bp->mac_addr[5] << 16);
4548         REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
4549
4550         /* Program the MTU.  Also include 4 bytes for CRC32. */
4551         val = bp->dev->mtu + ETH_HLEN + 4;
4552         if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
4553                 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
4554         REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
4555
4556         for (i = 0; i < BNX2_MAX_MSIX_VEC; i++)
4557                 bp->bnx2_napi[i].last_status_idx = 0;
4558
4559         bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;
4560
4561         /* Set up how to generate a link change interrupt. */
4562         REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
4563
4564         REG_WR(bp, BNX2_HC_STATUS_ADDR_L,
4565                (u64) bp->status_blk_mapping & 0xffffffff);
4566         REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
4567
4568         REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
4569                (u64) bp->stats_blk_mapping & 0xffffffff);
4570         REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
4571                (u64) bp->stats_blk_mapping >> 32);
4572
4573         REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
4574                (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
4575
4576         REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
4577                (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
4578
4579         REG_WR(bp, BNX2_HC_COMP_PROD_TRIP,
4580                (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
4581
4582         REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
4583
4584         REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
4585
4586         REG_WR(bp, BNX2_HC_COM_TICKS,
4587                (bp->com_ticks_int << 16) | bp->com_ticks);
4588
4589         REG_WR(bp, BNX2_HC_CMD_TICKS,
4590                (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
4591
4592         if (CHIP_NUM(bp) == CHIP_NUM_5708)
4593                 REG_WR(bp, BNX2_HC_STATS_TICKS, 0);
4594         else
4595                 REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks);
4596         REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8);  /* 3ms */
4597
4598         if (CHIP_ID(bp) == CHIP_ID_5706_A1)
4599                 val = BNX2_HC_CONFIG_COLLECT_STATS;
4600         else {
4601                 val = BNX2_HC_CONFIG_RX_TMR_MODE | BNX2_HC_CONFIG_TX_TMR_MODE |
4602                       BNX2_HC_CONFIG_COLLECT_STATS;
4603         }
4604
4605         if (bp->irq_nvecs > 1) {
4606                 REG_WR(bp, BNX2_HC_MSIX_BIT_VECTOR,
4607                        BNX2_HC_MSIX_BIT_VECTOR_VAL);
4608
4609                 val |= BNX2_HC_CONFIG_SB_ADDR_INC_128B;
4610         }
4611
4612         if (bp->flags & BNX2_FLAG_ONE_SHOT_MSI)
4613                 val |= BNX2_HC_CONFIG_ONE_SHOT;
4614
4615         REG_WR(bp, BNX2_HC_CONFIG, val);
4616
4617         for (i = 1; i < bp->irq_nvecs; i++) {
4618                 u32 base = ((i - 1) * BNX2_HC_SB_CONFIG_SIZE) +
4619                            BNX2_HC_SB_CONFIG_1;
4620
4621                 REG_WR(bp, base,
4622                         BNX2_HC_SB_CONFIG_1_TX_TMR_MODE |
4623                         BNX2_HC_SB_CONFIG_1_RX_TMR_MODE |
4624                         BNX2_HC_SB_CONFIG_1_ONE_SHOT);
4625
4626                 REG_WR(bp, base + BNX2_HC_TX_QUICK_CONS_TRIP_OFF,
4627                         (bp->tx_quick_cons_trip_int << 16) |
4628                          bp->tx_quick_cons_trip);
4629
4630                 REG_WR(bp, base + BNX2_HC_TX_TICKS_OFF,
4631                         (bp->tx_ticks_int << 16) | bp->tx_ticks);
4632
4633                 REG_WR(bp, base + BNX2_HC_RX_QUICK_CONS_TRIP_OFF,
4634                        (bp->rx_quick_cons_trip_int << 16) |
4635                         bp->rx_quick_cons_trip);
4636
4637                 REG_WR(bp, base + BNX2_HC_RX_TICKS_OFF,
4638                         (bp->rx_ticks_int << 16) | bp->rx_ticks);
4639         }
4640
4641         /* Clear internal stats counters. */
4642         REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
4643
4644         REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_EVENTS);
4645
4646         /* Initialize the receive filter. */
4647         bnx2_set_rx_mode(bp->dev);
4648
4649         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4650                 val = REG_RD(bp, BNX2_MISC_NEW_CORE_CTL);
4651                 val |= BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE;
4652                 REG_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
4653         }
4654         rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
4655                           1, 0);
4656
4657         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, BNX2_MISC_ENABLE_DEFAULT);
4658         REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
4659
4660         udelay(20);
4661
4662         bp->hc_cmd = REG_RD(bp, BNX2_HC_COMMAND);
4663
4664         return rc;
4665 }
4666
4667 static void
4668 bnx2_clear_ring_states(struct bnx2 *bp)
4669 {
4670         struct bnx2_napi *bnapi;
4671         struct bnx2_tx_ring_info *txr;
4672         struct bnx2_rx_ring_info *rxr;
4673         int i;
4674
4675         for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
4676                 bnapi = &bp->bnx2_napi[i];
4677                 txr = &bnapi->tx_ring;
4678                 rxr = &bnapi->rx_ring;
4679
4680                 txr->tx_cons = 0;
4681                 txr->hw_tx_cons = 0;
4682                 rxr->rx_prod_bseq = 0;
4683                 rxr->rx_prod = 0;
4684                 rxr->rx_cons = 0;
4685                 rxr->rx_pg_prod = 0;
4686                 rxr->rx_pg_cons = 0;
4687         }
4688 }
4689
4690 static void
4691 bnx2_init_tx_context(struct bnx2 *bp, u32 cid, struct bnx2_tx_ring_info *txr)
4692 {
4693         u32 val, offset0, offset1, offset2, offset3;
4694         u32 cid_addr = GET_CID_ADDR(cid);
4695
4696         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4697                 offset0 = BNX2_L2CTX_TYPE_XI;
4698                 offset1 = BNX2_L2CTX_CMD_TYPE_XI;
4699                 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
4700                 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
4701         } else {
4702                 offset0 = BNX2_L2CTX_TYPE;
4703                 offset1 = BNX2_L2CTX_CMD_TYPE;
4704                 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
4705                 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
4706         }
4707         val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
4708         bnx2_ctx_wr(bp, cid_addr, offset0, val);
4709
4710         val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
4711         bnx2_ctx_wr(bp, cid_addr, offset1, val);
4712
4713         val = (u64) txr->tx_desc_mapping >> 32;
4714         bnx2_ctx_wr(bp, cid_addr, offset2, val);
4715
4716         val = (u64) txr->tx_desc_mapping & 0xffffffff;
4717         bnx2_ctx_wr(bp, cid_addr, offset3, val);
4718 }
4719
4720 static void
4721 bnx2_init_tx_ring(struct bnx2 *bp, int ring_num)
4722 {
4723         struct tx_bd *txbd;
4724         u32 cid = TX_CID;
4725         struct bnx2_napi *bnapi;
4726         struct bnx2_tx_ring_info *txr;
4727
4728         bnapi = &bp->bnx2_napi[ring_num];
4729         txr = &bnapi->tx_ring;
4730
4731         if (ring_num == 0)
4732                 cid = TX_CID;
4733         else
4734                 cid = TX_TSS_CID + ring_num - 1;
4735
4736         bp->tx_wake_thresh = bp->tx_ring_size / 2;
4737
4738         txbd = &txr->tx_desc_ring[MAX_TX_DESC_CNT];
4739
4740         txbd->tx_bd_haddr_hi = (u64) txr->tx_desc_mapping >> 32;
4741         txbd->tx_bd_haddr_lo = (u64) txr->tx_desc_mapping & 0xffffffff;
4742
4743         txr->tx_prod = 0;
4744         txr->tx_prod_bseq = 0;
4745
4746         txr->tx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BIDX;
4747         txr->tx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BSEQ;
4748
4749         bnx2_init_tx_context(bp, cid, txr);
4750 }
4751
4752 static void
4753 bnx2_init_rxbd_rings(struct rx_bd *rx_ring[], dma_addr_t dma[], u32 buf_size,
4754                      int num_rings)
4755 {
4756         int i;
4757         struct rx_bd *rxbd;
4758
4759         for (i = 0; i < num_rings; i++) {
4760                 int j;
4761
4762                 rxbd = &rx_ring[i][0];
4763                 for (j = 0; j < MAX_RX_DESC_CNT; j++, rxbd++) {
4764                         rxbd->rx_bd_len = buf_size;
4765                         rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
4766                 }
4767                 if (i == (num_rings - 1))
4768                         j = 0;
4769                 else
4770                         j = i + 1;
4771                 rxbd->rx_bd_haddr_hi = (u64) dma[j] >> 32;
4772                 rxbd->rx_bd_haddr_lo = (u64) dma[j] & 0xffffffff;
4773         }
4774 }
4775
4776 static void
4777 bnx2_init_rx_ring(struct bnx2 *bp, int ring_num)
4778 {
4779         int i;
4780         u16 prod, ring_prod;
4781         u32 cid, rx_cid_addr, val;
4782         struct bnx2_napi *bnapi = &bp->bnx2_napi[ring_num];
4783         struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
4784
4785         if (ring_num == 0)
4786                 cid = RX_CID;
4787         else
4788                 cid = RX_RSS_CID + ring_num - 1;
4789
4790         rx_cid_addr = GET_CID_ADDR(cid);
4791
4792         bnx2_init_rxbd_rings(rxr->rx_desc_ring, rxr->rx_desc_mapping,
4793                              bp->rx_buf_use_size, bp->rx_max_ring);
4794
4795         bnx2_init_rx_context(bp, cid);
4796
4797         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4798                 val = REG_RD(bp, BNX2_MQ_MAP_L2_5);
4799                 REG_WR(bp, BNX2_MQ_MAP_L2_5, val | BNX2_MQ_MAP_L2_5_ARM);
4800         }
4801
4802         bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0);
4803         if (bp->rx_pg_ring_size) {
4804                 bnx2_init_rxbd_rings(rxr->rx_pg_desc_ring,
4805                                      rxr->rx_pg_desc_mapping,
4806                                      PAGE_SIZE, bp->rx_max_pg_ring);
4807                 val = (bp->rx_buf_use_size << 16) | PAGE_SIZE;
4808                 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, val);
4809                 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_RBDC_KEY,
4810                        BNX2_L2CTX_RBDC_JUMBO_KEY - ring_num);
4811
4812                 val = (u64) rxr->rx_pg_desc_mapping[0] >> 32;
4813                 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_HI, val);
4814
4815                 val = (u64) rxr->rx_pg_desc_mapping[0] & 0xffffffff;
4816                 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val);
4817
4818                 if (CHIP_NUM(bp) == CHIP_NUM_5709)
4819                         REG_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT);
4820         }
4821
4822         val = (u64) rxr->rx_desc_mapping[0] >> 32;
4823         bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
4824
4825         val = (u64) rxr->rx_desc_mapping[0] & 0xffffffff;
4826         bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
4827
4828         ring_prod = prod = rxr->rx_pg_prod;
4829         for (i = 0; i < bp->rx_pg_ring_size; i++) {
4830                 if (bnx2_alloc_rx_page(bp, rxr, ring_prod) < 0)
4831                         break;
4832                 prod = NEXT_RX_BD(prod);
4833                 ring_prod = RX_PG_RING_IDX(prod);
4834         }
4835         rxr->rx_pg_prod = prod;
4836
4837         ring_prod = prod = rxr->rx_prod;
4838         for (i = 0; i < bp->rx_ring_size; i++) {
4839                 if (bnx2_alloc_rx_skb(bp, rxr, ring_prod) < 0)
4840                         break;
4841                 prod = NEXT_RX_BD(prod);
4842                 ring_prod = RX_RING_IDX(prod);
4843         }
4844         rxr->rx_prod = prod;
4845
4846         rxr->rx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BDIDX;
4847         rxr->rx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BSEQ;
4848         rxr->rx_pg_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_PG_BDIDX;
4849
4850         REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
4851         REG_WR16(bp, rxr->rx_bidx_addr, prod);
4852
4853         REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
4854 }
4855
4856 static void
4857 bnx2_init_all_rings(struct bnx2 *bp)
4858 {
4859         int i;
4860         u32 val;
4861
4862         bnx2_clear_ring_states(bp);
4863
4864         REG_WR(bp, BNX2_TSCH_TSS_CFG, 0);
4865         for (i = 0; i < bp->num_tx_rings; i++)
4866                 bnx2_init_tx_ring(bp, i);
4867
4868         if (bp->num_tx_rings > 1)
4869                 REG_WR(bp, BNX2_TSCH_TSS_CFG, ((bp->num_tx_rings - 1) << 24) |
4870                        (TX_TSS_CID << 7));
4871
4872         REG_WR(bp, BNX2_RLUP_RSS_CONFIG, 0);
4873         bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ, 0);
4874
4875         for (i = 0; i < bp->num_rx_rings; i++)
4876                 bnx2_init_rx_ring(bp, i);
4877
4878         if (bp->num_rx_rings > 1) {
4879                 u32 tbl_32;
4880                 u8 *tbl = (u8 *) &tbl_32;
4881
4882                 bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ,
4883                                 BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES);
4884
4885                 for (i = 0; i < BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES; i++) {
4886                         tbl[i % 4] = i % (bp->num_rx_rings - 1);
4887                         if ((i % 4) == 3)
4888                                 bnx2_reg_wr_ind(bp,
4889                                                 BNX2_RXP_SCRATCH_RSS_TBL + i,
4890                                                 cpu_to_be32(tbl_32));
4891                 }
4892
4893                 val = BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_ALL_XI |
4894                       BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_ALL_XI;
4895
4896                 REG_WR(bp, BNX2_RLUP_RSS_CONFIG, val);
4897
4898         }
4899 }
4900
4901 static u32 bnx2_find_max_ring(u32 ring_size, u32 max_size)
4902 {
4903         u32 max, num_rings = 1;
4904
4905         while (ring_size > MAX_RX_DESC_CNT) {
4906                 ring_size -= MAX_RX_DESC_CNT;
4907                 num_rings++;
4908         }
4909         /* round to next power of 2 */
4910         max = max_size;
4911         while ((max & num_rings) == 0)
4912                 max >>= 1;
4913
4914         if (num_rings != max)
4915                 max <<= 1;
4916
4917         return max;
4918 }
4919
4920 static void
4921 bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size)
4922 {
4923         u32 rx_size, rx_space, jumbo_size;
4924
4925         /* 8 for CRC and VLAN */
4926         rx_size = bp->dev->mtu + ETH_HLEN + BNX2_RX_OFFSET + 8;
4927
4928         rx_space = SKB_DATA_ALIGN(rx_size + BNX2_RX_ALIGN) + NET_SKB_PAD +
4929                 sizeof(struct skb_shared_info);
4930
4931         bp->rx_copy_thresh = BNX2_RX_COPY_THRESH;
4932         bp->rx_pg_ring_size = 0;
4933         bp->rx_max_pg_ring = 0;
4934         bp->rx_max_pg_ring_idx = 0;
4935         if ((rx_space > PAGE_SIZE) && !(bp->flags & BNX2_FLAG_JUMBO_BROKEN)) {
4936                 int pages = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
4937
4938                 jumbo_size = size * pages;
4939                 if (jumbo_size > MAX_TOTAL_RX_PG_DESC_CNT)
4940                         jumbo_size = MAX_TOTAL_RX_PG_DESC_CNT;
4941
4942                 bp->rx_pg_ring_size = jumbo_size;
4943                 bp->rx_max_pg_ring = bnx2_find_max_ring(jumbo_size,
4944                                                         MAX_RX_PG_RINGS);
4945                 bp->rx_max_pg_ring_idx = (bp->rx_max_pg_ring * RX_DESC_CNT) - 1;
4946                 rx_size = BNX2_RX_COPY_THRESH + BNX2_RX_OFFSET;
4947                 bp->rx_copy_thresh = 0;
4948         }
4949
4950         bp->rx_buf_use_size = rx_size;
4951         /* hw alignment */
4952         bp->rx_buf_size = bp->rx_buf_use_size + BNX2_RX_ALIGN;
4953         bp->rx_jumbo_thresh = rx_size - BNX2_RX_OFFSET;
4954         bp->rx_ring_size = size;
4955         bp->rx_max_ring = bnx2_find_max_ring(size, MAX_RX_RINGS);
4956         bp->rx_max_ring_idx = (bp->rx_max_ring * RX_DESC_CNT) - 1;
4957 }
4958
4959 static void
4960 bnx2_free_tx_skbs(struct bnx2 *bp)
4961 {
4962         int i;
4963
4964         for (i = 0; i < bp->num_tx_rings; i++) {
4965                 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
4966                 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
4967                 int j;
4968
4969                 if (txr->tx_buf_ring == NULL)
4970                         continue;
4971
4972                 for (j = 0; j < TX_DESC_CNT; ) {
4973                         struct sw_bd *tx_buf = &txr->tx_buf_ring[j];
4974                         struct sk_buff *skb = tx_buf->skb;
4975                         int k, last;
4976
4977                         if (skb == NULL) {
4978                                 j++;
4979                                 continue;
4980                         }
4981
4982                         pci_unmap_single(bp->pdev,
4983                                          pci_unmap_addr(tx_buf, mapping),
4984                         skb_headlen(skb), PCI_DMA_TODEVICE);
4985
4986                         tx_buf->skb = NULL;
4987
4988                         last = skb_shinfo(skb)->nr_frags;
4989                         for (k = 0; k < last; k++) {
4990                                 tx_buf = &txr->tx_buf_ring[j + k + 1];
4991                                 pci_unmap_page(bp->pdev,
4992                                         pci_unmap_addr(tx_buf, mapping),
4993                                         skb_shinfo(skb)->frags[j].size,
4994                                         PCI_DMA_TODEVICE);
4995                         }
4996                         dev_kfree_skb(skb);
4997                         j += k + 1;
4998                 }
4999         }
5000 }
5001
5002 static void
5003 bnx2_free_rx_skbs(struct bnx2 *bp)
5004 {
5005         int i;
5006
5007         for (i = 0; i < bp->num_rx_rings; i++) {
5008                 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
5009                 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
5010                 int j;
5011
5012                 if (rxr->rx_buf_ring == NULL)
5013                         return;
5014
5015                 for (j = 0; j < bp->rx_max_ring_idx; j++) {
5016                         struct sw_bd *rx_buf = &rxr->rx_buf_ring[j];
5017                         struct sk_buff *skb = rx_buf->skb;
5018
5019                         if (skb == NULL)
5020                                 continue;
5021
5022                         pci_unmap_single(bp->pdev,
5023                                          pci_unmap_addr(rx_buf, mapping),
5024                                          bp->rx_buf_use_size,
5025                                          PCI_DMA_FROMDEVICE);
5026
5027                         rx_buf->skb = NULL;
5028
5029                         dev_kfree_skb(skb);
5030                 }
5031                 for (j = 0; j < bp->rx_max_pg_ring_idx; j++)
5032                         bnx2_free_rx_page(bp, rxr, j);
5033         }
5034 }
5035
5036 static void
5037 bnx2_free_skbs(struct bnx2 *bp)
5038 {
5039         bnx2_free_tx_skbs(bp);
5040         bnx2_free_rx_skbs(bp);
5041 }
5042
5043 static int
5044 bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
5045 {
5046         int rc;
5047
5048         rc = bnx2_reset_chip(bp, reset_code);
5049         bnx2_free_skbs(bp);
5050         if (rc)
5051                 return rc;
5052
5053         if ((rc = bnx2_init_chip(bp)) != 0)
5054                 return rc;
5055
5056         bnx2_init_all_rings(bp);
5057         return 0;
5058 }
5059
5060 static int
5061 bnx2_init_nic(struct bnx2 *bp, int reset_phy)
5062 {
5063         int rc;
5064
5065         if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
5066                 return rc;
5067
5068         spin_lock_bh(&bp->phy_lock);
5069         bnx2_init_phy(bp, reset_phy);
5070         bnx2_set_link(bp);
5071         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
5072                 bnx2_remote_phy_event(bp);
5073         spin_unlock_bh(&bp->phy_lock);
5074         return 0;
5075 }
5076
5077 static int
5078 bnx2_test_registers(struct bnx2 *bp)
5079 {
5080         int ret;
5081         int i, is_5709;
5082         static const struct {
5083                 u16   offset;
5084                 u16   flags;
5085 #define BNX2_FL_NOT_5709        1
5086                 u32   rw_mask;
5087                 u32   ro_mask;
5088         } reg_tbl[] = {
5089                 { 0x006c, 0, 0x00000000, 0x0000003f },
5090                 { 0x0090, 0, 0xffffffff, 0x00000000 },
5091                 { 0x0094, 0, 0x00000000, 0x00000000 },
5092
5093                 { 0x0404, BNX2_FL_NOT_5709, 0x00003f00, 0x00000000 },
5094                 { 0x0418, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5095                 { 0x041c, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5096                 { 0x0420, BNX2_FL_NOT_5709, 0x00000000, 0x80ffffff },
5097                 { 0x0424, BNX2_FL_NOT_5709, 0x00000000, 0x00000000 },
5098                 { 0x0428, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
5099                 { 0x0450, BNX2_FL_NOT_5709, 0x00000000, 0x0000ffff },
5100                 { 0x0454, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5101                 { 0x0458, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5102
5103                 { 0x0808, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5104                 { 0x0854, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5105                 { 0x0868, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5106                 { 0x086c, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5107                 { 0x0870, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5108                 { 0x0874, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5109
5110                 { 0x0c00, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
5111                 { 0x0c04, BNX2_FL_NOT_5709, 0x00000000, 0x03ff0001 },
5112                 { 0x0c08, BNX2_FL_NOT_5709,  0x0f0ff073, 0x00000000 },
5113
5114                 { 0x1000, 0, 0x00000000, 0x00000001 },
5115                 { 0x1004, BNX2_FL_NOT_5709, 0x00000000, 0x000f0001 },
5116
5117                 { 0x1408, 0, 0x01c00800, 0x00000000 },
5118                 { 0x149c, 0, 0x8000ffff, 0x00000000 },
5119                 { 0x14a8, 0, 0x00000000, 0x000001ff },
5120                 { 0x14ac, 0, 0x0fffffff, 0x10000000 },
5121                 { 0x14b0, 0, 0x00000002, 0x00000001 },
5122                 { 0x14b8, 0, 0x00000000, 0x00000000 },
5123                 { 0x14c0, 0, 0x00000000, 0x00000009 },
5124                 { 0x14c4, 0, 0x00003fff, 0x00000000 },
5125                 { 0x14cc, 0, 0x00000000, 0x00000001 },
5126                 { 0x14d0, 0, 0xffffffff, 0x00000000 },
5127
5128                 { 0x1800, 0, 0x00000000, 0x00000001 },
5129                 { 0x1804, 0, 0x00000000, 0x00000003 },
5130
5131                 { 0x2800, 0, 0x00000000, 0x00000001 },
5132                 { 0x2804, 0, 0x00000000, 0x00003f01 },
5133                 { 0x2808, 0, 0x0f3f3f03, 0x00000000 },
5134                 { 0x2810, 0, 0xffff0000, 0x00000000 },
5135                 { 0x2814, 0, 0xffff0000, 0x00000000 },
5136                 { 0x2818, 0, 0xffff0000, 0x00000000 },
5137                 { 0x281c, 0, 0xffff0000, 0x00000000 },
5138                 { 0x2834, 0, 0xffffffff, 0x00000000 },
5139                 { 0x2840, 0, 0x00000000, 0xffffffff },
5140                 { 0x2844, 0, 0x00000000, 0xffffffff },
5141                 { 0x2848, 0, 0xffffffff, 0x00000000 },
5142                 { 0x284c, 0, 0xf800f800, 0x07ff07ff },
5143
5144                 { 0x2c00, 0, 0x00000000, 0x00000011 },
5145                 { 0x2c04, 0, 0x00000000, 0x00030007 },
5146
5147                 { 0x3c00, 0, 0x00000000, 0x00000001 },
5148                 { 0x3c04, 0, 0x00000000, 0x00070000 },
5149                 { 0x3c08, 0, 0x00007f71, 0x07f00000 },
5150                 { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 },
5151                 { 0x3c10, 0, 0xffffffff, 0x00000000 },
5152                 { 0x3c14, 0, 0x00000000, 0xffffffff },
5153                 { 0x3c18, 0, 0x00000000, 0xffffffff },
5154                 { 0x3c1c, 0, 0xfffff000, 0x00000000 },
5155                 { 0x3c20, 0, 0xffffff00, 0x00000000 },
5156
5157                 { 0x5004, 0, 0x00000000, 0x0000007f },
5158                 { 0x5008, 0, 0x0f0007ff, 0x00000000 },
5159
5160                 { 0x5c00, 0, 0x00000000, 0x00000001 },
5161                 { 0x5c04, 0, 0x00000000, 0x0003000f },
5162                 { 0x5c08, 0, 0x00000003, 0x00000000 },
5163                 { 0x5c0c, 0, 0x0000fff8, 0x00000000 },
5164                 { 0x5c10, 0, 0x00000000, 0xffffffff },
5165                 { 0x5c80, 0, 0x00000000, 0x0f7113f1 },
5166                 { 0x5c84, 0, 0x00000000, 0x0000f333 },
5167                 { 0x5c88, 0, 0x00000000, 0x00077373 },
5168                 { 0x5c8c, 0, 0x00000000, 0x0007f737 },
5169
5170                 { 0x6808, 0, 0x0000ff7f, 0x00000000 },
5171                 { 0x680c, 0, 0xffffffff, 0x00000000 },
5172                 { 0x6810, 0, 0xffffffff, 0x00000000 },
5173                 { 0x6814, 0, 0xffffffff, 0x00000000 },
5174                 { 0x6818, 0, 0xffffffff, 0x00000000 },
5175                 { 0x681c, 0, 0xffffffff, 0x00000000 },
5176                 { 0x6820, 0, 0x00ff00ff, 0x00000000 },
5177                 { 0x6824, 0, 0x00ff00ff, 0x00000000 },
5178                 { 0x6828, 0, 0x00ff00ff, 0x00000000 },
5179                 { 0x682c, 0, 0x03ff03ff, 0x00000000 },
5180                 { 0x6830, 0, 0x03ff03ff, 0x00000000 },
5181                 { 0x6834, 0, 0x03ff03ff, 0x00000000 },
5182                 { 0x6838, 0, 0x03ff03ff, 0x00000000 },
5183                 { 0x683c, 0, 0x0000ffff, 0x00000000 },
5184                 { 0x6840, 0, 0x00000ff0, 0x00000000 },
5185                 { 0x6844, 0, 0x00ffff00, 0x00000000 },
5186                 { 0x684c, 0, 0xffffffff, 0x00000000 },
5187                 { 0x6850, 0, 0x7f7f7f7f, 0x00000000 },
5188                 { 0x6854, 0, 0x7f7f7f7f, 0x00000000 },
5189                 { 0x6858, 0, 0x7f7f7f7f, 0x00000000 },
5190                 { 0x685c, 0, 0x7f7f7f7f, 0x00000000 },
5191                 { 0x6908, 0, 0x00000000, 0x0001ff0f },
5192                 { 0x690c, 0, 0x00000000, 0x0ffe00f0 },
5193
5194                 { 0xffff, 0, 0x00000000, 0x00000000 },
5195         };
5196
5197         ret = 0;
5198         is_5709 = 0;
5199         if (CHIP_NUM(bp) == CHIP_NUM_5709)
5200                 is_5709 = 1;
5201
5202         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
5203                 u32 offset, rw_mask, ro_mask, save_val, val;
5204                 u16 flags = reg_tbl[i].flags;
5205
5206                 if (is_5709 && (flags & BNX2_FL_NOT_5709))
5207                         continue;
5208
5209                 offset = (u32) reg_tbl[i].offset;
5210                 rw_mask = reg_tbl[i].rw_mask;
5211                 ro_mask = reg_tbl[i].ro_mask;
5212
5213                 save_val = readl(bp->regview + offset);
5214
5215                 writel(0, bp->regview + offset);
5216
5217                 val = readl(bp->regview + offset);
5218                 if ((val & rw_mask) != 0) {
5219                         goto reg_test_err;
5220                 }
5221
5222                 if ((val & ro_mask) != (save_val & ro_mask)) {
5223                         goto reg_test_err;
5224                 }
5225
5226                 writel(0xffffffff, bp->regview + offset);
5227
5228                 val = readl(bp->regview + offset);
5229                 if ((val & rw_mask) != rw_mask) {
5230                         goto reg_test_err;
5231                 }
5232
5233                 if ((val & ro_mask) != (save_val & ro_mask)) {
5234                         goto reg_test_err;
5235                 }
5236
5237                 writel(save_val, bp->regview + offset);
5238                 continue;
5239
5240 reg_test_err:
5241                 writel(save_val, bp->regview + offset);
5242                 ret = -ENODEV;
5243                 break;
5244         }
5245         return ret;
5246 }
5247
5248 static int
5249 bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)
5250 {
5251         static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555,
5252                 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa };
5253         int i;
5254
5255         for (i = 0; i < sizeof(test_pattern) / 4; i++) {
5256                 u32 offset;
5257
5258                 for (offset = 0; offset < size; offset += 4) {
5259
5260                         bnx2_reg_wr_ind(bp, start + offset, test_pattern[i]);
5261
5262                         if (bnx2_reg_rd_ind(bp, start + offset) !=
5263                                 test_pattern[i]) {
5264                                 return -ENODEV;
5265                         }
5266                 }
5267         }
5268         return 0;
5269 }
5270
5271 static int
5272 bnx2_test_memory(struct bnx2 *bp)
5273 {
5274         int ret = 0;
5275         int i;
5276         static struct mem_entry {
5277                 u32   offset;
5278                 u32   len;
5279         } mem_tbl_5706[] = {
5280                 { 0x60000,  0x4000 },
5281                 { 0xa0000,  0x3000 },
5282                 { 0xe0000,  0x4000 },
5283                 { 0x120000, 0x4000 },
5284                 { 0x1a0000, 0x4000 },
5285                 { 0x160000, 0x4000 },
5286                 { 0xffffffff, 0    },
5287         },
5288         mem_tbl_5709[] = {
5289                 { 0x60000,  0x4000 },
5290                 { 0xa0000,  0x3000 },
5291                 { 0xe0000,  0x4000 },
5292                 { 0x120000, 0x4000 },
5293                 { 0x1a0000, 0x4000 },
5294                 { 0xffffffff, 0    },
5295         };
5296         struct mem_entry *mem_tbl;
5297
5298         if (CHIP_NUM(bp) == CHIP_NUM_5709)
5299                 mem_tbl = mem_tbl_5709;
5300         else
5301                 mem_tbl = mem_tbl_5706;
5302
5303         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
5304                 if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,
5305                         mem_tbl[i].len)) != 0) {
5306                         return ret;
5307                 }
5308         }
5309
5310         return ret;
5311 }
5312
5313 #define BNX2_MAC_LOOPBACK       0
5314 #define BNX2_PHY_LOOPBACK       1
5315
5316 static int
5317 bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
5318 {
5319         unsigned int pkt_size, num_pkts, i;
5320         struct sk_buff *skb, *rx_skb;
5321         unsigned char *packet;
5322         u16 rx_start_idx, rx_idx;
5323         dma_addr_t map;
5324         struct tx_bd *txbd;
5325         struct sw_bd *rx_buf;
5326         struct l2_fhdr *rx_hdr;
5327         int ret = -ENODEV;
5328         struct bnx2_napi *bnapi = &bp->bnx2_napi[0], *tx_napi;
5329         struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
5330         struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
5331
5332         tx_napi = bnapi;
5333
5334         txr = &tx_napi->tx_ring;
5335         rxr = &bnapi->rx_ring;
5336         if (loopback_mode == BNX2_MAC_LOOPBACK) {
5337                 bp->loopback = MAC_LOOPBACK;
5338                 bnx2_set_mac_loopback(bp);
5339         }
5340         else if (loopback_mode == BNX2_PHY_LOOPBACK) {
5341                 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
5342                         return 0;
5343
5344                 bp->loopback = PHY_LOOPBACK;
5345                 bnx2_set_phy_loopback(bp);
5346         }
5347         else
5348                 return -EINVAL;
5349
5350         pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_jumbo_thresh - 4);
5351         skb = netdev_alloc_skb(bp->dev, pkt_size);
5352         if (!skb)
5353                 return -ENOMEM;
5354         packet = skb_put(skb, pkt_size);
5355         memcpy(packet, bp->dev->dev_addr, 6);
5356         memset(packet + 6, 0x0, 8);
5357         for (i = 14; i < pkt_size; i++)
5358                 packet[i] = (unsigned char) (i & 0xff);
5359
5360         map = pci_map_single(bp->pdev, skb->data, pkt_size,
5361                 PCI_DMA_TODEVICE);
5362
5363         REG_WR(bp, BNX2_HC_COMMAND,
5364                bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5365
5366         REG_RD(bp, BNX2_HC_COMMAND);
5367
5368         udelay(5);
5369         rx_start_idx = bnx2_get_hw_rx_cons(bnapi);
5370
5371         num_pkts = 0;
5372
5373         txbd = &txr->tx_desc_ring[TX_RING_IDX(txr->tx_prod)];
5374
5375         txbd->tx_bd_haddr_hi = (u64) map >> 32;
5376         txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff;
5377         txbd->tx_bd_mss_nbytes = pkt_size;
5378         txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;
5379
5380         num_pkts++;
5381         txr->tx_prod = NEXT_TX_BD(txr->tx_prod);
5382         txr->tx_prod_bseq += pkt_size;
5383
5384         REG_WR16(bp, txr->tx_bidx_addr, txr->tx_prod);
5385         REG_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
5386
5387         udelay(100);
5388
5389         REG_WR(bp, BNX2_HC_COMMAND,
5390                bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5391
5392         REG_RD(bp, BNX2_HC_COMMAND);
5393
5394         udelay(5);
5395
5396         pci_unmap_single(bp->pdev, map, pkt_size, PCI_DMA_TODEVICE);
5397         dev_kfree_skb(skb);
5398
5399         if (bnx2_get_hw_tx_cons(tx_napi) != txr->tx_prod)
5400                 goto loopback_test_done;
5401
5402         rx_idx = bnx2_get_hw_rx_cons(bnapi);
5403         if (rx_idx != rx_start_idx + num_pkts) {
5404                 goto loopback_test_done;
5405         }
5406
5407         rx_buf = &rxr->rx_buf_ring[rx_start_idx];
5408         rx_skb = rx_buf->skb;
5409
5410         rx_hdr = (struct l2_fhdr *) rx_skb->data;
5411         skb_reserve(rx_skb, BNX2_RX_OFFSET);
5412
5413         pci_dma_sync_single_for_cpu(bp->pdev,
5414                 pci_unmap_addr(rx_buf, mapping),
5415                 bp->rx_buf_size, PCI_DMA_FROMDEVICE);
5416
5417         if (rx_hdr->l2_fhdr_status &
5418                 (L2_FHDR_ERRORS_BAD_CRC |
5419                 L2_FHDR_ERRORS_PHY_DECODE |
5420                 L2_FHDR_ERRORS_ALIGNMENT |
5421                 L2_FHDR_ERRORS_TOO_SHORT |
5422                 L2_FHDR_ERRORS_GIANT_FRAME)) {
5423
5424                 goto loopback_test_done;
5425         }
5426
5427         if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) {
5428                 goto loopback_test_done;
5429         }
5430
5431         for (i = 14; i < pkt_size; i++) {
5432                 if (*(rx_skb->data + i) != (unsigned char) (i & 0xff)) {
5433                         goto loopback_test_done;
5434                 }
5435         }
5436
5437         ret = 0;
5438
5439 loopback_test_done:
5440         bp->loopback = 0;
5441         return ret;
5442 }
5443
5444 #define BNX2_MAC_LOOPBACK_FAILED        1
5445 #define BNX2_PHY_LOOPBACK_FAILED        2
5446 #define BNX2_LOOPBACK_FAILED            (BNX2_MAC_LOOPBACK_FAILED |     \
5447                                          BNX2_PHY_LOOPBACK_FAILED)
5448
5449 static int
5450 bnx2_test_loopback(struct bnx2 *bp)
5451 {
5452         int rc = 0;
5453
5454         if (!netif_running(bp->dev))
5455                 return BNX2_LOOPBACK_FAILED;
5456
5457         bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
5458         spin_lock_bh(&bp->phy_lock);
5459         bnx2_init_phy(bp, 1);
5460         spin_unlock_bh(&bp->phy_lock);
5461         if (bnx2_run_loopback(bp, BNX2_MAC_LOOPBACK))
5462                 rc |= BNX2_MAC_LOOPBACK_FAILED;
5463         if (bnx2_run_loopback(bp, BNX2_PHY_LOOPBACK))
5464                 rc |= BNX2_PHY_LOOPBACK_FAILED;
5465         return rc;
5466 }
5467
5468 #define NVRAM_SIZE 0x200
5469 #define CRC32_RESIDUAL 0xdebb20e3
5470
5471 static int
5472 bnx2_test_nvram(struct bnx2 *bp)
5473 {
5474         __be32 buf[NVRAM_SIZE / 4];
5475         u8 *data = (u8 *) buf;
5476         int rc = 0;
5477         u32 magic, csum;
5478
5479         if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)
5480                 goto test_nvram_done;
5481
5482         magic = be32_to_cpu(buf[0]);
5483         if (magic != 0x669955aa) {
5484                 rc = -ENODEV;
5485                 goto test_nvram_done;
5486         }
5487
5488         if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)
5489                 goto test_nvram_done;
5490
5491         csum = ether_crc_le(0x100, data);
5492         if (csum != CRC32_RESIDUAL) {
5493                 rc = -ENODEV;
5494                 goto test_nvram_done;
5495         }
5496
5497         csum = ether_crc_le(0x100, data + 0x100);
5498         if (csum != CRC32_RESIDUAL) {
5499                 rc = -ENODEV;
5500         }
5501
5502 test_nvram_done:
5503         return rc;
5504 }
5505
5506 static int
5507 bnx2_test_link(struct bnx2 *bp)
5508 {
5509         u32 bmsr;
5510
5511         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
5512                 if (bp->link_up)
5513                         return 0;
5514                 return -ENODEV;
5515         }
5516         spin_lock_bh(&bp->phy_lock);
5517         bnx2_enable_bmsr1(bp);
5518         bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5519         bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5520         bnx2_disable_bmsr1(bp);
5521         spin_unlock_bh(&bp->phy_lock);
5522
5523         if (bmsr & BMSR_LSTATUS) {
5524                 return 0;
5525         }
5526         return -ENODEV;
5527 }
5528
5529 static int
5530 bnx2_test_intr(struct bnx2 *bp)
5531 {
5532         int i;
5533         u16 status_idx;
5534
5535         if (!netif_running(bp->dev))
5536                 return -ENODEV;
5537
5538         status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;
5539
5540         /* This register is not touched during run-time. */
5541         REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
5542         REG_RD(bp, BNX2_HC_COMMAND);
5543
5544         for (i = 0; i < 10; i++) {
5545                 if ((REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=
5546                         status_idx) {
5547
5548                         break;
5549                 }
5550
5551                 msleep_interruptible(10);
5552         }
5553         if (i < 10)
5554                 return 0;
5555
5556         return -ENODEV;
5557 }
5558
5559 /* Determining link for parallel detection. */
5560 static int
5561 bnx2_5706_serdes_has_link(struct bnx2 *bp)
5562 {
5563         u32 mode_ctl, an_dbg, exp;
5564
5565         if (bp->phy_flags & BNX2_PHY_FLAG_NO_PARALLEL)
5566                 return 0;
5567
5568         bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_MODE_CTL);
5569         bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &mode_ctl);
5570
5571         if (!(mode_ctl & MISC_SHDW_MODE_CTL_SIG_DET))
5572                 return 0;
5573
5574         bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
5575         bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
5576         bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
5577
5578         if (an_dbg & (MISC_SHDW_AN_DBG_NOSYNC | MISC_SHDW_AN_DBG_RUDI_INVALID))
5579                 return 0;
5580
5581         bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_REG1);
5582         bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
5583         bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
5584
5585         if (exp & MII_EXPAND_REG1_RUDI_C)       /* receiving CONFIG */
5586                 return 0;
5587
5588         return 1;
5589 }
5590
5591 static void
5592 bnx2_5706_serdes_timer(struct bnx2 *bp)
5593 {
5594         int check_link = 1;
5595
5596         spin_lock(&bp->phy_lock);
5597         if (bp->serdes_an_pending) {
5598                 bp->serdes_an_pending--;
5599                 check_link = 0;
5600         } else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
5601                 u32 bmcr;
5602
5603                 bp->current_interval = bp->timer_interval;
5604
5605                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
5606
5607                 if (bmcr & BMCR_ANENABLE) {
5608                         if (bnx2_5706_serdes_has_link(bp)) {
5609                                 bmcr &= ~BMCR_ANENABLE;
5610                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
5611                                 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
5612                                 bp->phy_flags |= BNX2_PHY_FLAG_PARALLEL_DETECT;
5613                         }
5614                 }
5615         }
5616         else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
5617                  (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)) {
5618                 u32 phy2;
5619
5620                 bnx2_write_phy(bp, 0x17, 0x0f01);
5621                 bnx2_read_phy(bp, 0x15, &phy2);
5622                 if (phy2 & 0x20) {
5623                         u32 bmcr;
5624
5625                         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
5626                         bmcr |= BMCR_ANENABLE;
5627                         bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
5628
5629                         bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
5630                 }
5631         } else
5632                 bp->current_interval = bp->timer_interval;
5633
5634         if (check_link) {
5635                 u32 val;
5636
5637                 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
5638                 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
5639                 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
5640
5641                 if (bp->link_up && (val & MISC_SHDW_AN_DBG_NOSYNC)) {
5642                         if (!(bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN)) {
5643                                 bnx2_5706s_force_link_dn(bp, 1);
5644                                 bp->phy_flags |= BNX2_PHY_FLAG_FORCED_DOWN;
5645                         } else
5646                                 bnx2_set_link(bp);
5647                 } else if (!bp->link_up && !(val & MISC_SHDW_AN_DBG_NOSYNC))
5648                         bnx2_set_link(bp);
5649         }
5650         spin_unlock(&bp->phy_lock);
5651 }
5652
5653 static void
5654 bnx2_5708_serdes_timer(struct bnx2 *bp)
5655 {
5656         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
5657                 return;
5658
5659         if ((bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) == 0) {
5660                 bp->serdes_an_pending = 0;
5661                 return;
5662         }
5663
5664         spin_lock(&bp->phy_lock);
5665         if (bp->serdes_an_pending)
5666                 bp->serdes_an_pending--;
5667         else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
5668                 u32 bmcr;
5669
5670                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
5671                 if (bmcr & BMCR_ANENABLE) {
5672                         bnx2_enable_forced_2g5(bp);
5673                         bp->current_interval = SERDES_FORCED_TIMEOUT;
5674                 } else {
5675                         bnx2_disable_forced_2g5(bp);
5676                         bp->serdes_an_pending = 2;
5677                         bp->current_interval = bp->timer_interval;
5678                 }
5679
5680         } else
5681                 bp->current_interval = bp->timer_interval;
5682
5683         spin_unlock(&bp->phy_lock);
5684 }
5685
5686 static void
5687 bnx2_timer(unsigned long data)
5688 {
5689         struct bnx2 *bp = (struct bnx2 *) data;
5690
5691         if (!netif_running(bp->dev))
5692                 return;
5693
5694         if (atomic_read(&bp->intr_sem) != 0)
5695                 goto bnx2_restart_timer;
5696
5697         bnx2_send_heart_beat(bp);
5698
5699         bp->stats_blk->stat_FwRxDrop =
5700                 bnx2_reg_rd_ind(bp, BNX2_FW_RX_DROP_COUNT);
5701
5702         /* workaround occasional corrupted counters */
5703         if (CHIP_NUM(bp) == CHIP_NUM_5708 && bp->stats_ticks)
5704                 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd |
5705                                             BNX2_HC_COMMAND_STATS_NOW);
5706
5707         if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
5708                 if (CHIP_NUM(bp) == CHIP_NUM_5706)
5709                         bnx2_5706_serdes_timer(bp);
5710                 else
5711                         bnx2_5708_serdes_timer(bp);
5712         }
5713
5714 bnx2_restart_timer:
5715         mod_timer(&bp->timer, jiffies + bp->current_interval);
5716 }
5717
5718 static int
5719 bnx2_request_irq(struct bnx2 *bp)
5720 {
5721         unsigned long flags;
5722         struct bnx2_irq *irq;
5723         int rc = 0, i;
5724
5725         if (bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)
5726                 flags = 0;
5727         else
5728                 flags = IRQF_SHARED;
5729
5730         for (i = 0; i < bp->irq_nvecs; i++) {
5731                 irq = &bp->irq_tbl[i];
5732                 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
5733                                  &bp->bnx2_napi[i]);
5734                 if (rc)
5735                         break;
5736                 irq->requested = 1;
5737         }
5738         return rc;
5739 }
5740
5741 static void
5742 bnx2_free_irq(struct bnx2 *bp)
5743 {
5744         struct bnx2_irq *irq;
5745         int i;
5746
5747         for (i = 0; i < bp->irq_nvecs; i++) {
5748                 irq = &bp->irq_tbl[i];
5749                 if (irq->requested)
5750                         free_irq(irq->vector, &bp->bnx2_napi[i]);
5751                 irq->requested = 0;
5752         }
5753         if (bp->flags & BNX2_FLAG_USING_MSI)
5754                 pci_disable_msi(bp->pdev);
5755         else if (bp->flags & BNX2_FLAG_USING_MSIX)
5756                 pci_disable_msix(bp->pdev);
5757
5758         bp->flags &= ~(BNX2_FLAG_USING_MSI_OR_MSIX | BNX2_FLAG_ONE_SHOT_MSI);
5759 }
5760
5761 static void
5762 bnx2_enable_msix(struct bnx2 *bp, int msix_vecs)
5763 {
5764         int i, rc;
5765         struct msix_entry msix_ent[BNX2_MAX_MSIX_VEC];
5766
5767         bnx2_setup_msix_tbl(bp);
5768         REG_WR(bp, BNX2_PCI_MSIX_CONTROL, BNX2_MAX_MSIX_HW_VEC - 1);
5769         REG_WR(bp, BNX2_PCI_MSIX_TBL_OFF_BIR, BNX2_PCI_GRC_WINDOW2_BASE);
5770         REG_WR(bp, BNX2_PCI_MSIX_PBA_OFF_BIT, BNX2_PCI_GRC_WINDOW3_BASE);
5771
5772         for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
5773                 msix_ent[i].entry = i;
5774                 msix_ent[i].vector = 0;
5775
5776                 strcpy(bp->irq_tbl[i].name, bp->dev->name);
5777                 bp->irq_tbl[i].handler = bnx2_msi_1shot;
5778         }
5779
5780         rc = pci_enable_msix(bp->pdev, msix_ent, BNX2_MAX_MSIX_VEC);
5781         if (rc != 0)
5782                 return;
5783
5784         bp->irq_nvecs = msix_vecs;
5785         bp->flags |= BNX2_FLAG_USING_MSIX | BNX2_FLAG_ONE_SHOT_MSI;
5786         for (i = 0; i < BNX2_MAX_MSIX_VEC; i++)
5787                 bp->irq_tbl[i].vector = msix_ent[i].vector;
5788 }
5789
5790 static void
5791 bnx2_setup_int_mode(struct bnx2 *bp, int dis_msi)
5792 {
5793         int cpus = num_online_cpus();
5794         int msix_vecs = min(cpus + 1, RX_MAX_RINGS);
5795
5796         bp->irq_tbl[0].handler = bnx2_interrupt;
5797         strcpy(bp->irq_tbl[0].name, bp->dev->name);
5798         bp->irq_nvecs = 1;
5799         bp->irq_tbl[0].vector = bp->pdev->irq;
5800
5801         if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !dis_msi && cpus > 1)
5802                 bnx2_enable_msix(bp, msix_vecs);
5803
5804         if ((bp->flags & BNX2_FLAG_MSI_CAP) && !dis_msi &&
5805             !(bp->flags & BNX2_FLAG_USING_MSIX)) {
5806                 if (pci_enable_msi(bp->pdev) == 0) {
5807                         bp->flags |= BNX2_FLAG_USING_MSI;
5808                         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
5809                                 bp->flags |= BNX2_FLAG_ONE_SHOT_MSI;
5810                                 bp->irq_tbl[0].handler = bnx2_msi_1shot;
5811                         } else
5812                                 bp->irq_tbl[0].handler = bnx2_msi;
5813
5814                         bp->irq_tbl[0].vector = bp->pdev->irq;
5815                 }
5816         }
5817
5818         bp->num_tx_rings = rounddown_pow_of_two(bp->irq_nvecs);
5819         bp->dev->real_num_tx_queues = bp->num_tx_rings;
5820
5821         bp->num_rx_rings = bp->irq_nvecs;
5822 }
5823
5824 /* Called with rtnl_lock */
5825 static int
5826 bnx2_open(struct net_device *dev)
5827 {
5828         struct bnx2 *bp = netdev_priv(dev);
5829         int rc;
5830
5831         netif_carrier_off(dev);
5832
5833         bnx2_set_power_state(bp, PCI_D0);
5834         bnx2_disable_int(bp);
5835
5836         bnx2_setup_int_mode(bp, disable_msi);
5837         bnx2_napi_enable(bp);
5838         rc = bnx2_alloc_mem(bp);
5839         if (rc)
5840                 goto open_err;
5841
5842         rc = bnx2_request_irq(bp);
5843         if (rc)
5844                 goto open_err;
5845
5846         rc = bnx2_init_nic(bp, 1);
5847         if (rc)
5848                 goto open_err;
5849
5850         mod_timer(&bp->timer, jiffies + bp->current_interval);
5851
5852         atomic_set(&bp->intr_sem, 0);
5853
5854         bnx2_enable_int(bp);
5855
5856         if (bp->flags & BNX2_FLAG_USING_MSI) {
5857                 /* Test MSI to make sure it is working
5858                  * If MSI test fails, go back to INTx mode
5859                  */
5860                 if (bnx2_test_intr(bp) != 0) {
5861                         printk(KERN_WARNING PFX "%s: No interrupt was generated"
5862                                " using MSI, switching to INTx mode. Please"
5863                                " report this failure to the PCI maintainer"
5864                                " and include system chipset information.\n",
5865                                bp->dev->name);
5866
5867                         bnx2_disable_int(bp);
5868                         bnx2_free_irq(bp);
5869
5870                         bnx2_setup_int_mode(bp, 1);
5871
5872                         rc = bnx2_init_nic(bp, 0);
5873
5874                         if (!rc)
5875                                 rc = bnx2_request_irq(bp);
5876
5877                         if (rc) {
5878                                 del_timer_sync(&bp->timer);
5879                                 goto open_err;
5880                         }
5881                         bnx2_enable_int(bp);
5882                 }
5883         }
5884         if (bp->flags & BNX2_FLAG_USING_MSI)
5885                 printk(KERN_INFO PFX "%s: using MSI\n", dev->name);
5886         else if (bp->flags & BNX2_FLAG_USING_MSIX)
5887                 printk(KERN_INFO PFX "%s: using MSIX\n", dev->name);
5888
5889         netif_tx_start_all_queues(dev);
5890
5891         return 0;
5892
5893 open_err:
5894         bnx2_napi_disable(bp);
5895         bnx2_free_skbs(bp);
5896         bnx2_free_irq(bp);
5897         bnx2_free_mem(bp);
5898         return rc;
5899 }
5900
5901 static void
5902 bnx2_reset_task(struct work_struct *work)
5903 {
5904         struct bnx2 *bp = container_of(work, struct bnx2, reset_task);
5905
5906         if (!netif_running(bp->dev))
5907                 return;
5908
5909         bnx2_netif_stop(bp);
5910
5911         bnx2_init_nic(bp, 1);
5912
5913         atomic_set(&bp->intr_sem, 1);
5914         bnx2_netif_start(bp);
5915 }
5916
5917 static void
5918 bnx2_tx_timeout(struct net_device *dev)
5919 {
5920         struct bnx2 *bp = netdev_priv(dev);
5921
5922         /* This allows the netif to be shutdown gracefully before resetting */
5923         schedule_work(&bp->reset_task);
5924 }
5925
5926 #ifdef BCM_VLAN
5927 /* Called with rtnl_lock */
5928 static void
5929 bnx2_vlan_rx_register(struct net_device *dev, struct vlan_group *vlgrp)
5930 {
5931         struct bnx2 *bp = netdev_priv(dev);
5932
5933         bnx2_netif_stop(bp);
5934
5935         bp->vlgrp = vlgrp;
5936         bnx2_set_rx_mode(dev);
5937         if (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN)
5938                 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_KEEP_VLAN_UPDATE, 0, 1);
5939
5940         bnx2_netif_start(bp);
5941 }
5942 #endif
5943
5944 /* Called with netif_tx_lock.
5945  * bnx2_tx_int() runs without netif_tx_lock unless it needs to call
5946  * netif_wake_queue().
5947  */
5948 static int
5949 bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
5950 {
5951         struct bnx2 *bp = netdev_priv(dev);
5952         dma_addr_t mapping;
5953         struct tx_bd *txbd;
5954         struct sw_bd *tx_buf;
5955         u32 len, vlan_tag_flags, last_frag, mss;
5956         u16 prod, ring_prod;
5957         int i;
5958         struct bnx2_napi *bnapi;
5959         struct bnx2_tx_ring_info *txr;
5960         struct netdev_queue *txq;
5961
5962         /*  Determine which tx ring we will be placed on */
5963         i = skb_get_queue_mapping(skb);
5964         bnapi = &bp->bnx2_napi[i];
5965         txr = &bnapi->tx_ring;
5966         txq = netdev_get_tx_queue(dev, i);
5967
5968         if (unlikely(bnx2_tx_avail(bp, txr) <
5969             (skb_shinfo(skb)->nr_frags + 1))) {
5970                 netif_tx_stop_queue(txq);
5971                 printk(KERN_ERR PFX "%s: BUG! Tx ring full when queue awake!\n",
5972                         dev->name);
5973
5974                 return NETDEV_TX_BUSY;
5975         }
5976         len = skb_headlen(skb);
5977         prod = txr->tx_prod;
5978         ring_prod = TX_RING_IDX(prod);
5979
5980         vlan_tag_flags = 0;
5981         if (skb->ip_summed == CHECKSUM_PARTIAL) {
5982                 vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
5983         }
5984
5985 #ifdef BCM_VLAN
5986         if (bp->vlgrp && vlan_tx_tag_present(skb)) {
5987                 vlan_tag_flags |=
5988                         (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16));
5989         }
5990 #endif
5991         if ((mss = skb_shinfo(skb)->gso_size)) {
5992                 u32 tcp_opt_len, ip_tcp_len;
5993                 struct iphdr *iph;
5994
5995                 vlan_tag_flags |= TX_BD_FLAGS_SW_LSO;
5996
5997                 tcp_opt_len = tcp_optlen(skb);
5998
5999                 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) {
6000                         u32 tcp_off = skb_transport_offset(skb) -
6001                                       sizeof(struct ipv6hdr) - ETH_HLEN;
6002
6003                         vlan_tag_flags |= ((tcp_opt_len >> 2) << 8) |
6004                                           TX_BD_FLAGS_SW_FLAGS;
6005                         if (likely(tcp_off == 0))
6006                                 vlan_tag_flags &= ~TX_BD_FLAGS_TCP6_OFF0_MSK;
6007                         else {
6008                                 tcp_off >>= 3;
6009                                 vlan_tag_flags |= ((tcp_off & 0x3) <<
6010                                                    TX_BD_FLAGS_TCP6_OFF0_SHL) |
6011                                                   ((tcp_off & 0x10) <<
6012                                                    TX_BD_FLAGS_TCP6_OFF4_SHL);
6013                                 mss |= (tcp_off & 0xc) << TX_BD_TCP6_OFF2_SHL;
6014                         }
6015                 } else {
6016                         if (skb_header_cloned(skb) &&
6017                             pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
6018                                 dev_kfree_skb(skb);
6019                                 return NETDEV_TX_OK;
6020                         }
6021
6022                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
6023
6024                         iph = ip_hdr(skb);
6025                         iph->check = 0;
6026                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
6027                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6028                                                                  iph->daddr, 0,
6029                                                                  IPPROTO_TCP,
6030                                                                  0);
6031                         if (tcp_opt_len || (iph->ihl > 5)) {
6032                                 vlan_tag_flags |= ((iph->ihl - 5) +
6033                                                    (tcp_opt_len >> 2)) << 8;
6034                         }
6035                 }
6036         } else
6037                 mss = 0;
6038
6039         mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE);
6040
6041         tx_buf = &txr->tx_buf_ring[ring_prod];
6042         tx_buf->skb = skb;
6043         pci_unmap_addr_set(tx_buf, mapping, mapping);
6044
6045         txbd = &txr->tx_desc_ring[ring_prod];
6046
6047         txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
6048         txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
6049         txbd->tx_bd_mss_nbytes = len | (mss << 16);
6050         txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START;
6051
6052         last_frag = skb_shinfo(skb)->nr_frags;
6053
6054         for (i = 0; i < last_frag; i++) {
6055                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6056
6057                 prod = NEXT_TX_BD(prod);
6058                 ring_prod = TX_RING_IDX(prod);
6059                 txbd = &txr->tx_desc_ring[ring_prod];
6060
6061                 len = frag->size;
6062                 mapping = pci_map_page(bp->pdev, frag->page, frag->page_offset,
6063                         len, PCI_DMA_TODEVICE);
6064                 pci_unmap_addr_set(&txr->tx_buf_ring[ring_prod],
6065                                 mapping, mapping);
6066
6067                 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
6068                 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
6069                 txbd->tx_bd_mss_nbytes = len | (mss << 16);
6070                 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags;
6071
6072         }
6073         txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END;
6074
6075         prod = NEXT_TX_BD(prod);
6076         txr->tx_prod_bseq += skb->len;
6077
6078         REG_WR16(bp, txr->tx_bidx_addr, prod);
6079         REG_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
6080
6081         mmiowb();
6082
6083         txr->tx_prod = prod;
6084         dev->trans_start = jiffies;
6085
6086         if (unlikely(bnx2_tx_avail(bp, txr) <= MAX_SKB_FRAGS)) {
6087                 netif_tx_stop_queue(txq);
6088                 if (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)
6089                         netif_tx_wake_queue(txq);
6090         }
6091
6092         return NETDEV_TX_OK;
6093 }
6094
6095 /* Called with rtnl_lock */
6096 static int
6097 bnx2_close(struct net_device *dev)
6098 {
6099         struct bnx2 *bp = netdev_priv(dev);
6100         u32 reset_code;
6101
6102         cancel_work_sync(&bp->reset_task);
6103
6104         bnx2_disable_int_sync(bp);
6105         bnx2_napi_disable(bp);
6106         del_timer_sync(&bp->timer);
6107         if (bp->flags & BNX2_FLAG_NO_WOL)
6108                 reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
6109         else if (bp->wol)
6110                 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
6111         else
6112                 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
6113         bnx2_reset_chip(bp, reset_code);
6114         bnx2_free_irq(bp);
6115         bnx2_free_skbs(bp);
6116         bnx2_free_mem(bp);
6117         bp->link_up = 0;
6118         netif_carrier_off(bp->dev);
6119         bnx2_set_power_state(bp, PCI_D3hot);
6120         return 0;
6121 }
6122
6123 #define GET_NET_STATS64(ctr)                                    \
6124         (unsigned long) ((unsigned long) (ctr##_hi) << 32) +    \
6125         (unsigned long) (ctr##_lo)
6126
6127 #define GET_NET_STATS32(ctr)            \
6128         (ctr##_lo)
6129
6130 #if (BITS_PER_LONG == 64)
6131 #define GET_NET_STATS   GET_NET_STATS64
6132 #else
6133 #define GET_NET_STATS   GET_NET_STATS32
6134 #endif
6135
6136 static struct net_device_stats *
6137 bnx2_get_stats(struct net_device *dev)
6138 {
6139         struct bnx2 *bp = netdev_priv(dev);
6140         struct statistics_block *stats_blk = bp->stats_blk;
6141         struct net_device_stats *net_stats = &bp->net_stats;
6142
6143         if (bp->stats_blk == NULL) {
6144                 return net_stats;
6145         }
6146         net_stats->rx_packets =
6147                 GET_NET_STATS(stats_blk->stat_IfHCInUcastPkts) +
6148                 GET_NET_STATS(stats_blk->stat_IfHCInMulticastPkts) +
6149                 GET_NET_STATS(stats_blk->stat_IfHCInBroadcastPkts);
6150
6151         net_stats->tx_packets =
6152                 GET_NET_STATS(stats_blk->stat_IfHCOutUcastPkts) +
6153                 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts) +
6154                 GET_NET_STATS(stats_blk->stat_IfHCOutBroadcastPkts);
6155
6156         net_stats->rx_bytes =
6157                 GET_NET_STATS(stats_blk->stat_IfHCInOctets);
6158
6159         net_stats->tx_bytes =
6160                 GET_NET_STATS(stats_blk->stat_IfHCOutOctets);
6161
6162         net_stats->multicast =
6163                 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts);
6164
6165         net_stats->collisions =
6166                 (unsigned long) stats_blk->stat_EtherStatsCollisions;
6167
6168         net_stats->rx_length_errors =
6169                 (unsigned long) (stats_blk->stat_EtherStatsUndersizePkts +
6170                 stats_blk->stat_EtherStatsOverrsizePkts);
6171
6172         net_stats->rx_over_errors =
6173                 (unsigned long) stats_blk->stat_IfInMBUFDiscards;
6174
6175         net_stats->rx_frame_errors =
6176                 (unsigned long) stats_blk->stat_Dot3StatsAlignmentErrors;
6177
6178         net_stats->rx_crc_errors =
6179                 (unsigned long) stats_blk->stat_Dot3StatsFCSErrors;
6180
6181         net_stats->rx_errors = net_stats->rx_length_errors +
6182                 net_stats->rx_over_errors + net_stats->rx_frame_errors +
6183                 net_stats->rx_crc_errors;
6184
6185         net_stats->tx_aborted_errors =
6186                 (unsigned long) (stats_blk->stat_Dot3StatsExcessiveCollisions +
6187                 stats_blk->stat_Dot3StatsLateCollisions);
6188
6189         if ((CHIP_NUM(bp) == CHIP_NUM_5706) ||
6190             (CHIP_ID(bp) == CHIP_ID_5708_A0))
6191                 net_stats->tx_carrier_errors = 0;
6192         else {
6193                 net_stats->tx_carrier_errors =
6194                         (unsigned long)
6195                         stats_blk->stat_Dot3StatsCarrierSenseErrors;
6196         }
6197
6198         net_stats->tx_errors =
6199                 (unsigned long)
6200                 stats_blk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors
6201                 +
6202                 net_stats->tx_aborted_errors +
6203                 net_stats->tx_carrier_errors;
6204
6205         net_stats->rx_missed_errors =
6206                 (unsigned long) (stats_blk->stat_IfInMBUFDiscards +
6207                 stats_blk->stat_FwRxDrop);
6208
6209         return net_stats;
6210 }
6211
6212 /* All ethtool functions called with rtnl_lock */
6213
6214 static int
6215 bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6216 {
6217         struct bnx2 *bp = netdev_priv(dev);
6218         int support_serdes = 0, support_copper = 0;
6219
6220         cmd->supported = SUPPORTED_Autoneg;
6221         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
6222                 support_serdes = 1;
6223                 support_copper = 1;
6224         } else if (bp->phy_port == PORT_FIBRE)
6225                 support_serdes = 1;
6226         else
6227                 support_copper = 1;
6228
6229         if (support_serdes) {
6230                 cmd->supported |= SUPPORTED_1000baseT_Full |
6231                         SUPPORTED_FIBRE;
6232                 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
6233                         cmd->supported |= SUPPORTED_2500baseX_Full;
6234
6235         }
6236         if (support_copper) {
6237                 cmd->supported |= SUPPORTED_10baseT_Half |
6238                         SUPPORTED_10baseT_Full |
6239                         SUPPORTED_100baseT_Half |
6240                         SUPPORTED_100baseT_Full |
6241                         SUPPORTED_1000baseT_Full |
6242                         SUPPORTED_TP;
6243
6244         }
6245
6246         spin_lock_bh(&bp->phy_lock);
6247         cmd->port = bp->phy_port;
6248         cmd->advertising = bp->advertising;
6249
6250         if (bp->autoneg & AUTONEG_SPEED) {
6251                 cmd->autoneg = AUTONEG_ENABLE;
6252         }
6253         else {
6254                 cmd->autoneg = AUTONEG_DISABLE;
6255         }
6256
6257         if (netif_carrier_ok(dev)) {
6258                 cmd->speed = bp->line_speed;
6259                 cmd->duplex = bp->duplex;
6260         }
6261         else {
6262                 cmd->speed = -1;
6263                 cmd->duplex = -1;
6264         }
6265         spin_unlock_bh(&bp->phy_lock);
6266
6267         cmd->transceiver = XCVR_INTERNAL;
6268         cmd->phy_address = bp->phy_addr;
6269
6270         return 0;
6271 }
6272
6273 static int
6274 bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6275 {
6276         struct bnx2 *bp = netdev_priv(dev);
6277         u8 autoneg = bp->autoneg;
6278         u8 req_duplex = bp->req_duplex;
6279         u16 req_line_speed = bp->req_line_speed;
6280         u32 advertising = bp->advertising;
6281         int err = -EINVAL;
6282
6283         spin_lock_bh(&bp->phy_lock);
6284
6285         if (cmd->port != PORT_TP && cmd->port != PORT_FIBRE)
6286                 goto err_out_unlock;
6287
6288         if (cmd->port != bp->phy_port &&
6289             !(bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP))
6290                 goto err_out_unlock;
6291
6292         /* If device is down, we can store the settings only if the user
6293          * is setting the currently active port.
6294          */
6295         if (!netif_running(dev) && cmd->port != bp->phy_port)
6296                 goto err_out_unlock;
6297
6298         if (cmd->autoneg == AUTONEG_ENABLE) {
6299                 autoneg |= AUTONEG_SPEED;
6300
6301                 cmd->advertising &= ETHTOOL_ALL_COPPER_SPEED;
6302
6303                 /* allow advertising 1 speed */
6304                 if ((cmd->advertising == ADVERTISED_10baseT_Half) ||
6305                         (cmd->advertising == ADVERTISED_10baseT_Full) ||
6306                         (cmd->advertising == ADVERTISED_100baseT_Half) ||
6307                         (cmd->advertising == ADVERTISED_100baseT_Full)) {
6308
6309                         if (cmd->port == PORT_FIBRE)
6310                                 goto err_out_unlock;
6311
6312                         advertising = cmd->advertising;
6313
6314                 } else if (cmd->advertising == ADVERTISED_2500baseX_Full) {
6315                         if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ||
6316                             (cmd->port == PORT_TP))
6317                                 goto err_out_unlock;
6318                 } else if (cmd->advertising == ADVERTISED_1000baseT_Full)
6319                         advertising = cmd->advertising;
6320                 else if (cmd->advertising == ADVERTISED_1000baseT_Half)
6321                         goto err_out_unlock;
6322                 else {
6323                         if (cmd->port == PORT_FIBRE)
6324                                 advertising = ETHTOOL_ALL_FIBRE_SPEED;
6325                         else
6326                                 advertising = ETHTOOL_ALL_COPPER_SPEED;
6327                 }
6328                 advertising |= ADVERTISED_Autoneg;
6329         }
6330         else {
6331                 if (cmd->port == PORT_FIBRE) {
6332                         if ((cmd->speed != SPEED_1000 &&
6333                              cmd->speed != SPEED_2500) ||
6334                             (cmd->duplex != DUPLEX_FULL))
6335                                 goto err_out_unlock;
6336
6337                         if (cmd->speed == SPEED_2500 &&
6338                             !(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
6339                                 goto err_out_unlock;
6340                 }
6341                 else if (cmd->speed == SPEED_1000 || cmd->speed == SPEED_2500)
6342                         goto err_out_unlock;
6343
6344                 autoneg &= ~AUTONEG_SPEED;
6345                 req_line_speed = cmd->speed;
6346                 req_duplex = cmd->duplex;
6347                 advertising = 0;
6348         }
6349
6350         bp->autoneg = autoneg;
6351         bp->advertising = advertising;
6352         bp->req_line_speed = req_line_speed;
6353         bp->req_duplex = req_duplex;
6354
6355         err = 0;
6356         /* If device is down, the new settings will be picked up when it is
6357          * brought up.
6358          */
6359         if (netif_running(dev))
6360                 err = bnx2_setup_phy(bp, cmd->port);
6361
6362 err_out_unlock:
6363         spin_unlock_bh(&bp->phy_lock);
6364
6365         return err;
6366 }
6367
6368 static void
6369 bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
6370 {
6371         struct bnx2 *bp = netdev_priv(dev);
6372
6373         strcpy(info->driver, DRV_MODULE_NAME);
6374         strcpy(info->version, DRV_MODULE_VERSION);
6375         strcpy(info->bus_info, pci_name(bp->pdev));
6376         strcpy(info->fw_version, bp->fw_version);
6377 }
6378
6379 #define BNX2_REGDUMP_LEN                (32 * 1024)
6380
6381 static int
6382 bnx2_get_regs_len(struct net_device *dev)
6383 {
6384         return BNX2_REGDUMP_LEN;
6385 }
6386
6387 static void
6388 bnx2_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *_p)
6389 {
6390         u32 *p = _p, i, offset;
6391         u8 *orig_p = _p;
6392         struct bnx2 *bp = netdev_priv(dev);
6393         u32 reg_boundaries[] = { 0x0000, 0x0098, 0x0400, 0x045c,
6394                                  0x0800, 0x0880, 0x0c00, 0x0c10,
6395                                  0x0c30, 0x0d08, 0x1000, 0x101c,
6396                                  0x1040, 0x1048, 0x1080, 0x10a4,
6397                                  0x1400, 0x1490, 0x1498, 0x14f0,
6398                                  0x1500, 0x155c, 0x1580, 0x15dc,
6399                                  0x1600, 0x1658, 0x1680, 0x16d8,
6400                                  0x1800, 0x1820, 0x1840, 0x1854,
6401                                  0x1880, 0x1894, 0x1900, 0x1984,
6402                                  0x1c00, 0x1c0c, 0x1c40, 0x1c54,
6403                                  0x1c80, 0x1c94, 0x1d00, 0x1d84,
6404                                  0x2000, 0x2030, 0x23c0, 0x2400,
6405                                  0x2800, 0x2820, 0x2830, 0x2850,
6406                                  0x2b40, 0x2c10, 0x2fc0, 0x3058,
6407                                  0x3c00, 0x3c94, 0x4000, 0x4010,
6408                                  0x4080, 0x4090, 0x43c0, 0x4458,
6409                                  0x4c00, 0x4c18, 0x4c40, 0x4c54,
6410                                  0x4fc0, 0x5010, 0x53c0, 0x5444,
6411                                  0x5c00, 0x5c18, 0x5c80, 0x5c90,
6412                                  0x5fc0, 0x6000, 0x6400, 0x6428,
6413                                  0x6800, 0x6848, 0x684c, 0x6860,
6414                                  0x6888, 0x6910, 0x8000 };
6415
6416         regs->version = 0;
6417
6418         memset(p, 0, BNX2_REGDUMP_LEN);
6419
6420         if (!netif_running(bp->dev))
6421                 return;
6422
6423         i = 0;
6424         offset = reg_boundaries[0];
6425         p += offset;
6426         while (offset < BNX2_REGDUMP_LEN) {
6427                 *p++ = REG_RD(bp, offset);
6428                 offset += 4;
6429                 if (offset == reg_boundaries[i + 1]) {
6430                         offset = reg_boundaries[i + 2];
6431                         p = (u32 *) (orig_p + offset);
6432                         i += 2;
6433                 }
6434         }
6435 }
6436
6437 static void
6438 bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6439 {
6440         struct bnx2 *bp = netdev_priv(dev);
6441
6442         if (bp->flags & BNX2_FLAG_NO_WOL) {
6443                 wol->supported = 0;
6444                 wol->wolopts = 0;
6445         }
6446         else {
6447                 wol->supported = WAKE_MAGIC;
6448                 if (bp->wol)
6449                         wol->wolopts = WAKE_MAGIC;
6450                 else
6451                         wol->wolopts = 0;
6452         }
6453         memset(&wol->sopass, 0, sizeof(wol->sopass));
6454 }
6455
6456 static int
6457 bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6458 {
6459         struct bnx2 *bp = netdev_priv(dev);
6460
6461         if (wol->wolopts & ~WAKE_MAGIC)
6462                 return -EINVAL;
6463
6464         if (wol->wolopts & WAKE_MAGIC) {
6465                 if (bp->flags & BNX2_FLAG_NO_WOL)
6466                         return -EINVAL;
6467
6468                 bp->wol = 1;
6469         }
6470         else {
6471                 bp->wol = 0;
6472         }
6473         return 0;
6474 }
6475
6476 static int
6477 bnx2_nway_reset(struct net_device *dev)
6478 {
6479         struct bnx2 *bp = netdev_priv(dev);
6480         u32 bmcr;
6481
6482         if (!(bp->autoneg & AUTONEG_SPEED)) {
6483                 return -EINVAL;
6484         }
6485
6486         spin_lock_bh(&bp->phy_lock);
6487
6488         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
6489                 int rc;
6490
6491                 rc = bnx2_setup_remote_phy(bp, bp->phy_port);
6492                 spin_unlock_bh(&bp->phy_lock);
6493                 return rc;
6494         }
6495
6496         /* Force a link down visible on the other side */
6497         if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
6498                 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
6499                 spin_unlock_bh(&bp->phy_lock);
6500
6501                 msleep(20);
6502
6503                 spin_lock_bh(&bp->phy_lock);
6504
6505                 bp->current_interval = SERDES_AN_TIMEOUT;
6506                 bp->serdes_an_pending = 1;
6507                 mod_timer(&bp->timer, jiffies + bp->current_interval);
6508         }
6509
6510         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
6511         bmcr &= ~BMCR_LOOPBACK;
6512         bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);
6513
6514         spin_unlock_bh(&bp->phy_lock);
6515
6516         return 0;
6517 }
6518
6519 static int
6520 bnx2_get_eeprom_len(struct net_device *dev)
6521 {
6522         struct bnx2 *bp = netdev_priv(dev);
6523
6524         if (bp->flash_info == NULL)
6525                 return 0;
6526
6527         return (int) bp->flash_size;
6528 }
6529
6530 static int
6531 bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
6532                 u8 *eebuf)
6533 {
6534         struct bnx2 *bp = netdev_priv(dev);
6535         int rc;
6536
6537         /* parameters already validated in ethtool_get_eeprom */
6538
6539         rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
6540
6541         return rc;
6542 }
6543
6544 static int
6545 bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
6546                 u8 *eebuf)
6547 {
6548         struct bnx2 *bp = netdev_priv(dev);
6549         int rc;
6550
6551         /* parameters already validated in ethtool_set_eeprom */
6552
6553         rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
6554
6555         return rc;
6556 }
6557
6558 static int
6559 bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
6560 {
6561         struct bnx2 *bp = netdev_priv(dev);
6562
6563         memset(coal, 0, sizeof(struct ethtool_coalesce));
6564
6565         coal->rx_coalesce_usecs = bp->rx_ticks;
6566         coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip;
6567         coal->rx_coalesce_usecs_irq = bp->rx_ticks_int;
6568         coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int;
6569
6570         coal->tx_coalesce_usecs = bp->tx_ticks;
6571         coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip;
6572         coal->tx_coalesce_usecs_irq = bp->tx_ticks_int;
6573         coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int;
6574
6575         coal->stats_block_coalesce_usecs = bp->stats_ticks;
6576
6577         return 0;
6578 }
6579
6580 static int
6581 bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
6582 {
6583         struct bnx2 *bp = netdev_priv(dev);
6584
6585         bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
6586         if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;
6587
6588         bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames;
6589         if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff;
6590
6591         bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq;
6592         if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff;
6593
6594         bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq;
6595         if (bp->rx_quick_cons_trip_int > 0xff)
6596                 bp->rx_quick_cons_trip_int = 0xff;
6597
6598         bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
6599         if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff;
6600
6601         bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames;
6602         if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff;
6603
6604         bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq;
6605         if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff;
6606
6607         bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq;
6608         if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int =
6609                 0xff;
6610
6611         bp->stats_ticks = coal->stats_block_coalesce_usecs;
6612         if (CHIP_NUM(bp) == CHIP_NUM_5708) {
6613                 if (bp->stats_ticks != 0 && bp->stats_ticks != USEC_PER_SEC)
6614                         bp->stats_ticks = USEC_PER_SEC;
6615         }
6616         if (bp->stats_ticks > BNX2_HC_STATS_TICKS_HC_STAT_TICKS)
6617                 bp->stats_ticks = BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
6618         bp->stats_ticks &= BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
6619
6620         if (netif_running(bp->dev)) {
6621                 bnx2_netif_stop(bp);
6622                 bnx2_init_nic(bp, 0);
6623                 bnx2_netif_start(bp);
6624         }
6625
6626         return 0;
6627 }
6628
6629 static void
6630 bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
6631 {
6632         struct bnx2 *bp = netdev_priv(dev);
6633
6634         ering->rx_max_pending = MAX_TOTAL_RX_DESC_CNT;
6635         ering->rx_mini_max_pending = 0;
6636         ering->rx_jumbo_max_pending = MAX_TOTAL_RX_PG_DESC_CNT;
6637
6638         ering->rx_pending = bp->rx_ring_size;
6639         ering->rx_mini_pending = 0;
6640         ering->rx_jumbo_pending = bp->rx_pg_ring_size;
6641
6642         ering->tx_max_pending = MAX_TX_DESC_CNT;
6643         ering->tx_pending = bp->tx_ring_size;
6644 }
6645
6646 static int
6647 bnx2_change_ring_size(struct bnx2 *bp, u32 rx, u32 tx)
6648 {
6649         if (netif_running(bp->dev)) {
6650                 bnx2_netif_stop(bp);
6651                 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
6652                 bnx2_free_skbs(bp);
6653                 bnx2_free_mem(bp);
6654         }
6655
6656         bnx2_set_rx_ring_size(bp, rx);
6657         bp->tx_ring_size = tx;
6658
6659         if (netif_running(bp->dev)) {
6660                 int rc;
6661
6662                 rc = bnx2_alloc_mem(bp);
6663                 if (rc)
6664                         return rc;
6665                 bnx2_init_nic(bp, 0);
6666                 bnx2_netif_start(bp);
6667         }
6668         return 0;
6669 }
6670
6671 static int
6672 bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
6673 {
6674         struct bnx2 *bp = netdev_priv(dev);
6675         int rc;
6676
6677         if ((ering->rx_pending > MAX_TOTAL_RX_DESC_CNT) ||
6678                 (ering->tx_pending > MAX_TX_DESC_CNT) ||
6679                 (ering->tx_pending <= MAX_SKB_FRAGS)) {
6680
6681                 return -EINVAL;
6682         }
6683         rc = bnx2_change_ring_size(bp, ering->rx_pending, ering->tx_pending);
6684         return rc;
6685 }
6686
6687 static void
6688 bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
6689 {
6690         struct bnx2 *bp = netdev_priv(dev);
6691
6692         epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);
6693         epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);
6694         epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0);
6695 }
6696
6697 static int
6698 bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
6699 {
6700         struct bnx2 *bp = netdev_priv(dev);
6701
6702         bp->req_flow_ctrl = 0;
6703         if (epause->rx_pause)
6704                 bp->req_flow_ctrl |= FLOW_CTRL_RX;
6705         if (epause->tx_pause)
6706                 bp->req_flow_ctrl |= FLOW_CTRL_TX;
6707
6708         if (epause->autoneg) {
6709                 bp->autoneg |= AUTONEG_FLOW_CTRL;
6710         }
6711         else {
6712                 bp->autoneg &= ~AUTONEG_FLOW_CTRL;
6713         }
6714
6715         spin_lock_bh(&bp->phy_lock);
6716
6717         bnx2_setup_phy(bp, bp->phy_port);
6718
6719         spin_unlock_bh(&bp->phy_lock);
6720
6721         return 0;
6722 }
6723
6724 static u32
6725 bnx2_get_rx_csum(struct net_device *dev)
6726 {
6727         struct bnx2 *bp = netdev_priv(dev);
6728
6729         return bp->rx_csum;
6730 }
6731
6732 static int
6733 bnx2_set_rx_csum(struct net_device *dev, u32 data)
6734 {
6735         struct bnx2 *bp = netdev_priv(dev);
6736
6737         bp->rx_csum = data;
6738         return 0;
6739 }
6740
6741 static int
6742 bnx2_set_tso(struct net_device *dev, u32 data)
6743 {
6744         struct bnx2 *bp = netdev_priv(dev);
6745
6746         if (data) {
6747                 dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
6748                 if (CHIP_NUM(bp) == CHIP_NUM_5709)
6749                         dev->features |= NETIF_F_TSO6;
6750         } else
6751                 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6 |
6752                                    NETIF_F_TSO_ECN);
6753         return 0;
6754 }
6755
6756 #define BNX2_NUM_STATS 46
6757
6758 static struct {
6759         char string[ETH_GSTRING_LEN];
6760 } bnx2_stats_str_arr[BNX2_NUM_STATS] = {
6761         { "rx_bytes" },
6762         { "rx_error_bytes" },
6763         { "tx_bytes" },
6764         { "tx_error_bytes" },
6765         { "rx_ucast_packets" },
6766         { "rx_mcast_packets" },
6767         { "rx_bcast_packets" },
6768         { "tx_ucast_packets" },
6769         { "tx_mcast_packets" },
6770         { "tx_bcast_packets" },
6771         { "tx_mac_errors" },
6772         { "tx_carrier_errors" },
6773         { "rx_crc_errors" },
6774         { "rx_align_errors" },
6775         { "tx_single_collisions" },
6776         { "tx_multi_collisions" },
6777         { "tx_deferred" },
6778         { "tx_excess_collisions" },
6779         { "tx_late_collisions" },
6780         { "tx_total_collisions" },
6781         { "rx_fragments" },
6782         { "rx_jabbers" },
6783         { "rx_undersize_packets" },
6784         { "rx_oversize_packets" },
6785         { "rx_64_byte_packets" },
6786         { "rx_65_to_127_byte_packets" },
6787         { "rx_128_to_255_byte_packets" },
6788         { "rx_256_to_511_byte_packets" },
6789         { "rx_512_to_1023_byte_packets" },
6790         { "rx_1024_to_1522_byte_packets" },
6791         { "rx_1523_to_9022_byte_packets" },
6792         { "tx_64_byte_packets" },
6793         { "tx_65_to_127_byte_packets" },
6794         { "tx_128_to_255_byte_packets" },
6795         { "tx_256_to_511_byte_packets" },
6796         { "tx_512_to_1023_byte_packets" },
6797         { "tx_1024_to_1522_byte_packets" },
6798         { "tx_1523_to_9022_byte_packets" },
6799         { "rx_xon_frames" },
6800         { "rx_xoff_frames" },
6801         { "tx_xon_frames" },
6802         { "tx_xoff_frames" },
6803         { "rx_mac_ctrl_frames" },
6804         { "rx_filtered_packets" },
6805         { "rx_discards" },
6806         { "rx_fw_discards" },
6807 };
6808
6809 #define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4)
6810
6811 static const unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = {
6812     STATS_OFFSET32(stat_IfHCInOctets_hi),
6813     STATS_OFFSET32(stat_IfHCInBadOctets_hi),
6814     STATS_OFFSET32(stat_IfHCOutOctets_hi),
6815     STATS_OFFSET32(stat_IfHCOutBadOctets_hi),
6816     STATS_OFFSET32(stat_IfHCInUcastPkts_hi),
6817     STATS_OFFSET32(stat_IfHCInMulticastPkts_hi),
6818     STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi),
6819     STATS_OFFSET32(stat_IfHCOutUcastPkts_hi),
6820     STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi),
6821     STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi),
6822     STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors),
6823     STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors),
6824     STATS_OFFSET32(stat_Dot3StatsFCSErrors),
6825     STATS_OFFSET32(stat_Dot3StatsAlignmentErrors),
6826     STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames),
6827     STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames),
6828     STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions),
6829     STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions),
6830     STATS_OFFSET32(stat_Dot3StatsLateCollisions),
6831     STATS_OFFSET32(stat_EtherStatsCollisions),
6832     STATS_OFFSET32(stat_EtherStatsFragments),
6833     STATS_OFFSET32(stat_EtherStatsJabbers),
6834     STATS_OFFSET32(stat_EtherStatsUndersizePkts),
6835     STATS_OFFSET32(stat_EtherStatsOverrsizePkts),
6836     STATS_OFFSET32(stat_EtherStatsPktsRx64Octets),
6837     STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets),
6838     STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets),
6839     STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets),
6840     STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets),
6841     STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets),
6842     STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets),
6843     STATS_OFFSET32(stat_EtherStatsPktsTx64Octets),
6844     STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets),
6845     STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets),
6846     STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets),
6847     STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets),
6848     STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets),
6849     STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets),
6850     STATS_OFFSET32(stat_XonPauseFramesReceived),
6851     STATS_OFFSET32(stat_XoffPauseFramesReceived),
6852     STATS_OFFSET32(stat_OutXonSent),
6853     STATS_OFFSET32(stat_OutXoffSent),
6854     STATS_OFFSET32(stat_MacControlFramesReceived),
6855     STATS_OFFSET32(stat_IfInFramesL2FilterDiscards),
6856     STATS_OFFSET32(stat_IfInMBUFDiscards),
6857     STATS_OFFSET32(stat_FwRxDrop),
6858 };
6859
6860 /* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are
6861  * skipped because of errata.
6862  */
6863 static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = {
6864         8,0,8,8,8,8,8,8,8,8,
6865         4,0,4,4,4,4,4,4,4,4,
6866         4,4,4,4,4,4,4,4,4,4,
6867         4,4,4,4,4,4,4,4,4,4,
6868         4,4,4,4,4,4,
6869 };
6870
6871 static u8 bnx2_5708_stats_len_arr[BNX2_NUM_STATS] = {
6872         8,0,8,8,8,8,8,8,8,8,
6873         4,4,4,4,4,4,4,4,4,4,
6874         4,4,4,4,4,4,4,4,4,4,
6875         4,4,4,4,4,4,4,4,4,4,
6876         4,4,4,4,4,4,
6877 };
6878
6879 #define BNX2_NUM_TESTS 6
6880
6881 static struct {
6882         char string[ETH_GSTRING_LEN];
6883 } bnx2_tests_str_arr[BNX2_NUM_TESTS] = {
6884         { "register_test (offline)" },
6885         { "memory_test (offline)" },
6886         { "loopback_test (offline)" },
6887         { "nvram_test (online)" },
6888         { "interrupt_test (online)" },
6889         { "link_test (online)" },
6890 };
6891
6892 static int
6893 bnx2_get_sset_count(struct net_device *dev, int sset)
6894 {
6895         switch (sset) {
6896         case ETH_SS_TEST:
6897                 return BNX2_NUM_TESTS;
6898         case ETH_SS_STATS:
6899                 return BNX2_NUM_STATS;
6900         default:
6901                 return -EOPNOTSUPP;
6902         }
6903 }
6904
6905 static void
6906 bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
6907 {
6908         struct bnx2 *bp = netdev_priv(dev);
6909
6910         memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS);
6911         if (etest->flags & ETH_TEST_FL_OFFLINE) {
6912                 int i;
6913
6914                 bnx2_netif_stop(bp);
6915                 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);
6916                 bnx2_free_skbs(bp);
6917
6918                 if (bnx2_test_registers(bp) != 0) {
6919                         buf[0] = 1;
6920                         etest->flags |= ETH_TEST_FL_FAILED;
6921                 }
6922                 if (bnx2_test_memory(bp) != 0) {
6923                         buf[1] = 1;
6924                         etest->flags |= ETH_TEST_FL_FAILED;
6925                 }
6926                 if ((buf[2] = bnx2_test_loopback(bp)) != 0)
6927                         etest->flags |= ETH_TEST_FL_FAILED;
6928
6929                 if (!netif_running(bp->dev)) {
6930                         bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
6931                 }
6932                 else {
6933                         bnx2_init_nic(bp, 1);
6934                         bnx2_netif_start(bp);
6935                 }
6936
6937                 /* wait for link up */
6938                 for (i = 0; i < 7; i++) {
6939                         if (bp->link_up)
6940                                 break;
6941                         msleep_interruptible(1000);
6942                 }
6943         }
6944
6945         if (bnx2_test_nvram(bp) != 0) {
6946                 buf[3] = 1;
6947                 etest->flags |= ETH_TEST_FL_FAILED;
6948         }
6949         if (bnx2_test_intr(bp) != 0) {
6950                 buf[4] = 1;
6951                 etest->flags |= ETH_TEST_FL_FAILED;
6952         }
6953
6954         if (bnx2_test_link(bp) != 0) {
6955                 buf[5] = 1;
6956                 etest->flags |= ETH_TEST_FL_FAILED;
6957
6958         }
6959 }
6960
6961 static void
6962 bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
6963 {
6964         switch (stringset) {
6965         case ETH_SS_STATS:
6966                 memcpy(buf, bnx2_stats_str_arr,
6967                         sizeof(bnx2_stats_str_arr));
6968                 break;
6969         case ETH_SS_TEST:
6970                 memcpy(buf, bnx2_tests_str_arr,
6971                         sizeof(bnx2_tests_str_arr));
6972                 break;
6973         }
6974 }
6975
6976 static void
6977 bnx2_get_ethtool_stats(struct net_device *dev,
6978                 struct ethtool_stats *stats, u64 *buf)
6979 {
6980         struct bnx2 *bp = netdev_priv(dev);
6981         int i;
6982         u32 *hw_stats = (u32 *) bp->stats_blk;
6983         u8 *stats_len_arr = NULL;
6984
6985         if (hw_stats == NULL) {
6986                 memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS);
6987                 return;
6988         }
6989
6990         if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
6991             (CHIP_ID(bp) == CHIP_ID_5706_A1) ||
6992             (CHIP_ID(bp) == CHIP_ID_5706_A2) ||
6993             (CHIP_ID(bp) == CHIP_ID_5708_A0))
6994                 stats_len_arr = bnx2_5706_stats_len_arr;
6995         else
6996                 stats_len_arr = bnx2_5708_stats_len_arr;
6997
6998         for (i = 0; i < BNX2_NUM_STATS; i++) {
6999                 if (stats_len_arr[i] == 0) {
7000                         /* skip this counter */
7001                         buf[i] = 0;
7002                         continue;
7003                 }
7004                 if (stats_len_arr[i] == 4) {
7005                         /* 4-byte counter */
7006                         buf[i] = (u64)
7007                                 *(hw_stats + bnx2_stats_offset_arr[i]);
7008                         continue;
7009                 }
7010                 /* 8-byte counter */
7011                 buf[i] = (((u64) *(hw_stats +
7012                                         bnx2_stats_offset_arr[i])) << 32) +
7013                                 *(hw_stats + bnx2_stats_offset_arr[i] + 1);
7014         }
7015 }
7016
7017 static int
7018 bnx2_phys_id(struct net_device *dev, u32 data)
7019 {
7020         struct bnx2 *bp = netdev_priv(dev);
7021         int i;
7022         u32 save;
7023
7024         if (data == 0)
7025                 data = 2;
7026
7027         save = REG_RD(bp, BNX2_MISC_CFG);
7028         REG_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);
7029
7030         for (i = 0; i < (data * 2); i++) {
7031                 if ((i % 2) == 0) {
7032                         REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);
7033                 }
7034                 else {
7035                         REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |
7036                                 BNX2_EMAC_LED_1000MB_OVERRIDE |
7037                                 BNX2_EMAC_LED_100MB_OVERRIDE |
7038                                 BNX2_EMAC_LED_10MB_OVERRIDE |
7039                                 BNX2_EMAC_LED_TRAFFIC_OVERRIDE |
7040                                 BNX2_EMAC_LED_TRAFFIC);
7041                 }
7042                 msleep_interruptible(500);
7043                 if (signal_pending(current))
7044                         break;
7045         }
7046         REG_WR(bp, BNX2_EMAC_LED, 0);
7047         REG_WR(bp, BNX2_MISC_CFG, save);
7048         return 0;
7049 }
7050
7051 static int
7052 bnx2_set_tx_csum(struct net_device *dev, u32 data)
7053 {
7054         struct bnx2 *bp = netdev_priv(dev);
7055
7056         if (CHIP_NUM(bp) == CHIP_NUM_5709)
7057                 return (ethtool_op_set_tx_ipv6_csum(dev, data));
7058         else
7059                 return (ethtool_op_set_tx_csum(dev, data));
7060 }
7061
7062 static const struct ethtool_ops bnx2_ethtool_ops = {
7063         .get_settings           = bnx2_get_settings,
7064         .set_settings           = bnx2_set_settings,
7065         .get_drvinfo            = bnx2_get_drvinfo,
7066         .get_regs_len           = bnx2_get_regs_len,
7067         .get_regs               = bnx2_get_regs,
7068         .get_wol                = bnx2_get_wol,
7069         .set_wol                = bnx2_set_wol,
7070         .nway_reset             = bnx2_nway_reset,
7071         .get_link               = ethtool_op_get_link,
7072         .get_eeprom_len         = bnx2_get_eeprom_len,
7073         .get_eeprom             = bnx2_get_eeprom,
7074         .set_eeprom             = bnx2_set_eeprom,
7075         .get_coalesce           = bnx2_get_coalesce,
7076         .set_coalesce           = bnx2_set_coalesce,
7077         .get_ringparam          = bnx2_get_ringparam,
7078         .set_ringparam          = bnx2_set_ringparam,
7079         .get_pauseparam         = bnx2_get_pauseparam,
7080         .set_pauseparam         = bnx2_set_pauseparam,
7081         .get_rx_csum            = bnx2_get_rx_csum,
7082         .set_rx_csum            = bnx2_set_rx_csum,
7083         .set_tx_csum            = bnx2_set_tx_csum,
7084         .set_sg                 = ethtool_op_set_sg,
7085         .set_tso                = bnx2_set_tso,
7086         .self_test              = bnx2_self_test,
7087         .get_strings            = bnx2_get_strings,
7088         .phys_id                = bnx2_phys_id,
7089         .get_ethtool_stats      = bnx2_get_ethtool_stats,
7090         .get_sset_count         = bnx2_get_sset_count,
7091 };
7092
7093 /* Called with rtnl_lock */
7094 static int
7095 bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
7096 {
7097         struct mii_ioctl_data *data = if_mii(ifr);
7098         struct bnx2 *bp = netdev_priv(dev);
7099         int err;
7100
7101         switch(cmd) {
7102         case SIOCGMIIPHY:
7103                 data->phy_id = bp->phy_addr;
7104
7105                 /* fallthru */
7106         case SIOCGMIIREG: {
7107                 u32 mii_regval;
7108
7109                 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
7110                         return -EOPNOTSUPP;
7111
7112                 if (!netif_running(dev))
7113                         return -EAGAIN;
7114
7115                 spin_lock_bh(&bp->phy_lock);
7116                 err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval);
7117                 spin_unlock_bh(&bp->phy_lock);
7118
7119                 data->val_out = mii_regval;
7120
7121                 return err;
7122         }
7123
7124         case SIOCSMIIREG:
7125                 if (!capable(CAP_NET_ADMIN))
7126                         return -EPERM;
7127
7128                 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
7129                         return -EOPNOTSUPP;
7130
7131                 if (!netif_running(dev))
7132                         return -EAGAIN;
7133
7134                 spin_lock_bh(&bp->phy_lock);
7135                 err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);
7136                 spin_unlock_bh(&bp->phy_lock);
7137
7138                 return err;
7139
7140         default:
7141                 /* do nothing */
7142                 break;
7143         }
7144         return -EOPNOTSUPP;
7145 }
7146
7147 /* Called with rtnl_lock */
7148 static int
7149 bnx2_change_mac_addr(struct net_device *dev, void *p)
7150 {
7151         struct sockaddr *addr = p;
7152         struct bnx2 *bp = netdev_priv(dev);
7153
7154         if (!is_valid_ether_addr(addr->sa_data))
7155                 return -EINVAL;
7156
7157         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7158         if (netif_running(dev))
7159                 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
7160
7161         return 0;
7162 }
7163
7164 /* Called with rtnl_lock */
7165 static int
7166 bnx2_change_mtu(struct net_device *dev, int new_mtu)
7167 {
7168         struct bnx2 *bp = netdev_priv(dev);
7169
7170         if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
7171                 ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE))
7172                 return -EINVAL;
7173
7174         dev->mtu = new_mtu;
7175         return (bnx2_change_ring_size(bp, bp->rx_ring_size, bp->tx_ring_size));
7176 }
7177
7178 #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
7179 static void
7180 poll_bnx2(struct net_device *dev)
7181 {
7182         struct bnx2 *bp = netdev_priv(dev);
7183
7184         disable_irq(bp->pdev->irq);
7185         bnx2_interrupt(bp->pdev->irq, dev);
7186         enable_irq(bp->pdev->irq);
7187 }
7188 #endif
7189
7190 static void __devinit
7191 bnx2_get_5709_media(struct bnx2 *bp)
7192 {
7193         u32 val = REG_RD(bp, BNX2_MISC_DUAL_MEDIA_CTRL);
7194         u32 bond_id = val & BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID;
7195         u32 strap;
7196
7197         if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C)
7198                 return;
7199         else if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
7200                 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7201                 return;
7202         }
7203
7204         if (val & BNX2_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE)
7205                 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
7206         else
7207                 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
7208
7209         if (PCI_FUNC(bp->pdev->devfn) == 0) {
7210                 switch (strap) {
7211                 case 0x4:
7212                 case 0x5:
7213                 case 0x6:
7214                         bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7215                         return;
7216                 }
7217         } else {
7218                 switch (strap) {
7219                 case 0x1:
7220                 case 0x2:
7221                 case 0x4:
7222                         bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7223                         return;
7224                 }
7225         }
7226 }
7227
7228 static void __devinit
7229 bnx2_get_pci_speed(struct bnx2 *bp)
7230 {
7231         u32 reg;
7232
7233         reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);
7234         if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
7235                 u32 clkreg;
7236
7237                 bp->flags |= BNX2_FLAG_PCIX;
7238
7239                 clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
7240
7241                 clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
7242                 switch (clkreg) {
7243                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
7244                         bp->bus_speed_mhz = 133;
7245                         break;
7246
7247                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
7248                         bp->bus_speed_mhz = 100;
7249                         break;
7250
7251                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
7252                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
7253                         bp->bus_speed_mhz = 66;
7254                         break;
7255
7256                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
7257                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
7258                         bp->bus_speed_mhz = 50;
7259                         break;
7260
7261                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
7262                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
7263                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
7264                         bp->bus_speed_mhz = 33;
7265                         break;
7266                 }
7267         }
7268         else {
7269                 if (reg & BNX2_PCICFG_MISC_STATUS_M66EN)
7270                         bp->bus_speed_mhz = 66;
7271                 else
7272                         bp->bus_speed_mhz = 33;
7273         }
7274
7275         if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET)
7276                 bp->flags |= BNX2_FLAG_PCI_32BIT;
7277
7278 }
7279
7280 static int __devinit
7281 bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
7282 {
7283         struct bnx2 *bp;
7284         unsigned long mem_len;
7285         int rc, i, j;
7286         u32 reg;
7287         u64 dma_mask, persist_dma_mask;
7288
7289         SET_NETDEV_DEV(dev, &pdev->dev);
7290         bp = netdev_priv(dev);
7291
7292         bp->flags = 0;
7293         bp->phy_flags = 0;
7294
7295         /* enable device (incl. PCI PM wakeup), and bus-mastering */
7296         rc = pci_enable_device(pdev);
7297         if (rc) {
7298                 dev_err(&pdev->dev, "Cannot enable PCI device, aborting.\n");
7299                 goto err_out;
7300         }
7301
7302         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
7303                 dev_err(&pdev->dev,
7304                         "Cannot find PCI device base address, aborting.\n");
7305                 rc = -ENODEV;
7306                 goto err_out_disable;
7307         }
7308
7309         rc = pci_request_regions(pdev, DRV_MODULE_NAME);
7310         if (rc) {
7311                 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting.\n");
7312                 goto err_out_disable;
7313         }
7314
7315         pci_set_master(pdev);
7316         pci_save_state(pdev);
7317
7318         bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
7319         if (bp->pm_cap == 0) {
7320                 dev_err(&pdev->dev,
7321                         "Cannot find power management capability, aborting.\n");
7322                 rc = -EIO;
7323                 goto err_out_release;
7324         }
7325
7326         bp->dev = dev;
7327         bp->pdev = pdev;
7328
7329         spin_lock_init(&bp->phy_lock);
7330         spin_lock_init(&bp->indirect_lock);
7331         INIT_WORK(&bp->reset_task, bnx2_reset_task);
7332
7333         dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0);
7334         mem_len = MB_GET_CID_ADDR(TX_TSS_CID + TX_MAX_TSS_RINGS);
7335         dev->mem_end = dev->mem_start + mem_len;
7336         dev->irq = pdev->irq;
7337
7338         bp->regview = ioremap_nocache(dev->base_addr, mem_len);
7339
7340         if (!bp->regview) {
7341                 dev_err(&pdev->dev, "Cannot map register space, aborting.\n");
7342                 rc = -ENOMEM;
7343                 goto err_out_release;
7344         }
7345
7346         /* Configure byte swap and enable write to the reg_window registers.
7347          * Rely on CPU to do target byte swapping on big endian systems
7348          * The chip's target access swapping will not swap all accesses
7349          */
7350         pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG,
7351                                BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
7352                                BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
7353
7354         bnx2_set_power_state(bp, PCI_D0);
7355
7356         bp->chip_id = REG_RD(bp, BNX2_MISC_ID);
7357
7358         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
7359                 if (pci_find_capability(pdev, PCI_CAP_ID_EXP) == 0) {
7360                         dev_err(&pdev->dev,
7361                                 "Cannot find PCIE capability, aborting.\n");
7362                         rc = -EIO;
7363                         goto err_out_unmap;
7364                 }
7365                 bp->flags |= BNX2_FLAG_PCIE;
7366                 if (CHIP_REV(bp) == CHIP_REV_Ax)
7367                         bp->flags |= BNX2_FLAG_JUMBO_BROKEN;
7368         } else {
7369                 bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
7370                 if (bp->pcix_cap == 0) {
7371                         dev_err(&pdev->dev,
7372                                 "Cannot find PCIX capability, aborting.\n");
7373                         rc = -EIO;
7374                         goto err_out_unmap;
7375                 }
7376         }
7377
7378         if (CHIP_NUM(bp) == CHIP_NUM_5709 && CHIP_REV(bp) != CHIP_REV_Ax) {
7379                 if (pci_find_capability(pdev, PCI_CAP_ID_MSIX))
7380                         bp->flags |= BNX2_FLAG_MSIX_CAP;
7381         }
7382
7383         if (CHIP_ID(bp) != CHIP_ID_5706_A0 && CHIP_ID(bp) != CHIP_ID_5706_A1) {
7384                 if (pci_find_capability(pdev, PCI_CAP_ID_MSI))
7385                         bp->flags |= BNX2_FLAG_MSI_CAP;
7386         }
7387
7388         /* 5708 cannot support DMA addresses > 40-bit.  */
7389         if (CHIP_NUM(bp) == CHIP_NUM_5708)
7390                 persist_dma_mask = dma_mask = DMA_40BIT_MASK;
7391         else
7392                 persist_dma_mask = dma_mask = DMA_64BIT_MASK;
7393
7394         /* Configure DMA attributes. */
7395         if (pci_set_dma_mask(pdev, dma_mask) == 0) {
7396                 dev->features |= NETIF_F_HIGHDMA;
7397                 rc = pci_set_consistent_dma_mask(pdev, persist_dma_mask);
7398                 if (rc) {
7399                         dev_err(&pdev->dev,
7400                                 "pci_set_consistent_dma_mask failed, aborting.\n");
7401                         goto err_out_unmap;
7402                 }
7403         } else if ((rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK)) != 0) {
7404                 dev_err(&pdev->dev, "System does not support DMA, aborting.\n");
7405                 goto err_out_unmap;
7406         }
7407
7408         if (!(bp->flags & BNX2_FLAG_PCIE))
7409                 bnx2_get_pci_speed(bp);
7410
7411         /* 5706A0 may falsely detect SERR and PERR. */
7412         if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
7413                 reg = REG_RD(bp, PCI_COMMAND);
7414                 reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
7415                 REG_WR(bp, PCI_COMMAND, reg);
7416         }
7417         else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) &&
7418                 !(bp->flags & BNX2_FLAG_PCIX)) {
7419
7420                 dev_err(&pdev->dev,
7421                         "5706 A1 can only be used in a PCIX bus, aborting.\n");
7422                 goto err_out_unmap;
7423         }
7424
7425         bnx2_init_nvram(bp);
7426
7427         reg = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_SIGNATURE);
7428
7429         if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) ==
7430             BNX2_SHM_HDR_SIGNATURE_SIG) {
7431                 u32 off = PCI_FUNC(pdev->devfn) << 2;
7432
7433                 bp->shmem_base = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_ADDR_0 + off);
7434         } else
7435                 bp->shmem_base = HOST_VIEW_SHMEM_BASE;
7436
7437         /* Get the permanent MAC address.  First we need to make sure the
7438          * firmware is actually running.
7439          */
7440         reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE);
7441
7442         if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
7443             BNX2_DEV_INFO_SIGNATURE_MAGIC) {
7444                 dev_err(&pdev->dev, "Firmware not running, aborting.\n");
7445                 rc = -ENODEV;
7446                 goto err_out_unmap;
7447         }
7448
7449         reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_BC_REV);
7450         for (i = 0, j = 0; i < 3; i++) {
7451                 u8 num, k, skip0;
7452
7453                 num = (u8) (reg >> (24 - (i * 8)));
7454                 for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
7455                         if (num >= k || !skip0 || k == 1) {
7456                                 bp->fw_version[j++] = (num / k) + '0';
7457                                 skip0 = 0;
7458                         }
7459                 }
7460                 if (i != 2)
7461                         bp->fw_version[j++] = '.';
7462         }
7463         reg = bnx2_shmem_rd(bp, BNX2_PORT_FEATURE);
7464         if (reg & BNX2_PORT_FEATURE_WOL_ENABLED)
7465                 bp->wol = 1;
7466
7467         if (reg & BNX2_PORT_FEATURE_ASF_ENABLED) {
7468                 bp->flags |= BNX2_FLAG_ASF_ENABLE;
7469
7470                 for (i = 0; i < 30; i++) {
7471                         reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
7472                         if (reg & BNX2_CONDITION_MFW_RUN_MASK)
7473                                 break;
7474                         msleep(10);
7475                 }
7476         }
7477         reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
7478         reg &= BNX2_CONDITION_MFW_RUN_MASK;
7479         if (reg != BNX2_CONDITION_MFW_RUN_UNKNOWN &&
7480             reg != BNX2_CONDITION_MFW_RUN_NONE) {
7481                 u32 addr = bnx2_shmem_rd(bp, BNX2_MFW_VER_PTR);
7482
7483                 bp->fw_version[j++] = ' ';
7484                 for (i = 0; i < 3; i++) {
7485                         reg = bnx2_reg_rd_ind(bp, addr + i * 4);
7486                         reg = swab32(reg);
7487                         memcpy(&bp->fw_version[j], &reg, 4);
7488                         j += 4;
7489                 }
7490         }
7491
7492         reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_UPPER);
7493         bp->mac_addr[0] = (u8) (reg >> 8);
7494         bp->mac_addr[1] = (u8) reg;
7495
7496         reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_LOWER);
7497         bp->mac_addr[2] = (u8) (reg >> 24);
7498         bp->mac_addr[3] = (u8) (reg >> 16);
7499         bp->mac_addr[4] = (u8) (reg >> 8);
7500         bp->mac_addr[5] = (u8) reg;
7501
7502         bp->tx_ring_size = MAX_TX_DESC_CNT;
7503         bnx2_set_rx_ring_size(bp, 255);
7504
7505         bp->rx_csum = 1;
7506
7507         bp->tx_quick_cons_trip_int = 20;
7508         bp->tx_quick_cons_trip = 20;
7509         bp->tx_ticks_int = 80;
7510         bp->tx_ticks = 80;
7511
7512         bp->rx_quick_cons_trip_int = 6;
7513         bp->rx_quick_cons_trip = 6;
7514         bp->rx_ticks_int = 18;
7515         bp->rx_ticks = 18;
7516
7517         bp->stats_ticks = USEC_PER_SEC & BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
7518
7519         bp->timer_interval =  HZ;
7520         bp->current_interval =  HZ;
7521
7522         bp->phy_addr = 1;
7523
7524         /* Disable WOL support if we are running on a SERDES chip. */
7525         if (CHIP_NUM(bp) == CHIP_NUM_5709)
7526                 bnx2_get_5709_media(bp);
7527         else if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT)
7528                 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7529
7530         bp->phy_port = PORT_TP;
7531         if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
7532                 bp->phy_port = PORT_FIBRE;
7533                 reg = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
7534                 if (!(reg & BNX2_SHARED_HW_CFG_GIG_LINK_ON_VAUX)) {
7535                         bp->flags |= BNX2_FLAG_NO_WOL;
7536                         bp->wol = 0;
7537                 }
7538                 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
7539                         /* Don't do parallel detect on this board because of
7540                          * some board problems.  The link will not go down
7541                          * if we do parallel detect.
7542                          */
7543                         if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
7544                             pdev->subsystem_device == 0x310c)
7545                                 bp->phy_flags |= BNX2_PHY_FLAG_NO_PARALLEL;
7546                 } else {
7547                         bp->phy_addr = 2;
7548                         if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
7549                                 bp->phy_flags |= BNX2_PHY_FLAG_2_5G_CAPABLE;
7550                 }
7551         } else if (CHIP_NUM(bp) == CHIP_NUM_5706 ||
7552                    CHIP_NUM(bp) == CHIP_NUM_5708)
7553                 bp->phy_flags |= BNX2_PHY_FLAG_CRC_FIX;
7554         else if (CHIP_NUM(bp) == CHIP_NUM_5709 &&
7555                  (CHIP_REV(bp) == CHIP_REV_Ax ||
7556                   CHIP_REV(bp) == CHIP_REV_Bx))
7557                 bp->phy_flags |= BNX2_PHY_FLAG_DIS_EARLY_DAC;
7558
7559         bnx2_init_fw_cap(bp);
7560
7561         if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
7562             (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
7563             (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
7564                 bp->flags |= BNX2_FLAG_NO_WOL;
7565                 bp->wol = 0;
7566         }
7567
7568         if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
7569                 bp->tx_quick_cons_trip_int =
7570                         bp->tx_quick_cons_trip;
7571                 bp->tx_ticks_int = bp->tx_ticks;
7572                 bp->rx_quick_cons_trip_int =
7573                         bp->rx_quick_cons_trip;
7574                 bp->rx_ticks_int = bp->rx_ticks;
7575                 bp->comp_prod_trip_int = bp->comp_prod_trip;
7576                 bp->com_ticks_int = bp->com_ticks;
7577                 bp->cmd_ticks_int = bp->cmd_ticks;
7578         }
7579
7580         /* Disable MSI on 5706 if AMD 8132 bridge is found.
7581          *
7582          * MSI is defined to be 32-bit write.  The 5706 does 64-bit MSI writes
7583          * with byte enables disabled on the unused 32-bit word.  This is legal
7584          * but causes problems on the AMD 8132 which will eventually stop
7585          * responding after a while.
7586          *
7587          * AMD believes this incompatibility is unique to the 5706, and
7588          * prefers to locally disable MSI rather than globally disabling it.
7589          */
7590         if (CHIP_NUM(bp) == CHIP_NUM_5706 && disable_msi == 0) {
7591                 struct pci_dev *amd_8132 = NULL;
7592
7593                 while ((amd_8132 = pci_get_device(PCI_VENDOR_ID_AMD,
7594                                                   PCI_DEVICE_ID_AMD_8132_BRIDGE,
7595                                                   amd_8132))) {
7596
7597                         if (amd_8132->revision >= 0x10 &&
7598                             amd_8132->revision <= 0x13) {
7599                                 disable_msi = 1;
7600                                 pci_dev_put(amd_8132);
7601                                 break;
7602                         }
7603                 }
7604         }
7605
7606         bnx2_set_default_link(bp);
7607         bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
7608
7609         init_timer(&bp->timer);
7610         bp->timer.expires = RUN_AT(bp->timer_interval);
7611         bp->timer.data = (unsigned long) bp;
7612         bp->timer.function = bnx2_timer;
7613
7614         return 0;
7615
7616 err_out_unmap:
7617         if (bp->regview) {
7618                 iounmap(bp->regview);
7619                 bp->regview = NULL;
7620         }
7621
7622 err_out_release:
7623         pci_release_regions(pdev);
7624
7625 err_out_disable:
7626         pci_disable_device(pdev);
7627         pci_set_drvdata(pdev, NULL);
7628
7629 err_out:
7630         return rc;
7631 }
7632
7633 static char * __devinit
7634 bnx2_bus_string(struct bnx2 *bp, char *str)
7635 {
7636         char *s = str;
7637
7638         if (bp->flags & BNX2_FLAG_PCIE) {
7639                 s += sprintf(s, "PCI Express");
7640         } else {
7641                 s += sprintf(s, "PCI");
7642                 if (bp->flags & BNX2_FLAG_PCIX)
7643                         s += sprintf(s, "-X");
7644                 if (bp->flags & BNX2_FLAG_PCI_32BIT)
7645                         s += sprintf(s, " 32-bit");
7646                 else
7647                         s += sprintf(s, " 64-bit");
7648                 s += sprintf(s, " %dMHz", bp->bus_speed_mhz);
7649         }
7650         return str;
7651 }
7652
7653 static void __devinit
7654 bnx2_init_napi(struct bnx2 *bp)
7655 {
7656         int i;
7657
7658         for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
7659                 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
7660                 int (*poll)(struct napi_struct *, int);
7661
7662                 if (i == 0)
7663                         poll = bnx2_poll;
7664                 else
7665                         poll = bnx2_poll_msix;
7666
7667                 netif_napi_add(bp->dev, &bp->bnx2_napi[i].napi, poll, 64);
7668                 bnapi->bp = bp;
7669         }
7670 }
7671
7672 static int __devinit
7673 bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
7674 {
7675         static int version_printed = 0;
7676         struct net_device *dev = NULL;
7677         struct bnx2 *bp;
7678         int rc;
7679         char str[40];
7680         DECLARE_MAC_BUF(mac);
7681
7682         if (version_printed++ == 0)
7683                 printk(KERN_INFO "%s", version);
7684
7685         /* dev zeroed in init_etherdev */
7686         dev = alloc_etherdev_mq(sizeof(*bp), TX_MAX_RINGS);
7687
7688         if (!dev)
7689                 return -ENOMEM;
7690
7691         rc = bnx2_init_board(pdev, dev);
7692         if (rc < 0) {
7693                 free_netdev(dev);
7694                 return rc;
7695         }
7696
7697         dev->open = bnx2_open;
7698         dev->hard_start_xmit = bnx2_start_xmit;
7699         dev->stop = bnx2_close;
7700         dev->get_stats = bnx2_get_stats;
7701         dev->set_rx_mode = bnx2_set_rx_mode;
7702         dev->do_ioctl = bnx2_ioctl;
7703         dev->set_mac_address = bnx2_change_mac_addr;
7704         dev->change_mtu = bnx2_change_mtu;
7705         dev->tx_timeout = bnx2_tx_timeout;
7706         dev->watchdog_timeo = TX_TIMEOUT;
7707 #ifdef BCM_VLAN
7708         dev->vlan_rx_register = bnx2_vlan_rx_register;
7709 #endif
7710         dev->ethtool_ops = &bnx2_ethtool_ops;
7711
7712         bp = netdev_priv(dev);
7713         bnx2_init_napi(bp);
7714
7715 #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
7716         dev->poll_controller = poll_bnx2;
7717 #endif
7718
7719         pci_set_drvdata(pdev, dev);
7720
7721         memcpy(dev->dev_addr, bp->mac_addr, 6);
7722         memcpy(dev->perm_addr, bp->mac_addr, 6);
7723         bp->name = board_info[ent->driver_data].name;
7724
7725         dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
7726         if (CHIP_NUM(bp) == CHIP_NUM_5709)
7727                 dev->features |= NETIF_F_IPV6_CSUM;
7728
7729 #ifdef BCM_VLAN
7730         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
7731 #endif
7732         dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
7733         if (CHIP_NUM(bp) == CHIP_NUM_5709)
7734                 dev->features |= NETIF_F_TSO6;
7735
7736         if ((rc = register_netdev(dev))) {
7737                 dev_err(&pdev->dev, "Cannot register net device\n");
7738                 if (bp->regview)
7739                         iounmap(bp->regview);
7740                 pci_release_regions(pdev);
7741                 pci_disable_device(pdev);
7742                 pci_set_drvdata(pdev, NULL);
7743                 free_netdev(dev);
7744                 return rc;
7745         }
7746
7747         printk(KERN_INFO "%s: %s (%c%d) %s found at mem %lx, "
7748                 "IRQ %d, node addr %s\n",
7749                 dev->name,
7750                 bp->name,
7751                 ((CHIP_ID(bp) & 0xf000) >> 12) + 'A',
7752                 ((CHIP_ID(bp) & 0x0ff0) >> 4),
7753                 bnx2_bus_string(bp, str),
7754                 dev->base_addr,
7755                 bp->pdev->irq, print_mac(mac, dev->dev_addr));
7756
7757         return 0;
7758 }
7759
7760 static void __devexit
7761 bnx2_remove_one(struct pci_dev *pdev)
7762 {
7763         struct net_device *dev = pci_get_drvdata(pdev);
7764         struct bnx2 *bp = netdev_priv(dev);
7765
7766         flush_scheduled_work();
7767
7768         unregister_netdev(dev);
7769
7770         if (bp->regview)
7771                 iounmap(bp->regview);
7772
7773         free_netdev(dev);
7774         pci_release_regions(pdev);
7775         pci_disable_device(pdev);
7776         pci_set_drvdata(pdev, NULL);
7777 }
7778
7779 static int
7780 bnx2_suspend(struct pci_dev *pdev, pm_message_t state)
7781 {
7782         struct net_device *dev = pci_get_drvdata(pdev);
7783         struct bnx2 *bp = netdev_priv(dev);
7784         u32 reset_code;
7785
7786         /* PCI register 4 needs to be saved whether netif_running() or not.
7787          * MSI address and data need to be saved if using MSI and
7788          * netif_running().
7789          */
7790         pci_save_state(pdev);
7791         if (!netif_running(dev))
7792                 return 0;
7793
7794         flush_scheduled_work();
7795         bnx2_netif_stop(bp);
7796         netif_device_detach(dev);
7797         del_timer_sync(&bp->timer);
7798         if (bp->flags & BNX2_FLAG_NO_WOL)
7799                 reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
7800         else if (bp->wol)
7801                 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
7802         else
7803                 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
7804         bnx2_reset_chip(bp, reset_code);
7805         bnx2_free_skbs(bp);
7806         bnx2_set_power_state(bp, pci_choose_state(pdev, state));
7807         return 0;
7808 }
7809
7810 static int
7811 bnx2_resume(struct pci_dev *pdev)
7812 {
7813         struct net_device *dev = pci_get_drvdata(pdev);
7814         struct bnx2 *bp = netdev_priv(dev);
7815
7816         pci_restore_state(pdev);
7817         if (!netif_running(dev))
7818                 return 0;
7819
7820         bnx2_set_power_state(bp, PCI_D0);
7821         netif_device_attach(dev);
7822         bnx2_init_nic(bp, 1);
7823         bnx2_netif_start(bp);
7824         return 0;
7825 }
7826
7827 /**
7828  * bnx2_io_error_detected - called when PCI error is detected
7829  * @pdev: Pointer to PCI device
7830  * @state: The current pci connection state
7831  *
7832  * This function is called after a PCI bus error affecting
7833  * this device has been detected.
7834  */
7835 static pci_ers_result_t bnx2_io_error_detected(struct pci_dev *pdev,
7836                                                pci_channel_state_t state)
7837 {
7838         struct net_device *dev = pci_get_drvdata(pdev);
7839         struct bnx2 *bp = netdev_priv(dev);
7840
7841         rtnl_lock();
7842         netif_device_detach(dev);
7843
7844         if (netif_running(dev)) {
7845                 bnx2_netif_stop(bp);
7846                 del_timer_sync(&bp->timer);
7847                 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
7848         }
7849
7850         pci_disable_device(pdev);
7851         rtnl_unlock();
7852
7853         /* Request a slot slot reset. */
7854         return PCI_ERS_RESULT_NEED_RESET;
7855 }
7856
7857 /**
7858  * bnx2_io_slot_reset - called after the pci bus has been reset.
7859  * @pdev: Pointer to PCI device
7860  *
7861  * Restart the card from scratch, as if from a cold-boot.
7862  */
7863 static pci_ers_result_t bnx2_io_slot_reset(struct pci_dev *pdev)
7864 {
7865         struct net_device *dev = pci_get_drvdata(pdev);
7866         struct bnx2 *bp = netdev_priv(dev);
7867
7868         rtnl_lock();
7869         if (pci_enable_device(pdev)) {
7870                 dev_err(&pdev->dev,
7871                         "Cannot re-enable PCI device after reset.\n");
7872                 rtnl_unlock();
7873                 return PCI_ERS_RESULT_DISCONNECT;
7874         }
7875         pci_set_master(pdev);
7876         pci_restore_state(pdev);
7877
7878         if (netif_running(dev)) {
7879                 bnx2_set_power_state(bp, PCI_D0);
7880                 bnx2_init_nic(bp, 1);
7881         }
7882
7883         rtnl_unlock();
7884         return PCI_ERS_RESULT_RECOVERED;
7885 }
7886
7887 /**
7888  * bnx2_io_resume - called when traffic can start flowing again.
7889  * @pdev: Pointer to PCI device
7890  *
7891  * This callback is called when the error recovery driver tells us that
7892  * its OK to resume normal operation.
7893  */
7894 static void bnx2_io_resume(struct pci_dev *pdev)
7895 {
7896         struct net_device *dev = pci_get_drvdata(pdev);
7897         struct bnx2 *bp = netdev_priv(dev);
7898
7899         rtnl_lock();
7900         if (netif_running(dev))
7901                 bnx2_netif_start(bp);
7902
7903         netif_device_attach(dev);
7904         rtnl_unlock();
7905 }
7906
7907 static struct pci_error_handlers bnx2_err_handler = {
7908         .error_detected = bnx2_io_error_detected,
7909         .slot_reset     = bnx2_io_slot_reset,
7910         .resume         = bnx2_io_resume,
7911 };
7912
7913 static struct pci_driver bnx2_pci_driver = {
7914         .name           = DRV_MODULE_NAME,
7915         .id_table       = bnx2_pci_tbl,
7916         .probe          = bnx2_init_one,
7917         .remove         = __devexit_p(bnx2_remove_one),
7918         .suspend        = bnx2_suspend,
7919         .resume         = bnx2_resume,
7920         .err_handler    = &bnx2_err_handler,
7921 };
7922
7923 static int __init bnx2_init(void)
7924 {
7925         return pci_register_driver(&bnx2_pci_driver);
7926 }
7927
7928 static void __exit bnx2_cleanup(void)
7929 {
7930         pci_unregister_driver(&bnx2_pci_driver);
7931 }
7932
7933 module_init(bnx2_init);
7934 module_exit(bnx2_cleanup);
7935
7936
7937