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   1 /*
   2  * arch/sh/kernel/cpu/sh4/probe.c
   3  *
   4  * CPU Subtype Probing for SH-4.
   5  *
   6  * Copyright (C) 2001, 2002, 2003, 2004  Paul Mundt
   7  * Copyright (C) 2003  Richard Curnow
   8  *
   9  * This file is subject to the terms and conditions of the GNU General Public
  10  * License.  See the file "COPYING" in the main directory of this archive
  11  * for more details.
  12  */
  13
  14 #include <linux/init.h>
  15 #include <asm/processor.h>
  16 #include <asm/cache.h>
  17 #include <asm/io.h>
  18
  19 int __init detect_cpu_and_cache_system(void)
  20 {
  21         unsigned long pvr, prr, cvr;
  22         unsigned long size;
  23
  24         static unsigned long sizes[16] = {
  25                 [1] = (1 << 12),
  26                 [2] = (1 << 13),
  27                 [4] = (1 << 14),
  28                 [8] = (1 << 15),
  29                 [9] = (1 << 16)
  30         };
  31
  32         pvr = (ctrl_inl(CCN_PVR) >> 8) & 0xffff;
  33         prr = (ctrl_inl(CCN_PRR) >> 4) & 0xff;
  34         cvr = (ctrl_inl(CCN_CVR));
  35
  36         /*
  37          * Setup some sane SH-4 defaults for the icache
  38          */
  39         cpu_data->icache.way_incr       = (1 << 13);
  40         cpu_data->icache.entry_shift    = 5;
  41         cpu_data->icache.entry_mask     = 0x1fe0;
  42         cpu_data->icache.sets           = 256;
  43         cpu_data->icache.ways           = 1;
  44         cpu_data->icache.linesz         = L1_CACHE_BYTES;
  45
  46         /*
  47          * And again for the dcache ..
  48          */
  49         cpu_data->dcache.way_incr       = (1 << 14);
  50         cpu_data->dcache.entry_shift    = 5;
  51         cpu_data->dcache.entry_mask     = 0x3fe0;
  52         cpu_data->dcache.sets           = 512;
  53         cpu_data->dcache.ways           = 1;
  54         cpu_data->dcache.linesz         = L1_CACHE_BYTES;
  55
  56         /* Set the FPU flag, virtually all SH-4's have one */
  57         cpu_data->flags |= CPU_HAS_FPU;
  58
  59         /*
  60          * Probe the underlying processor version/revision and
  61          * adjust cpu_data setup accordingly.
  62          */
  63         switch (pvr) {
  64         case 0x205:
  65                 cpu_data->type = CPU_SH7750;
  66                 cpu_data->flags |= CPU_HAS_P2_FLUSH_BUG | CPU_HAS_PERF_COUNTER;
  67                 break;
  68         case 0x206:
  69                 cpu_data->type = CPU_SH7750S;
  70                 cpu_data->flags |= CPU_HAS_P2_FLUSH_BUG | CPU_HAS_PERF_COUNTER;
  71                 break;
  72         case 0x1100:
  73                 cpu_data->type = CPU_SH7751;
  74                 break;
  75         case 0x2000:
  76                 cpu_data->type = CPU_SH73180;
  77                 cpu_data->icache.ways = 4;
  78                 cpu_data->dcache.ways = 4;
  79                 cpu_data->flags &= ~CPU_HAS_FPU;
  80                 break;
  81         case 0x8000:
  82                 cpu_data->type = CPU_ST40RA;
  83                 break;
  84         case 0x8100:
  85                 cpu_data->type = CPU_ST40GX1;
  86                 break;
  87         case 0x700:
  88                 cpu_data->type = CPU_SH4_501;
  89                 cpu_data->icache.ways = 2;
  90                 cpu_data->dcache.ways = 2;
  91
  92                 /* No FPU on the SH4-500 series.. */
  93                 cpu_data->flags &= ~CPU_HAS_FPU;
  94                 break;
  95         case 0x600:
  96                 cpu_data->type = CPU_SH4_202;
  97                 cpu_data->icache.ways = 2;
  98                 cpu_data->dcache.ways = 2;
  99                 break;
 100         case 0x500 ... 0x501:
 101                 switch (prr) {
 102                     case 0x10: cpu_data->type = CPU_SH7750R; break;
 103                     case 0x11: cpu_data->type = CPU_SH7751R; break;
 104                     case 0x50: cpu_data->type = CPU_SH7760;  break;
 105                 }
 106
 107                 cpu_data->icache.ways = 2;
 108                 cpu_data->dcache.ways = 2;
 109
 110                 break;
 111         default:
 112                 cpu_data->type = CPU_SH_NONE;
 113                 break;
 114         }
 115
 116         /*
 117          * On anything that's not a direct-mapped cache, look to the CVR
 118          * for I/D-cache specifics.
 119          */
 120         if (cpu_data->icache.ways > 1) {
 121                 size = sizes[(cvr >> 20) & 0xf];
 122                 cpu_data->icache.way_incr       = (size >> 1);
 123                 cpu_data->icache.sets           = (size >> 6);
 124                 cpu_data->icache.entry_mask     =
 125                         (cpu_data->icache.way_incr - (1 << 5));
 126         }
 127
 128         if (cpu_data->dcache.ways > 1) {
 129                 size = sizes[(cvr >> 16) & 0xf];
 130                 cpu_data->dcache.way_incr       = (size >> 1);
 131                 cpu_data->dcache.sets           = (size >> 6);
 132                 cpu_data->dcache.entry_mask     =
 133                         (cpu_data->dcache.way_incr - (1 << 5));
 134         }
 135
 136         return 0;
 137 }
 138