Merge commit 'origin/HEAD' into test-merge
[linux-2.6] / drivers / net / wireless / rt2x00 / rt2400pci.c
1 /*
2         Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
3         <http://rt2x00.serialmonkey.com>
4
5         This program is free software; you can redistribute it and/or modify
6         it under the terms of the GNU General Public License as published by
7         the Free Software Foundation; either version 2 of the License, or
8         (at your option) any later version.
9
10         This program is distributed in the hope that it will be useful,
11         but WITHOUT ANY WARRANTY; without even the implied warranty of
12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13         GNU General Public License for more details.
14
15         You should have received a copy of the GNU General Public License
16         along with this program; if not, write to the
17         Free Software Foundation, Inc.,
18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19  */
20
21 /*
22         Module: rt2400pci
23         Abstract: rt2400pci device specific routines.
24         Supported chipsets: RT2460.
25  */
26
27 #include <linux/delay.h>
28 #include <linux/etherdevice.h>
29 #include <linux/init.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/pci.h>
33 #include <linux/eeprom_93cx6.h>
34
35 #include "rt2x00.h"
36 #include "rt2x00pci.h"
37 #include "rt2400pci.h"
38
39 /*
40  * Register access.
41  * All access to the CSR registers will go through the methods
42  * rt2x00pci_register_read and rt2x00pci_register_write.
43  * BBP and RF register require indirect register access,
44  * and use the CSR registers BBPCSR and RFCSR to achieve this.
45  * These indirect registers work with busy bits,
46  * and we will try maximal REGISTER_BUSY_COUNT times to access
47  * the register while taking a REGISTER_BUSY_DELAY us delay
48  * between each attampt. When the busy bit is still set at that time,
49  * the access attempt is considered to have failed,
50  * and we will print an error.
51  */
52 static u32 rt2400pci_bbp_check(struct rt2x00_dev *rt2x00dev)
53 {
54         u32 reg;
55         unsigned int i;
56
57         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
58                 rt2x00pci_register_read(rt2x00dev, BBPCSR, &reg);
59                 if (!rt2x00_get_field32(reg, BBPCSR_BUSY))
60                         break;
61                 udelay(REGISTER_BUSY_DELAY);
62         }
63
64         return reg;
65 }
66
67 static void rt2400pci_bbp_write(struct rt2x00_dev *rt2x00dev,
68                                 const unsigned int word, const u8 value)
69 {
70         u32 reg;
71
72         /*
73          * Wait until the BBP becomes ready.
74          */
75         reg = rt2400pci_bbp_check(rt2x00dev);
76         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
77                 ERROR(rt2x00dev, "BBPCSR register busy. Write failed.\n");
78                 return;
79         }
80
81         /*
82          * Write the data into the BBP.
83          */
84         reg = 0;
85         rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
86         rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
87         rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
88         rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
89
90         rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
91 }
92
93 static void rt2400pci_bbp_read(struct rt2x00_dev *rt2x00dev,
94                                const unsigned int word, u8 *value)
95 {
96         u32 reg;
97
98         /*
99          * Wait until the BBP becomes ready.
100          */
101         reg = rt2400pci_bbp_check(rt2x00dev);
102         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
103                 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
104                 return;
105         }
106
107         /*
108          * Write the request into the BBP.
109          */
110         reg = 0;
111         rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
112         rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
113         rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
114
115         rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
116
117         /*
118          * Wait until the BBP becomes ready.
119          */
120         reg = rt2400pci_bbp_check(rt2x00dev);
121         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
122                 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
123                 *value = 0xff;
124                 return;
125         }
126
127         *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
128 }
129
130 static void rt2400pci_rf_write(struct rt2x00_dev *rt2x00dev,
131                                const unsigned int word, const u32 value)
132 {
133         u32 reg;
134         unsigned int i;
135
136         if (!word)
137                 return;
138
139         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
140                 rt2x00pci_register_read(rt2x00dev, RFCSR, &reg);
141                 if (!rt2x00_get_field32(reg, RFCSR_BUSY))
142                         goto rf_write;
143                 udelay(REGISTER_BUSY_DELAY);
144         }
145
146         ERROR(rt2x00dev, "RFCSR register busy. Write failed.\n");
147         return;
148
149 rf_write:
150         reg = 0;
151         rt2x00_set_field32(&reg, RFCSR_VALUE, value);
152         rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
153         rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
154         rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
155
156         rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
157         rt2x00_rf_write(rt2x00dev, word, value);
158 }
159
160 static void rt2400pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
161 {
162         struct rt2x00_dev *rt2x00dev = eeprom->data;
163         u32 reg;
164
165         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
166
167         eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
168         eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
169         eeprom->reg_data_clock =
170             !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
171         eeprom->reg_chip_select =
172             !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
173 }
174
175 static void rt2400pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
176 {
177         struct rt2x00_dev *rt2x00dev = eeprom->data;
178         u32 reg = 0;
179
180         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
181         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
182         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
183                            !!eeprom->reg_data_clock);
184         rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
185                            !!eeprom->reg_chip_select);
186
187         rt2x00pci_register_write(rt2x00dev, CSR21, reg);
188 }
189
190 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
191 #define CSR_OFFSET(__word)      ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
192
193 static void rt2400pci_read_csr(struct rt2x00_dev *rt2x00dev,
194                                const unsigned int word, u32 *data)
195 {
196         rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
197 }
198
199 static void rt2400pci_write_csr(struct rt2x00_dev *rt2x00dev,
200                                 const unsigned int word, u32 data)
201 {
202         rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
203 }
204
205 static const struct rt2x00debug rt2400pci_rt2x00debug = {
206         .owner  = THIS_MODULE,
207         .csr    = {
208                 .read           = rt2400pci_read_csr,
209                 .write          = rt2400pci_write_csr,
210                 .word_size      = sizeof(u32),
211                 .word_count     = CSR_REG_SIZE / sizeof(u32),
212         },
213         .eeprom = {
214                 .read           = rt2x00_eeprom_read,
215                 .write          = rt2x00_eeprom_write,
216                 .word_size      = sizeof(u16),
217                 .word_count     = EEPROM_SIZE / sizeof(u16),
218         },
219         .bbp    = {
220                 .read           = rt2400pci_bbp_read,
221                 .write          = rt2400pci_bbp_write,
222                 .word_size      = sizeof(u8),
223                 .word_count     = BBP_SIZE / sizeof(u8),
224         },
225         .rf     = {
226                 .read           = rt2x00_rf_read,
227                 .write          = rt2400pci_rf_write,
228                 .word_size      = sizeof(u32),
229                 .word_count     = RF_SIZE / sizeof(u32),
230         },
231 };
232 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
233
234 #ifdef CONFIG_RT2400PCI_RFKILL
235 static int rt2400pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
236 {
237         u32 reg;
238
239         rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
240         return rt2x00_get_field32(reg, GPIOCSR_BIT0);
241 }
242 #else
243 #define rt2400pci_rfkill_poll   NULL
244 #endif /* CONFIG_RT2400PCI_RFKILL */
245
246 #ifdef CONFIG_RT2400PCI_LEDS
247 static void rt2400pci_brightness_set(struct led_classdev *led_cdev,
248                                      enum led_brightness brightness)
249 {
250         struct rt2x00_led *led =
251             container_of(led_cdev, struct rt2x00_led, led_dev);
252         unsigned int enabled = brightness != LED_OFF;
253         u32 reg;
254
255         rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
256
257         if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC)
258                 rt2x00_set_field32(&reg, LEDCSR_LINK, enabled);
259         else if (led->type == LED_TYPE_ACTIVITY)
260                 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled);
261
262         rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
263 }
264
265 static int rt2400pci_blink_set(struct led_classdev *led_cdev,
266                                unsigned long *delay_on,
267                                unsigned long *delay_off)
268 {
269         struct rt2x00_led *led =
270             container_of(led_cdev, struct rt2x00_led, led_dev);
271         u32 reg;
272
273         rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
274         rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, *delay_on);
275         rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, *delay_off);
276         rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
277
278         return 0;
279 }
280 #endif /* CONFIG_RT2400PCI_LEDS */
281
282 /*
283  * Configuration handlers.
284  */
285 static void rt2400pci_config_filter(struct rt2x00_dev *rt2x00dev,
286                                     const unsigned int filter_flags)
287 {
288         u32 reg;
289
290         /*
291          * Start configuration steps.
292          * Note that the version error will always be dropped
293          * since there is no filter for it at this time.
294          */
295         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
296         rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
297                            !(filter_flags & FIF_FCSFAIL));
298         rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
299                            !(filter_flags & FIF_PLCPFAIL));
300         rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
301                            !(filter_flags & FIF_CONTROL));
302         rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
303                            !(filter_flags & FIF_PROMISC_IN_BSS));
304         rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
305                            !(filter_flags & FIF_PROMISC_IN_BSS) &&
306                            !rt2x00dev->intf_ap_count);
307         rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
308         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
309 }
310
311 static void rt2400pci_config_intf(struct rt2x00_dev *rt2x00dev,
312                                   struct rt2x00_intf *intf,
313                                   struct rt2x00intf_conf *conf,
314                                   const unsigned int flags)
315 {
316         unsigned int bcn_preload;
317         u32 reg;
318
319         if (flags & CONFIG_UPDATE_TYPE) {
320                 /*
321                  * Enable beacon config
322                  */
323                 bcn_preload = PREAMBLE + get_duration(IEEE80211_HEADER, 20);
324                 rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
325                 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload);
326                 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
327
328                 /*
329                  * Enable synchronisation.
330                  */
331                 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
332                 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
333                 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
334                 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
335                 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
336         }
337
338         if (flags & CONFIG_UPDATE_MAC)
339                 rt2x00pci_register_multiwrite(rt2x00dev, CSR3,
340                                               conf->mac, sizeof(conf->mac));
341
342         if (flags & CONFIG_UPDATE_BSSID)
343                 rt2x00pci_register_multiwrite(rt2x00dev, CSR5,
344                                               conf->bssid, sizeof(conf->bssid));
345 }
346
347 static void rt2400pci_config_erp(struct rt2x00_dev *rt2x00dev,
348                                  struct rt2x00lib_erp *erp)
349 {
350         int preamble_mask;
351         u32 reg;
352
353         /*
354          * When short preamble is enabled, we should set bit 0x08
355          */
356         preamble_mask = erp->short_preamble << 3;
357
358         rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
359         rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT,
360                            erp->ack_timeout);
361         rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME,
362                            erp->ack_consume_time);
363         rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
364
365         rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
366         rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00);
367         rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
368         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 10));
369         rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
370
371         rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
372         rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
373         rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
374         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 20));
375         rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
376
377         rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
378         rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
379         rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
380         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 55));
381         rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
382
383         rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
384         rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
385         rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
386         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 110));
387         rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
388 }
389
390 static void rt2400pci_config_phymode(struct rt2x00_dev *rt2x00dev,
391                                      const int basic_rate_mask)
392 {
393         rt2x00pci_register_write(rt2x00dev, ARCSR1, basic_rate_mask);
394 }
395
396 static void rt2400pci_config_channel(struct rt2x00_dev *rt2x00dev,
397                                      struct rf_channel *rf)
398 {
399         /*
400          * Switch on tuning bits.
401          */
402         rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
403         rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
404
405         rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
406         rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
407         rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
408
409         /*
410          * RF2420 chipset don't need any additional actions.
411          */
412         if (rt2x00_rf(&rt2x00dev->chip, RF2420))
413                 return;
414
415         /*
416          * For the RT2421 chipsets we need to write an invalid
417          * reference clock rate to activate auto_tune.
418          * After that we set the value back to the correct channel.
419          */
420         rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
421         rt2400pci_rf_write(rt2x00dev, 2, 0x000c2a32);
422         rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
423
424         msleep(1);
425
426         rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
427         rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
428         rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
429
430         msleep(1);
431
432         /*
433          * Switch off tuning bits.
434          */
435         rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
436         rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
437
438         rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
439         rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
440
441         /*
442          * Clear false CRC during channel switch.
443          */
444         rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
445 }
446
447 static void rt2400pci_config_txpower(struct rt2x00_dev *rt2x00dev, int txpower)
448 {
449         rt2400pci_bbp_write(rt2x00dev, 3, TXPOWER_TO_DEV(txpower));
450 }
451
452 static void rt2400pci_config_antenna(struct rt2x00_dev *rt2x00dev,
453                                      struct antenna_setup *ant)
454 {
455         u8 r1;
456         u8 r4;
457
458         /*
459          * We should never come here because rt2x00lib is supposed
460          * to catch this and send us the correct antenna explicitely.
461          */
462         BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
463                ant->tx == ANTENNA_SW_DIVERSITY);
464
465         rt2400pci_bbp_read(rt2x00dev, 4, &r4);
466         rt2400pci_bbp_read(rt2x00dev, 1, &r1);
467
468         /*
469          * Configure the TX antenna.
470          */
471         switch (ant->tx) {
472         case ANTENNA_HW_DIVERSITY:
473                 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 1);
474                 break;
475         case ANTENNA_A:
476                 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 0);
477                 break;
478         case ANTENNA_B:
479         default:
480                 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 2);
481                 break;
482         }
483
484         /*
485          * Configure the RX antenna.
486          */
487         switch (ant->rx) {
488         case ANTENNA_HW_DIVERSITY:
489                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
490                 break;
491         case ANTENNA_A:
492                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 0);
493                 break;
494         case ANTENNA_B:
495         default:
496                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
497                 break;
498         }
499
500         rt2400pci_bbp_write(rt2x00dev, 4, r4);
501         rt2400pci_bbp_write(rt2x00dev, 1, r1);
502 }
503
504 static void rt2400pci_config_duration(struct rt2x00_dev *rt2x00dev,
505                                       struct rt2x00lib_conf *libconf)
506 {
507         u32 reg;
508
509         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
510         rt2x00_set_field32(&reg, CSR11_SLOT_TIME, libconf->slot_time);
511         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
512
513         rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
514         rt2x00_set_field32(&reg, CSR18_SIFS, libconf->sifs);
515         rt2x00_set_field32(&reg, CSR18_PIFS, libconf->pifs);
516         rt2x00pci_register_write(rt2x00dev, CSR18, reg);
517
518         rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
519         rt2x00_set_field32(&reg, CSR19_DIFS, libconf->difs);
520         rt2x00_set_field32(&reg, CSR19_EIFS, libconf->eifs);
521         rt2x00pci_register_write(rt2x00dev, CSR19, reg);
522
523         rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
524         rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
525         rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
526         rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
527
528         rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
529         rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,
530                            libconf->conf->beacon_int * 16);
531         rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
532                            libconf->conf->beacon_int * 16);
533         rt2x00pci_register_write(rt2x00dev, CSR12, reg);
534 }
535
536 static void rt2400pci_config(struct rt2x00_dev *rt2x00dev,
537                              struct rt2x00lib_conf *libconf,
538                              const unsigned int flags)
539 {
540         if (flags & CONFIG_UPDATE_PHYMODE)
541                 rt2400pci_config_phymode(rt2x00dev, libconf->basic_rates);
542         if (flags & CONFIG_UPDATE_CHANNEL)
543                 rt2400pci_config_channel(rt2x00dev, &libconf->rf);
544         if (flags & CONFIG_UPDATE_TXPOWER)
545                 rt2400pci_config_txpower(rt2x00dev,
546                                          libconf->conf->power_level);
547         if (flags & CONFIG_UPDATE_ANTENNA)
548                 rt2400pci_config_antenna(rt2x00dev, &libconf->ant);
549         if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
550                 rt2400pci_config_duration(rt2x00dev, libconf);
551 }
552
553 static void rt2400pci_config_cw(struct rt2x00_dev *rt2x00dev,
554                                 const int cw_min, const int cw_max)
555 {
556         u32 reg;
557
558         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
559         rt2x00_set_field32(&reg, CSR11_CWMIN, cw_min);
560         rt2x00_set_field32(&reg, CSR11_CWMAX, cw_max);
561         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
562 }
563
564 /*
565  * Link tuning
566  */
567 static void rt2400pci_link_stats(struct rt2x00_dev *rt2x00dev,
568                                  struct link_qual *qual)
569 {
570         u32 reg;
571         u8 bbp;
572
573         /*
574          * Update FCS error count from register.
575          */
576         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
577         qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
578
579         /*
580          * Update False CCA count from register.
581          */
582         rt2400pci_bbp_read(rt2x00dev, 39, &bbp);
583         qual->false_cca = bbp;
584 }
585
586 static void rt2400pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
587 {
588         rt2400pci_bbp_write(rt2x00dev, 13, 0x08);
589         rt2x00dev->link.vgc_level = 0x08;
590 }
591
592 static void rt2400pci_link_tuner(struct rt2x00_dev *rt2x00dev)
593 {
594         u8 reg;
595
596         /*
597          * The link tuner should not run longer then 60 seconds,
598          * and should run once every 2 seconds.
599          */
600         if (rt2x00dev->link.count > 60 || !(rt2x00dev->link.count & 1))
601                 return;
602
603         /*
604          * Base r13 link tuning on the false cca count.
605          */
606         rt2400pci_bbp_read(rt2x00dev, 13, &reg);
607
608         if (rt2x00dev->link.qual.false_cca > 512 && reg < 0x20) {
609                 rt2400pci_bbp_write(rt2x00dev, 13, ++reg);
610                 rt2x00dev->link.vgc_level = reg;
611         } else if (rt2x00dev->link.qual.false_cca < 100 && reg > 0x08) {
612                 rt2400pci_bbp_write(rt2x00dev, 13, --reg);
613                 rt2x00dev->link.vgc_level = reg;
614         }
615 }
616
617 /*
618  * Initialization functions.
619  */
620 static void rt2400pci_init_rxentry(struct rt2x00_dev *rt2x00dev,
621                                    struct queue_entry *entry)
622 {
623         struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data;
624         u32 word;
625
626         rt2x00_desc_read(priv_rx->desc, 2, &word);
627         rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH,
628                            entry->queue->data_size);
629         rt2x00_desc_write(priv_rx->desc, 2, word);
630
631         rt2x00_desc_read(priv_rx->desc, 1, &word);
632         rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, priv_rx->data_dma);
633         rt2x00_desc_write(priv_rx->desc, 1, word);
634
635         rt2x00_desc_read(priv_rx->desc, 0, &word);
636         rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
637         rt2x00_desc_write(priv_rx->desc, 0, word);
638 }
639
640 static void rt2400pci_init_txentry(struct rt2x00_dev *rt2x00dev,
641                                    struct queue_entry *entry)
642 {
643         struct queue_entry_priv_pci_tx *priv_tx = entry->priv_data;
644         u32 word;
645
646         rt2x00_desc_read(priv_tx->desc, 1, &word);
647         rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, priv_tx->data_dma);
648         rt2x00_desc_write(priv_tx->desc, 1, word);
649
650         rt2x00_desc_read(priv_tx->desc, 2, &word);
651         rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH,
652                            entry->queue->data_size);
653         rt2x00_desc_write(priv_tx->desc, 2, word);
654
655         rt2x00_desc_read(priv_tx->desc, 0, &word);
656         rt2x00_set_field32(&word, TXD_W0_VALID, 0);
657         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
658         rt2x00_desc_write(priv_tx->desc, 0, word);
659 }
660
661 static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev)
662 {
663         struct queue_entry_priv_pci_rx *priv_rx;
664         struct queue_entry_priv_pci_tx *priv_tx;
665         u32 reg;
666
667         /*
668          * Initialize registers.
669          */
670         rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
671         rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
672         rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
673         rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit);
674         rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
675         rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
676
677         priv_tx = rt2x00dev->tx[1].entries[0].priv_data;
678         rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
679         rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
680                            priv_tx->desc_dma);
681         rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
682
683         priv_tx = rt2x00dev->tx[0].entries[0].priv_data;
684         rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
685         rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
686                            priv_tx->desc_dma);
687         rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
688
689         priv_tx = rt2x00dev->bcn[1].entries[0].priv_data;
690         rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
691         rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
692                            priv_tx->desc_dma);
693         rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
694
695         priv_tx = rt2x00dev->bcn[0].entries[0].priv_data;
696         rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
697         rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
698                            priv_tx->desc_dma);
699         rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
700
701         rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
702         rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
703         rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
704         rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
705
706         priv_rx = rt2x00dev->rx->entries[0].priv_data;
707         rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
708         rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER, priv_rx->desc_dma);
709         rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
710
711         return 0;
712 }
713
714 static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev)
715 {
716         u32 reg;
717
718         rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
719         rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
720         rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00023f20);
721         rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
722
723         rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
724         rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
725         rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
726         rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
727         rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
728
729         rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
730         rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
731                            (rt2x00dev->rx->data_size / 128));
732         rt2x00pci_register_write(rt2x00dev, CSR9, reg);
733
734         rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
735         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
736         rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 0);
737         rt2x00_set_field32(&reg, CSR14_TBCN, 0);
738         rt2x00_set_field32(&reg, CSR14_TCFP, 0);
739         rt2x00_set_field32(&reg, CSR14_TATIMW, 0);
740         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
741         rt2x00_set_field32(&reg, CSR14_CFP_COUNT_PRELOAD, 0);
742         rt2x00_set_field32(&reg, CSR14_TBCM_PRELOAD, 0);
743         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
744
745         rt2x00pci_register_write(rt2x00dev, CNT3, 0x3f080000);
746
747         rt2x00pci_register_read(rt2x00dev, ARCSR0, &reg);
748         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA0, 133);
749         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID0, 134);
750         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA1, 136);
751         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID1, 135);
752         rt2x00pci_register_write(rt2x00dev, ARCSR0, reg);
753
754         rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
755         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 3); /* Tx power.*/
756         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
757         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 32); /* Signal */
758         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
759         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 36); /* Rssi */
760         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
761         rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
762
763         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
764
765         if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
766                 return -EBUSY;
767
768         rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00217223);
769         rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
770
771         rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
772         rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
773         rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
774
775         rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
776         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
777         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 154);
778         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
779         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 154);
780         rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
781
782         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
783         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
784         rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
785         rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
786         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
787
788         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
789         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
790         rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
791         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
792
793         /*
794          * We must clear the FCS and FIFO error count.
795          * These registers are cleared on read,
796          * so we may pass a useless variable to store the value.
797          */
798         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
799         rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
800
801         return 0;
802 }
803
804 static int rt2400pci_init_bbp(struct rt2x00_dev *rt2x00dev)
805 {
806         unsigned int i;
807         u16 eeprom;
808         u8 reg_id;
809         u8 value;
810
811         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
812                 rt2400pci_bbp_read(rt2x00dev, 0, &value);
813                 if ((value != 0xff) && (value != 0x00))
814                         goto continue_csr_init;
815                 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
816                 udelay(REGISTER_BUSY_DELAY);
817         }
818
819         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
820         return -EACCES;
821
822 continue_csr_init:
823         rt2400pci_bbp_write(rt2x00dev, 1, 0x00);
824         rt2400pci_bbp_write(rt2x00dev, 3, 0x27);
825         rt2400pci_bbp_write(rt2x00dev, 4, 0x08);
826         rt2400pci_bbp_write(rt2x00dev, 10, 0x0f);
827         rt2400pci_bbp_write(rt2x00dev, 15, 0x72);
828         rt2400pci_bbp_write(rt2x00dev, 16, 0x74);
829         rt2400pci_bbp_write(rt2x00dev, 17, 0x20);
830         rt2400pci_bbp_write(rt2x00dev, 18, 0x72);
831         rt2400pci_bbp_write(rt2x00dev, 19, 0x0b);
832         rt2400pci_bbp_write(rt2x00dev, 20, 0x00);
833         rt2400pci_bbp_write(rt2x00dev, 28, 0x11);
834         rt2400pci_bbp_write(rt2x00dev, 29, 0x04);
835         rt2400pci_bbp_write(rt2x00dev, 30, 0x21);
836         rt2400pci_bbp_write(rt2x00dev, 31, 0x00);
837
838         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
839                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
840
841                 if (eeprom != 0xffff && eeprom != 0x0000) {
842                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
843                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
844                         rt2400pci_bbp_write(rt2x00dev, reg_id, value);
845                 }
846         }
847
848         return 0;
849 }
850
851 /*
852  * Device state switch handlers.
853  */
854 static void rt2400pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
855                                 enum dev_state state)
856 {
857         u32 reg;
858
859         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
860         rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
861                            state == STATE_RADIO_RX_OFF);
862         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
863 }
864
865 static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
866                                  enum dev_state state)
867 {
868         int mask = (state == STATE_RADIO_IRQ_OFF);
869         u32 reg;
870
871         /*
872          * When interrupts are being enabled, the interrupt registers
873          * should clear the register to assure a clean state.
874          */
875         if (state == STATE_RADIO_IRQ_ON) {
876                 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
877                 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
878         }
879
880         /*
881          * Only toggle the interrupts bits we are going to use.
882          * Non-checked interrupt bits are disabled by default.
883          */
884         rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
885         rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
886         rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
887         rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
888         rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
889         rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
890         rt2x00pci_register_write(rt2x00dev, CSR8, reg);
891 }
892
893 static int rt2400pci_enable_radio(struct rt2x00_dev *rt2x00dev)
894 {
895         /*
896          * Initialize all registers.
897          */
898         if (rt2400pci_init_queues(rt2x00dev) ||
899             rt2400pci_init_registers(rt2x00dev) ||
900             rt2400pci_init_bbp(rt2x00dev)) {
901                 ERROR(rt2x00dev, "Register initialization failed.\n");
902                 return -EIO;
903         }
904
905         /*
906          * Enable interrupts.
907          */
908         rt2400pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_ON);
909
910         return 0;
911 }
912
913 static void rt2400pci_disable_radio(struct rt2x00_dev *rt2x00dev)
914 {
915         u32 reg;
916
917         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
918
919         /*
920          * Disable synchronisation.
921          */
922         rt2x00pci_register_write(rt2x00dev, CSR14, 0);
923
924         /*
925          * Cancel RX and TX.
926          */
927         rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
928         rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
929         rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
930
931         /*
932          * Disable interrupts.
933          */
934         rt2400pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_OFF);
935 }
936
937 static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev,
938                                enum dev_state state)
939 {
940         u32 reg;
941         unsigned int i;
942         char put_to_sleep;
943         char bbp_state;
944         char rf_state;
945
946         put_to_sleep = (state != STATE_AWAKE);
947
948         rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
949         rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
950         rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
951         rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
952         rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
953         rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
954
955         /*
956          * Device is not guaranteed to be in the requested state yet.
957          * We must wait until the register indicates that the
958          * device has entered the correct state.
959          */
960         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
961                 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
962                 bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
963                 rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
964                 if (bbp_state == state && rf_state == state)
965                         return 0;
966                 msleep(10);
967         }
968
969         NOTICE(rt2x00dev, "Device failed to enter state %d, "
970                "current device state: bbp %d and rf %d.\n",
971                state, bbp_state, rf_state);
972
973         return -EBUSY;
974 }
975
976 static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev,
977                                       enum dev_state state)
978 {
979         int retval = 0;
980
981         switch (state) {
982         case STATE_RADIO_ON:
983                 retval = rt2400pci_enable_radio(rt2x00dev);
984                 break;
985         case STATE_RADIO_OFF:
986                 rt2400pci_disable_radio(rt2x00dev);
987                 break;
988         case STATE_RADIO_RX_ON:
989         case STATE_RADIO_RX_ON_LINK:
990                 rt2400pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_ON);
991                 break;
992         case STATE_RADIO_RX_OFF:
993         case STATE_RADIO_RX_OFF_LINK:
994                 rt2400pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_OFF);
995                 break;
996         case STATE_DEEP_SLEEP:
997         case STATE_SLEEP:
998         case STATE_STANDBY:
999         case STATE_AWAKE:
1000                 retval = rt2400pci_set_state(rt2x00dev, state);
1001                 break;
1002         default:
1003                 retval = -ENOTSUPP;
1004                 break;
1005         }
1006
1007         return retval;
1008 }
1009
1010 /*
1011  * TX descriptor initialization
1012  */
1013 static void rt2400pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1014                                     struct sk_buff *skb,
1015                                     struct txentry_desc *txdesc,
1016                                     struct ieee80211_tx_control *control)
1017 {
1018         struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1019         __le32 *txd = skbdesc->desc;
1020         u32 word;
1021
1022         /*
1023          * Start writing the descriptor words.
1024          */
1025         rt2x00_desc_read(txd, 2, &word);
1026         rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, skbdesc->data_len);
1027         rt2x00_desc_write(txd, 2, word);
1028
1029         rt2x00_desc_read(txd, 3, &word);
1030         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->signal);
1031         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_REGNUM, 5);
1032         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_BUSY, 1);
1033         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->service);
1034         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_REGNUM, 6);
1035         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_BUSY, 1);
1036         rt2x00_desc_write(txd, 3, word);
1037
1038         rt2x00_desc_read(txd, 4, &word);
1039         rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_LOW, txdesc->length_low);
1040         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_REGNUM, 8);
1041         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_BUSY, 1);
1042         rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_HIGH, txdesc->length_high);
1043         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_REGNUM, 7);
1044         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_BUSY, 1);
1045         rt2x00_desc_write(txd, 4, word);
1046
1047         rt2x00_desc_read(txd, 0, &word);
1048         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1049         rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1050         rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1051                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1052         rt2x00_set_field32(&word, TXD_W0_ACK,
1053                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1054         rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1055                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1056         rt2x00_set_field32(&word, TXD_W0_RTS,
1057                            test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
1058         rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1059         rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1060                            !!(control->flags &
1061                               IEEE80211_TXCTL_LONG_RETRY_LIMIT));
1062         rt2x00_desc_write(txd, 0, word);
1063 }
1064
1065 /*
1066  * TX data initialization
1067  */
1068 static void rt2400pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1069                                     const unsigned int queue)
1070 {
1071         u32 reg;
1072
1073         if (queue == RT2X00_BCN_QUEUE_BEACON) {
1074                 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1075                 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
1076                         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
1077                         rt2x00_set_field32(&reg, CSR14_TBCN, 1);
1078                         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1079                         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1080                 }
1081                 return;
1082         }
1083
1084         rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1085         rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO,
1086                            (queue == IEEE80211_TX_QUEUE_DATA0));
1087         rt2x00_set_field32(&reg, TXCSR0_KICK_TX,
1088                            (queue == IEEE80211_TX_QUEUE_DATA1));
1089         rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM,
1090                            (queue == RT2X00_BCN_QUEUE_ATIM));
1091         rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1092 }
1093
1094 /*
1095  * RX control handlers
1096  */
1097 static void rt2400pci_fill_rxdone(struct queue_entry *entry,
1098                                   struct rxdone_entry_desc *rxdesc)
1099 {
1100         struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data;
1101         u32 word0;
1102         u32 word2;
1103         u32 word3;
1104
1105         rt2x00_desc_read(priv_rx->desc, 0, &word0);
1106         rt2x00_desc_read(priv_rx->desc, 2, &word2);
1107         rt2x00_desc_read(priv_rx->desc, 3, &word3);
1108
1109         rxdesc->flags = 0;
1110         if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1111                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1112         if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
1113                 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
1114
1115         /*
1116          * Obtain the status about this packet.
1117          * The signal is the PLCP value, and needs to be stripped
1118          * of the preamble bit (0x08).
1119          */
1120         rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL) & ~0x08;
1121         rxdesc->rssi = rt2x00_get_field32(word2, RXD_W3_RSSI) -
1122             entry->queue->rt2x00dev->rssi_offset;
1123         rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1124
1125         rxdesc->dev_flags = RXDONE_SIGNAL_PLCP;
1126         if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1127                 rxdesc->dev_flags |= RXDONE_MY_BSS;
1128 }
1129
1130 /*
1131  * Interrupt functions.
1132  */
1133 static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev,
1134                              const enum ieee80211_tx_queue queue_idx)
1135 {
1136         struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
1137         struct queue_entry_priv_pci_tx *priv_tx;
1138         struct queue_entry *entry;
1139         struct txdone_entry_desc txdesc;
1140         u32 word;
1141
1142         while (!rt2x00queue_empty(queue)) {
1143                 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1144                 priv_tx = entry->priv_data;
1145                 rt2x00_desc_read(priv_tx->desc, 0, &word);
1146
1147                 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1148                     !rt2x00_get_field32(word, TXD_W0_VALID))
1149                         break;
1150
1151                 /*
1152                  * Obtain the status about this packet.
1153                  */
1154                 txdesc.status = rt2x00_get_field32(word, TXD_W0_RESULT);
1155                 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1156
1157                 rt2x00pci_txdone(rt2x00dev, entry, &txdesc);
1158         }
1159 }
1160
1161 static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance)
1162 {
1163         struct rt2x00_dev *rt2x00dev = dev_instance;
1164         u32 reg;
1165
1166         /*
1167          * Get the interrupt sources & saved to local variable.
1168          * Write register value back to clear pending interrupts.
1169          */
1170         rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1171         rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1172
1173         if (!reg)
1174                 return IRQ_NONE;
1175
1176         if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
1177                 return IRQ_HANDLED;
1178
1179         /*
1180          * Handle interrupts, walk through all bits
1181          * and run the tasks, the bits are checked in order of
1182          * priority.
1183          */
1184
1185         /*
1186          * 1 - Beacon timer expired interrupt.
1187          */
1188         if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1189                 rt2x00lib_beacondone(rt2x00dev);
1190
1191         /*
1192          * 2 - Rx ring done interrupt.
1193          */
1194         if (rt2x00_get_field32(reg, CSR7_RXDONE))
1195                 rt2x00pci_rxdone(rt2x00dev);
1196
1197         /*
1198          * 3 - Atim ring transmit done interrupt.
1199          */
1200         if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
1201                 rt2400pci_txdone(rt2x00dev, RT2X00_BCN_QUEUE_ATIM);
1202
1203         /*
1204          * 4 - Priority ring transmit done interrupt.
1205          */
1206         if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
1207                 rt2400pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
1208
1209         /*
1210          * 5 - Tx ring transmit done interrupt.
1211          */
1212         if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
1213                 rt2400pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
1214
1215         return IRQ_HANDLED;
1216 }
1217
1218 /*
1219  * Device probe functions.
1220  */
1221 static int rt2400pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1222 {
1223         struct eeprom_93cx6 eeprom;
1224         u32 reg;
1225         u16 word;
1226         u8 *mac;
1227
1228         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1229
1230         eeprom.data = rt2x00dev;
1231         eeprom.register_read = rt2400pci_eepromregister_read;
1232         eeprom.register_write = rt2400pci_eepromregister_write;
1233         eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1234             PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1235         eeprom.reg_data_in = 0;
1236         eeprom.reg_data_out = 0;
1237         eeprom.reg_data_clock = 0;
1238         eeprom.reg_chip_select = 0;
1239
1240         eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1241                                EEPROM_SIZE / sizeof(u16));
1242
1243         /*
1244          * Start validation of the data that has been read.
1245          */
1246         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1247         if (!is_valid_ether_addr(mac)) {
1248                 DECLARE_MAC_BUF(macbuf);
1249
1250                 random_ether_addr(mac);
1251                 EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
1252         }
1253
1254         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1255         if (word == 0xffff) {
1256                 ERROR(rt2x00dev, "Invalid EEPROM data detected.\n");
1257                 return -EINVAL;
1258         }
1259
1260         return 0;
1261 }
1262
1263 static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1264 {
1265         u32 reg;
1266         u16 value;
1267         u16 eeprom;
1268
1269         /*
1270          * Read EEPROM word for configuration.
1271          */
1272         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1273
1274         /*
1275          * Identify RF chipset.
1276          */
1277         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1278         rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
1279         rt2x00_set_chip(rt2x00dev, RT2460, value, reg);
1280
1281         if (!rt2x00_rf(&rt2x00dev->chip, RF2420) &&
1282             !rt2x00_rf(&rt2x00dev->chip, RF2421)) {
1283                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1284                 return -ENODEV;
1285         }
1286
1287         /*
1288          * Identify default antenna configuration.
1289          */
1290         rt2x00dev->default_ant.tx =
1291             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1292         rt2x00dev->default_ant.rx =
1293             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1294
1295         /*
1296          * When the eeprom indicates SW_DIVERSITY use HW_DIVERSITY instead.
1297          * I am not 100% sure about this, but the legacy drivers do not
1298          * indicate antenna swapping in software is required when
1299          * diversity is enabled.
1300          */
1301         if (rt2x00dev->default_ant.tx == ANTENNA_SW_DIVERSITY)
1302                 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY;
1303         if (rt2x00dev->default_ant.rx == ANTENNA_SW_DIVERSITY)
1304                 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY;
1305
1306         /*
1307          * Store led mode, for correct led behaviour.
1308          */
1309 #ifdef CONFIG_RT2400PCI_LEDS
1310         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1311
1312         rt2x00dev->led_radio.rt2x00dev = rt2x00dev;
1313         rt2x00dev->led_radio.type = LED_TYPE_RADIO;
1314         rt2x00dev->led_radio.led_dev.brightness_set =
1315             rt2400pci_brightness_set;
1316         rt2x00dev->led_radio.led_dev.blink_set =
1317             rt2400pci_blink_set;
1318         rt2x00dev->led_radio.flags = LED_INITIALIZED;
1319
1320         if (value == LED_MODE_TXRX_ACTIVITY) {
1321                 rt2x00dev->led_qual.rt2x00dev = rt2x00dev;
1322                 rt2x00dev->led_qual.type = LED_TYPE_ACTIVITY;
1323                 rt2x00dev->led_qual.led_dev.brightness_set =
1324                     rt2400pci_brightness_set;
1325                 rt2x00dev->led_qual.led_dev.blink_set =
1326                     rt2400pci_blink_set;
1327                 rt2x00dev->led_qual.flags = LED_INITIALIZED;
1328         }
1329 #endif /* CONFIG_RT2400PCI_LEDS */
1330
1331         /*
1332          * Detect if this device has an hardware controlled radio.
1333          */
1334 #ifdef CONFIG_RT2400PCI_RFKILL
1335         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1336                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1337 #endif /* CONFIG_RT2400PCI_RFKILL */
1338
1339         /*
1340          * Check if the BBP tuning should be enabled.
1341          */
1342         if (!rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_AGCVGC_TUNING))
1343                 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1344
1345         return 0;
1346 }
1347
1348 /*
1349  * RF value list for RF2420 & RF2421
1350  * Supports: 2.4 GHz
1351  */
1352 static const struct rf_channel rf_vals_bg[] = {
1353         { 1,  0x00022058, 0x000c1fda, 0x00000101, 0 },
1354         { 2,  0x00022058, 0x000c1fee, 0x00000101, 0 },
1355         { 3,  0x00022058, 0x000c2002, 0x00000101, 0 },
1356         { 4,  0x00022058, 0x000c2016, 0x00000101, 0 },
1357         { 5,  0x00022058, 0x000c202a, 0x00000101, 0 },
1358         { 6,  0x00022058, 0x000c203e, 0x00000101, 0 },
1359         { 7,  0x00022058, 0x000c2052, 0x00000101, 0 },
1360         { 8,  0x00022058, 0x000c2066, 0x00000101, 0 },
1361         { 9,  0x00022058, 0x000c207a, 0x00000101, 0 },
1362         { 10, 0x00022058, 0x000c208e, 0x00000101, 0 },
1363         { 11, 0x00022058, 0x000c20a2, 0x00000101, 0 },
1364         { 12, 0x00022058, 0x000c20b6, 0x00000101, 0 },
1365         { 13, 0x00022058, 0x000c20ca, 0x00000101, 0 },
1366         { 14, 0x00022058, 0x000c20fa, 0x00000101, 0 },
1367 };
1368
1369 static void rt2400pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1370 {
1371         struct hw_mode_spec *spec = &rt2x00dev->spec;
1372         u8 *txpower;
1373         unsigned int i;
1374
1375         /*
1376          * Initialize all hw fields.
1377          */
1378         rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
1379         rt2x00dev->hw->extra_tx_headroom = 0;
1380         rt2x00dev->hw->max_signal = MAX_SIGNAL;
1381         rt2x00dev->hw->max_rssi = MAX_RX_SSI;
1382         rt2x00dev->hw->queues = 2;
1383
1384         SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
1385         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1386                                 rt2x00_eeprom_addr(rt2x00dev,
1387                                                    EEPROM_MAC_ADDR_0));
1388
1389         /*
1390          * Convert tx_power array in eeprom.
1391          */
1392         txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1393         for (i = 0; i < 14; i++)
1394                 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1395
1396         /*
1397          * Initialize hw_mode information.
1398          */
1399         spec->supported_bands = SUPPORT_BAND_2GHZ;
1400         spec->supported_rates = SUPPORT_RATE_CCK;
1401         spec->tx_power_a = NULL;
1402         spec->tx_power_bg = txpower;
1403         spec->tx_power_default = DEFAULT_TXPOWER;
1404
1405         spec->num_channels = ARRAY_SIZE(rf_vals_bg);
1406         spec->channels = rf_vals_bg;
1407 }
1408
1409 static int rt2400pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1410 {
1411         int retval;
1412
1413         /*
1414          * Allocate eeprom data.
1415          */
1416         retval = rt2400pci_validate_eeprom(rt2x00dev);
1417         if (retval)
1418                 return retval;
1419
1420         retval = rt2400pci_init_eeprom(rt2x00dev);
1421         if (retval)
1422                 return retval;
1423
1424         /*
1425          * Initialize hw specifications.
1426          */
1427         rt2400pci_probe_hw_mode(rt2x00dev);
1428
1429         /*
1430          * This device requires the atim queue
1431          */
1432         __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
1433
1434         /*
1435          * Set the rssi offset.
1436          */
1437         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1438
1439         return 0;
1440 }
1441
1442 /*
1443  * IEEE80211 stack callback functions.
1444  */
1445 static int rt2400pci_set_retry_limit(struct ieee80211_hw *hw,
1446                                      u32 short_retry, u32 long_retry)
1447 {
1448         struct rt2x00_dev *rt2x00dev = hw->priv;
1449         u32 reg;
1450
1451         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
1452         rt2x00_set_field32(&reg, CSR11_LONG_RETRY, long_retry);
1453         rt2x00_set_field32(&reg, CSR11_SHORT_RETRY, short_retry);
1454         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
1455
1456         return 0;
1457 }
1458
1459 static int rt2400pci_conf_tx(struct ieee80211_hw *hw,
1460                              int queue,
1461                              const struct ieee80211_tx_queue_params *params)
1462 {
1463         struct rt2x00_dev *rt2x00dev = hw->priv;
1464
1465         /*
1466          * We don't support variating cw_min and cw_max variables
1467          * per queue. So by default we only configure the TX queue,
1468          * and ignore all other configurations.
1469          */
1470         if (queue != IEEE80211_TX_QUEUE_DATA0)
1471                 return -EINVAL;
1472
1473         if (rt2x00mac_conf_tx(hw, queue, params))
1474                 return -EINVAL;
1475
1476         /*
1477          * Write configuration to register.
1478          */
1479         rt2400pci_config_cw(rt2x00dev,
1480                             rt2x00dev->tx->cw_min, rt2x00dev->tx->cw_max);
1481
1482         return 0;
1483 }
1484
1485 static u64 rt2400pci_get_tsf(struct ieee80211_hw *hw)
1486 {
1487         struct rt2x00_dev *rt2x00dev = hw->priv;
1488         u64 tsf;
1489         u32 reg;
1490
1491         rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1492         tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1493         rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1494         tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1495
1496         return tsf;
1497 }
1498
1499 static int rt2400pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
1500                                    struct ieee80211_tx_control *control)
1501 {
1502         struct rt2x00_dev *rt2x00dev = hw->priv;
1503         struct rt2x00_intf *intf = vif_to_intf(control->vif);
1504         struct queue_entry_priv_pci_tx *priv_tx;
1505         struct skb_frame_desc *skbdesc;
1506         u32 reg;
1507
1508         if (unlikely(!intf->beacon))
1509                 return -ENOBUFS;
1510         priv_tx = intf->beacon->priv_data;
1511
1512         /*
1513          * Fill in skb descriptor
1514          */
1515         skbdesc = get_skb_frame_desc(skb);
1516         memset(skbdesc, 0, sizeof(*skbdesc));
1517         skbdesc->flags |= FRAME_DESC_DRIVER_GENERATED;
1518         skbdesc->data = skb->data;
1519         skbdesc->data_len = skb->len;
1520         skbdesc->desc = priv_tx->desc;
1521         skbdesc->desc_len = intf->beacon->queue->desc_size;
1522         skbdesc->entry = intf->beacon;
1523
1524         /*
1525          * Disable beaconing while we are reloading the beacon data,
1526          * otherwise we might be sending out invalid data.
1527          */
1528         rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1529         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
1530         rt2x00_set_field32(&reg, CSR14_TBCN, 0);
1531         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
1532         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1533
1534         /*
1535          * mac80211 doesn't provide the control->queue variable
1536          * for beacons. Set our own queue identification so
1537          * it can be used during descriptor initialization.
1538          */
1539         control->queue = RT2X00_BCN_QUEUE_BEACON;
1540         rt2x00lib_write_tx_desc(rt2x00dev, skb, control);
1541
1542         /*
1543          * Enable beacon generation.
1544          * Write entire beacon with descriptor to register,
1545          * and kick the beacon generator.
1546          */
1547         memcpy(priv_tx->data, skb->data, skb->len);
1548         rt2x00dev->ops->lib->kick_tx_queue(rt2x00dev, control->queue);
1549
1550         return 0;
1551 }
1552
1553 static int rt2400pci_tx_last_beacon(struct ieee80211_hw *hw)
1554 {
1555         struct rt2x00_dev *rt2x00dev = hw->priv;
1556         u32 reg;
1557
1558         rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1559         return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1560 }
1561
1562 static const struct ieee80211_ops rt2400pci_mac80211_ops = {
1563         .tx                     = rt2x00mac_tx,
1564         .start                  = rt2x00mac_start,
1565         .stop                   = rt2x00mac_stop,
1566         .add_interface          = rt2x00mac_add_interface,
1567         .remove_interface       = rt2x00mac_remove_interface,
1568         .config                 = rt2x00mac_config,
1569         .config_interface       = rt2x00mac_config_interface,
1570         .configure_filter       = rt2x00mac_configure_filter,
1571         .get_stats              = rt2x00mac_get_stats,
1572         .set_retry_limit        = rt2400pci_set_retry_limit,
1573         .bss_info_changed       = rt2x00mac_bss_info_changed,
1574         .conf_tx                = rt2400pci_conf_tx,
1575         .get_tx_stats           = rt2x00mac_get_tx_stats,
1576         .get_tsf                = rt2400pci_get_tsf,
1577         .beacon_update          = rt2400pci_beacon_update,
1578         .tx_last_beacon         = rt2400pci_tx_last_beacon,
1579 };
1580
1581 static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = {
1582         .irq_handler            = rt2400pci_interrupt,
1583         .probe_hw               = rt2400pci_probe_hw,
1584         .initialize             = rt2x00pci_initialize,
1585         .uninitialize           = rt2x00pci_uninitialize,
1586         .init_rxentry           = rt2400pci_init_rxentry,
1587         .init_txentry           = rt2400pci_init_txentry,
1588         .set_device_state       = rt2400pci_set_device_state,
1589         .rfkill_poll            = rt2400pci_rfkill_poll,
1590         .link_stats             = rt2400pci_link_stats,
1591         .reset_tuner            = rt2400pci_reset_tuner,
1592         .link_tuner             = rt2400pci_link_tuner,
1593         .write_tx_desc          = rt2400pci_write_tx_desc,
1594         .write_tx_data          = rt2x00pci_write_tx_data,
1595         .kick_tx_queue          = rt2400pci_kick_tx_queue,
1596         .fill_rxdone            = rt2400pci_fill_rxdone,
1597         .config_filter          = rt2400pci_config_filter,
1598         .config_intf            = rt2400pci_config_intf,
1599         .config_erp             = rt2400pci_config_erp,
1600         .config                 = rt2400pci_config,
1601 };
1602
1603 static const struct data_queue_desc rt2400pci_queue_rx = {
1604         .entry_num              = RX_ENTRIES,
1605         .data_size              = DATA_FRAME_SIZE,
1606         .desc_size              = RXD_DESC_SIZE,
1607         .priv_size              = sizeof(struct queue_entry_priv_pci_rx),
1608 };
1609
1610 static const struct data_queue_desc rt2400pci_queue_tx = {
1611         .entry_num              = TX_ENTRIES,
1612         .data_size              = DATA_FRAME_SIZE,
1613         .desc_size              = TXD_DESC_SIZE,
1614         .priv_size              = sizeof(struct queue_entry_priv_pci_tx),
1615 };
1616
1617 static const struct data_queue_desc rt2400pci_queue_bcn = {
1618         .entry_num              = BEACON_ENTRIES,
1619         .data_size              = MGMT_FRAME_SIZE,
1620         .desc_size              = TXD_DESC_SIZE,
1621         .priv_size              = sizeof(struct queue_entry_priv_pci_tx),
1622 };
1623
1624 static const struct data_queue_desc rt2400pci_queue_atim = {
1625         .entry_num              = ATIM_ENTRIES,
1626         .data_size              = DATA_FRAME_SIZE,
1627         .desc_size              = TXD_DESC_SIZE,
1628         .priv_size              = sizeof(struct queue_entry_priv_pci_tx),
1629 };
1630
1631 static const struct rt2x00_ops rt2400pci_ops = {
1632         .name           = KBUILD_MODNAME,
1633         .max_sta_intf   = 1,
1634         .max_ap_intf    = 1,
1635         .eeprom_size    = EEPROM_SIZE,
1636         .rf_size        = RF_SIZE,
1637         .rx             = &rt2400pci_queue_rx,
1638         .tx             = &rt2400pci_queue_tx,
1639         .bcn            = &rt2400pci_queue_bcn,
1640         .atim           = &rt2400pci_queue_atim,
1641         .lib            = &rt2400pci_rt2x00_ops,
1642         .hw             = &rt2400pci_mac80211_ops,
1643 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1644         .debugfs        = &rt2400pci_rt2x00debug,
1645 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1646 };
1647
1648 /*
1649  * RT2400pci module information.
1650  */
1651 static struct pci_device_id rt2400pci_device_table[] = {
1652         { PCI_DEVICE(0x1814, 0x0101), PCI_DEVICE_DATA(&rt2400pci_ops) },
1653         { 0, }
1654 };
1655
1656 MODULE_AUTHOR(DRV_PROJECT);
1657 MODULE_VERSION(DRV_VERSION);
1658 MODULE_DESCRIPTION("Ralink RT2400 PCI & PCMCIA Wireless LAN driver.");
1659 MODULE_SUPPORTED_DEVICE("Ralink RT2460 PCI & PCMCIA chipset based cards");
1660 MODULE_DEVICE_TABLE(pci, rt2400pci_device_table);
1661 MODULE_LICENSE("GPL");
1662
1663 static struct pci_driver rt2400pci_driver = {
1664         .name           = KBUILD_MODNAME,
1665         .id_table       = rt2400pci_device_table,
1666         .probe          = rt2x00pci_probe,
1667         .remove         = __devexit_p(rt2x00pci_remove),
1668         .suspend        = rt2x00pci_suspend,
1669         .resume         = rt2x00pci_resume,
1670 };
1671
1672 static int __init rt2400pci_init(void)
1673 {
1674         return pci_register_driver(&rt2400pci_driver);
1675 }
1676
1677 static void __exit rt2400pci_exit(void)
1678 {
1679         pci_unregister_driver(&rt2400pci_driver);
1680 }
1681
1682 module_init(rt2400pci_init);
1683 module_exit(rt2400pci_exit);