2 * QLogic qlge NIC HBA Driver
3 * Copyright (c) 2003-2008 QLogic Corporation
4 * See LICENSE.qlge for copyright and licensing details.
5 * Author: Linux qlge network device driver by
6 * Ron Mercer <ron.mercer@qlogic.com>
8 #include <linux/kernel.h>
9 #include <linux/init.h>
10 #include <linux/types.h>
11 #include <linux/module.h>
12 #include <linux/list.h>
13 #include <linux/pci.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/pagemap.h>
16 #include <linux/sched.h>
17 #include <linux/slab.h>
18 #include <linux/dmapool.h>
19 #include <linux/mempool.h>
20 #include <linux/spinlock.h>
21 #include <linux/kthread.h>
22 #include <linux/interrupt.h>
23 #include <linux/errno.h>
24 #include <linux/ioport.h>
27 #include <linux/ipv6.h>
29 #include <linux/tcp.h>
30 #include <linux/udp.h>
31 #include <linux/if_arp.h>
32 #include <linux/if_ether.h>
33 #include <linux/netdevice.h>
34 #include <linux/etherdevice.h>
35 #include <linux/ethtool.h>
36 #include <linux/skbuff.h>
37 #include <linux/rtnetlink.h>
38 #include <linux/if_vlan.h>
39 #include <linux/delay.h>
41 #include <linux/vmalloc.h>
42 #include <net/ip6_checksum.h>
46 char qlge_driver_name[] = DRV_NAME;
47 const char qlge_driver_version[] = DRV_VERSION;
49 MODULE_AUTHOR("Ron Mercer <ron.mercer@qlogic.com>");
50 MODULE_DESCRIPTION(DRV_STRING " ");
51 MODULE_LICENSE("GPL");
52 MODULE_VERSION(DRV_VERSION);
54 static const u32 default_msg =
55 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK |
56 /* NETIF_MSG_TIMER | */
62 NETIF_MSG_INTR | NETIF_MSG_TX_DONE | NETIF_MSG_RX_STATUS |
63 /* NETIF_MSG_PKTDATA | */
64 NETIF_MSG_HW | NETIF_MSG_WOL | 0;
66 static int debug = 0x00007fff; /* defaults above */
67 module_param(debug, int, 0);
68 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
73 static int irq_type = MSIX_IRQ;
74 module_param(irq_type, int, MSIX_IRQ);
75 MODULE_PARM_DESC(irq_type, "0 = MSI-X, 1 = MSI, 2 = Legacy.");
77 static struct pci_device_id qlge_pci_tbl[] __devinitdata = {
78 {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QLGE_DEVICE_ID)},
79 /* required last entry */
83 MODULE_DEVICE_TABLE(pci, qlge_pci_tbl);
85 /* This hardware semaphore causes exclusive access to
86 * resources shared between the NIC driver, MPI firmware,
87 * FCOE firmware and the FC driver.
89 static int ql_sem_trylock(struct ql_adapter *qdev, u32 sem_mask)
95 sem_bits = SEM_SET << SEM_XGMAC0_SHIFT;
98 sem_bits = SEM_SET << SEM_XGMAC1_SHIFT;
101 sem_bits = SEM_SET << SEM_ICB_SHIFT;
103 case SEM_MAC_ADDR_MASK:
104 sem_bits = SEM_SET << SEM_MAC_ADDR_SHIFT;
107 sem_bits = SEM_SET << SEM_FLASH_SHIFT;
110 sem_bits = SEM_SET << SEM_PROBE_SHIFT;
112 case SEM_RT_IDX_MASK:
113 sem_bits = SEM_SET << SEM_RT_IDX_SHIFT;
115 case SEM_PROC_REG_MASK:
116 sem_bits = SEM_SET << SEM_PROC_REG_SHIFT;
119 QPRINTK(qdev, PROBE, ALERT, "Bad Semaphore mask!.\n");
123 ql_write32(qdev, SEM, sem_bits | sem_mask);
124 return !(ql_read32(qdev, SEM) & sem_bits);
127 int ql_sem_spinlock(struct ql_adapter *qdev, u32 sem_mask)
129 unsigned int wait_count = 30;
131 if (!ql_sem_trylock(qdev, sem_mask))
134 } while (--wait_count);
138 void ql_sem_unlock(struct ql_adapter *qdev, u32 sem_mask)
140 ql_write32(qdev, SEM, sem_mask);
141 ql_read32(qdev, SEM); /* flush */
144 /* This function waits for a specific bit to come ready
145 * in a given register. It is used mostly by the initialize
146 * process, but is also used in kernel thread API such as
147 * netdev->set_multi, netdev->set_mac_address, netdev->vlan_rx_add_vid.
149 int ql_wait_reg_rdy(struct ql_adapter *qdev, u32 reg, u32 bit, u32 err_bit)
152 int count = UDELAY_COUNT;
155 temp = ql_read32(qdev, reg);
157 /* check for errors */
158 if (temp & err_bit) {
159 QPRINTK(qdev, PROBE, ALERT,
160 "register 0x%.08x access error, value = 0x%.08x!.\n",
163 } else if (temp & bit)
165 udelay(UDELAY_DELAY);
168 QPRINTK(qdev, PROBE, ALERT,
169 "Timed out waiting for reg %x to come ready.\n", reg);
173 /* The CFG register is used to download TX and RX control blocks
174 * to the chip. This function waits for an operation to complete.
176 static int ql_wait_cfg(struct ql_adapter *qdev, u32 bit)
178 int count = UDELAY_COUNT;
182 temp = ql_read32(qdev, CFG);
187 udelay(UDELAY_DELAY);
194 /* Used to issue init control blocks to hw. Maps control block,
195 * sets address, triggers download, waits for completion.
197 int ql_write_cfg(struct ql_adapter *qdev, void *ptr, int size, u32 bit,
207 (bit & (CFG_LRQ | CFG_LR | CFG_LCQ)) ? PCI_DMA_TODEVICE :
210 map = pci_map_single(qdev->pdev, ptr, size, direction);
211 if (pci_dma_mapping_error(qdev->pdev, map)) {
212 QPRINTK(qdev, IFUP, ERR, "Couldn't map DMA area.\n");
216 status = ql_wait_cfg(qdev, bit);
218 QPRINTK(qdev, IFUP, ERR,
219 "Timed out waiting for CFG to come ready.\n");
223 status = ql_sem_spinlock(qdev, SEM_ICB_MASK);
226 ql_write32(qdev, ICB_L, (u32) map);
227 ql_write32(qdev, ICB_H, (u32) (map >> 32));
228 ql_sem_unlock(qdev, SEM_ICB_MASK); /* does flush too */
230 mask = CFG_Q_MASK | (bit << 16);
231 value = bit | (q_id << CFG_Q_SHIFT);
232 ql_write32(qdev, CFG, (mask | value));
235 * Wait for the bit to clear after signaling hw.
237 status = ql_wait_cfg(qdev, bit);
239 pci_unmap_single(qdev->pdev, map, size, direction);
243 /* Get a specific MAC address from the CAM. Used for debug and reg dump. */
244 int ql_get_mac_addr_reg(struct ql_adapter *qdev, u32 type, u16 index,
251 case MAC_ADDR_TYPE_MULTI_MAC:
252 case MAC_ADDR_TYPE_CAM_MAC:
255 ql_wait_reg_rdy(qdev,
256 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
259 ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
260 (index << MAC_ADDR_IDX_SHIFT) | /* index */
261 MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
263 ql_wait_reg_rdy(qdev,
264 MAC_ADDR_IDX, MAC_ADDR_MR, 0);
267 *value++ = ql_read32(qdev, MAC_ADDR_DATA);
269 ql_wait_reg_rdy(qdev,
270 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
273 ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
274 (index << MAC_ADDR_IDX_SHIFT) | /* index */
275 MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
277 ql_wait_reg_rdy(qdev,
278 MAC_ADDR_IDX, MAC_ADDR_MR, 0);
281 *value++ = ql_read32(qdev, MAC_ADDR_DATA);
282 if (type == MAC_ADDR_TYPE_CAM_MAC) {
284 ql_wait_reg_rdy(qdev,
285 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
288 ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
289 (index << MAC_ADDR_IDX_SHIFT) | /* index */
290 MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
292 ql_wait_reg_rdy(qdev, MAC_ADDR_IDX,
296 *value++ = ql_read32(qdev, MAC_ADDR_DATA);
300 case MAC_ADDR_TYPE_VLAN:
301 case MAC_ADDR_TYPE_MULTI_FLTR:
303 QPRINTK(qdev, IFUP, CRIT,
304 "Address type %d not yet supported.\n", type);
311 /* Set up a MAC, multicast or VLAN address for the
312 * inbound frame matching.
314 static int ql_set_mac_addr_reg(struct ql_adapter *qdev, u8 *addr, u32 type,
321 case MAC_ADDR_TYPE_MULTI_MAC:
322 case MAC_ADDR_TYPE_CAM_MAC:
325 u32 upper = (addr[0] << 8) | addr[1];
327 (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) |
330 QPRINTK(qdev, IFUP, INFO,
331 "Adding %s address %pM"
332 " at index %d in the CAM.\n",
334 MAC_ADDR_TYPE_MULTI_MAC) ? "MULTICAST" :
335 "UNICAST"), addr, index);
338 ql_wait_reg_rdy(qdev,
339 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
342 ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
343 (index << MAC_ADDR_IDX_SHIFT) | /* index */
345 ql_write32(qdev, MAC_ADDR_DATA, lower);
347 ql_wait_reg_rdy(qdev,
348 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
351 ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
352 (index << MAC_ADDR_IDX_SHIFT) | /* index */
354 ql_write32(qdev, MAC_ADDR_DATA, upper);
356 ql_wait_reg_rdy(qdev,
357 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
360 ql_write32(qdev, MAC_ADDR_IDX, (offset) | /* offset */
361 (index << MAC_ADDR_IDX_SHIFT) | /* index */
363 /* This field should also include the queue id
364 and possibly the function id. Right now we hardcode
365 the route field to NIC core.
367 if (type == MAC_ADDR_TYPE_CAM_MAC) {
368 cam_output = (CAM_OUT_ROUTE_NIC |
370 func << CAM_OUT_FUNC_SHIFT) |
372 rss_ring_first_cq_id <<
373 CAM_OUT_CQ_ID_SHIFT));
375 cam_output |= CAM_OUT_RV;
376 /* route to NIC core */
377 ql_write32(qdev, MAC_ADDR_DATA, cam_output);
381 case MAC_ADDR_TYPE_VLAN:
383 u32 enable_bit = *((u32 *) &addr[0]);
384 /* For VLAN, the addr actually holds a bit that
385 * either enables or disables the vlan id we are
386 * addressing. It's either MAC_ADDR_E on or off.
387 * That's bit-27 we're talking about.
389 QPRINTK(qdev, IFUP, INFO, "%s VLAN ID %d %s the CAM.\n",
390 (enable_bit ? "Adding" : "Removing"),
391 index, (enable_bit ? "to" : "from"));
394 ql_wait_reg_rdy(qdev,
395 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
398 ql_write32(qdev, MAC_ADDR_IDX, offset | /* offset */
399 (index << MAC_ADDR_IDX_SHIFT) | /* index */
401 enable_bit); /* enable/disable */
404 case MAC_ADDR_TYPE_MULTI_FLTR:
406 QPRINTK(qdev, IFUP, CRIT,
407 "Address type %d not yet supported.\n", type);
414 /* Get a specific frame routing value from the CAM.
415 * Used for debug and reg dump.
417 int ql_get_routing_reg(struct ql_adapter *qdev, u32 index, u32 *value)
421 status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MW, 0);
425 ql_write32(qdev, RT_IDX,
426 RT_IDX_TYPE_NICQ | RT_IDX_RS | (index << RT_IDX_IDX_SHIFT));
427 status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MR, 0);
430 *value = ql_read32(qdev, RT_DATA);
435 /* The NIC function for this chip has 16 routing indexes. Each one can be used
436 * to route different frame types to various inbound queues. We send broadcast/
437 * multicast/error frames to the default queue for slow handling,
438 * and CAM hit/RSS frames to the fast handling queues.
440 static int ql_set_routing_reg(struct ql_adapter *qdev, u32 index, u32 mask,
443 int status = -EINVAL; /* Return error if no mask match. */
446 QPRINTK(qdev, IFUP, DEBUG,
447 "%s %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s mask %s the routing reg.\n",
448 (enable ? "Adding" : "Removing"),
449 ((index == RT_IDX_ALL_ERR_SLOT) ? "MAC ERROR/ALL ERROR" : ""),
450 ((index == RT_IDX_IP_CSUM_ERR_SLOT) ? "IP CSUM ERROR" : ""),
452 RT_IDX_TCP_UDP_CSUM_ERR_SLOT) ? "TCP/UDP CSUM ERROR" : ""),
453 ((index == RT_IDX_BCAST_SLOT) ? "BROADCAST" : ""),
454 ((index == RT_IDX_MCAST_MATCH_SLOT) ? "MULTICAST MATCH" : ""),
455 ((index == RT_IDX_ALLMULTI_SLOT) ? "ALL MULTICAST MATCH" : ""),
456 ((index == RT_IDX_UNUSED6_SLOT) ? "UNUSED6" : ""),
457 ((index == RT_IDX_UNUSED7_SLOT) ? "UNUSED7" : ""),
458 ((index == RT_IDX_RSS_MATCH_SLOT) ? "RSS ALL/IPV4 MATCH" : ""),
459 ((index == RT_IDX_RSS_IPV6_SLOT) ? "RSS IPV6" : ""),
460 ((index == RT_IDX_RSS_TCP4_SLOT) ? "RSS TCP4" : ""),
461 ((index == RT_IDX_RSS_TCP6_SLOT) ? "RSS TCP6" : ""),
462 ((index == RT_IDX_CAM_HIT_SLOT) ? "CAM HIT" : ""),
463 ((index == RT_IDX_UNUSED013) ? "UNUSED13" : ""),
464 ((index == RT_IDX_UNUSED014) ? "UNUSED14" : ""),
465 ((index == RT_IDX_PROMISCUOUS_SLOT) ? "PROMISCUOUS" : ""),
466 (enable ? "to" : "from"));
471 value = RT_IDX_DST_CAM_Q | /* dest */
472 RT_IDX_TYPE_NICQ | /* type */
473 (RT_IDX_CAM_HIT_SLOT << RT_IDX_IDX_SHIFT);/* index */
476 case RT_IDX_VALID: /* Promiscuous Mode frames. */
478 value = RT_IDX_DST_DFLT_Q | /* dest */
479 RT_IDX_TYPE_NICQ | /* type */
480 (RT_IDX_PROMISCUOUS_SLOT << RT_IDX_IDX_SHIFT);/* index */
483 case RT_IDX_ERR: /* Pass up MAC,IP,TCP/UDP error frames. */
485 value = RT_IDX_DST_DFLT_Q | /* dest */
486 RT_IDX_TYPE_NICQ | /* type */
487 (RT_IDX_ALL_ERR_SLOT << RT_IDX_IDX_SHIFT);/* index */
490 case RT_IDX_BCAST: /* Pass up Broadcast frames to default Q. */
492 value = RT_IDX_DST_DFLT_Q | /* dest */
493 RT_IDX_TYPE_NICQ | /* type */
494 (RT_IDX_BCAST_SLOT << RT_IDX_IDX_SHIFT);/* index */
497 case RT_IDX_MCAST: /* Pass up All Multicast frames. */
499 value = RT_IDX_DST_CAM_Q | /* dest */
500 RT_IDX_TYPE_NICQ | /* type */
501 (RT_IDX_ALLMULTI_SLOT << RT_IDX_IDX_SHIFT);/* index */
504 case RT_IDX_MCAST_MATCH: /* Pass up matched Multicast frames. */
506 value = RT_IDX_DST_CAM_Q | /* dest */
507 RT_IDX_TYPE_NICQ | /* type */
508 (RT_IDX_MCAST_MATCH_SLOT << RT_IDX_IDX_SHIFT);/* index */
511 case RT_IDX_RSS_MATCH: /* Pass up matched RSS frames. */
513 value = RT_IDX_DST_RSS | /* dest */
514 RT_IDX_TYPE_NICQ | /* type */
515 (RT_IDX_RSS_MATCH_SLOT << RT_IDX_IDX_SHIFT);/* index */
518 case 0: /* Clear the E-bit on an entry. */
520 value = RT_IDX_DST_DFLT_Q | /* dest */
521 RT_IDX_TYPE_NICQ | /* type */
522 (index << RT_IDX_IDX_SHIFT);/* index */
526 QPRINTK(qdev, IFUP, ERR, "Mask type %d not yet supported.\n",
533 status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MW, 0);
536 value |= (enable ? RT_IDX_E : 0);
537 ql_write32(qdev, RT_IDX, value);
538 ql_write32(qdev, RT_DATA, enable ? mask : 0);
544 static void ql_enable_interrupts(struct ql_adapter *qdev)
546 ql_write32(qdev, INTR_EN, (INTR_EN_EI << 16) | INTR_EN_EI);
549 static void ql_disable_interrupts(struct ql_adapter *qdev)
551 ql_write32(qdev, INTR_EN, (INTR_EN_EI << 16));
554 /* If we're running with multiple MSI-X vectors then we enable on the fly.
555 * Otherwise, we may have multiple outstanding workers and don't want to
556 * enable until the last one finishes. In this case, the irq_cnt gets
557 * incremented everytime we queue a worker and decremented everytime
558 * a worker finishes. Once it hits zero we enable the interrupt.
560 u32 ql_enable_completion_interrupt(struct ql_adapter *qdev, u32 intr)
563 unsigned long hw_flags = 0;
564 struct intr_context *ctx = qdev->intr_context + intr;
566 if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags) && intr)) {
567 /* Always enable if we're MSIX multi interrupts and
568 * it's not the default (zeroeth) interrupt.
570 ql_write32(qdev, INTR_EN,
572 var = ql_read32(qdev, STS);
576 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
577 if (atomic_dec_and_test(&ctx->irq_cnt)) {
578 ql_write32(qdev, INTR_EN,
580 var = ql_read32(qdev, STS);
582 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
586 static u32 ql_disable_completion_interrupt(struct ql_adapter *qdev, u32 intr)
589 unsigned long hw_flags;
590 struct intr_context *ctx;
592 /* HW disables for us if we're MSIX multi interrupts and
593 * it's not the default (zeroeth) interrupt.
595 if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags) && intr))
598 ctx = qdev->intr_context + intr;
599 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
600 if (!atomic_read(&ctx->irq_cnt)) {
601 ql_write32(qdev, INTR_EN,
603 var = ql_read32(qdev, STS);
605 atomic_inc(&ctx->irq_cnt);
606 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
610 static void ql_enable_all_completion_interrupts(struct ql_adapter *qdev)
613 for (i = 0; i < qdev->intr_count; i++) {
614 /* The enable call does a atomic_dec_and_test
615 * and enables only if the result is zero.
616 * So we precharge it here.
618 if (unlikely(!test_bit(QL_MSIX_ENABLED, &qdev->flags) ||
620 atomic_set(&qdev->intr_context[i].irq_cnt, 1);
621 ql_enable_completion_interrupt(qdev, i);
626 static int ql_read_flash_word(struct ql_adapter *qdev, int offset, __le32 *data)
629 /* wait for reg to come ready */
630 status = ql_wait_reg_rdy(qdev,
631 FLASH_ADDR, FLASH_ADDR_RDY, FLASH_ADDR_ERR);
634 /* set up for reg read */
635 ql_write32(qdev, FLASH_ADDR, FLASH_ADDR_R | offset);
636 /* wait for reg to come ready */
637 status = ql_wait_reg_rdy(qdev,
638 FLASH_ADDR, FLASH_ADDR_RDY, FLASH_ADDR_ERR);
641 /* This data is stored on flash as an array of
642 * __le32. Since ql_read32() returns cpu endian
643 * we need to swap it back.
645 *data = cpu_to_le32(ql_read32(qdev, FLASH_DATA));
650 static int ql_get_flash_params(struct ql_adapter *qdev)
654 __le32 *p = (__le32 *)&qdev->flash;
657 /* Second function's parameters follow the first
661 offset = sizeof(qdev->flash) / sizeof(u32);
663 if (ql_sem_spinlock(qdev, SEM_FLASH_MASK))
666 for (i = 0; i < sizeof(qdev->flash) / sizeof(u32); i++, p++) {
667 status = ql_read_flash_word(qdev, i+offset, p);
669 QPRINTK(qdev, IFUP, ERR, "Error reading flash.\n");
675 ql_sem_unlock(qdev, SEM_FLASH_MASK);
679 /* xgmac register are located behind the xgmac_addr and xgmac_data
680 * register pair. Each read/write requires us to wait for the ready
681 * bit before reading/writing the data.
683 static int ql_write_xgmac_reg(struct ql_adapter *qdev, u32 reg, u32 data)
686 /* wait for reg to come ready */
687 status = ql_wait_reg_rdy(qdev,
688 XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
691 /* write the data to the data reg */
692 ql_write32(qdev, XGMAC_DATA, data);
693 /* trigger the write */
694 ql_write32(qdev, XGMAC_ADDR, reg);
698 /* xgmac register are located behind the xgmac_addr and xgmac_data
699 * register pair. Each read/write requires us to wait for the ready
700 * bit before reading/writing the data.
702 int ql_read_xgmac_reg(struct ql_adapter *qdev, u32 reg, u32 *data)
705 /* wait for reg to come ready */
706 status = ql_wait_reg_rdy(qdev,
707 XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
710 /* set up for reg read */
711 ql_write32(qdev, XGMAC_ADDR, reg | XGMAC_ADDR_R);
712 /* wait for reg to come ready */
713 status = ql_wait_reg_rdy(qdev,
714 XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
718 *data = ql_read32(qdev, XGMAC_DATA);
723 /* This is used for reading the 64-bit statistics regs. */
724 int ql_read_xgmac_reg64(struct ql_adapter *qdev, u32 reg, u64 *data)
730 status = ql_read_xgmac_reg(qdev, reg, &lo);
734 status = ql_read_xgmac_reg(qdev, reg + 4, &hi);
738 *data = (u64) lo | ((u64) hi << 32);
744 /* Take the MAC Core out of reset.
745 * Enable statistics counting.
746 * Take the transmitter/receiver out of reset.
747 * This functionality may be done in the MPI firmware at a
750 static int ql_port_initialize(struct ql_adapter *qdev)
755 if (ql_sem_trylock(qdev, qdev->xg_sem_mask)) {
756 /* Another function has the semaphore, so
757 * wait for the port init bit to come ready.
759 QPRINTK(qdev, LINK, INFO,
760 "Another function has the semaphore, so wait for the port init bit to come ready.\n");
761 status = ql_wait_reg_rdy(qdev, STS, qdev->port_init, 0);
763 QPRINTK(qdev, LINK, CRIT,
764 "Port initialize timed out.\n");
769 QPRINTK(qdev, LINK, INFO, "Got xgmac semaphore!.\n");
770 /* Set the core reset. */
771 status = ql_read_xgmac_reg(qdev, GLOBAL_CFG, &data);
774 data |= GLOBAL_CFG_RESET;
775 status = ql_write_xgmac_reg(qdev, GLOBAL_CFG, data);
779 /* Clear the core reset and turn on jumbo for receiver. */
780 data &= ~GLOBAL_CFG_RESET; /* Clear core reset. */
781 data |= GLOBAL_CFG_JUMBO; /* Turn on jumbo. */
782 data |= GLOBAL_CFG_TX_STAT_EN;
783 data |= GLOBAL_CFG_RX_STAT_EN;
784 status = ql_write_xgmac_reg(qdev, GLOBAL_CFG, data);
788 /* Enable transmitter, and clear it's reset. */
789 status = ql_read_xgmac_reg(qdev, TX_CFG, &data);
792 data &= ~TX_CFG_RESET; /* Clear the TX MAC reset. */
793 data |= TX_CFG_EN; /* Enable the transmitter. */
794 status = ql_write_xgmac_reg(qdev, TX_CFG, data);
798 /* Enable receiver and clear it's reset. */
799 status = ql_read_xgmac_reg(qdev, RX_CFG, &data);
802 data &= ~RX_CFG_RESET; /* Clear the RX MAC reset. */
803 data |= RX_CFG_EN; /* Enable the receiver. */
804 status = ql_write_xgmac_reg(qdev, RX_CFG, data);
810 ql_write_xgmac_reg(qdev, MAC_TX_PARAMS, MAC_TX_PARAMS_JUMBO | (0x2580 << 16));
814 ql_write_xgmac_reg(qdev, MAC_RX_PARAMS, 0x2580);
818 /* Signal to the world that the port is enabled. */
819 ql_write32(qdev, STS, ((qdev->port_init << 16) | qdev->port_init));
821 ql_sem_unlock(qdev, qdev->xg_sem_mask);
825 /* Get the next large buffer. */
826 static struct bq_desc *ql_get_curr_lbuf(struct rx_ring *rx_ring)
828 struct bq_desc *lbq_desc = &rx_ring->lbq[rx_ring->lbq_curr_idx];
829 rx_ring->lbq_curr_idx++;
830 if (rx_ring->lbq_curr_idx == rx_ring->lbq_len)
831 rx_ring->lbq_curr_idx = 0;
832 rx_ring->lbq_free_cnt++;
836 /* Get the next small buffer. */
837 static struct bq_desc *ql_get_curr_sbuf(struct rx_ring *rx_ring)
839 struct bq_desc *sbq_desc = &rx_ring->sbq[rx_ring->sbq_curr_idx];
840 rx_ring->sbq_curr_idx++;
841 if (rx_ring->sbq_curr_idx == rx_ring->sbq_len)
842 rx_ring->sbq_curr_idx = 0;
843 rx_ring->sbq_free_cnt++;
847 /* Update an rx ring index. */
848 static void ql_update_cq(struct rx_ring *rx_ring)
850 rx_ring->cnsmr_idx++;
851 rx_ring->curr_entry++;
852 if (unlikely(rx_ring->cnsmr_idx == rx_ring->cq_len)) {
853 rx_ring->cnsmr_idx = 0;
854 rx_ring->curr_entry = rx_ring->cq_base;
858 static void ql_write_cq_idx(struct rx_ring *rx_ring)
860 ql_write_db_reg(rx_ring->cnsmr_idx, rx_ring->cnsmr_idx_db_reg);
863 /* Process (refill) a large buffer queue. */
864 static void ql_update_lbq(struct ql_adapter *qdev, struct rx_ring *rx_ring)
866 u32 clean_idx = rx_ring->lbq_clean_idx;
867 u32 start_idx = clean_idx;
868 struct bq_desc *lbq_desc;
872 while (rx_ring->lbq_free_cnt > 16) {
873 for (i = 0; i < 16; i++) {
874 QPRINTK(qdev, RX_STATUS, DEBUG,
875 "lbq: try cleaning clean_idx = %d.\n",
877 lbq_desc = &rx_ring->lbq[clean_idx];
878 if (lbq_desc->p.lbq_page == NULL) {
879 QPRINTK(qdev, RX_STATUS, DEBUG,
880 "lbq: getting new page for index %d.\n",
882 lbq_desc->p.lbq_page = alloc_page(GFP_ATOMIC);
883 if (lbq_desc->p.lbq_page == NULL) {
884 rx_ring->lbq_clean_idx = clean_idx;
885 QPRINTK(qdev, RX_STATUS, ERR,
886 "Couldn't get a page.\n");
889 map = pci_map_page(qdev->pdev,
890 lbq_desc->p.lbq_page,
893 if (pci_dma_mapping_error(qdev->pdev, map)) {
894 rx_ring->lbq_clean_idx = clean_idx;
895 put_page(lbq_desc->p.lbq_page);
896 lbq_desc->p.lbq_page = NULL;
897 QPRINTK(qdev, RX_STATUS, ERR,
898 "PCI mapping failed.\n");
901 pci_unmap_addr_set(lbq_desc, mapaddr, map);
902 pci_unmap_len_set(lbq_desc, maplen, PAGE_SIZE);
903 *lbq_desc->addr = cpu_to_le64(map);
906 if (clean_idx == rx_ring->lbq_len)
910 rx_ring->lbq_clean_idx = clean_idx;
911 rx_ring->lbq_prod_idx += 16;
912 if (rx_ring->lbq_prod_idx == rx_ring->lbq_len)
913 rx_ring->lbq_prod_idx = 0;
914 rx_ring->lbq_free_cnt -= 16;
917 if (start_idx != clean_idx) {
918 QPRINTK(qdev, RX_STATUS, DEBUG,
919 "lbq: updating prod idx = %d.\n",
920 rx_ring->lbq_prod_idx);
921 ql_write_db_reg(rx_ring->lbq_prod_idx,
922 rx_ring->lbq_prod_idx_db_reg);
926 /* Process (refill) a small buffer queue. */
927 static void ql_update_sbq(struct ql_adapter *qdev, struct rx_ring *rx_ring)
929 u32 clean_idx = rx_ring->sbq_clean_idx;
930 u32 start_idx = clean_idx;
931 struct bq_desc *sbq_desc;
935 while (rx_ring->sbq_free_cnt > 16) {
936 for (i = 0; i < 16; i++) {
937 sbq_desc = &rx_ring->sbq[clean_idx];
938 QPRINTK(qdev, RX_STATUS, DEBUG,
939 "sbq: try cleaning clean_idx = %d.\n",
941 if (sbq_desc->p.skb == NULL) {
942 QPRINTK(qdev, RX_STATUS, DEBUG,
943 "sbq: getting new skb for index %d.\n",
946 netdev_alloc_skb(qdev->ndev,
947 rx_ring->sbq_buf_size);
948 if (sbq_desc->p.skb == NULL) {
949 QPRINTK(qdev, PROBE, ERR,
950 "Couldn't get an skb.\n");
951 rx_ring->sbq_clean_idx = clean_idx;
954 skb_reserve(sbq_desc->p.skb, QLGE_SB_PAD);
955 map = pci_map_single(qdev->pdev,
956 sbq_desc->p.skb->data,
957 rx_ring->sbq_buf_size /
958 2, PCI_DMA_FROMDEVICE);
959 if (pci_dma_mapping_error(qdev->pdev, map)) {
960 QPRINTK(qdev, IFUP, ERR, "PCI mapping failed.\n");
961 rx_ring->sbq_clean_idx = clean_idx;
962 dev_kfree_skb_any(sbq_desc->p.skb);
963 sbq_desc->p.skb = NULL;
966 pci_unmap_addr_set(sbq_desc, mapaddr, map);
967 pci_unmap_len_set(sbq_desc, maplen,
968 rx_ring->sbq_buf_size / 2);
969 *sbq_desc->addr = cpu_to_le64(map);
973 if (clean_idx == rx_ring->sbq_len)
976 rx_ring->sbq_clean_idx = clean_idx;
977 rx_ring->sbq_prod_idx += 16;
978 if (rx_ring->sbq_prod_idx == rx_ring->sbq_len)
979 rx_ring->sbq_prod_idx = 0;
980 rx_ring->sbq_free_cnt -= 16;
983 if (start_idx != clean_idx) {
984 QPRINTK(qdev, RX_STATUS, DEBUG,
985 "sbq: updating prod idx = %d.\n",
986 rx_ring->sbq_prod_idx);
987 ql_write_db_reg(rx_ring->sbq_prod_idx,
988 rx_ring->sbq_prod_idx_db_reg);
992 static void ql_update_buffer_queues(struct ql_adapter *qdev,
993 struct rx_ring *rx_ring)
995 ql_update_sbq(qdev, rx_ring);
996 ql_update_lbq(qdev, rx_ring);
999 /* Unmaps tx buffers. Can be called from send() if a pci mapping
1000 * fails at some stage, or from the interrupt when a tx completes.
1002 static void ql_unmap_send(struct ql_adapter *qdev,
1003 struct tx_ring_desc *tx_ring_desc, int mapped)
1006 for (i = 0; i < mapped; i++) {
1007 if (i == 0 || (i == 7 && mapped > 7)) {
1009 * Unmap the skb->data area, or the
1010 * external sglist (AKA the Outbound
1011 * Address List (OAL)).
1012 * If its the zeroeth element, then it's
1013 * the skb->data area. If it's the 7th
1014 * element and there is more than 6 frags,
1018 QPRINTK(qdev, TX_DONE, DEBUG,
1019 "unmapping OAL area.\n");
1021 pci_unmap_single(qdev->pdev,
1022 pci_unmap_addr(&tx_ring_desc->map[i],
1024 pci_unmap_len(&tx_ring_desc->map[i],
1028 QPRINTK(qdev, TX_DONE, DEBUG, "unmapping frag %d.\n",
1030 pci_unmap_page(qdev->pdev,
1031 pci_unmap_addr(&tx_ring_desc->map[i],
1033 pci_unmap_len(&tx_ring_desc->map[i],
1034 maplen), PCI_DMA_TODEVICE);
1040 /* Map the buffers for this transmit. This will return
1041 * NETDEV_TX_BUSY or NETDEV_TX_OK based on success.
1043 static int ql_map_send(struct ql_adapter *qdev,
1044 struct ob_mac_iocb_req *mac_iocb_ptr,
1045 struct sk_buff *skb, struct tx_ring_desc *tx_ring_desc)
1047 int len = skb_headlen(skb);
1049 int frag_idx, err, map_idx = 0;
1050 struct tx_buf_desc *tbd = mac_iocb_ptr->tbd;
1051 int frag_cnt = skb_shinfo(skb)->nr_frags;
1054 QPRINTK(qdev, TX_QUEUED, DEBUG, "frag_cnt = %d.\n", frag_cnt);
1057 * Map the skb buffer first.
1059 map = pci_map_single(qdev->pdev, skb->data, len, PCI_DMA_TODEVICE);
1061 err = pci_dma_mapping_error(qdev->pdev, map);
1063 QPRINTK(qdev, TX_QUEUED, ERR,
1064 "PCI mapping failed with error: %d\n", err);
1066 return NETDEV_TX_BUSY;
1069 tbd->len = cpu_to_le32(len);
1070 tbd->addr = cpu_to_le64(map);
1071 pci_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr, map);
1072 pci_unmap_len_set(&tx_ring_desc->map[map_idx], maplen, len);
1076 * This loop fills the remainder of the 8 address descriptors
1077 * in the IOCB. If there are more than 7 fragments, then the
1078 * eighth address desc will point to an external list (OAL).
1079 * When this happens, the remainder of the frags will be stored
1082 for (frag_idx = 0; frag_idx < frag_cnt; frag_idx++, map_idx++) {
1083 skb_frag_t *frag = &skb_shinfo(skb)->frags[frag_idx];
1085 if (frag_idx == 6 && frag_cnt > 7) {
1086 /* Let's tack on an sglist.
1087 * Our control block will now
1089 * iocb->seg[0] = skb->data
1090 * iocb->seg[1] = frag[0]
1091 * iocb->seg[2] = frag[1]
1092 * iocb->seg[3] = frag[2]
1093 * iocb->seg[4] = frag[3]
1094 * iocb->seg[5] = frag[4]
1095 * iocb->seg[6] = frag[5]
1096 * iocb->seg[7] = ptr to OAL (external sglist)
1097 * oal->seg[0] = frag[6]
1098 * oal->seg[1] = frag[7]
1099 * oal->seg[2] = frag[8]
1100 * oal->seg[3] = frag[9]
1101 * oal->seg[4] = frag[10]
1104 /* Tack on the OAL in the eighth segment of IOCB. */
1105 map = pci_map_single(qdev->pdev, &tx_ring_desc->oal,
1108 err = pci_dma_mapping_error(qdev->pdev, map);
1110 QPRINTK(qdev, TX_QUEUED, ERR,
1111 "PCI mapping outbound address list with error: %d\n",
1116 tbd->addr = cpu_to_le64(map);
1118 * The length is the number of fragments
1119 * that remain to be mapped times the length
1120 * of our sglist (OAL).
1123 cpu_to_le32((sizeof(struct tx_buf_desc) *
1124 (frag_cnt - frag_idx)) | TX_DESC_C);
1125 pci_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr,
1127 pci_unmap_len_set(&tx_ring_desc->map[map_idx], maplen,
1128 sizeof(struct oal));
1129 tbd = (struct tx_buf_desc *)&tx_ring_desc->oal;
1134 pci_map_page(qdev->pdev, frag->page,
1135 frag->page_offset, frag->size,
1138 err = pci_dma_mapping_error(qdev->pdev, map);
1140 QPRINTK(qdev, TX_QUEUED, ERR,
1141 "PCI mapping frags failed with error: %d.\n",
1146 tbd->addr = cpu_to_le64(map);
1147 tbd->len = cpu_to_le32(frag->size);
1148 pci_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr, map);
1149 pci_unmap_len_set(&tx_ring_desc->map[map_idx], maplen,
1153 /* Save the number of segments we've mapped. */
1154 tx_ring_desc->map_cnt = map_idx;
1155 /* Terminate the last segment. */
1156 tbd->len = cpu_to_le32(le32_to_cpu(tbd->len) | TX_DESC_E);
1157 return NETDEV_TX_OK;
1161 * If the first frag mapping failed, then i will be zero.
1162 * This causes the unmap of the skb->data area. Otherwise
1163 * we pass in the number of frags that mapped successfully
1164 * so they can be umapped.
1166 ql_unmap_send(qdev, tx_ring_desc, map_idx);
1167 return NETDEV_TX_BUSY;
1170 static void ql_realign_skb(struct sk_buff *skb, int len)
1172 void *temp_addr = skb->data;
1174 /* Undo the skb_reserve(skb,32) we did before
1175 * giving to hardware, and realign data on
1176 * a 2-byte boundary.
1178 skb->data -= QLGE_SB_PAD - NET_IP_ALIGN;
1179 skb->tail -= QLGE_SB_PAD - NET_IP_ALIGN;
1180 skb_copy_to_linear_data(skb, temp_addr,
1185 * This function builds an skb for the given inbound
1186 * completion. It will be rewritten for readability in the near
1187 * future, but for not it works well.
1189 static struct sk_buff *ql_build_rx_skb(struct ql_adapter *qdev,
1190 struct rx_ring *rx_ring,
1191 struct ib_mac_iocb_rsp *ib_mac_rsp)
1193 struct bq_desc *lbq_desc;
1194 struct bq_desc *sbq_desc;
1195 struct sk_buff *skb = NULL;
1196 u32 length = le32_to_cpu(ib_mac_rsp->data_len);
1197 u32 hdr_len = le32_to_cpu(ib_mac_rsp->hdr_len);
1200 * Handle the header buffer if present.
1202 if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HV &&
1203 ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1204 QPRINTK(qdev, RX_STATUS, DEBUG, "Header of %d bytes in small buffer.\n", hdr_len);
1206 * Headers fit nicely into a small buffer.
1208 sbq_desc = ql_get_curr_sbuf(rx_ring);
1209 pci_unmap_single(qdev->pdev,
1210 pci_unmap_addr(sbq_desc, mapaddr),
1211 pci_unmap_len(sbq_desc, maplen),
1212 PCI_DMA_FROMDEVICE);
1213 skb = sbq_desc->p.skb;
1214 ql_realign_skb(skb, hdr_len);
1215 skb_put(skb, hdr_len);
1216 sbq_desc->p.skb = NULL;
1220 * Handle the data buffer(s).
1222 if (unlikely(!length)) { /* Is there data too? */
1223 QPRINTK(qdev, RX_STATUS, DEBUG,
1224 "No Data buffer in this packet.\n");
1228 if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DS) {
1229 if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1230 QPRINTK(qdev, RX_STATUS, DEBUG,
1231 "Headers in small, data of %d bytes in small, combine them.\n", length);
1233 * Data is less than small buffer size so it's
1234 * stuffed in a small buffer.
1235 * For this case we append the data
1236 * from the "data" small buffer to the "header" small
1239 sbq_desc = ql_get_curr_sbuf(rx_ring);
1240 pci_dma_sync_single_for_cpu(qdev->pdev,
1242 (sbq_desc, mapaddr),
1245 PCI_DMA_FROMDEVICE);
1246 memcpy(skb_put(skb, length),
1247 sbq_desc->p.skb->data, length);
1248 pci_dma_sync_single_for_device(qdev->pdev,
1255 PCI_DMA_FROMDEVICE);
1257 QPRINTK(qdev, RX_STATUS, DEBUG,
1258 "%d bytes in a single small buffer.\n", length);
1259 sbq_desc = ql_get_curr_sbuf(rx_ring);
1260 skb = sbq_desc->p.skb;
1261 ql_realign_skb(skb, length);
1262 skb_put(skb, length);
1263 pci_unmap_single(qdev->pdev,
1264 pci_unmap_addr(sbq_desc,
1266 pci_unmap_len(sbq_desc,
1268 PCI_DMA_FROMDEVICE);
1269 sbq_desc->p.skb = NULL;
1271 } else if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DL) {
1272 if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1273 QPRINTK(qdev, RX_STATUS, DEBUG,
1274 "Header in small, %d bytes in large. Chain large to small!\n", length);
1276 * The data is in a single large buffer. We
1277 * chain it to the header buffer's skb and let
1280 lbq_desc = ql_get_curr_lbuf(rx_ring);
1281 pci_unmap_page(qdev->pdev,
1282 pci_unmap_addr(lbq_desc,
1284 pci_unmap_len(lbq_desc, maplen),
1285 PCI_DMA_FROMDEVICE);
1286 QPRINTK(qdev, RX_STATUS, DEBUG,
1287 "Chaining page to skb.\n");
1288 skb_fill_page_desc(skb, 0, lbq_desc->p.lbq_page,
1291 skb->data_len += length;
1292 skb->truesize += length;
1293 lbq_desc->p.lbq_page = NULL;
1296 * The headers and data are in a single large buffer. We
1297 * copy it to a new skb and let it go. This can happen with
1298 * jumbo mtu on a non-TCP/UDP frame.
1300 lbq_desc = ql_get_curr_lbuf(rx_ring);
1301 skb = netdev_alloc_skb(qdev->ndev, length);
1303 QPRINTK(qdev, PROBE, DEBUG,
1304 "No skb available, drop the packet.\n");
1307 pci_unmap_page(qdev->pdev,
1308 pci_unmap_addr(lbq_desc,
1310 pci_unmap_len(lbq_desc, maplen),
1311 PCI_DMA_FROMDEVICE);
1312 skb_reserve(skb, NET_IP_ALIGN);
1313 QPRINTK(qdev, RX_STATUS, DEBUG,
1314 "%d bytes of headers and data in large. Chain page to new skb and pull tail.\n", length);
1315 skb_fill_page_desc(skb, 0, lbq_desc->p.lbq_page,
1318 skb->data_len += length;
1319 skb->truesize += length;
1321 lbq_desc->p.lbq_page = NULL;
1322 __pskb_pull_tail(skb,
1323 (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) ?
1324 VLAN_ETH_HLEN : ETH_HLEN);
1328 * The data is in a chain of large buffers
1329 * pointed to by a small buffer. We loop
1330 * thru and chain them to the our small header
1332 * frags: There are 18 max frags and our small
1333 * buffer will hold 32 of them. The thing is,
1334 * we'll use 3 max for our 9000 byte jumbo
1335 * frames. If the MTU goes up we could
1336 * eventually be in trouble.
1338 int size, offset, i = 0;
1339 __le64 *bq, bq_array[8];
1340 sbq_desc = ql_get_curr_sbuf(rx_ring);
1341 pci_unmap_single(qdev->pdev,
1342 pci_unmap_addr(sbq_desc, mapaddr),
1343 pci_unmap_len(sbq_desc, maplen),
1344 PCI_DMA_FROMDEVICE);
1345 if (!(ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS)) {
1347 * This is an non TCP/UDP IP frame, so
1348 * the headers aren't split into a small
1349 * buffer. We have to use the small buffer
1350 * that contains our sg list as our skb to
1351 * send upstairs. Copy the sg list here to
1352 * a local buffer and use it to find the
1355 QPRINTK(qdev, RX_STATUS, DEBUG,
1356 "%d bytes of headers & data in chain of large.\n", length);
1357 skb = sbq_desc->p.skb;
1359 memcpy(bq, skb->data, sizeof(bq_array));
1360 sbq_desc->p.skb = NULL;
1361 skb_reserve(skb, NET_IP_ALIGN);
1363 QPRINTK(qdev, RX_STATUS, DEBUG,
1364 "Headers in small, %d bytes of data in chain of large.\n", length);
1365 bq = (__le64 *)sbq_desc->p.skb->data;
1367 while (length > 0) {
1368 lbq_desc = ql_get_curr_lbuf(rx_ring);
1369 pci_unmap_page(qdev->pdev,
1370 pci_unmap_addr(lbq_desc,
1372 pci_unmap_len(lbq_desc,
1374 PCI_DMA_FROMDEVICE);
1375 size = (length < PAGE_SIZE) ? length : PAGE_SIZE;
1378 QPRINTK(qdev, RX_STATUS, DEBUG,
1379 "Adding page %d to skb for %d bytes.\n",
1381 skb_fill_page_desc(skb, i, lbq_desc->p.lbq_page,
1384 skb->data_len += size;
1385 skb->truesize += size;
1387 lbq_desc->p.lbq_page = NULL;
1391 __pskb_pull_tail(skb, (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) ?
1392 VLAN_ETH_HLEN : ETH_HLEN);
1397 /* Process an inbound completion from an rx ring. */
1398 static void ql_process_mac_rx_intr(struct ql_adapter *qdev,
1399 struct rx_ring *rx_ring,
1400 struct ib_mac_iocb_rsp *ib_mac_rsp)
1402 struct net_device *ndev = qdev->ndev;
1403 struct sk_buff *skb = NULL;
1405 QL_DUMP_IB_MAC_RSP(ib_mac_rsp);
1407 skb = ql_build_rx_skb(qdev, rx_ring, ib_mac_rsp);
1408 if (unlikely(!skb)) {
1409 QPRINTK(qdev, RX_STATUS, DEBUG,
1410 "No skb available, drop packet.\n");
1414 prefetch(skb->data);
1416 if (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) {
1417 QPRINTK(qdev, RX_STATUS, DEBUG, "%s%s%s Multicast.\n",
1418 (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1419 IB_MAC_IOCB_RSP_M_HASH ? "Hash" : "",
1420 (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1421 IB_MAC_IOCB_RSP_M_REG ? "Registered" : "",
1422 (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1423 IB_MAC_IOCB_RSP_M_PROM ? "Promiscuous" : "");
1425 if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_P) {
1426 QPRINTK(qdev, RX_STATUS, DEBUG, "Promiscuous Packet.\n");
1428 if (ib_mac_rsp->flags1 & (IB_MAC_IOCB_RSP_IE | IB_MAC_IOCB_RSP_TE)) {
1429 QPRINTK(qdev, RX_STATUS, ERR,
1430 "Bad checksum for this %s packet.\n",
1432 flags2 & IB_MAC_IOCB_RSP_T) ? "TCP" : "UDP"));
1433 skb->ip_summed = CHECKSUM_NONE;
1434 } else if (qdev->rx_csum &&
1435 ((ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_T) ||
1436 ((ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_U) &&
1437 !(ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_NU)))) {
1438 QPRINTK(qdev, RX_STATUS, DEBUG, "RX checksum done!\n");
1439 skb->ip_summed = CHECKSUM_UNNECESSARY;
1441 qdev->stats.rx_packets++;
1442 qdev->stats.rx_bytes += skb->len;
1443 skb->protocol = eth_type_trans(skb, ndev);
1444 skb_record_rx_queue(skb, rx_ring - &qdev->rx_ring[0]);
1445 if (qdev->vlgrp && (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V)) {
1446 QPRINTK(qdev, RX_STATUS, DEBUG,
1447 "Passing a VLAN packet upstream.\n");
1448 vlan_hwaccel_receive_skb(skb, qdev->vlgrp,
1449 le16_to_cpu(ib_mac_rsp->vlan_id));
1451 QPRINTK(qdev, RX_STATUS, DEBUG,
1452 "Passing a normal packet upstream.\n");
1453 netif_receive_skb(skb);
1457 /* Process an outbound completion from an rx ring. */
1458 static void ql_process_mac_tx_intr(struct ql_adapter *qdev,
1459 struct ob_mac_iocb_rsp *mac_rsp)
1461 struct tx_ring *tx_ring;
1462 struct tx_ring_desc *tx_ring_desc;
1464 QL_DUMP_OB_MAC_RSP(mac_rsp);
1465 tx_ring = &qdev->tx_ring[mac_rsp->txq_idx];
1466 tx_ring_desc = &tx_ring->q[mac_rsp->tid];
1467 ql_unmap_send(qdev, tx_ring_desc, tx_ring_desc->map_cnt);
1468 qdev->stats.tx_bytes += tx_ring_desc->map_cnt;
1469 qdev->stats.tx_packets++;
1470 dev_kfree_skb(tx_ring_desc->skb);
1471 tx_ring_desc->skb = NULL;
1473 if (unlikely(mac_rsp->flags1 & (OB_MAC_IOCB_RSP_E |
1476 OB_MAC_IOCB_RSP_P | OB_MAC_IOCB_RSP_B))) {
1477 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_E) {
1478 QPRINTK(qdev, TX_DONE, WARNING,
1479 "Total descriptor length did not match transfer length.\n");
1481 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_S) {
1482 QPRINTK(qdev, TX_DONE, WARNING,
1483 "Frame too short to be legal, not sent.\n");
1485 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_L) {
1486 QPRINTK(qdev, TX_DONE, WARNING,
1487 "Frame too long, but sent anyway.\n");
1489 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_B) {
1490 QPRINTK(qdev, TX_DONE, WARNING,
1491 "PCI backplane error. Frame not sent.\n");
1494 atomic_inc(&tx_ring->tx_count);
1497 /* Fire up a handler to reset the MPI processor. */
1498 void ql_queue_fw_error(struct ql_adapter *qdev)
1500 netif_stop_queue(qdev->ndev);
1501 netif_carrier_off(qdev->ndev);
1502 queue_delayed_work(qdev->workqueue, &qdev->mpi_reset_work, 0);
1505 void ql_queue_asic_error(struct ql_adapter *qdev)
1507 netif_stop_queue(qdev->ndev);
1508 netif_carrier_off(qdev->ndev);
1509 ql_disable_interrupts(qdev);
1510 /* Clear adapter up bit to signal the recovery
1511 * process that it shouldn't kill the reset worker
1514 clear_bit(QL_ADAPTER_UP, &qdev->flags);
1515 queue_delayed_work(qdev->workqueue, &qdev->asic_reset_work, 0);
1518 static void ql_process_chip_ae_intr(struct ql_adapter *qdev,
1519 struct ib_ae_iocb_rsp *ib_ae_rsp)
1521 switch (ib_ae_rsp->event) {
1522 case MGMT_ERR_EVENT:
1523 QPRINTK(qdev, RX_ERR, ERR,
1524 "Management Processor Fatal Error.\n");
1525 ql_queue_fw_error(qdev);
1528 case CAM_LOOKUP_ERR_EVENT:
1529 QPRINTK(qdev, LINK, ERR,
1530 "Multiple CAM hits lookup occurred.\n");
1531 QPRINTK(qdev, DRV, ERR, "This event shouldn't occur.\n");
1532 ql_queue_asic_error(qdev);
1535 case SOFT_ECC_ERROR_EVENT:
1536 QPRINTK(qdev, RX_ERR, ERR, "Soft ECC error detected.\n");
1537 ql_queue_asic_error(qdev);
1540 case PCI_ERR_ANON_BUF_RD:
1541 QPRINTK(qdev, RX_ERR, ERR,
1542 "PCI error occurred when reading anonymous buffers from rx_ring %d.\n",
1544 ql_queue_asic_error(qdev);
1548 QPRINTK(qdev, DRV, ERR, "Unexpected event %d.\n",
1550 ql_queue_asic_error(qdev);
1555 static int ql_clean_outbound_rx_ring(struct rx_ring *rx_ring)
1557 struct ql_adapter *qdev = rx_ring->qdev;
1558 u32 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1559 struct ob_mac_iocb_rsp *net_rsp = NULL;
1562 /* While there are entries in the completion queue. */
1563 while (prod != rx_ring->cnsmr_idx) {
1565 QPRINTK(qdev, RX_STATUS, DEBUG,
1566 "cq_id = %d, prod = %d, cnsmr = %d.\n.", rx_ring->cq_id,
1567 prod, rx_ring->cnsmr_idx);
1569 net_rsp = (struct ob_mac_iocb_rsp *)rx_ring->curr_entry;
1571 switch (net_rsp->opcode) {
1573 case OPCODE_OB_MAC_TSO_IOCB:
1574 case OPCODE_OB_MAC_IOCB:
1575 ql_process_mac_tx_intr(qdev, net_rsp);
1578 QPRINTK(qdev, RX_STATUS, DEBUG,
1579 "Hit default case, not handled! dropping the packet, opcode = %x.\n",
1583 ql_update_cq(rx_ring);
1584 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1586 ql_write_cq_idx(rx_ring);
1587 if (netif_queue_stopped(qdev->ndev) && net_rsp != NULL) {
1588 struct tx_ring *tx_ring = &qdev->tx_ring[net_rsp->txq_idx];
1589 if (atomic_read(&tx_ring->queue_stopped) &&
1590 (atomic_read(&tx_ring->tx_count) > (tx_ring->wq_len / 4)))
1592 * The queue got stopped because the tx_ring was full.
1593 * Wake it up, because it's now at least 25% empty.
1595 netif_wake_queue(qdev->ndev);
1601 static int ql_clean_inbound_rx_ring(struct rx_ring *rx_ring, int budget)
1603 struct ql_adapter *qdev = rx_ring->qdev;
1604 u32 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1605 struct ql_net_rsp_iocb *net_rsp;
1608 /* While there are entries in the completion queue. */
1609 while (prod != rx_ring->cnsmr_idx) {
1611 QPRINTK(qdev, RX_STATUS, DEBUG,
1612 "cq_id = %d, prod = %d, cnsmr = %d.\n.", rx_ring->cq_id,
1613 prod, rx_ring->cnsmr_idx);
1615 net_rsp = rx_ring->curr_entry;
1617 switch (net_rsp->opcode) {
1618 case OPCODE_IB_MAC_IOCB:
1619 ql_process_mac_rx_intr(qdev, rx_ring,
1620 (struct ib_mac_iocb_rsp *)
1624 case OPCODE_IB_AE_IOCB:
1625 ql_process_chip_ae_intr(qdev, (struct ib_ae_iocb_rsp *)
1630 QPRINTK(qdev, RX_STATUS, DEBUG,
1631 "Hit default case, not handled! dropping the packet, opcode = %x.\n",
1636 ql_update_cq(rx_ring);
1637 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1638 if (count == budget)
1641 ql_update_buffer_queues(qdev, rx_ring);
1642 ql_write_cq_idx(rx_ring);
1646 static int ql_napi_poll_msix(struct napi_struct *napi, int budget)
1648 struct rx_ring *rx_ring = container_of(napi, struct rx_ring, napi);
1649 struct ql_adapter *qdev = rx_ring->qdev;
1650 int work_done = ql_clean_inbound_rx_ring(rx_ring, budget);
1652 QPRINTK(qdev, RX_STATUS, DEBUG, "Enter, NAPI POLL cq_id = %d.\n",
1655 if (work_done < budget) {
1656 __napi_complete(napi);
1657 ql_enable_completion_interrupt(qdev, rx_ring->irq);
1662 static void ql_vlan_rx_register(struct net_device *ndev, struct vlan_group *grp)
1664 struct ql_adapter *qdev = netdev_priv(ndev);
1668 QPRINTK(qdev, IFUP, DEBUG, "Turning on VLAN in NIC_RCV_CFG.\n");
1669 ql_write32(qdev, NIC_RCV_CFG, NIC_RCV_CFG_VLAN_MASK |
1670 NIC_RCV_CFG_VLAN_MATCH_AND_NON);
1672 QPRINTK(qdev, IFUP, DEBUG,
1673 "Turning off VLAN in NIC_RCV_CFG.\n");
1674 ql_write32(qdev, NIC_RCV_CFG, NIC_RCV_CFG_VLAN_MASK);
1678 static void ql_vlan_rx_add_vid(struct net_device *ndev, u16 vid)
1680 struct ql_adapter *qdev = netdev_priv(ndev);
1681 u32 enable_bit = MAC_ADDR_E;
1684 status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
1687 spin_lock(&qdev->hw_lock);
1688 if (ql_set_mac_addr_reg
1689 (qdev, (u8 *) &enable_bit, MAC_ADDR_TYPE_VLAN, vid)) {
1690 QPRINTK(qdev, IFUP, ERR, "Failed to init vlan address.\n");
1692 spin_unlock(&qdev->hw_lock);
1693 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
1696 static void ql_vlan_rx_kill_vid(struct net_device *ndev, u16 vid)
1698 struct ql_adapter *qdev = netdev_priv(ndev);
1702 status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
1706 spin_lock(&qdev->hw_lock);
1707 if (ql_set_mac_addr_reg
1708 (qdev, (u8 *) &enable_bit, MAC_ADDR_TYPE_VLAN, vid)) {
1709 QPRINTK(qdev, IFUP, ERR, "Failed to clear vlan address.\n");
1711 spin_unlock(&qdev->hw_lock);
1712 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
1716 /* Worker thread to process a given rx_ring that is dedicated
1717 * to outbound completions.
1719 static void ql_tx_clean(struct work_struct *work)
1721 struct rx_ring *rx_ring =
1722 container_of(work, struct rx_ring, rx_work.work);
1723 ql_clean_outbound_rx_ring(rx_ring);
1724 ql_enable_completion_interrupt(rx_ring->qdev, rx_ring->irq);
1728 /* Worker thread to process a given rx_ring that is dedicated
1729 * to inbound completions.
1731 static void ql_rx_clean(struct work_struct *work)
1733 struct rx_ring *rx_ring =
1734 container_of(work, struct rx_ring, rx_work.work);
1735 ql_clean_inbound_rx_ring(rx_ring, 64);
1736 ql_enable_completion_interrupt(rx_ring->qdev, rx_ring->irq);
1739 /* MSI-X Multiple Vector Interrupt Handler for outbound completions. */
1740 static irqreturn_t qlge_msix_tx_isr(int irq, void *dev_id)
1742 struct rx_ring *rx_ring = dev_id;
1743 queue_delayed_work_on(rx_ring->cpu, rx_ring->qdev->q_workqueue,
1744 &rx_ring->rx_work, 0);
1748 /* MSI-X Multiple Vector Interrupt Handler for inbound completions. */
1749 static irqreturn_t qlge_msix_rx_isr(int irq, void *dev_id)
1751 struct rx_ring *rx_ring = dev_id;
1752 napi_schedule(&rx_ring->napi);
1756 /* This handles a fatal error, MPI activity, and the default
1757 * rx_ring in an MSI-X multiple vector environment.
1758 * In MSI/Legacy environment it also process the rest of
1761 static irqreturn_t qlge_isr(int irq, void *dev_id)
1763 struct rx_ring *rx_ring = dev_id;
1764 struct ql_adapter *qdev = rx_ring->qdev;
1765 struct intr_context *intr_context = &qdev->intr_context[0];
1770 spin_lock(&qdev->hw_lock);
1771 if (atomic_read(&qdev->intr_context[0].irq_cnt)) {
1772 QPRINTK(qdev, INTR, DEBUG, "Shared Interrupt, Not ours!\n");
1773 spin_unlock(&qdev->hw_lock);
1776 spin_unlock(&qdev->hw_lock);
1778 var = ql_disable_completion_interrupt(qdev, intr_context->intr);
1781 * Check for fatal error.
1784 ql_queue_asic_error(qdev);
1785 QPRINTK(qdev, INTR, ERR, "Got fatal error, STS = %x.\n", var);
1786 var = ql_read32(qdev, ERR_STS);
1787 QPRINTK(qdev, INTR, ERR,
1788 "Resetting chip. Error Status Register = 0x%x\n", var);
1793 * Check MPI processor activity.
1797 * We've got an async event or mailbox completion.
1798 * Handle it and clear the source of the interrupt.
1800 QPRINTK(qdev, INTR, ERR, "Got MPI processor interrupt.\n");
1801 ql_disable_completion_interrupt(qdev, intr_context->intr);
1802 queue_delayed_work_on(smp_processor_id(), qdev->workqueue,
1803 &qdev->mpi_work, 0);
1808 * Check the default queue and wake handler if active.
1810 rx_ring = &qdev->rx_ring[0];
1811 if (ql_read_sh_reg(rx_ring->prod_idx_sh_reg) != rx_ring->cnsmr_idx) {
1812 QPRINTK(qdev, INTR, INFO, "Waking handler for rx_ring[0].\n");
1813 ql_disable_completion_interrupt(qdev, intr_context->intr);
1814 queue_delayed_work_on(smp_processor_id(), qdev->q_workqueue,
1815 &rx_ring->rx_work, 0);
1819 if (!test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
1821 * Start the DPC for each active queue.
1823 for (i = 1; i < qdev->rx_ring_count; i++) {
1824 rx_ring = &qdev->rx_ring[i];
1825 if (ql_read_sh_reg(rx_ring->prod_idx_sh_reg) !=
1826 rx_ring->cnsmr_idx) {
1827 QPRINTK(qdev, INTR, INFO,
1828 "Waking handler for rx_ring[%d].\n", i);
1829 ql_disable_completion_interrupt(qdev,
1832 if (i < qdev->rss_ring_first_cq_id)
1833 queue_delayed_work_on(rx_ring->cpu,
1838 napi_schedule(&rx_ring->napi);
1843 ql_enable_completion_interrupt(qdev, intr_context->intr);
1844 return work_done ? IRQ_HANDLED : IRQ_NONE;
1847 static int ql_tso(struct sk_buff *skb, struct ob_mac_tso_iocb_req *mac_iocb_ptr)
1850 if (skb_is_gso(skb)) {
1852 if (skb_header_cloned(skb)) {
1853 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
1858 mac_iocb_ptr->opcode = OPCODE_OB_MAC_TSO_IOCB;
1859 mac_iocb_ptr->flags3 |= OB_MAC_TSO_IOCB_IC;
1860 mac_iocb_ptr->frame_len = cpu_to_le32((u32) skb->len);
1861 mac_iocb_ptr->total_hdrs_len =
1862 cpu_to_le16(skb_transport_offset(skb) + tcp_hdrlen(skb));
1863 mac_iocb_ptr->net_trans_offset =
1864 cpu_to_le16(skb_network_offset(skb) |
1865 skb_transport_offset(skb)
1866 << OB_MAC_TRANSPORT_HDR_SHIFT);
1867 mac_iocb_ptr->mss = cpu_to_le16(skb_shinfo(skb)->gso_size);
1868 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_LSO;
1869 if (likely(skb->protocol == htons(ETH_P_IP))) {
1870 struct iphdr *iph = ip_hdr(skb);
1872 mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP4;
1873 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
1877 } else if (skb->protocol == htons(ETH_P_IPV6)) {
1878 mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP6;
1879 tcp_hdr(skb)->check =
1880 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
1881 &ipv6_hdr(skb)->daddr,
1889 static void ql_hw_csum_setup(struct sk_buff *skb,
1890 struct ob_mac_tso_iocb_req *mac_iocb_ptr)
1893 struct iphdr *iph = ip_hdr(skb);
1895 mac_iocb_ptr->opcode = OPCODE_OB_MAC_TSO_IOCB;
1896 mac_iocb_ptr->frame_len = cpu_to_le32((u32) skb->len);
1897 mac_iocb_ptr->net_trans_offset =
1898 cpu_to_le16(skb_network_offset(skb) |
1899 skb_transport_offset(skb) << OB_MAC_TRANSPORT_HDR_SHIFT);
1901 mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP4;
1902 len = (ntohs(iph->tot_len) - (iph->ihl << 2));
1903 if (likely(iph->protocol == IPPROTO_TCP)) {
1904 check = &(tcp_hdr(skb)->check);
1905 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_TC;
1906 mac_iocb_ptr->total_hdrs_len =
1907 cpu_to_le16(skb_transport_offset(skb) +
1908 (tcp_hdr(skb)->doff << 2));
1910 check = &(udp_hdr(skb)->check);
1911 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_UC;
1912 mac_iocb_ptr->total_hdrs_len =
1913 cpu_to_le16(skb_transport_offset(skb) +
1914 sizeof(struct udphdr));
1916 *check = ~csum_tcpudp_magic(iph->saddr,
1917 iph->daddr, len, iph->protocol, 0);
1920 static int qlge_send(struct sk_buff *skb, struct net_device *ndev)
1922 struct tx_ring_desc *tx_ring_desc;
1923 struct ob_mac_iocb_req *mac_iocb_ptr;
1924 struct ql_adapter *qdev = netdev_priv(ndev);
1926 struct tx_ring *tx_ring;
1927 u32 tx_ring_idx = (u32) QL_TXQ_IDX(qdev, skb);
1929 tx_ring = &qdev->tx_ring[tx_ring_idx];
1931 if (unlikely(atomic_read(&tx_ring->tx_count) < 2)) {
1932 QPRINTK(qdev, TX_QUEUED, INFO,
1933 "%s: shutting down tx queue %d du to lack of resources.\n",
1934 __func__, tx_ring_idx);
1935 netif_stop_queue(ndev);
1936 atomic_inc(&tx_ring->queue_stopped);
1937 return NETDEV_TX_BUSY;
1939 tx_ring_desc = &tx_ring->q[tx_ring->prod_idx];
1940 mac_iocb_ptr = tx_ring_desc->queue_entry;
1941 memset((void *)mac_iocb_ptr, 0, sizeof(mac_iocb_ptr));
1943 mac_iocb_ptr->opcode = OPCODE_OB_MAC_IOCB;
1944 mac_iocb_ptr->tid = tx_ring_desc->index;
1945 /* We use the upper 32-bits to store the tx queue for this IO.
1946 * When we get the completion we can use it to establish the context.
1948 mac_iocb_ptr->txq_idx = tx_ring_idx;
1949 tx_ring_desc->skb = skb;
1951 mac_iocb_ptr->frame_len = cpu_to_le16((u16) skb->len);
1953 if (qdev->vlgrp && vlan_tx_tag_present(skb)) {
1954 QPRINTK(qdev, TX_QUEUED, DEBUG, "Adding a vlan tag %d.\n",
1955 vlan_tx_tag_get(skb));
1956 mac_iocb_ptr->flags3 |= OB_MAC_IOCB_V;
1957 mac_iocb_ptr->vlan_tci = cpu_to_le16(vlan_tx_tag_get(skb));
1959 tso = ql_tso(skb, (struct ob_mac_tso_iocb_req *)mac_iocb_ptr);
1961 dev_kfree_skb_any(skb);
1962 return NETDEV_TX_OK;
1963 } else if (unlikely(!tso) && (skb->ip_summed == CHECKSUM_PARTIAL)) {
1964 ql_hw_csum_setup(skb,
1965 (struct ob_mac_tso_iocb_req *)mac_iocb_ptr);
1967 if (ql_map_send(qdev, mac_iocb_ptr, skb, tx_ring_desc) !=
1969 QPRINTK(qdev, TX_QUEUED, ERR,
1970 "Could not map the segments.\n");
1971 return NETDEV_TX_BUSY;
1973 QL_DUMP_OB_MAC_IOCB(mac_iocb_ptr);
1974 tx_ring->prod_idx++;
1975 if (tx_ring->prod_idx == tx_ring->wq_len)
1976 tx_ring->prod_idx = 0;
1979 ql_write_db_reg(tx_ring->prod_idx, tx_ring->prod_idx_db_reg);
1980 ndev->trans_start = jiffies;
1981 QPRINTK(qdev, TX_QUEUED, DEBUG, "tx queued, slot %d, len %d\n",
1982 tx_ring->prod_idx, skb->len);
1984 atomic_dec(&tx_ring->tx_count);
1985 return NETDEV_TX_OK;
1988 static void ql_free_shadow_space(struct ql_adapter *qdev)
1990 if (qdev->rx_ring_shadow_reg_area) {
1991 pci_free_consistent(qdev->pdev,
1993 qdev->rx_ring_shadow_reg_area,
1994 qdev->rx_ring_shadow_reg_dma);
1995 qdev->rx_ring_shadow_reg_area = NULL;
1997 if (qdev->tx_ring_shadow_reg_area) {
1998 pci_free_consistent(qdev->pdev,
2000 qdev->tx_ring_shadow_reg_area,
2001 qdev->tx_ring_shadow_reg_dma);
2002 qdev->tx_ring_shadow_reg_area = NULL;
2006 static int ql_alloc_shadow_space(struct ql_adapter *qdev)
2008 qdev->rx_ring_shadow_reg_area =
2009 pci_alloc_consistent(qdev->pdev,
2010 PAGE_SIZE, &qdev->rx_ring_shadow_reg_dma);
2011 if (qdev->rx_ring_shadow_reg_area == NULL) {
2012 QPRINTK(qdev, IFUP, ERR,
2013 "Allocation of RX shadow space failed.\n");
2016 qdev->tx_ring_shadow_reg_area =
2017 pci_alloc_consistent(qdev->pdev, PAGE_SIZE,
2018 &qdev->tx_ring_shadow_reg_dma);
2019 if (qdev->tx_ring_shadow_reg_area == NULL) {
2020 QPRINTK(qdev, IFUP, ERR,
2021 "Allocation of TX shadow space failed.\n");
2022 goto err_wqp_sh_area;
2027 pci_free_consistent(qdev->pdev,
2029 qdev->rx_ring_shadow_reg_area,
2030 qdev->rx_ring_shadow_reg_dma);
2034 static void ql_init_tx_ring(struct ql_adapter *qdev, struct tx_ring *tx_ring)
2036 struct tx_ring_desc *tx_ring_desc;
2038 struct ob_mac_iocb_req *mac_iocb_ptr;
2040 mac_iocb_ptr = tx_ring->wq_base;
2041 tx_ring_desc = tx_ring->q;
2042 for (i = 0; i < tx_ring->wq_len; i++) {
2043 tx_ring_desc->index = i;
2044 tx_ring_desc->skb = NULL;
2045 tx_ring_desc->queue_entry = mac_iocb_ptr;
2049 atomic_set(&tx_ring->tx_count, tx_ring->wq_len);
2050 atomic_set(&tx_ring->queue_stopped, 0);
2053 static void ql_free_tx_resources(struct ql_adapter *qdev,
2054 struct tx_ring *tx_ring)
2056 if (tx_ring->wq_base) {
2057 pci_free_consistent(qdev->pdev, tx_ring->wq_size,
2058 tx_ring->wq_base, tx_ring->wq_base_dma);
2059 tx_ring->wq_base = NULL;
2065 static int ql_alloc_tx_resources(struct ql_adapter *qdev,
2066 struct tx_ring *tx_ring)
2069 pci_alloc_consistent(qdev->pdev, tx_ring->wq_size,
2070 &tx_ring->wq_base_dma);
2072 if ((tx_ring->wq_base == NULL)
2073 || tx_ring->wq_base_dma & (tx_ring->wq_size - 1)) {
2074 QPRINTK(qdev, IFUP, ERR, "tx_ring alloc failed.\n");
2078 kmalloc(tx_ring->wq_len * sizeof(struct tx_ring_desc), GFP_KERNEL);
2079 if (tx_ring->q == NULL)
2084 pci_free_consistent(qdev->pdev, tx_ring->wq_size,
2085 tx_ring->wq_base, tx_ring->wq_base_dma);
2089 static void ql_free_lbq_buffers(struct ql_adapter *qdev, struct rx_ring *rx_ring)
2092 struct bq_desc *lbq_desc;
2094 for (i = 0; i < rx_ring->lbq_len; i++) {
2095 lbq_desc = &rx_ring->lbq[i];
2096 if (lbq_desc->p.lbq_page) {
2097 pci_unmap_page(qdev->pdev,
2098 pci_unmap_addr(lbq_desc, mapaddr),
2099 pci_unmap_len(lbq_desc, maplen),
2100 PCI_DMA_FROMDEVICE);
2102 put_page(lbq_desc->p.lbq_page);
2103 lbq_desc->p.lbq_page = NULL;
2108 static void ql_free_sbq_buffers(struct ql_adapter *qdev, struct rx_ring *rx_ring)
2111 struct bq_desc *sbq_desc;
2113 for (i = 0; i < rx_ring->sbq_len; i++) {
2114 sbq_desc = &rx_ring->sbq[i];
2115 if (sbq_desc == NULL) {
2116 QPRINTK(qdev, IFUP, ERR, "sbq_desc %d is NULL.\n", i);
2119 if (sbq_desc->p.skb) {
2120 pci_unmap_single(qdev->pdev,
2121 pci_unmap_addr(sbq_desc, mapaddr),
2122 pci_unmap_len(sbq_desc, maplen),
2123 PCI_DMA_FROMDEVICE);
2124 dev_kfree_skb(sbq_desc->p.skb);
2125 sbq_desc->p.skb = NULL;
2130 /* Free all large and small rx buffers associated
2131 * with the completion queues for this device.
2133 static void ql_free_rx_buffers(struct ql_adapter *qdev)
2136 struct rx_ring *rx_ring;
2138 for (i = 0; i < qdev->rx_ring_count; i++) {
2139 rx_ring = &qdev->rx_ring[i];
2141 ql_free_lbq_buffers(qdev, rx_ring);
2143 ql_free_sbq_buffers(qdev, rx_ring);
2147 static void ql_alloc_rx_buffers(struct ql_adapter *qdev)
2149 struct rx_ring *rx_ring;
2152 for (i = 0; i < qdev->rx_ring_count; i++) {
2153 rx_ring = &qdev->rx_ring[i];
2154 if (rx_ring->type != TX_Q)
2155 ql_update_buffer_queues(qdev, rx_ring);
2159 static void ql_init_lbq_ring(struct ql_adapter *qdev,
2160 struct rx_ring *rx_ring)
2163 struct bq_desc *lbq_desc;
2164 __le64 *bq = rx_ring->lbq_base;
2166 memset(rx_ring->lbq, 0, rx_ring->lbq_len * sizeof(struct bq_desc));
2167 for (i = 0; i < rx_ring->lbq_len; i++) {
2168 lbq_desc = &rx_ring->lbq[i];
2169 memset(lbq_desc, 0, sizeof(*lbq_desc));
2170 lbq_desc->index = i;
2171 lbq_desc->addr = bq;
2176 static void ql_init_sbq_ring(struct ql_adapter *qdev,
2177 struct rx_ring *rx_ring)
2180 struct bq_desc *sbq_desc;
2181 __le64 *bq = rx_ring->sbq_base;
2183 memset(rx_ring->sbq, 0, rx_ring->sbq_len * sizeof(struct bq_desc));
2184 for (i = 0; i < rx_ring->sbq_len; i++) {
2185 sbq_desc = &rx_ring->sbq[i];
2186 memset(sbq_desc, 0, sizeof(*sbq_desc));
2187 sbq_desc->index = i;
2188 sbq_desc->addr = bq;
2193 static void ql_free_rx_resources(struct ql_adapter *qdev,
2194 struct rx_ring *rx_ring)
2196 /* Free the small buffer queue. */
2197 if (rx_ring->sbq_base) {
2198 pci_free_consistent(qdev->pdev,
2200 rx_ring->sbq_base, rx_ring->sbq_base_dma);
2201 rx_ring->sbq_base = NULL;
2204 /* Free the small buffer queue control blocks. */
2205 kfree(rx_ring->sbq);
2206 rx_ring->sbq = NULL;
2208 /* Free the large buffer queue. */
2209 if (rx_ring->lbq_base) {
2210 pci_free_consistent(qdev->pdev,
2212 rx_ring->lbq_base, rx_ring->lbq_base_dma);
2213 rx_ring->lbq_base = NULL;
2216 /* Free the large buffer queue control blocks. */
2217 kfree(rx_ring->lbq);
2218 rx_ring->lbq = NULL;
2220 /* Free the rx queue. */
2221 if (rx_ring->cq_base) {
2222 pci_free_consistent(qdev->pdev,
2224 rx_ring->cq_base, rx_ring->cq_base_dma);
2225 rx_ring->cq_base = NULL;
2229 /* Allocate queues and buffers for this completions queue based
2230 * on the values in the parameter structure. */
2231 static int ql_alloc_rx_resources(struct ql_adapter *qdev,
2232 struct rx_ring *rx_ring)
2236 * Allocate the completion queue for this rx_ring.
2239 pci_alloc_consistent(qdev->pdev, rx_ring->cq_size,
2240 &rx_ring->cq_base_dma);
2242 if (rx_ring->cq_base == NULL) {
2243 QPRINTK(qdev, IFUP, ERR, "rx_ring alloc failed.\n");
2247 if (rx_ring->sbq_len) {
2249 * Allocate small buffer queue.
2252 pci_alloc_consistent(qdev->pdev, rx_ring->sbq_size,
2253 &rx_ring->sbq_base_dma);
2255 if (rx_ring->sbq_base == NULL) {
2256 QPRINTK(qdev, IFUP, ERR,
2257 "Small buffer queue allocation failed.\n");
2262 * Allocate small buffer queue control blocks.
2265 kmalloc(rx_ring->sbq_len * sizeof(struct bq_desc),
2267 if (rx_ring->sbq == NULL) {
2268 QPRINTK(qdev, IFUP, ERR,
2269 "Small buffer queue control block allocation failed.\n");
2273 ql_init_sbq_ring(qdev, rx_ring);
2276 if (rx_ring->lbq_len) {
2278 * Allocate large buffer queue.
2281 pci_alloc_consistent(qdev->pdev, rx_ring->lbq_size,
2282 &rx_ring->lbq_base_dma);
2284 if (rx_ring->lbq_base == NULL) {
2285 QPRINTK(qdev, IFUP, ERR,
2286 "Large buffer queue allocation failed.\n");
2290 * Allocate large buffer queue control blocks.
2293 kmalloc(rx_ring->lbq_len * sizeof(struct bq_desc),
2295 if (rx_ring->lbq == NULL) {
2296 QPRINTK(qdev, IFUP, ERR,
2297 "Large buffer queue control block allocation failed.\n");
2301 ql_init_lbq_ring(qdev, rx_ring);
2307 ql_free_rx_resources(qdev, rx_ring);
2311 static void ql_tx_ring_clean(struct ql_adapter *qdev)
2313 struct tx_ring *tx_ring;
2314 struct tx_ring_desc *tx_ring_desc;
2318 * Loop through all queues and free
2321 for (j = 0; j < qdev->tx_ring_count; j++) {
2322 tx_ring = &qdev->tx_ring[j];
2323 for (i = 0; i < tx_ring->wq_len; i++) {
2324 tx_ring_desc = &tx_ring->q[i];
2325 if (tx_ring_desc && tx_ring_desc->skb) {
2326 QPRINTK(qdev, IFDOWN, ERR,
2327 "Freeing lost SKB %p, from queue %d, index %d.\n",
2328 tx_ring_desc->skb, j,
2329 tx_ring_desc->index);
2330 ql_unmap_send(qdev, tx_ring_desc,
2331 tx_ring_desc->map_cnt);
2332 dev_kfree_skb(tx_ring_desc->skb);
2333 tx_ring_desc->skb = NULL;
2339 static void ql_free_mem_resources(struct ql_adapter *qdev)
2343 for (i = 0; i < qdev->tx_ring_count; i++)
2344 ql_free_tx_resources(qdev, &qdev->tx_ring[i]);
2345 for (i = 0; i < qdev->rx_ring_count; i++)
2346 ql_free_rx_resources(qdev, &qdev->rx_ring[i]);
2347 ql_free_shadow_space(qdev);
2350 static int ql_alloc_mem_resources(struct ql_adapter *qdev)
2354 /* Allocate space for our shadow registers and such. */
2355 if (ql_alloc_shadow_space(qdev))
2358 for (i = 0; i < qdev->rx_ring_count; i++) {
2359 if (ql_alloc_rx_resources(qdev, &qdev->rx_ring[i]) != 0) {
2360 QPRINTK(qdev, IFUP, ERR,
2361 "RX resource allocation failed.\n");
2365 /* Allocate tx queue resources */
2366 for (i = 0; i < qdev->tx_ring_count; i++) {
2367 if (ql_alloc_tx_resources(qdev, &qdev->tx_ring[i]) != 0) {
2368 QPRINTK(qdev, IFUP, ERR,
2369 "TX resource allocation failed.\n");
2376 ql_free_mem_resources(qdev);
2380 /* Set up the rx ring control block and pass it to the chip.
2381 * The control block is defined as
2382 * "Completion Queue Initialization Control Block", or cqicb.
2384 static int ql_start_rx_ring(struct ql_adapter *qdev, struct rx_ring *rx_ring)
2386 struct cqicb *cqicb = &rx_ring->cqicb;
2387 void *shadow_reg = qdev->rx_ring_shadow_reg_area +
2388 (rx_ring->cq_id * sizeof(u64) * 4);
2389 u64 shadow_reg_dma = qdev->rx_ring_shadow_reg_dma +
2390 (rx_ring->cq_id * sizeof(u64) * 4);
2391 void __iomem *doorbell_area =
2392 qdev->doorbell_area + (DB_PAGE_SIZE * (128 + rx_ring->cq_id));
2396 /* Set up the shadow registers for this ring. */
2397 rx_ring->prod_idx_sh_reg = shadow_reg;
2398 rx_ring->prod_idx_sh_reg_dma = shadow_reg_dma;
2399 shadow_reg += sizeof(u64);
2400 shadow_reg_dma += sizeof(u64);
2401 rx_ring->lbq_base_indirect = shadow_reg;
2402 rx_ring->lbq_base_indirect_dma = shadow_reg_dma;
2403 shadow_reg += sizeof(u64);
2404 shadow_reg_dma += sizeof(u64);
2405 rx_ring->sbq_base_indirect = shadow_reg;
2406 rx_ring->sbq_base_indirect_dma = shadow_reg_dma;
2408 /* PCI doorbell mem area + 0x00 for consumer index register */
2409 rx_ring->cnsmr_idx_db_reg = (u32 __iomem *) doorbell_area;
2410 rx_ring->cnsmr_idx = 0;
2411 rx_ring->curr_entry = rx_ring->cq_base;
2413 /* PCI doorbell mem area + 0x04 for valid register */
2414 rx_ring->valid_db_reg = doorbell_area + 0x04;
2416 /* PCI doorbell mem area + 0x18 for large buffer consumer */
2417 rx_ring->lbq_prod_idx_db_reg = (u32 __iomem *) (doorbell_area + 0x18);
2419 /* PCI doorbell mem area + 0x1c */
2420 rx_ring->sbq_prod_idx_db_reg = (u32 __iomem *) (doorbell_area + 0x1c);
2422 memset((void *)cqicb, 0, sizeof(struct cqicb));
2423 cqicb->msix_vect = rx_ring->irq;
2425 bq_len = (rx_ring->cq_len == 65536) ? 0 : (u16) rx_ring->cq_len;
2426 cqicb->len = cpu_to_le16(bq_len | LEN_V | LEN_CPP_CONT);
2428 cqicb->addr = cpu_to_le64(rx_ring->cq_base_dma);
2430 cqicb->prod_idx_addr = cpu_to_le64(rx_ring->prod_idx_sh_reg_dma);
2433 * Set up the control block load flags.
2435 cqicb->flags = FLAGS_LC | /* Load queue base address */
2436 FLAGS_LV | /* Load MSI-X vector */
2437 FLAGS_LI; /* Load irq delay values */
2438 if (rx_ring->lbq_len) {
2439 cqicb->flags |= FLAGS_LL; /* Load lbq values */
2440 *((u64 *) rx_ring->lbq_base_indirect) = rx_ring->lbq_base_dma;
2442 cpu_to_le64(rx_ring->lbq_base_indirect_dma);
2443 bq_len = (rx_ring->lbq_buf_size == 65536) ? 0 :
2444 (u16) rx_ring->lbq_buf_size;
2445 cqicb->lbq_buf_size = cpu_to_le16(bq_len);
2446 bq_len = (rx_ring->lbq_len == 65536) ? 0 :
2447 (u16) rx_ring->lbq_len;
2448 cqicb->lbq_len = cpu_to_le16(bq_len);
2449 rx_ring->lbq_prod_idx = 0;
2450 rx_ring->lbq_curr_idx = 0;
2451 rx_ring->lbq_clean_idx = 0;
2452 rx_ring->lbq_free_cnt = rx_ring->lbq_len;
2454 if (rx_ring->sbq_len) {
2455 cqicb->flags |= FLAGS_LS; /* Load sbq values */
2456 *((u64 *) rx_ring->sbq_base_indirect) = rx_ring->sbq_base_dma;
2458 cpu_to_le64(rx_ring->sbq_base_indirect_dma);
2459 cqicb->sbq_buf_size =
2460 cpu_to_le16(((rx_ring->sbq_buf_size / 2) + 8) & 0xfffffff8);
2461 bq_len = (rx_ring->sbq_len == 65536) ? 0 :
2462 (u16) rx_ring->sbq_len;
2463 cqicb->sbq_len = cpu_to_le16(bq_len);
2464 rx_ring->sbq_prod_idx = 0;
2465 rx_ring->sbq_curr_idx = 0;
2466 rx_ring->sbq_clean_idx = 0;
2467 rx_ring->sbq_free_cnt = rx_ring->sbq_len;
2469 switch (rx_ring->type) {
2471 /* If there's only one interrupt, then we use
2472 * worker threads to process the outbound
2473 * completion handling rx_rings. We do this so
2474 * they can be run on multiple CPUs. There is
2475 * room to play with this more where we would only
2476 * run in a worker if there are more than x number
2477 * of outbound completions on the queue and more
2478 * than one queue active. Some threshold that
2479 * would indicate a benefit in spite of the cost
2480 * of a context switch.
2481 * If there's more than one interrupt, then the
2482 * outbound completions are processed in the ISR.
2484 if (!test_bit(QL_MSIX_ENABLED, &qdev->flags))
2485 INIT_DELAYED_WORK(&rx_ring->rx_work, ql_tx_clean);
2487 /* With all debug warnings on we see a WARN_ON message
2488 * when we free the skb in the interrupt context.
2490 INIT_DELAYED_WORK(&rx_ring->rx_work, ql_tx_clean);
2492 cqicb->irq_delay = cpu_to_le16(qdev->tx_coalesce_usecs);
2493 cqicb->pkt_delay = cpu_to_le16(qdev->tx_max_coalesced_frames);
2496 INIT_DELAYED_WORK(&rx_ring->rx_work, ql_rx_clean);
2497 cqicb->irq_delay = 0;
2498 cqicb->pkt_delay = 0;
2501 /* Inbound completion handling rx_rings run in
2502 * separate NAPI contexts.
2504 netif_napi_add(qdev->ndev, &rx_ring->napi, ql_napi_poll_msix,
2506 cqicb->irq_delay = cpu_to_le16(qdev->rx_coalesce_usecs);
2507 cqicb->pkt_delay = cpu_to_le16(qdev->rx_max_coalesced_frames);
2510 QPRINTK(qdev, IFUP, DEBUG, "Invalid rx_ring->type = %d.\n",
2513 QPRINTK(qdev, IFUP, INFO, "Initializing rx work queue.\n");
2514 err = ql_write_cfg(qdev, cqicb, sizeof(struct cqicb),
2515 CFG_LCQ, rx_ring->cq_id);
2517 QPRINTK(qdev, IFUP, ERR, "Failed to load CQICB.\n");
2523 static int ql_start_tx_ring(struct ql_adapter *qdev, struct tx_ring *tx_ring)
2525 struct wqicb *wqicb = (struct wqicb *)tx_ring;
2526 void __iomem *doorbell_area =
2527 qdev->doorbell_area + (DB_PAGE_SIZE * tx_ring->wq_id);
2528 void *shadow_reg = qdev->tx_ring_shadow_reg_area +
2529 (tx_ring->wq_id * sizeof(u64));
2530 u64 shadow_reg_dma = qdev->tx_ring_shadow_reg_dma +
2531 (tx_ring->wq_id * sizeof(u64));
2535 * Assign doorbell registers for this tx_ring.
2537 /* TX PCI doorbell mem area for tx producer index */
2538 tx_ring->prod_idx_db_reg = (u32 __iomem *) doorbell_area;
2539 tx_ring->prod_idx = 0;
2540 /* TX PCI doorbell mem area + 0x04 */
2541 tx_ring->valid_db_reg = doorbell_area + 0x04;
2544 * Assign shadow registers for this tx_ring.
2546 tx_ring->cnsmr_idx_sh_reg = shadow_reg;
2547 tx_ring->cnsmr_idx_sh_reg_dma = shadow_reg_dma;
2549 wqicb->len = cpu_to_le16(tx_ring->wq_len | Q_LEN_V | Q_LEN_CPP_CONT);
2550 wqicb->flags = cpu_to_le16(Q_FLAGS_LC |
2551 Q_FLAGS_LB | Q_FLAGS_LI | Q_FLAGS_LO);
2552 wqicb->cq_id_rss = cpu_to_le16(tx_ring->cq_id);
2554 wqicb->addr = cpu_to_le64(tx_ring->wq_base_dma);
2556 wqicb->cnsmr_idx_addr = cpu_to_le64(tx_ring->cnsmr_idx_sh_reg_dma);
2558 ql_init_tx_ring(qdev, tx_ring);
2560 err = ql_write_cfg(qdev, wqicb, sizeof(wqicb), CFG_LRQ,
2561 (u16) tx_ring->wq_id);
2563 QPRINTK(qdev, IFUP, ERR, "Failed to load tx_ring.\n");
2566 QPRINTK(qdev, IFUP, INFO, "Successfully loaded WQICB.\n");
2570 static void ql_disable_msix(struct ql_adapter *qdev)
2572 if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
2573 pci_disable_msix(qdev->pdev);
2574 clear_bit(QL_MSIX_ENABLED, &qdev->flags);
2575 kfree(qdev->msi_x_entry);
2576 qdev->msi_x_entry = NULL;
2577 } else if (test_bit(QL_MSI_ENABLED, &qdev->flags)) {
2578 pci_disable_msi(qdev->pdev);
2579 clear_bit(QL_MSI_ENABLED, &qdev->flags);
2583 static void ql_enable_msix(struct ql_adapter *qdev)
2587 qdev->intr_count = 1;
2588 /* Get the MSIX vectors. */
2589 if (irq_type == MSIX_IRQ) {
2590 /* Try to alloc space for the msix struct,
2591 * if it fails then go to MSI/legacy.
2593 qdev->msi_x_entry = kcalloc(qdev->rx_ring_count,
2594 sizeof(struct msix_entry),
2596 if (!qdev->msi_x_entry) {
2601 for (i = 0; i < qdev->rx_ring_count; i++)
2602 qdev->msi_x_entry[i].entry = i;
2604 if (!pci_enable_msix
2605 (qdev->pdev, qdev->msi_x_entry, qdev->rx_ring_count)) {
2606 set_bit(QL_MSIX_ENABLED, &qdev->flags);
2607 qdev->intr_count = qdev->rx_ring_count;
2608 QPRINTK(qdev, IFUP, INFO,
2609 "MSI-X Enabled, got %d vectors.\n",
2613 kfree(qdev->msi_x_entry);
2614 qdev->msi_x_entry = NULL;
2615 QPRINTK(qdev, IFUP, WARNING,
2616 "MSI-X Enable failed, trying MSI.\n");
2621 if (irq_type == MSI_IRQ) {
2622 if (!pci_enable_msi(qdev->pdev)) {
2623 set_bit(QL_MSI_ENABLED, &qdev->flags);
2624 QPRINTK(qdev, IFUP, INFO,
2625 "Running with MSI interrupts.\n");
2630 QPRINTK(qdev, IFUP, DEBUG, "Running with legacy interrupts.\n");
2634 * Here we build the intr_context structures based on
2635 * our rx_ring count and intr vector count.
2636 * The intr_context structure is used to hook each vector
2637 * to possibly different handlers.
2639 static void ql_resolve_queues_to_irqs(struct ql_adapter *qdev)
2642 struct intr_context *intr_context = &qdev->intr_context[0];
2644 ql_enable_msix(qdev);
2646 if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags))) {
2647 /* Each rx_ring has it's
2648 * own intr_context since we have separate
2649 * vectors for each queue.
2650 * This only true when MSI-X is enabled.
2652 for (i = 0; i < qdev->intr_count; i++, intr_context++) {
2653 qdev->rx_ring[i].irq = i;
2654 intr_context->intr = i;
2655 intr_context->qdev = qdev;
2657 * We set up each vectors enable/disable/read bits so
2658 * there's no bit/mask calculations in the critical path.
2660 intr_context->intr_en_mask =
2661 INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2662 INTR_EN_TYPE_ENABLE | INTR_EN_IHD_MASK | INTR_EN_IHD
2664 intr_context->intr_dis_mask =
2665 INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2666 INTR_EN_TYPE_DISABLE | INTR_EN_IHD_MASK |
2668 intr_context->intr_read_mask =
2669 INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2670 INTR_EN_TYPE_READ | INTR_EN_IHD_MASK | INTR_EN_IHD |
2675 * Default queue handles bcast/mcast plus
2676 * async events. Needs buffers.
2678 intr_context->handler = qlge_isr;
2679 sprintf(intr_context->name, "%s-default-queue",
2681 } else if (i < qdev->rss_ring_first_cq_id) {
2683 * Outbound queue is for outbound completions only.
2685 intr_context->handler = qlge_msix_tx_isr;
2686 sprintf(intr_context->name, "%s-tx-%d",
2687 qdev->ndev->name, i);
2690 * Inbound queues handle unicast frames only.
2692 intr_context->handler = qlge_msix_rx_isr;
2693 sprintf(intr_context->name, "%s-rx-%d",
2694 qdev->ndev->name, i);
2699 * All rx_rings use the same intr_context since
2700 * there is only one vector.
2702 intr_context->intr = 0;
2703 intr_context->qdev = qdev;
2705 * We set up each vectors enable/disable/read bits so
2706 * there's no bit/mask calculations in the critical path.
2708 intr_context->intr_en_mask =
2709 INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK | INTR_EN_TYPE_ENABLE;
2710 intr_context->intr_dis_mask =
2711 INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2712 INTR_EN_TYPE_DISABLE;
2713 intr_context->intr_read_mask =
2714 INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK | INTR_EN_TYPE_READ;
2716 * Single interrupt means one handler for all rings.
2718 intr_context->handler = qlge_isr;
2719 sprintf(intr_context->name, "%s-single_irq", qdev->ndev->name);
2720 for (i = 0; i < qdev->rx_ring_count; i++)
2721 qdev->rx_ring[i].irq = 0;
2725 static void ql_free_irq(struct ql_adapter *qdev)
2728 struct intr_context *intr_context = &qdev->intr_context[0];
2730 for (i = 0; i < qdev->intr_count; i++, intr_context++) {
2731 if (intr_context->hooked) {
2732 if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
2733 free_irq(qdev->msi_x_entry[i].vector,
2735 QPRINTK(qdev, IFDOWN, ERR,
2736 "freeing msix interrupt %d.\n", i);
2738 free_irq(qdev->pdev->irq, &qdev->rx_ring[0]);
2739 QPRINTK(qdev, IFDOWN, ERR,
2740 "freeing msi interrupt %d.\n", i);
2744 ql_disable_msix(qdev);
2747 static int ql_request_irq(struct ql_adapter *qdev)
2751 struct pci_dev *pdev = qdev->pdev;
2752 struct intr_context *intr_context = &qdev->intr_context[0];
2754 ql_resolve_queues_to_irqs(qdev);
2756 for (i = 0; i < qdev->intr_count; i++, intr_context++) {
2757 atomic_set(&intr_context->irq_cnt, 0);
2758 if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
2759 status = request_irq(qdev->msi_x_entry[i].vector,
2760 intr_context->handler,
2765 QPRINTK(qdev, IFUP, ERR,
2766 "Failed request for MSIX interrupt %d.\n",
2770 QPRINTK(qdev, IFUP, INFO,
2771 "Hooked intr %d, queue type %s%s%s, with name %s.\n",
2773 qdev->rx_ring[i].type ==
2774 DEFAULT_Q ? "DEFAULT_Q" : "",
2775 qdev->rx_ring[i].type ==
2777 qdev->rx_ring[i].type ==
2778 RX_Q ? "RX_Q" : "", intr_context->name);
2781 QPRINTK(qdev, IFUP, DEBUG,
2782 "trying msi or legacy interrupts.\n");
2783 QPRINTK(qdev, IFUP, DEBUG,
2784 "%s: irq = %d.\n", __func__, pdev->irq);
2785 QPRINTK(qdev, IFUP, DEBUG,
2786 "%s: context->name = %s.\n", __func__,
2787 intr_context->name);
2788 QPRINTK(qdev, IFUP, DEBUG,
2789 "%s: dev_id = 0x%p.\n", __func__,
2792 request_irq(pdev->irq, qlge_isr,
2793 test_bit(QL_MSI_ENABLED,
2795 flags) ? 0 : IRQF_SHARED,
2796 intr_context->name, &qdev->rx_ring[0]);
2800 QPRINTK(qdev, IFUP, ERR,
2801 "Hooked intr %d, queue type %s%s%s, with name %s.\n",
2803 qdev->rx_ring[0].type ==
2804 DEFAULT_Q ? "DEFAULT_Q" : "",
2805 qdev->rx_ring[0].type == TX_Q ? "TX_Q" : "",
2806 qdev->rx_ring[0].type == RX_Q ? "RX_Q" : "",
2807 intr_context->name);
2809 intr_context->hooked = 1;
2813 QPRINTK(qdev, IFUP, ERR, "Failed to get the interrupts!!!/n");
2818 static int ql_start_rss(struct ql_adapter *qdev)
2820 struct ricb *ricb = &qdev->ricb;
2823 u8 *hash_id = (u8 *) ricb->hash_cq_id;
2825 memset((void *)ricb, 0, sizeof(ricb));
2827 ricb->base_cq = qdev->rss_ring_first_cq_id | RSS_L4K;
2829 (RSS_L6K | RSS_LI | RSS_LB | RSS_LM | RSS_RI4 | RSS_RI6 | RSS_RT4 |
2831 ricb->mask = cpu_to_le16(qdev->rss_ring_count - 1);
2834 * Fill out the Indirection Table.
2836 for (i = 0; i < 256; i++)
2837 hash_id[i] = i & (qdev->rss_ring_count - 1);
2840 * Random values for the IPv6 and IPv4 Hash Keys.
2842 get_random_bytes((void *)&ricb->ipv6_hash_key[0], 40);
2843 get_random_bytes((void *)&ricb->ipv4_hash_key[0], 16);
2845 QPRINTK(qdev, IFUP, INFO, "Initializing RSS.\n");
2847 status = ql_write_cfg(qdev, ricb, sizeof(ricb), CFG_LR, 0);
2849 QPRINTK(qdev, IFUP, ERR, "Failed to load RICB.\n");
2852 QPRINTK(qdev, IFUP, INFO, "Successfully loaded RICB.\n");
2856 /* Initialize the frame-to-queue routing. */
2857 static int ql_route_initialize(struct ql_adapter *qdev)
2862 status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
2866 /* Clear all the entries in the routing table. */
2867 for (i = 0; i < 16; i++) {
2868 status = ql_set_routing_reg(qdev, i, 0, 0);
2870 QPRINTK(qdev, IFUP, ERR,
2871 "Failed to init routing register for CAM packets.\n");
2876 status = ql_set_routing_reg(qdev, RT_IDX_ALL_ERR_SLOT, RT_IDX_ERR, 1);
2878 QPRINTK(qdev, IFUP, ERR,
2879 "Failed to init routing register for error packets.\n");
2882 status = ql_set_routing_reg(qdev, RT_IDX_BCAST_SLOT, RT_IDX_BCAST, 1);
2884 QPRINTK(qdev, IFUP, ERR,
2885 "Failed to init routing register for broadcast packets.\n");
2888 /* If we have more than one inbound queue, then turn on RSS in the
2891 if (qdev->rss_ring_count > 1) {
2892 status = ql_set_routing_reg(qdev, RT_IDX_RSS_MATCH_SLOT,
2893 RT_IDX_RSS_MATCH, 1);
2895 QPRINTK(qdev, IFUP, ERR,
2896 "Failed to init routing register for MATCH RSS packets.\n");
2901 status = ql_set_routing_reg(qdev, RT_IDX_CAM_HIT_SLOT,
2904 QPRINTK(qdev, IFUP, ERR,
2905 "Failed to init routing register for CAM packets.\n");
2907 ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
2911 static int ql_cam_route_initialize(struct ql_adapter *qdev)
2915 status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
2918 status = ql_set_mac_addr_reg(qdev, (u8 *) qdev->ndev->perm_addr,
2919 MAC_ADDR_TYPE_CAM_MAC, qdev->func * MAX_CQ);
2920 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
2922 QPRINTK(qdev, IFUP, ERR, "Failed to init mac address.\n");
2926 status = ql_route_initialize(qdev);
2928 QPRINTK(qdev, IFUP, ERR, "Failed to init routing table.\n");
2933 static int ql_adapter_initialize(struct ql_adapter *qdev)
2940 * Set up the System register to halt on errors.
2942 value = SYS_EFE | SYS_FAE;
2944 ql_write32(qdev, SYS, mask | value);
2946 /* Set the default queue. */
2947 value = NIC_RCV_CFG_DFQ;
2948 mask = NIC_RCV_CFG_DFQ_MASK;
2949 ql_write32(qdev, NIC_RCV_CFG, (mask | value));
2951 /* Set the MPI interrupt to enabled. */
2952 ql_write32(qdev, INTR_MASK, (INTR_MASK_PI << 16) | INTR_MASK_PI);
2954 /* Enable the function, set pagesize, enable error checking. */
2955 value = FSC_FE | FSC_EPC_INBOUND | FSC_EPC_OUTBOUND |
2956 FSC_EC | FSC_VM_PAGE_4K | FSC_SH;
2958 /* Set/clear header splitting. */
2959 mask = FSC_VM_PAGESIZE_MASK |
2960 FSC_DBL_MASK | FSC_DBRST_MASK | (value << 16);
2961 ql_write32(qdev, FSC, mask | value);
2963 ql_write32(qdev, SPLT_HDR, SPLT_HDR_EP |
2964 min(SMALL_BUFFER_SIZE, MAX_SPLIT_SIZE));
2966 /* Start up the rx queues. */
2967 for (i = 0; i < qdev->rx_ring_count; i++) {
2968 status = ql_start_rx_ring(qdev, &qdev->rx_ring[i]);
2970 QPRINTK(qdev, IFUP, ERR,
2971 "Failed to start rx ring[%d].\n", i);
2976 /* If there is more than one inbound completion queue
2977 * then download a RICB to configure RSS.
2979 if (qdev->rss_ring_count > 1) {
2980 status = ql_start_rss(qdev);
2982 QPRINTK(qdev, IFUP, ERR, "Failed to start RSS.\n");
2987 /* Start up the tx queues. */
2988 for (i = 0; i < qdev->tx_ring_count; i++) {
2989 status = ql_start_tx_ring(qdev, &qdev->tx_ring[i]);
2991 QPRINTK(qdev, IFUP, ERR,
2992 "Failed to start tx ring[%d].\n", i);
2997 status = ql_port_initialize(qdev);
2999 QPRINTK(qdev, IFUP, ERR, "Failed to start port.\n");
3003 /* Set up the MAC address and frame routing filter. */
3004 status = ql_cam_route_initialize(qdev);
3006 QPRINTK(qdev, IFUP, ERR,
3007 "Failed to init CAM/Routing tables.\n");
3011 /* Start NAPI for the RSS queues. */
3012 for (i = qdev->rss_ring_first_cq_id; i < qdev->rx_ring_count; i++) {
3013 QPRINTK(qdev, IFUP, INFO, "Enabling NAPI for rx_ring[%d].\n",
3015 napi_enable(&qdev->rx_ring[i].napi);
3021 /* Issue soft reset to chip. */
3022 static int ql_adapter_reset(struct ql_adapter *qdev)
3029 #define MAX_RESET_CNT 1
3032 QPRINTK(qdev, IFDOWN, DEBUG, "Issue soft reset to chip.\n");
3033 ql_write32(qdev, RST_FO, (RST_FO_FR << 16) | RST_FO_FR);
3034 /* Wait for reset to complete. */
3036 QPRINTK(qdev, IFDOWN, DEBUG, "Wait %d seconds for reset to complete.\n",
3039 value = ql_read32(qdev, RST_FO);
3040 if ((value & RST_FO_FR) == 0)
3044 } while ((--max_wait_time));
3045 if (value & RST_FO_FR) {
3046 QPRINTK(qdev, IFDOWN, ERR,
3047 "Stuck in SoftReset: FSC_SR:0x%08x\n", value);
3048 if (resetCnt < MAX_RESET_CNT)
3051 if (max_wait_time == 0) {
3052 status = -ETIMEDOUT;
3053 QPRINTK(qdev, IFDOWN, ERR,
3054 "ETIMEOUT!!! errored out of resetting the chip!\n");
3060 static void ql_display_dev_info(struct net_device *ndev)
3062 struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3064 QPRINTK(qdev, PROBE, INFO,
3065 "Function #%d, NIC Roll %d, NIC Rev = %d, "
3066 "XG Roll = %d, XG Rev = %d.\n",
3068 qdev->chip_rev_id & 0x0000000f,
3069 qdev->chip_rev_id >> 4 & 0x0000000f,
3070 qdev->chip_rev_id >> 8 & 0x0000000f,
3071 qdev->chip_rev_id >> 12 & 0x0000000f);
3072 QPRINTK(qdev, PROBE, INFO, "MAC address %pM\n", ndev->dev_addr);
3075 static int ql_adapter_down(struct ql_adapter *qdev)
3077 struct net_device *ndev = qdev->ndev;
3079 struct rx_ring *rx_ring;
3081 netif_stop_queue(ndev);
3082 netif_carrier_off(ndev);
3084 /* Don't kill the reset worker thread if we
3085 * are in the process of recovery.
3087 if (test_bit(QL_ADAPTER_UP, &qdev->flags))
3088 cancel_delayed_work_sync(&qdev->asic_reset_work);
3089 cancel_delayed_work_sync(&qdev->mpi_reset_work);
3090 cancel_delayed_work_sync(&qdev->mpi_work);
3092 /* The default queue at index 0 is always processed in
3095 cancel_delayed_work_sync(&qdev->rx_ring[0].rx_work);
3097 /* The rest of the rx_rings are processed in
3098 * a workqueue only if it's a single interrupt
3099 * environment (MSI/Legacy).
3101 for (i = 1; i < qdev->rx_ring_count; i++) {
3102 rx_ring = &qdev->rx_ring[i];
3103 /* Only the RSS rings use NAPI on multi irq
3104 * environment. Outbound completion processing
3105 * is done in interrupt context.
3107 if (i >= qdev->rss_ring_first_cq_id) {
3108 napi_disable(&rx_ring->napi);
3110 cancel_delayed_work_sync(&rx_ring->rx_work);
3114 clear_bit(QL_ADAPTER_UP, &qdev->flags);
3116 ql_disable_interrupts(qdev);
3118 ql_tx_ring_clean(qdev);
3120 ql_free_rx_buffers(qdev);
3121 spin_lock(&qdev->hw_lock);
3122 status = ql_adapter_reset(qdev);
3124 QPRINTK(qdev, IFDOWN, ERR, "reset(func #%d) FAILED!\n",
3126 spin_unlock(&qdev->hw_lock);
3130 static int ql_adapter_up(struct ql_adapter *qdev)
3134 spin_lock(&qdev->hw_lock);
3135 err = ql_adapter_initialize(qdev);
3137 QPRINTK(qdev, IFUP, INFO, "Unable to initialize adapter.\n");
3138 spin_unlock(&qdev->hw_lock);
3141 spin_unlock(&qdev->hw_lock);
3142 set_bit(QL_ADAPTER_UP, &qdev->flags);
3143 ql_alloc_rx_buffers(qdev);
3144 ql_enable_interrupts(qdev);
3145 ql_enable_all_completion_interrupts(qdev);
3146 if ((ql_read32(qdev, STS) & qdev->port_init)) {
3147 netif_carrier_on(qdev->ndev);
3148 netif_start_queue(qdev->ndev);
3153 ql_adapter_reset(qdev);
3157 static int ql_cycle_adapter(struct ql_adapter *qdev)
3161 status = ql_adapter_down(qdev);
3165 status = ql_adapter_up(qdev);
3171 QPRINTK(qdev, IFUP, ALERT,
3172 "Driver up/down cycle failed, closing device\n");
3174 dev_close(qdev->ndev);
3179 static void ql_release_adapter_resources(struct ql_adapter *qdev)
3181 ql_free_mem_resources(qdev);
3185 static int ql_get_adapter_resources(struct ql_adapter *qdev)
3189 if (ql_alloc_mem_resources(qdev)) {
3190 QPRINTK(qdev, IFUP, ERR, "Unable to allocate memory.\n");
3193 status = ql_request_irq(qdev);
3198 ql_free_mem_resources(qdev);
3202 static int qlge_close(struct net_device *ndev)
3204 struct ql_adapter *qdev = netdev_priv(ndev);
3207 * Wait for device to recover from a reset.
3208 * (Rarely happens, but possible.)
3210 while (!test_bit(QL_ADAPTER_UP, &qdev->flags))
3212 ql_adapter_down(qdev);
3213 ql_release_adapter_resources(qdev);
3217 static int ql_configure_rings(struct ql_adapter *qdev)
3220 struct rx_ring *rx_ring;
3221 struct tx_ring *tx_ring;
3222 int cpu_cnt = num_online_cpus();
3225 * For each processor present we allocate one
3226 * rx_ring for outbound completions, and one
3227 * rx_ring for inbound completions. Plus there is
3228 * always the one default queue. For the CPU
3229 * counts we end up with the following rx_rings:
3231 * one default queue +
3232 * (CPU count * outbound completion rx_ring) +
3233 * (CPU count * inbound (RSS) completion rx_ring)
3234 * To keep it simple we limit the total number of
3235 * queues to < 32, so we truncate CPU to 8.
3236 * This limitation can be removed when requested.
3239 if (cpu_cnt > MAX_CPUS)
3243 * rx_ring[0] is always the default queue.
3245 /* Allocate outbound completion ring for each CPU. */
3246 qdev->tx_ring_count = cpu_cnt;
3247 /* Allocate inbound completion (RSS) ring for each CPU. */
3248 qdev->rss_ring_count = cpu_cnt;
3249 /* cq_id for the first inbound ring handler. */
3250 qdev->rss_ring_first_cq_id = cpu_cnt + 1;
3252 * qdev->rx_ring_count:
3253 * Total number of rx_rings. This includes the one
3254 * default queue, a number of outbound completion
3255 * handler rx_rings, and the number of inbound
3256 * completion handler rx_rings.
3258 qdev->rx_ring_count = qdev->tx_ring_count + qdev->rss_ring_count + 1;
3260 for (i = 0; i < qdev->tx_ring_count; i++) {
3261 tx_ring = &qdev->tx_ring[i];
3262 memset((void *)tx_ring, 0, sizeof(tx_ring));
3263 tx_ring->qdev = qdev;
3265 tx_ring->wq_len = qdev->tx_ring_size;
3267 tx_ring->wq_len * sizeof(struct ob_mac_iocb_req);
3270 * The completion queue ID for the tx rings start
3271 * immediately after the default Q ID, which is zero.
3273 tx_ring->cq_id = i + 1;
3276 for (i = 0; i < qdev->rx_ring_count; i++) {
3277 rx_ring = &qdev->rx_ring[i];
3278 memset((void *)rx_ring, 0, sizeof(rx_ring));
3279 rx_ring->qdev = qdev;
3281 rx_ring->cpu = i % cpu_cnt; /* CPU to run handler on. */
3282 if (i == 0) { /* Default queue at index 0. */
3284 * Default queue handles bcast/mcast plus
3285 * async events. Needs buffers.
3287 rx_ring->cq_len = qdev->rx_ring_size;
3289 rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
3290 rx_ring->lbq_len = NUM_LARGE_BUFFERS;
3292 rx_ring->lbq_len * sizeof(__le64);
3293 rx_ring->lbq_buf_size = LARGE_BUFFER_SIZE;
3294 rx_ring->sbq_len = NUM_SMALL_BUFFERS;
3296 rx_ring->sbq_len * sizeof(__le64);
3297 rx_ring->sbq_buf_size = SMALL_BUFFER_SIZE * 2;
3298 rx_ring->type = DEFAULT_Q;
3299 } else if (i < qdev->rss_ring_first_cq_id) {
3301 * Outbound queue handles outbound completions only.
3303 /* outbound cq is same size as tx_ring it services. */
3304 rx_ring->cq_len = qdev->tx_ring_size;
3306 rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
3307 rx_ring->lbq_len = 0;
3308 rx_ring->lbq_size = 0;
3309 rx_ring->lbq_buf_size = 0;
3310 rx_ring->sbq_len = 0;
3311 rx_ring->sbq_size = 0;
3312 rx_ring->sbq_buf_size = 0;
3313 rx_ring->type = TX_Q;
3314 } else { /* Inbound completions (RSS) queues */
3316 * Inbound queues handle unicast frames only.
3318 rx_ring->cq_len = qdev->rx_ring_size;
3320 rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
3321 rx_ring->lbq_len = NUM_LARGE_BUFFERS;
3323 rx_ring->lbq_len * sizeof(__le64);
3324 rx_ring->lbq_buf_size = LARGE_BUFFER_SIZE;
3325 rx_ring->sbq_len = NUM_SMALL_BUFFERS;
3327 rx_ring->sbq_len * sizeof(__le64);
3328 rx_ring->sbq_buf_size = SMALL_BUFFER_SIZE * 2;
3329 rx_ring->type = RX_Q;
3335 static int qlge_open(struct net_device *ndev)
3338 struct ql_adapter *qdev = netdev_priv(ndev);
3340 err = ql_configure_rings(qdev);
3344 err = ql_get_adapter_resources(qdev);
3348 err = ql_adapter_up(qdev);
3355 ql_release_adapter_resources(qdev);
3359 static int qlge_change_mtu(struct net_device *ndev, int new_mtu)
3361 struct ql_adapter *qdev = netdev_priv(ndev);
3363 if (ndev->mtu == 1500 && new_mtu == 9000) {
3364 QPRINTK(qdev, IFUP, ERR, "Changing to jumbo MTU.\n");
3365 } else if (ndev->mtu == 9000 && new_mtu == 1500) {
3366 QPRINTK(qdev, IFUP, ERR, "Changing to normal MTU.\n");
3367 } else if ((ndev->mtu == 1500 && new_mtu == 1500) ||
3368 (ndev->mtu == 9000 && new_mtu == 9000)) {
3372 ndev->mtu = new_mtu;
3376 static struct net_device_stats *qlge_get_stats(struct net_device
3379 struct ql_adapter *qdev = netdev_priv(ndev);
3380 return &qdev->stats;
3383 static void qlge_set_multicast_list(struct net_device *ndev)
3385 struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3386 struct dev_mc_list *mc_ptr;
3389 status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
3392 spin_lock(&qdev->hw_lock);
3394 * Set or clear promiscuous mode if a
3395 * transition is taking place.
3397 if (ndev->flags & IFF_PROMISC) {
3398 if (!test_bit(QL_PROMISCUOUS, &qdev->flags)) {
3399 if (ql_set_routing_reg
3400 (qdev, RT_IDX_PROMISCUOUS_SLOT, RT_IDX_VALID, 1)) {
3401 QPRINTK(qdev, HW, ERR,
3402 "Failed to set promiscous mode.\n");
3404 set_bit(QL_PROMISCUOUS, &qdev->flags);
3408 if (test_bit(QL_PROMISCUOUS, &qdev->flags)) {
3409 if (ql_set_routing_reg
3410 (qdev, RT_IDX_PROMISCUOUS_SLOT, RT_IDX_VALID, 0)) {
3411 QPRINTK(qdev, HW, ERR,
3412 "Failed to clear promiscous mode.\n");
3414 clear_bit(QL_PROMISCUOUS, &qdev->flags);
3420 * Set or clear all multicast mode if a
3421 * transition is taking place.
3423 if ((ndev->flags & IFF_ALLMULTI) ||
3424 (ndev->mc_count > MAX_MULTICAST_ENTRIES)) {
3425 if (!test_bit(QL_ALLMULTI, &qdev->flags)) {
3426 if (ql_set_routing_reg
3427 (qdev, RT_IDX_ALLMULTI_SLOT, RT_IDX_MCAST, 1)) {
3428 QPRINTK(qdev, HW, ERR,
3429 "Failed to set all-multi mode.\n");
3431 set_bit(QL_ALLMULTI, &qdev->flags);
3435 if (test_bit(QL_ALLMULTI, &qdev->flags)) {
3436 if (ql_set_routing_reg
3437 (qdev, RT_IDX_ALLMULTI_SLOT, RT_IDX_MCAST, 0)) {
3438 QPRINTK(qdev, HW, ERR,
3439 "Failed to clear all-multi mode.\n");
3441 clear_bit(QL_ALLMULTI, &qdev->flags);
3446 if (ndev->mc_count) {
3447 status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
3450 for (i = 0, mc_ptr = ndev->mc_list; mc_ptr;
3451 i++, mc_ptr = mc_ptr->next)
3452 if (ql_set_mac_addr_reg(qdev, (u8 *) mc_ptr->dmi_addr,
3453 MAC_ADDR_TYPE_MULTI_MAC, i)) {
3454 QPRINTK(qdev, HW, ERR,
3455 "Failed to loadmulticast address.\n");
3456 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
3459 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
3460 if (ql_set_routing_reg
3461 (qdev, RT_IDX_MCAST_MATCH_SLOT, RT_IDX_MCAST_MATCH, 1)) {
3462 QPRINTK(qdev, HW, ERR,
3463 "Failed to set multicast match mode.\n");
3465 set_bit(QL_ALLMULTI, &qdev->flags);
3469 spin_unlock(&qdev->hw_lock);
3470 ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
3473 static int qlge_set_mac_address(struct net_device *ndev, void *p)
3475 struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3476 struct sockaddr *addr = p;
3479 if (netif_running(ndev))
3482 if (!is_valid_ether_addr(addr->sa_data))
3483 return -EADDRNOTAVAIL;
3484 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
3486 status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
3489 spin_lock(&qdev->hw_lock);
3490 status = ql_set_mac_addr_reg(qdev, (u8 *) ndev->dev_addr,
3491 MAC_ADDR_TYPE_CAM_MAC, qdev->func * MAX_CQ);
3492 spin_unlock(&qdev->hw_lock);
3494 QPRINTK(qdev, HW, ERR, "Failed to load MAC address.\n");
3495 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
3499 static void qlge_tx_timeout(struct net_device *ndev)
3501 struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3502 ql_queue_asic_error(qdev);
3505 static void ql_asic_reset_work(struct work_struct *work)
3507 struct ql_adapter *qdev =
3508 container_of(work, struct ql_adapter, asic_reset_work.work);
3509 ql_cycle_adapter(qdev);
3512 static void ql_get_board_info(struct ql_adapter *qdev)
3515 (ql_read32(qdev, STS) & STS_FUNC_ID_MASK) >> STS_FUNC_ID_SHIFT;
3517 qdev->xg_sem_mask = SEM_XGMAC1_MASK;
3518 qdev->port_link_up = STS_PL1;
3519 qdev->port_init = STS_PI1;
3520 qdev->mailbox_in = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC2_MBI;
3521 qdev->mailbox_out = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC2_MBO;
3523 qdev->xg_sem_mask = SEM_XGMAC0_MASK;
3524 qdev->port_link_up = STS_PL0;
3525 qdev->port_init = STS_PI0;
3526 qdev->mailbox_in = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC0_MBI;
3527 qdev->mailbox_out = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC0_MBO;
3529 qdev->chip_rev_id = ql_read32(qdev, REV_ID);
3532 static void ql_release_all(struct pci_dev *pdev)
3534 struct net_device *ndev = pci_get_drvdata(pdev);
3535 struct ql_adapter *qdev = netdev_priv(ndev);
3537 if (qdev->workqueue) {
3538 destroy_workqueue(qdev->workqueue);
3539 qdev->workqueue = NULL;
3541 if (qdev->q_workqueue) {
3542 destroy_workqueue(qdev->q_workqueue);
3543 qdev->q_workqueue = NULL;
3546 iounmap(qdev->reg_base);
3547 if (qdev->doorbell_area)
3548 iounmap(qdev->doorbell_area);
3549 pci_release_regions(pdev);
3550 pci_set_drvdata(pdev, NULL);
3553 static int __devinit ql_init_device(struct pci_dev *pdev,
3554 struct net_device *ndev, int cards_found)
3556 struct ql_adapter *qdev = netdev_priv(ndev);
3560 memset((void *)qdev, 0, sizeof(qdev));
3561 err = pci_enable_device(pdev);
3563 dev_err(&pdev->dev, "PCI device enable failed.\n");
3567 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3569 dev_err(&pdev->dev, PFX "Cannot find PCI Express capability, "
3573 pci_read_config_word(pdev, pos + PCI_EXP_DEVCTL, &val16);
3574 val16 &= ~PCI_EXP_DEVCTL_NOSNOOP_EN;
3575 val16 |= (PCI_EXP_DEVCTL_CERE |
3576 PCI_EXP_DEVCTL_NFERE |
3577 PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE);
3578 pci_write_config_word(pdev, pos + PCI_EXP_DEVCTL, val16);
3581 err = pci_request_regions(pdev, DRV_NAME);
3583 dev_err(&pdev->dev, "PCI region request failed.\n");
3587 pci_set_master(pdev);
3588 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
3589 set_bit(QL_DMA64, &qdev->flags);
3590 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3592 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3594 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3598 dev_err(&pdev->dev, "No usable DMA configuration.\n");
3602 pci_set_drvdata(pdev, ndev);
3604 ioremap_nocache(pci_resource_start(pdev, 1),
3605 pci_resource_len(pdev, 1));
3606 if (!qdev->reg_base) {
3607 dev_err(&pdev->dev, "Register mapping failed.\n");
3612 qdev->doorbell_area_size = pci_resource_len(pdev, 3);
3613 qdev->doorbell_area =
3614 ioremap_nocache(pci_resource_start(pdev, 3),
3615 pci_resource_len(pdev, 3));
3616 if (!qdev->doorbell_area) {
3617 dev_err(&pdev->dev, "Doorbell register mapping failed.\n");
3622 ql_get_board_info(qdev);
3625 qdev->msg_enable = netif_msg_init(debug, default_msg);
3626 spin_lock_init(&qdev->hw_lock);
3627 spin_lock_init(&qdev->stats_lock);
3629 /* make sure the EEPROM is good */
3630 err = ql_get_flash_params(qdev);
3632 dev_err(&pdev->dev, "Invalid FLASH.\n");
3636 if (!is_valid_ether_addr(qdev->flash.mac_addr))
3639 memcpy(ndev->dev_addr, qdev->flash.mac_addr, ndev->addr_len);
3640 memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
3642 /* Set up the default ring sizes. */
3643 qdev->tx_ring_size = NUM_TX_RING_ENTRIES;
3644 qdev->rx_ring_size = NUM_RX_RING_ENTRIES;
3646 /* Set up the coalescing parameters. */
3647 qdev->rx_coalesce_usecs = DFLT_COALESCE_WAIT;
3648 qdev->tx_coalesce_usecs = DFLT_COALESCE_WAIT;
3649 qdev->rx_max_coalesced_frames = DFLT_INTER_FRAME_WAIT;
3650 qdev->tx_max_coalesced_frames = DFLT_INTER_FRAME_WAIT;
3653 * Set up the operating parameters.
3657 qdev->q_workqueue = create_workqueue(ndev->name);
3658 qdev->workqueue = create_singlethread_workqueue(ndev->name);
3659 INIT_DELAYED_WORK(&qdev->asic_reset_work, ql_asic_reset_work);
3660 INIT_DELAYED_WORK(&qdev->mpi_reset_work, ql_mpi_reset_work);
3661 INIT_DELAYED_WORK(&qdev->mpi_work, ql_mpi_work);
3662 mutex_init(&qdev->mpi_mutex);
3665 dev_info(&pdev->dev, "%s\n", DRV_STRING);
3666 dev_info(&pdev->dev, "Driver name: %s, Version: %s.\n",
3667 DRV_NAME, DRV_VERSION);
3671 ql_release_all(pdev);
3672 pci_disable_device(pdev);
3677 static const struct net_device_ops qlge_netdev_ops = {
3678 .ndo_open = qlge_open,
3679 .ndo_stop = qlge_close,
3680 .ndo_start_xmit = qlge_send,
3681 .ndo_change_mtu = qlge_change_mtu,
3682 .ndo_get_stats = qlge_get_stats,
3683 .ndo_set_multicast_list = qlge_set_multicast_list,
3684 .ndo_set_mac_address = qlge_set_mac_address,
3685 .ndo_validate_addr = eth_validate_addr,
3686 .ndo_tx_timeout = qlge_tx_timeout,
3687 .ndo_vlan_rx_register = ql_vlan_rx_register,
3688 .ndo_vlan_rx_add_vid = ql_vlan_rx_add_vid,
3689 .ndo_vlan_rx_kill_vid = ql_vlan_rx_kill_vid,
3692 static int __devinit qlge_probe(struct pci_dev *pdev,
3693 const struct pci_device_id *pci_entry)
3695 struct net_device *ndev = NULL;
3696 struct ql_adapter *qdev = NULL;
3697 static int cards_found = 0;
3700 ndev = alloc_etherdev(sizeof(struct ql_adapter));
3704 err = ql_init_device(pdev, ndev, cards_found);
3710 qdev = netdev_priv(ndev);
3711 SET_NETDEV_DEV(ndev, &pdev->dev);
3718 | NETIF_F_HW_VLAN_TX
3719 | NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_FILTER);
3721 if (test_bit(QL_DMA64, &qdev->flags))
3722 ndev->features |= NETIF_F_HIGHDMA;
3725 * Set up net_device structure.
3727 ndev->tx_queue_len = qdev->tx_ring_size;
3728 ndev->irq = pdev->irq;
3730 ndev->netdev_ops = &qlge_netdev_ops;
3731 SET_ETHTOOL_OPS(ndev, &qlge_ethtool_ops);
3732 ndev->watchdog_timeo = 10 * HZ;
3734 err = register_netdev(ndev);
3736 dev_err(&pdev->dev, "net device registration failed.\n");
3737 ql_release_all(pdev);
3738 pci_disable_device(pdev);
3741 netif_carrier_off(ndev);
3742 netif_stop_queue(ndev);
3743 ql_display_dev_info(ndev);
3748 static void __devexit qlge_remove(struct pci_dev *pdev)
3750 struct net_device *ndev = pci_get_drvdata(pdev);
3751 unregister_netdev(ndev);
3752 ql_release_all(pdev);
3753 pci_disable_device(pdev);
3758 * This callback is called by the PCI subsystem whenever
3759 * a PCI bus error is detected.
3761 static pci_ers_result_t qlge_io_error_detected(struct pci_dev *pdev,
3762 enum pci_channel_state state)
3764 struct net_device *ndev = pci_get_drvdata(pdev);
3765 struct ql_adapter *qdev = netdev_priv(ndev);
3767 if (netif_running(ndev))
3768 ql_adapter_down(qdev);
3770 pci_disable_device(pdev);
3772 /* Request a slot reset. */
3773 return PCI_ERS_RESULT_NEED_RESET;
3777 * This callback is called after the PCI buss has been reset.
3778 * Basically, this tries to restart the card from scratch.
3779 * This is a shortened version of the device probe/discovery code,
3780 * it resembles the first-half of the () routine.
3782 static pci_ers_result_t qlge_io_slot_reset(struct pci_dev *pdev)
3784 struct net_device *ndev = pci_get_drvdata(pdev);
3785 struct ql_adapter *qdev = netdev_priv(ndev);
3787 if (pci_enable_device(pdev)) {
3788 QPRINTK(qdev, IFUP, ERR,
3789 "Cannot re-enable PCI device after reset.\n");
3790 return PCI_ERS_RESULT_DISCONNECT;
3793 pci_set_master(pdev);
3795 netif_carrier_off(ndev);
3796 netif_stop_queue(ndev);
3797 ql_adapter_reset(qdev);
3799 /* Make sure the EEPROM is good */
3800 memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
3802 if (!is_valid_ether_addr(ndev->perm_addr)) {
3803 QPRINTK(qdev, IFUP, ERR, "After reset, invalid MAC address.\n");
3804 return PCI_ERS_RESULT_DISCONNECT;
3807 return PCI_ERS_RESULT_RECOVERED;
3810 static void qlge_io_resume(struct pci_dev *pdev)
3812 struct net_device *ndev = pci_get_drvdata(pdev);
3813 struct ql_adapter *qdev = netdev_priv(ndev);
3815 pci_set_master(pdev);
3817 if (netif_running(ndev)) {
3818 if (ql_adapter_up(qdev)) {
3819 QPRINTK(qdev, IFUP, ERR,
3820 "Device initialization failed after reset.\n");
3825 netif_device_attach(ndev);
3828 static struct pci_error_handlers qlge_err_handler = {
3829 .error_detected = qlge_io_error_detected,
3830 .slot_reset = qlge_io_slot_reset,
3831 .resume = qlge_io_resume,
3834 static int qlge_suspend(struct pci_dev *pdev, pm_message_t state)
3836 struct net_device *ndev = pci_get_drvdata(pdev);
3837 struct ql_adapter *qdev = netdev_priv(ndev);
3840 netif_device_detach(ndev);
3842 if (netif_running(ndev)) {
3843 err = ql_adapter_down(qdev);
3848 for (i = qdev->rss_ring_first_cq_id; i < qdev->rx_ring_count; i++)
3849 netif_napi_del(&qdev->rx_ring[i].napi);
3851 err = pci_save_state(pdev);
3855 pci_disable_device(pdev);
3857 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3863 static int qlge_resume(struct pci_dev *pdev)
3865 struct net_device *ndev = pci_get_drvdata(pdev);
3866 struct ql_adapter *qdev = netdev_priv(ndev);
3869 pci_set_power_state(pdev, PCI_D0);
3870 pci_restore_state(pdev);
3871 err = pci_enable_device(pdev);
3873 QPRINTK(qdev, IFUP, ERR, "Cannot enable PCI device from suspend\n");
3876 pci_set_master(pdev);
3878 pci_enable_wake(pdev, PCI_D3hot, 0);
3879 pci_enable_wake(pdev, PCI_D3cold, 0);
3881 if (netif_running(ndev)) {
3882 err = ql_adapter_up(qdev);
3887 netif_device_attach(ndev);
3891 #endif /* CONFIG_PM */
3893 static void qlge_shutdown(struct pci_dev *pdev)
3895 qlge_suspend(pdev, PMSG_SUSPEND);
3898 static struct pci_driver qlge_driver = {
3900 .id_table = qlge_pci_tbl,
3901 .probe = qlge_probe,
3902 .remove = __devexit_p(qlge_remove),
3904 .suspend = qlge_suspend,
3905 .resume = qlge_resume,
3907 .shutdown = qlge_shutdown,
3908 .err_handler = &qlge_err_handler
3911 static int __init qlge_init_module(void)
3913 return pci_register_driver(&qlge_driver);
3916 static void __exit qlge_exit(void)
3918 pci_unregister_driver(&qlge_driver);
3921 module_init(qlge_init_module);
3922 module_exit(qlge_exit);