1 /******************************************************************************
5 * Copyright(c) 2008 Intel Corporation. All rights reserved.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
24 * Contact Information:
25 * Tomas Winkler <tomas.winkler@intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *****************************************************************************/
29 #include <linux/kernel.h>
30 #include <linux/module.h>
31 #include <net/mac80211.h>
33 struct iwl_priv; /* FIXME: remove */
34 #include "iwl-debug.h"
35 #include "iwl-eeprom.h"
36 #include "iwl-dev.h" /* FIXME: remove */
39 #include "iwl-rfkill.h"
40 #include "iwl-power.h"
43 MODULE_DESCRIPTION("iwl core");
44 MODULE_VERSION(IWLWIFI_VERSION);
45 MODULE_AUTHOR(DRV_COPYRIGHT);
46 MODULE_LICENSE("GPL");
48 #define IWL_DECLARE_RATE_INFO(r, s, ip, in, rp, rn, pp, np) \
49 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
50 IWL_RATE_SISO_##s##M_PLCP, \
51 IWL_RATE_MIMO2_##s##M_PLCP,\
52 IWL_RATE_MIMO3_##s##M_PLCP,\
53 IWL_RATE_##r##M_IEEE, \
54 IWL_RATE_##ip##M_INDEX, \
55 IWL_RATE_##in##M_INDEX, \
56 IWL_RATE_##rp##M_INDEX, \
57 IWL_RATE_##rn##M_INDEX, \
58 IWL_RATE_##pp##M_INDEX, \
59 IWL_RATE_##np##M_INDEX }
63 * rate, ht rate, prev rate, next rate, prev tgg rate, next tgg rate
65 * If there isn't a valid next or previous rate then INV is used which
66 * maps to IWL_RATE_INVALID
69 const struct iwl_rate_info iwl_rates[IWL_RATE_COUNT] = {
70 IWL_DECLARE_RATE_INFO(1, INV, INV, 2, INV, 2, INV, 2), /* 1mbps */
71 IWL_DECLARE_RATE_INFO(2, INV, 1, 5, 1, 5, 1, 5), /* 2mbps */
72 IWL_DECLARE_RATE_INFO(5, INV, 2, 6, 2, 11, 2, 11), /*5.5mbps */
73 IWL_DECLARE_RATE_INFO(11, INV, 9, 12, 9, 12, 5, 18), /* 11mbps */
74 IWL_DECLARE_RATE_INFO(6, 6, 5, 9, 5, 11, 5, 11), /* 6mbps */
75 IWL_DECLARE_RATE_INFO(9, 6, 6, 11, 6, 11, 5, 11), /* 9mbps */
76 IWL_DECLARE_RATE_INFO(12, 12, 11, 18, 11, 18, 11, 18), /* 12mbps */
77 IWL_DECLARE_RATE_INFO(18, 18, 12, 24, 12, 24, 11, 24), /* 18mbps */
78 IWL_DECLARE_RATE_INFO(24, 24, 18, 36, 18, 36, 18, 36), /* 24mbps */
79 IWL_DECLARE_RATE_INFO(36, 36, 24, 48, 24, 48, 24, 48), /* 36mbps */
80 IWL_DECLARE_RATE_INFO(48, 48, 36, 54, 36, 54, 36, 54), /* 48mbps */
81 IWL_DECLARE_RATE_INFO(54, 54, 48, INV, 48, INV, 48, INV),/* 54mbps */
82 IWL_DECLARE_RATE_INFO(60, 60, 48, INV, 48, INV, 48, INV),/* 60mbps */
83 /* FIXME:RS: ^^ should be INV (legacy) */
85 EXPORT_SYMBOL(iwl_rates);
88 * translate ucode response to mac80211 tx status control values
90 void iwl_hwrate_to_tx_control(struct iwl_priv *priv, u32 rate_n_flags,
91 struct ieee80211_tx_info *control)
95 control->antenna_sel_tx =
96 ((rate_n_flags & RATE_MCS_ANT_ABC_MSK) >> RATE_MCS_ANT_POS);
97 if (rate_n_flags & RATE_MCS_HT_MSK)
98 control->flags |= IEEE80211_TX_CTL_OFDM_HT;
99 if (rate_n_flags & RATE_MCS_GF_MSK)
100 control->flags |= IEEE80211_TX_CTL_GREEN_FIELD;
101 if (rate_n_flags & RATE_MCS_FAT_MSK)
102 control->flags |= IEEE80211_TX_CTL_40_MHZ_WIDTH;
103 if (rate_n_flags & RATE_MCS_DUP_MSK)
104 control->flags |= IEEE80211_TX_CTL_DUP_DATA;
105 if (rate_n_flags & RATE_MCS_SGI_MSK)
106 control->flags |= IEEE80211_TX_CTL_SHORT_GI;
107 rate_index = iwl_hwrate_to_plcp_idx(rate_n_flags);
108 if (control->band == IEEE80211_BAND_5GHZ)
109 rate_index -= IWL_FIRST_OFDM_RATE;
110 control->tx_rate_idx = rate_index;
112 EXPORT_SYMBOL(iwl_hwrate_to_tx_control);
114 int iwl_hwrate_to_plcp_idx(u32 rate_n_flags)
119 if (rate_n_flags & RATE_MCS_HT_MSK) {
120 idx = (rate_n_flags & 0xff);
122 if (idx >= IWL_RATE_MIMO2_6M_PLCP)
123 idx = idx - IWL_RATE_MIMO2_6M_PLCP;
125 idx += IWL_FIRST_OFDM_RATE;
126 /* skip 9M not supported in ht*/
127 if (idx >= IWL_RATE_9M_INDEX)
129 if ((idx >= IWL_FIRST_OFDM_RATE) && (idx <= IWL_LAST_OFDM_RATE))
132 /* legacy rate format, search for match in table */
134 for (idx = 0; idx < ARRAY_SIZE(iwl_rates); idx++)
135 if (iwl_rates[idx].plcp == (rate_n_flags & 0xFF))
141 EXPORT_SYMBOL(iwl_hwrate_to_plcp_idx);
145 const u8 iwl_bcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
146 EXPORT_SYMBOL(iwl_bcast_addr);
149 /* This function both allocates and initializes hw and priv. */
150 struct ieee80211_hw *iwl_alloc_all(struct iwl_cfg *cfg,
151 struct ieee80211_ops *hw_ops)
153 struct iwl_priv *priv;
155 /* mac80211 allocates memory for this device instance, including
156 * space for this driver's private structure */
157 struct ieee80211_hw *hw =
158 ieee80211_alloc_hw(sizeof(struct iwl_priv), hw_ops);
160 IWL_ERROR("Can not allocate network device\n");
170 EXPORT_SYMBOL(iwl_alloc_all);
172 void iwl_hw_detect(struct iwl_priv *priv)
174 priv->hw_rev = _iwl_read32(priv, CSR_HW_REV);
175 priv->hw_wa_rev = _iwl_read32(priv, CSR_HW_REV_WA_REG);
176 pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &priv->rev_id);
178 EXPORT_SYMBOL(iwl_hw_detect);
180 /* Tell nic where to find the "keep warm" buffer */
181 int iwl_kw_init(struct iwl_priv *priv)
186 spin_lock_irqsave(&priv->lock, flags);
187 ret = iwl_grab_nic_access(priv);
191 iwl_write_direct32(priv, FH_KW_MEM_ADDR_REG,
192 priv->kw.dma_addr >> 4);
193 iwl_release_nic_access(priv);
195 spin_unlock_irqrestore(&priv->lock, flags);
199 int iwl_kw_alloc(struct iwl_priv *priv)
201 struct pci_dev *dev = priv->pci_dev;
202 struct iwl_kw *kw = &priv->kw;
204 kw->size = IWL_KW_SIZE;
205 kw->v_addr = pci_alloc_consistent(dev, kw->size, &kw->dma_addr);
213 * iwl_kw_free - Free the "keep warm" buffer
215 void iwl_kw_free(struct iwl_priv *priv)
217 struct pci_dev *dev = priv->pci_dev;
218 struct iwl_kw *kw = &priv->kw;
221 pci_free_consistent(dev, kw->size, kw->v_addr, kw->dma_addr);
222 memset(kw, 0, sizeof(*kw));
226 int iwl_hw_nic_init(struct iwl_priv *priv)
229 struct iwl_rx_queue *rxq = &priv->rxq;
233 spin_lock_irqsave(&priv->lock, flags);
234 priv->cfg->ops->lib->apm_ops.init(priv);
235 iwl_write32(priv, CSR_INT_COALESCING, 512 / 32);
236 spin_unlock_irqrestore(&priv->lock, flags);
238 ret = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
240 priv->cfg->ops->lib->apm_ops.config(priv);
242 /* Allocate the RX queue, or reset if it is already allocated */
244 ret = iwl_rx_queue_alloc(priv);
246 IWL_ERROR("Unable to initialize Rx queue\n");
250 iwl_rx_queue_reset(priv, rxq);
252 iwl_rx_replenish(priv);
254 iwl_rx_init(priv, rxq);
256 spin_lock_irqsave(&priv->lock, flags);
258 rxq->need_update = 1;
259 iwl_rx_queue_update_write_ptr(priv, rxq);
261 spin_unlock_irqrestore(&priv->lock, flags);
263 /* Allocate and init all Tx and Command queues */
264 ret = iwl_txq_ctx_reset(priv);
268 set_bit(STATUS_INIT, &priv->status);
272 EXPORT_SYMBOL(iwl_hw_nic_init);
275 * iwl_clear_stations_table - Clear the driver's station table
277 * NOTE: This does not clear or otherwise alter the device's station table.
279 void iwl_clear_stations_table(struct iwl_priv *priv)
283 spin_lock_irqsave(&priv->sta_lock, flags);
285 if (iwl_is_alive(priv) &&
286 !test_bit(STATUS_EXIT_PENDING, &priv->status) &&
287 iwl_send_cmd_pdu_async(priv, REPLY_REMOVE_ALL_STA, 0, NULL, NULL))
288 IWL_ERROR("Couldn't clear the station table\n");
290 priv->num_stations = 0;
291 memset(priv->stations, 0, sizeof(priv->stations));
293 spin_unlock_irqrestore(&priv->sta_lock, flags);
295 EXPORT_SYMBOL(iwl_clear_stations_table);
297 void iwl_reset_qos(struct iwl_priv *priv)
306 spin_lock_irqsave(&priv->lock, flags);
307 priv->qos_data.qos_active = 0;
309 if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS) {
310 if (priv->qos_data.qos_enable)
311 priv->qos_data.qos_active = 1;
312 if (!(priv->active_rate & 0xfff0)) {
316 } else if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
317 if (priv->qos_data.qos_enable)
318 priv->qos_data.qos_active = 1;
319 } else if (!(priv->staging_rxon.flags & RXON_FLG_SHORT_SLOT_MSK)) {
324 if (priv->qos_data.qos_active)
327 priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min);
328 priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max);
329 priv->qos_data.def_qos_parm.ac[0].aifsn = aifs;
330 priv->qos_data.def_qos_parm.ac[0].edca_txop = 0;
331 priv->qos_data.def_qos_parm.ac[0].reserved1 = 0;
333 if (priv->qos_data.qos_active) {
335 priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min);
336 priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max);
337 priv->qos_data.def_qos_parm.ac[i].aifsn = 7;
338 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
339 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
342 priv->qos_data.def_qos_parm.ac[i].cw_min =
343 cpu_to_le16((cw_min + 1) / 2 - 1);
344 priv->qos_data.def_qos_parm.ac[i].cw_max =
346 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
348 priv->qos_data.def_qos_parm.ac[i].edca_txop =
351 priv->qos_data.def_qos_parm.ac[i].edca_txop =
353 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
356 priv->qos_data.def_qos_parm.ac[i].cw_min =
357 cpu_to_le16((cw_min + 1) / 4 - 1);
358 priv->qos_data.def_qos_parm.ac[i].cw_max =
359 cpu_to_le16((cw_max + 1) / 2 - 1);
360 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
361 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
363 priv->qos_data.def_qos_parm.ac[i].edca_txop =
366 priv->qos_data.def_qos_parm.ac[i].edca_txop =
369 for (i = 1; i < 4; i++) {
370 priv->qos_data.def_qos_parm.ac[i].cw_min =
372 priv->qos_data.def_qos_parm.ac[i].cw_max =
374 priv->qos_data.def_qos_parm.ac[i].aifsn = aifs;
375 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
376 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
379 IWL_DEBUG_QOS("set QoS to default \n");
381 spin_unlock_irqrestore(&priv->lock, flags);
383 EXPORT_SYMBOL(iwl_reset_qos);
385 #define MAX_BIT_RATE_40_MHZ 0x96 /* 150 Mbps */
386 #define MAX_BIT_RATE_20_MHZ 0x48 /* 72 Mbps */
387 static void iwlcore_init_ht_hw_capab(const struct iwl_priv *priv,
388 struct ieee80211_ht_info *ht_info,
389 enum ieee80211_band band)
391 u16 max_bit_rate = 0;
392 u8 rx_chains_num = priv->hw_params.rx_chains_num;
393 u8 tx_chains_num = priv->hw_params.tx_chains_num;
396 memset(ht_info->supp_mcs_set, 0, 16);
398 ht_info->ht_supported = 1;
400 ht_info->cap |= (u16)IEEE80211_HT_CAP_GRN_FLD;
401 ht_info->cap |= (u16)IEEE80211_HT_CAP_SGI_20;
402 ht_info->cap |= (u16)(IEEE80211_HT_CAP_SM_PS &
403 (WLAN_HT_CAP_SM_PS_DISABLED << 2));
405 max_bit_rate = MAX_BIT_RATE_20_MHZ;
406 if (priv->hw_params.fat_channel & BIT(band)) {
407 ht_info->cap |= (u16)IEEE80211_HT_CAP_SUP_WIDTH;
408 ht_info->cap |= (u16)IEEE80211_HT_CAP_SGI_40;
409 ht_info->supp_mcs_set[4] = 0x01;
410 max_bit_rate = MAX_BIT_RATE_40_MHZ;
413 if (priv->cfg->mod_params->amsdu_size_8K)
414 ht_info->cap |= (u16)IEEE80211_HT_CAP_MAX_AMSDU;
416 ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF;
417 ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF;
419 ht_info->supp_mcs_set[0] = 0xFF;
420 if (rx_chains_num >= 2)
421 ht_info->supp_mcs_set[1] = 0xFF;
422 if (rx_chains_num >= 3)
423 ht_info->supp_mcs_set[2] = 0xFF;
425 /* Highest supported Rx data rate */
426 max_bit_rate *= rx_chains_num;
427 ht_info->supp_mcs_set[10] = (u8)(max_bit_rate & 0x00FF);
428 ht_info->supp_mcs_set[11] = (u8)((max_bit_rate & 0xFF00) >> 8);
430 /* Tx MCS capabilities */
431 ht_info->supp_mcs_set[12] = IEEE80211_HT_CAP_MCS_TX_DEFINED;
432 if (tx_chains_num != rx_chains_num) {
433 ht_info->supp_mcs_set[12] |= IEEE80211_HT_CAP_MCS_TX_RX_DIFF;
434 ht_info->supp_mcs_set[12] |= ((tx_chains_num - 1) << 2);
438 static void iwlcore_init_hw_rates(struct iwl_priv *priv,
439 struct ieee80211_rate *rates)
443 for (i = 0; i < IWL_RATE_COUNT; i++) {
444 rates[i].bitrate = iwl_rates[i].ieee * 5;
445 rates[i].hw_value = i; /* Rate scaling will work on indexes */
446 rates[i].hw_value_short = i;
448 if ((i > IWL_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) {
450 * If CCK != 1M then set short preamble rate flag.
453 (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
454 0 : IEEE80211_RATE_SHORT_PREAMBLE;
460 * iwlcore_init_geos - Initialize mac80211's geo/channel info based from eeprom
462 static int iwlcore_init_geos(struct iwl_priv *priv)
464 struct iwl_channel_info *ch;
465 struct ieee80211_supported_band *sband;
466 struct ieee80211_channel *channels;
467 struct ieee80211_channel *geo_ch;
468 struct ieee80211_rate *rates;
471 if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
472 priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
473 IWL_DEBUG_INFO("Geography modes already initialized.\n");
474 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
478 channels = kzalloc(sizeof(struct ieee80211_channel) *
479 priv->channel_count, GFP_KERNEL);
483 rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_RATE_COUNT + 1)),
490 /* 5.2GHz channels start after the 2.4GHz channels */
491 sband = &priv->bands[IEEE80211_BAND_5GHZ];
492 sband->channels = &channels[ARRAY_SIZE(iwl_eeprom_band_1)];
494 sband->bitrates = &rates[IWL_FIRST_OFDM_RATE];
495 sband->n_bitrates = IWL_RATE_COUNT - IWL_FIRST_OFDM_RATE;
497 if (priv->cfg->sku & IWL_SKU_N)
498 iwlcore_init_ht_hw_capab(priv, &sband->ht_info,
499 IEEE80211_BAND_5GHZ);
501 sband = &priv->bands[IEEE80211_BAND_2GHZ];
502 sband->channels = channels;
504 sband->bitrates = rates;
505 sband->n_bitrates = IWL_RATE_COUNT;
507 if (priv->cfg->sku & IWL_SKU_N)
508 iwlcore_init_ht_hw_capab(priv, &sband->ht_info,
509 IEEE80211_BAND_2GHZ);
511 priv->ieee_channels = channels;
512 priv->ieee_rates = rates;
514 iwlcore_init_hw_rates(priv, rates);
516 for (i = 0; i < priv->channel_count; i++) {
517 ch = &priv->channel_info[i];
519 /* FIXME: might be removed if scan is OK */
520 if (!is_channel_valid(ch))
523 if (is_channel_a_band(ch))
524 sband = &priv->bands[IEEE80211_BAND_5GHZ];
526 sband = &priv->bands[IEEE80211_BAND_2GHZ];
528 geo_ch = &sband->channels[sband->n_channels++];
530 geo_ch->center_freq =
531 ieee80211_channel_to_frequency(ch->channel);
532 geo_ch->max_power = ch->max_power_avg;
533 geo_ch->max_antenna_gain = 0xff;
534 geo_ch->hw_value = ch->channel;
536 if (is_channel_valid(ch)) {
537 if (!(ch->flags & EEPROM_CHANNEL_IBSS))
538 geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
540 if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
541 geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
543 if (ch->flags & EEPROM_CHANNEL_RADAR)
544 geo_ch->flags |= IEEE80211_CHAN_RADAR;
546 geo_ch->flags |= ch->fat_extension_channel;
548 if (ch->max_power_avg > priv->tx_power_channel_lmt)
549 priv->tx_power_channel_lmt = ch->max_power_avg;
551 geo_ch->flags |= IEEE80211_CHAN_DISABLED;
554 /* Save flags for reg domain usage */
555 geo_ch->orig_flags = geo_ch->flags;
557 IWL_DEBUG_INFO("Channel %d Freq=%d[%sGHz] %s flag=0x%X\n",
558 ch->channel, geo_ch->center_freq,
559 is_channel_a_band(ch) ? "5.2" : "2.4",
560 geo_ch->flags & IEEE80211_CHAN_DISABLED ?
561 "restricted" : "valid",
565 if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) &&
566 priv->cfg->sku & IWL_SKU_A) {
567 printk(KERN_INFO DRV_NAME
568 ": Incorrectly detected BG card as ABG. Please send "
569 "your PCI ID 0x%04X:0x%04X to maintainer.\n",
570 priv->pci_dev->device, priv->pci_dev->subsystem_device);
571 priv->cfg->sku &= ~IWL_SKU_A;
574 printk(KERN_INFO DRV_NAME
575 ": Tunable channels: %d 802.11bg, %d 802.11a channels\n",
576 priv->bands[IEEE80211_BAND_2GHZ].n_channels,
577 priv->bands[IEEE80211_BAND_5GHZ].n_channels);
580 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
586 * iwlcore_free_geos - undo allocations in iwlcore_init_geos
588 static void iwlcore_free_geos(struct iwl_priv *priv)
590 kfree(priv->ieee_channels);
591 kfree(priv->ieee_rates);
592 clear_bit(STATUS_GEO_CONFIGURED, &priv->status);
595 static bool is_single_rx_stream(struct iwl_priv *priv)
597 return !priv->current_ht_config.is_ht ||
598 ((priv->current_ht_config.supp_mcs_set[1] == 0) &&
599 (priv->current_ht_config.supp_mcs_set[2] == 0));
602 static u8 iwl_is_channel_extension(struct iwl_priv *priv,
603 enum ieee80211_band band,
604 u16 channel, u8 extension_chan_offset)
606 const struct iwl_channel_info *ch_info;
608 ch_info = iwl_get_channel_info(priv, band, channel);
609 if (!is_channel_valid(ch_info))
612 if (extension_chan_offset == IEEE80211_HT_IE_CHA_SEC_ABOVE)
613 return !(ch_info->fat_extension_channel &
614 IEEE80211_CHAN_NO_FAT_ABOVE);
615 else if (extension_chan_offset == IEEE80211_HT_IE_CHA_SEC_BELOW)
616 return !(ch_info->fat_extension_channel &
617 IEEE80211_CHAN_NO_FAT_BELOW);
622 u8 iwl_is_fat_tx_allowed(struct iwl_priv *priv,
623 struct ieee80211_ht_info *sta_ht_inf)
625 struct iwl_ht_info *iwl_ht_conf = &priv->current_ht_config;
627 if ((!iwl_ht_conf->is_ht) ||
628 (iwl_ht_conf->supported_chan_width != IWL_CHANNEL_WIDTH_40MHZ) ||
629 (iwl_ht_conf->extension_chan_offset == IEEE80211_HT_IE_CHA_SEC_NONE))
633 if ((!sta_ht_inf->ht_supported) ||
634 (!(sta_ht_inf->cap & IEEE80211_HT_CAP_SUP_WIDTH)))
638 return iwl_is_channel_extension(priv, priv->band,
639 iwl_ht_conf->control_channel,
640 iwl_ht_conf->extension_chan_offset);
642 EXPORT_SYMBOL(iwl_is_fat_tx_allowed);
644 void iwl_set_rxon_ht(struct iwl_priv *priv, struct iwl_ht_info *ht_info)
646 struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
652 /* Set up channel bandwidth: 20 MHz only, or 20/40 mixed if fat ok */
653 if (iwl_is_fat_tx_allowed(priv, NULL))
654 rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED_MSK;
656 rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED_MSK |
657 RXON_FLG_CHANNEL_MODE_PURE_40_MSK);
659 if (le16_to_cpu(rxon->channel) != ht_info->control_channel) {
660 IWL_DEBUG_ASSOC("control diff than current %d %d\n",
661 le16_to_cpu(rxon->channel),
662 ht_info->control_channel);
666 /* Note: control channel is opposite of extension channel */
667 switch (ht_info->extension_chan_offset) {
668 case IEEE80211_HT_IE_CHA_SEC_ABOVE:
669 rxon->flags &= ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
671 case IEEE80211_HT_IE_CHA_SEC_BELOW:
672 rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
674 case IEEE80211_HT_IE_CHA_SEC_NONE:
676 rxon->flags &= ~RXON_FLG_CHANNEL_MODE_MIXED_MSK;
680 val = ht_info->ht_protection;
682 rxon->flags |= cpu_to_le32(val << RXON_FLG_HT_OPERATING_MODE_POS);
684 iwl_set_rxon_chain(priv);
686 IWL_DEBUG_ASSOC("supported HT rate 0x%X 0x%X 0x%X "
687 "rxon flags 0x%X operation mode :0x%X "
688 "extension channel offset 0x%x "
690 ht_info->supp_mcs_set[0],
691 ht_info->supp_mcs_set[1],
692 ht_info->supp_mcs_set[2],
693 le32_to_cpu(rxon->flags), ht_info->ht_protection,
694 ht_info->extension_chan_offset,
695 ht_info->control_channel);
698 EXPORT_SYMBOL(iwl_set_rxon_ht);
701 * Determine how many receiver/antenna chains to use.
702 * More provides better reception via diversity. Fewer saves power.
703 * MIMO (dual stream) requires at least 2, but works better with 3.
704 * This does not determine *which* chains to use, just how many.
706 static int iwl_get_active_rx_chain_count(struct iwl_priv *priv)
708 bool is_single = is_single_rx_stream(priv);
709 bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
711 /* # of Rx chains to use when expecting MIMO. */
712 if (is_single || (!is_cam && (priv->current_ht_config.sm_ps ==
713 WLAN_HT_CAP_SM_PS_STATIC)))
719 static int iwl_get_idle_rx_chain_count(struct iwl_priv *priv, int active_cnt)
722 bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
723 /* # Rx chains when idling and maybe trying to save power */
724 switch (priv->current_ht_config.sm_ps) {
725 case WLAN_HT_CAP_SM_PS_STATIC:
726 case WLAN_HT_CAP_SM_PS_DYNAMIC:
727 idle_cnt = (is_cam) ? 2 : 1;
729 case WLAN_HT_CAP_SM_PS_DISABLED:
730 idle_cnt = (is_cam) ? active_cnt : 1;
732 case WLAN_HT_CAP_SM_PS_INVALID:
734 IWL_ERROR("invalide mimo ps mode %d\n",
735 priv->current_ht_config.sm_ps);
744 * iwl_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
746 * Selects how many and which Rx receivers/antennas/chains to use.
747 * This should not be used for scan command ... it puts data in wrong place.
749 void iwl_set_rxon_chain(struct iwl_priv *priv)
751 bool is_single = is_single_rx_stream(priv);
752 bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
753 u8 idle_rx_cnt, active_rx_cnt;
756 /* Tell uCode which antennas are actually connected.
757 * Before first association, we assume all antennas are connected.
758 * Just after first association, iwl_chain_noise_calibration()
759 * checks which antennas actually *are* connected. */
760 rx_chain = priv->hw_params.valid_rx_ant << RXON_RX_CHAIN_VALID_POS;
762 /* How many receivers should we use? */
763 active_rx_cnt = iwl_get_active_rx_chain_count(priv);
764 idle_rx_cnt = iwl_get_idle_rx_chain_count(priv, active_rx_cnt);
766 /* correct rx chain count accoridng hw settings */
767 if (priv->hw_params.rx_chains_num < active_rx_cnt)
768 active_rx_cnt = priv->hw_params.rx_chains_num;
770 if (priv->hw_params.rx_chains_num < idle_rx_cnt)
771 idle_rx_cnt = priv->hw_params.rx_chains_num;
773 rx_chain |= active_rx_cnt << RXON_RX_CHAIN_MIMO_CNT_POS;
774 rx_chain |= idle_rx_cnt << RXON_RX_CHAIN_CNT_POS;
776 priv->staging_rxon.rx_chain = cpu_to_le16(rx_chain);
778 if (!is_single && (active_rx_cnt >= 2) && is_cam)
779 priv->staging_rxon.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
781 priv->staging_rxon.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
783 IWL_DEBUG_ASSOC("rx_chain=0x%Xi active=%d idle=%d\n",
784 priv->staging_rxon.rx_chain,
785 active_rx_cnt, idle_rx_cnt);
787 WARN_ON(active_rx_cnt == 0 || idle_rx_cnt == 0 ||
788 active_rx_cnt < idle_rx_cnt);
790 EXPORT_SYMBOL(iwl_set_rxon_chain);
793 * iwl_set_rxon_channel - Set the phymode and channel values in staging RXON
794 * @phymode: MODE_IEEE80211A sets to 5.2GHz; all else set to 2.4GHz
795 * @channel: Any channel valid for the requested phymode
797 * In addition to setting the staging RXON, priv->phymode is also set.
799 * NOTE: Does not commit to the hardware; it sets appropriate bit fields
800 * in the staging RXON flag structure based on the phymode
802 int iwl_set_rxon_channel(struct iwl_priv *priv, struct ieee80211_channel *ch)
804 enum ieee80211_band band = ch->band;
805 u16 channel = ieee80211_frequency_to_channel(ch->center_freq);
807 if (!iwl_get_channel_info(priv, band, channel)) {
808 IWL_DEBUG_INFO("Could not set channel to %d [%d]\n",
813 if ((le16_to_cpu(priv->staging_rxon.channel) == channel) &&
814 (priv->band == band))
817 priv->staging_rxon.channel = cpu_to_le16(channel);
818 if (band == IEEE80211_BAND_5GHZ)
819 priv->staging_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
821 priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
825 IWL_DEBUG_INFO("Staging channel set to %d [%d]\n", channel, band);
829 EXPORT_SYMBOL(iwl_set_rxon_channel);
831 int iwl_setup_mac(struct iwl_priv *priv)
834 struct ieee80211_hw *hw = priv->hw;
835 hw->rate_control_algorithm = "iwl-agn-rs";
837 /* Tell mac80211 our characteristics */
838 hw->flags = IEEE80211_HW_SIGNAL_DBM |
839 IEEE80211_HW_NOISE_DBM;
840 hw->wiphy->interface_modes =
841 BIT(NL80211_IFTYPE_AP) |
842 BIT(NL80211_IFTYPE_STATION) |
843 BIT(NL80211_IFTYPE_ADHOC);
844 /* Default value; 4 EDCA QOS priorities */
846 /* queues to support 11n aggregation */
847 if (priv->cfg->sku & IWL_SKU_N)
848 hw->ampdu_queues = priv->cfg->mod_params->num_of_ampdu_queues;
850 hw->conf.beacon_int = 100;
851 hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
853 if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
854 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
855 &priv->bands[IEEE80211_BAND_2GHZ];
856 if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
857 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
858 &priv->bands[IEEE80211_BAND_5GHZ];
860 ret = ieee80211_register_hw(priv->hw);
862 IWL_ERROR("Failed to register hw (error %d)\n", ret);
865 priv->mac80211_registered = 1;
869 EXPORT_SYMBOL(iwl_setup_mac);
871 int iwl_set_hw_params(struct iwl_priv *priv)
873 priv->hw_params.sw_crypto = priv->cfg->mod_params->sw_crypto;
874 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
875 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
876 if (priv->cfg->mod_params->amsdu_size_8K)
877 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_8K;
879 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_4K;
880 priv->hw_params.max_pkt_size = priv->hw_params.rx_buf_size - 256;
882 if (priv->cfg->mod_params->disable_11n)
883 priv->cfg->sku &= ~IWL_SKU_N;
885 /* Device-specific setup */
886 return priv->cfg->ops->lib->set_hw_params(priv);
888 EXPORT_SYMBOL(iwl_set_hw_params);
890 int iwl_init_drv(struct iwl_priv *priv)
894 priv->retry_rate = 1;
895 priv->ibss_beacon = NULL;
897 spin_lock_init(&priv->lock);
898 spin_lock_init(&priv->power_data.lock);
899 spin_lock_init(&priv->sta_lock);
900 spin_lock_init(&priv->hcmd_lock);
902 INIT_LIST_HEAD(&priv->free_frames);
904 mutex_init(&priv->mutex);
906 /* Clear the driver's (not device's) station table */
907 iwl_clear_stations_table(priv);
909 priv->data_retry_limit = -1;
910 priv->ieee_channels = NULL;
911 priv->ieee_rates = NULL;
912 priv->band = IEEE80211_BAND_2GHZ;
914 priv->iw_mode = IEEE80211_IF_TYPE_STA;
916 priv->use_ant_b_for_management_frame = 1; /* start with ant B */
917 priv->current_ht_config.sm_ps = WLAN_HT_CAP_SM_PS_DISABLED;
919 /* Choose which receivers/antennas to use */
920 iwl_set_rxon_chain(priv);
921 iwl_init_scan_params(priv);
923 if (priv->cfg->mod_params->enable_qos)
924 priv->qos_data.qos_enable = 1;
928 priv->qos_data.qos_active = 0;
929 priv->qos_data.qos_cap.val = 0;
931 priv->rates_mask = IWL_RATES_MASK;
932 /* If power management is turned on, default to AC mode */
933 priv->power_mode = IWL_POWER_AC;
934 priv->tx_power_user_lmt = IWL_TX_POWER_TARGET_POWER_MAX;
936 ret = iwl_init_channel_map(priv);
938 IWL_ERROR("initializing regulatory failed: %d\n", ret);
942 ret = iwlcore_init_geos(priv);
944 IWL_ERROR("initializing geos failed: %d\n", ret);
945 goto err_free_channel_map;
950 err_free_channel_map:
951 iwl_free_channel_map(priv);
955 EXPORT_SYMBOL(iwl_init_drv);
957 int iwl_set_tx_power(struct iwl_priv *priv, s8 tx_power, bool force)
960 if (tx_power < IWL_TX_POWER_TARGET_POWER_MIN) {
961 IWL_WARNING("Requested user TXPOWER %d below limit.\n",
962 priv->tx_power_user_lmt);
966 if (tx_power > IWL_TX_POWER_TARGET_POWER_MAX) {
967 IWL_WARNING("Requested user TXPOWER %d above limit.\n",
968 priv->tx_power_user_lmt);
972 if (priv->tx_power_user_lmt != tx_power)
975 priv->tx_power_user_lmt = tx_power;
977 if (force && priv->cfg->ops->lib->send_tx_power)
978 ret = priv->cfg->ops->lib->send_tx_power(priv);
982 EXPORT_SYMBOL(iwl_set_tx_power);
984 void iwl_uninit_drv(struct iwl_priv *priv)
986 iwl_calib_free_results(priv);
987 iwlcore_free_geos(priv);
988 iwl_free_channel_map(priv);
991 EXPORT_SYMBOL(iwl_uninit_drv);
993 int iwl_send_statistics_request(struct iwl_priv *priv, u8 flags)
996 struct iwl_host_cmd cmd = {
997 .id = REPLY_STATISTICS_CMD,
999 .len = sizeof(stat_flags),
1000 .data = (u8 *) &stat_flags,
1002 return iwl_send_cmd(priv, &cmd);
1004 EXPORT_SYMBOL(iwl_send_statistics_request);
1007 * iwl_verify_inst_sparse - verify runtime uCode image in card vs. host,
1008 * using sample data 100 bytes apart. If these sample points are good,
1009 * it's a pretty good bet that everything between them is good, too.
1011 static int iwlcore_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len)
1018 IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
1020 ret = iwl_grab_nic_access(priv);
1024 for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
1025 /* read data comes through single port, auto-incr addr */
1026 /* NOTE: Use the debugless read so we don't flood kernel log
1027 * if IWL_DL_IO is set */
1028 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
1029 i + RTC_INST_LOWER_BOUND);
1030 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
1031 if (val != le32_to_cpu(*image)) {
1039 iwl_release_nic_access(priv);
1045 * iwlcore_verify_inst_full - verify runtime uCode image in card vs. host,
1046 * looking at all data.
1048 static int iwl_verify_inst_full(struct iwl_priv *priv, __le32 *image,
1056 IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
1058 ret = iwl_grab_nic_access(priv);
1062 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, RTC_INST_LOWER_BOUND);
1065 for (; len > 0; len -= sizeof(u32), image++) {
1066 /* read data comes through single port, auto-incr addr */
1067 /* NOTE: Use the debugless read so we don't flood kernel log
1068 * if IWL_DL_IO is set */
1069 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
1070 if (val != le32_to_cpu(*image)) {
1071 IWL_ERROR("uCode INST section is invalid at "
1072 "offset 0x%x, is 0x%x, s/b 0x%x\n",
1073 save_len - len, val, le32_to_cpu(*image));
1081 iwl_release_nic_access(priv);
1085 ("ucode image in INSTRUCTION memory is good\n");
1091 * iwl_verify_ucode - determine which instruction image is in SRAM,
1092 * and verify its contents
1094 int iwl_verify_ucode(struct iwl_priv *priv)
1101 image = (__le32 *)priv->ucode_boot.v_addr;
1102 len = priv->ucode_boot.len;
1103 ret = iwlcore_verify_inst_sparse(priv, image, len);
1105 IWL_DEBUG_INFO("Bootstrap uCode is good in inst SRAM\n");
1109 /* Try initialize */
1110 image = (__le32 *)priv->ucode_init.v_addr;
1111 len = priv->ucode_init.len;
1112 ret = iwlcore_verify_inst_sparse(priv, image, len);
1114 IWL_DEBUG_INFO("Initialize uCode is good in inst SRAM\n");
1118 /* Try runtime/protocol */
1119 image = (__le32 *)priv->ucode_code.v_addr;
1120 len = priv->ucode_code.len;
1121 ret = iwlcore_verify_inst_sparse(priv, image, len);
1123 IWL_DEBUG_INFO("Runtime uCode is good in inst SRAM\n");
1127 IWL_ERROR("NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
1129 /* Since nothing seems to match, show first several data entries in
1130 * instruction SRAM, so maybe visual inspection will give a clue.
1131 * Selection of bootstrap image (vs. other images) is arbitrary. */
1132 image = (__le32 *)priv->ucode_boot.v_addr;
1133 len = priv->ucode_boot.len;
1134 ret = iwl_verify_inst_full(priv, image, len);
1138 EXPORT_SYMBOL(iwl_verify_ucode);
1141 static const char *desc_lookup(int i)
1149 return "BAD_CHECKSUM";
1151 return "NMI_INTERRUPT";
1155 return "FATAL_ERROR";
1161 #define ERROR_START_OFFSET (1 * sizeof(u32))
1162 #define ERROR_ELEM_SIZE (7 * sizeof(u32))
1164 void iwl_dump_nic_error_log(struct iwl_priv *priv)
1167 u32 desc, time, count, base, data1;
1168 u32 blink1, blink2, ilink1, ilink2;
1171 if (priv->ucode_type == UCODE_INIT)
1172 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
1174 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
1176 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
1177 IWL_ERROR("Not valid error log pointer 0x%08X\n", base);
1181 ret = iwl_grab_nic_access(priv);
1183 IWL_WARNING("Can not read from adapter at this time.\n");
1187 count = iwl_read_targ_mem(priv, base);
1189 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
1190 IWL_ERROR("Start IWL Error Log Dump:\n");
1191 IWL_ERROR("Status: 0x%08lX, count: %d\n", priv->status, count);
1194 desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
1195 blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
1196 blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
1197 ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
1198 ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
1199 data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
1200 data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
1201 line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
1202 time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
1204 IWL_ERROR("Desc Time "
1205 "data1 data2 line\n");
1206 IWL_ERROR("%-13s (#%d) %010u 0x%08X 0x%08X %u\n",
1207 desc_lookup(desc), desc, time, data1, data2, line);
1208 IWL_ERROR("blink1 blink2 ilink1 ilink2\n");
1209 IWL_ERROR("0x%05X 0x%05X 0x%05X 0x%05X\n", blink1, blink2,
1212 iwl_release_nic_access(priv);
1214 EXPORT_SYMBOL(iwl_dump_nic_error_log);
1216 #define EVENT_START_OFFSET (4 * sizeof(u32))
1219 * iwl_print_event_log - Dump error event log to syslog
1221 * NOTE: Must be called with iwl4965_grab_nic_access() already obtained!
1223 void iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
1224 u32 num_events, u32 mode)
1227 u32 base; /* SRAM byte address of event log header */
1228 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
1229 u32 ptr; /* SRAM byte address of log data */
1230 u32 ev, time, data; /* event log data */
1232 if (num_events == 0)
1234 if (priv->ucode_type == UCODE_INIT)
1235 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
1237 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
1240 event_size = 2 * sizeof(u32);
1242 event_size = 3 * sizeof(u32);
1244 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
1246 /* "time" is actually "data" for mode 0 (no timestamp).
1247 * place event id # at far right for easier visual parsing. */
1248 for (i = 0; i < num_events; i++) {
1249 ev = iwl_read_targ_mem(priv, ptr);
1251 time = iwl_read_targ_mem(priv, ptr);
1255 IWL_ERROR("EVT_LOG:0x%08x:%04u\n", time, ev);
1257 data = iwl_read_targ_mem(priv, ptr);
1259 IWL_ERROR("EVT_LOGT:%010u:0x%08x:%04u\n",
1264 EXPORT_SYMBOL(iwl_print_event_log);
1267 void iwl_dump_nic_event_log(struct iwl_priv *priv)
1270 u32 base; /* SRAM byte address of event log header */
1271 u32 capacity; /* event log capacity in # entries */
1272 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
1273 u32 num_wraps; /* # times uCode wrapped to top of log */
1274 u32 next_entry; /* index of next entry to be written by uCode */
1275 u32 size; /* # entries that we'll print */
1277 if (priv->ucode_type == UCODE_INIT)
1278 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
1280 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
1282 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
1283 IWL_ERROR("Invalid event log pointer 0x%08X\n", base);
1287 ret = iwl_grab_nic_access(priv);
1289 IWL_WARNING("Can not read from adapter at this time.\n");
1293 /* event log header */
1294 capacity = iwl_read_targ_mem(priv, base);
1295 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
1296 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
1297 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
1299 size = num_wraps ? capacity : next_entry;
1301 /* bail out if nothing in log */
1303 IWL_ERROR("Start IWL Event Log Dump: nothing in log\n");
1304 iwl_release_nic_access(priv);
1308 IWL_ERROR("Start IWL Event Log Dump: display count %d, wraps %d\n",
1311 /* if uCode has wrapped back to top of log, start at the oldest entry,
1312 * i.e the next one that uCode would fill. */
1314 iwl_print_event_log(priv, next_entry,
1315 capacity - next_entry, mode);
1316 /* (then/else) start at top of log */
1317 iwl_print_event_log(priv, 0, next_entry, mode);
1319 iwl_release_nic_access(priv);
1321 EXPORT_SYMBOL(iwl_dump_nic_event_log);
1323 void iwl_rf_kill_ct_config(struct iwl_priv *priv)
1325 struct iwl_ct_kill_config cmd;
1326 unsigned long flags;
1329 spin_lock_irqsave(&priv->lock, flags);
1330 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
1331 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
1332 spin_unlock_irqrestore(&priv->lock, flags);
1334 cmd.critical_temperature_R =
1335 cpu_to_le32(priv->hw_params.ct_kill_threshold);
1337 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
1340 IWL_ERROR("REPLY_CT_KILL_CONFIG_CMD failed\n");
1342 IWL_DEBUG_INFO("REPLY_CT_KILL_CONFIG_CMD succeeded, "
1343 "critical temperature is %d\n",
1344 cmd.critical_temperature_R);
1346 EXPORT_SYMBOL(iwl_rf_kill_ct_config);
1351 * Use: Sets the device's internal card state to enable, disable, or halt
1353 * When in the 'enable' state the card operates as normal.
1354 * When in the 'disable' state, the card enters into a low power mode.
1355 * When in the 'halt' state, the card is shut down and must be fully
1356 * restarted to come back on.
1358 static int iwl_send_card_state(struct iwl_priv *priv, u32 flags, u8 meta_flag)
1360 struct iwl_host_cmd cmd = {
1361 .id = REPLY_CARD_STATE_CMD,
1364 .meta.flags = meta_flag,
1367 return iwl_send_cmd(priv, &cmd);
1370 void iwl_radio_kill_sw_disable_radio(struct iwl_priv *priv)
1372 unsigned long flags;
1374 if (test_bit(STATUS_RF_KILL_SW, &priv->status))
1377 IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO OFF\n");
1379 iwl_scan_cancel(priv);
1380 /* FIXME: This is a workaround for AP */
1381 if (priv->iw_mode != IEEE80211_IF_TYPE_AP) {
1382 spin_lock_irqsave(&priv->lock, flags);
1383 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
1384 CSR_UCODE_SW_BIT_RFKILL);
1385 spin_unlock_irqrestore(&priv->lock, flags);
1386 /* call the host command only if no hw rf-kill set */
1387 if (!test_bit(STATUS_RF_KILL_HW, &priv->status) &&
1389 iwl_send_card_state(priv,
1390 CARD_STATE_CMD_DISABLE, 0);
1391 set_bit(STATUS_RF_KILL_SW, &priv->status);
1392 /* make sure mac80211 stop sending Tx frame */
1393 if (priv->mac80211_registered)
1394 ieee80211_stop_queues(priv->hw);
1397 EXPORT_SYMBOL(iwl_radio_kill_sw_disable_radio);
1399 int iwl_radio_kill_sw_enable_radio(struct iwl_priv *priv)
1401 unsigned long flags;
1403 if (!test_bit(STATUS_RF_KILL_SW, &priv->status))
1406 IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO ON\n");
1408 spin_lock_irqsave(&priv->lock, flags);
1409 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1411 /* If the driver is up it will receive CARD_STATE_NOTIFICATION
1412 * notification where it will clear SW rfkill status.
1413 * Setting it here would break the handler. Only if the
1414 * interface is down we can set here since we don't
1415 * receive any further notification.
1418 clear_bit(STATUS_RF_KILL_SW, &priv->status);
1419 spin_unlock_irqrestore(&priv->lock, flags);
1424 spin_lock_irqsave(&priv->lock, flags);
1425 iwl_read32(priv, CSR_UCODE_DRV_GP1);
1426 if (!iwl_grab_nic_access(priv))
1427 iwl_release_nic_access(priv);
1428 spin_unlock_irqrestore(&priv->lock, flags);
1430 if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
1431 IWL_DEBUG_RF_KILL("Can not turn radio back on - "
1432 "disabled by HW switch\n");
1436 /* If the driver is already loaded, it will receive
1437 * CARD_STATE_NOTIFICATION notifications and the handler will
1438 * call restart to reload the driver.
1442 EXPORT_SYMBOL(iwl_radio_kill_sw_enable_radio);