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   1 /*
   2  * Copyright(c) 2006, Intel Corporation.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along with
  14  * this program; if not, write to the Free Software Foundation, Inc.,
  15  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  16  *
  17  */
  18 #ifndef _ADMA_H
  19 #define _ADMA_H
  20 #include <linux/types.h>
  21 #include <linux/io.h>
  22 #include <asm/hardware.h>
  23 #include <asm/hardware/iop_adma.h>
  24
  25 #define ADMA_ACCR(chan) (chan->mmr_base + 0x0)
  26 #define ADMA_ACSR(chan) (chan->mmr_base + 0x4)
  27 #define ADMA_ADAR(chan) (chan->mmr_base + 0x8)
  28 #define ADMA_IIPCR(chan)        (chan->mmr_base + 0x18)
  29 #define ADMA_IIPAR(chan)        (chan->mmr_base + 0x1c)
  30 #define ADMA_IIPUAR(chan)       (chan->mmr_base + 0x20)
  31 #define ADMA_ANDAR(chan)        (chan->mmr_base + 0x24)
  32 #define ADMA_ADCR(chan) (chan->mmr_base + 0x28)
  33 #define ADMA_CARMD(chan)        (chan->mmr_base + 0x2c)
  34 #define ADMA_ABCR(chan) (chan->mmr_base + 0x30)
  35 #define ADMA_DLADR(chan)        (chan->mmr_base + 0x34)
  36 #define ADMA_DUADR(chan)        (chan->mmr_base + 0x38)
  37 #define ADMA_SLAR(src, chan)    (chan->mmr_base + (0x3c + (src << 3)))
  38 #define ADMA_SUAR(src, chan)    (chan->mmr_base + (0x40 + (src << 3)))
  39
  40 struct iop13xx_adma_src {
  41         u32 src_addr;
  42         union {
  43                 u32 upper_src_addr;
  44                 struct {
  45                         unsigned int pq_upper_src_addr:24;
  46                         unsigned int pq_dmlt:8;
  47                 };
  48         };
  49 };
  50
  51 struct iop13xx_adma_desc_ctrl {
  52         unsigned int int_en:1;
  53         unsigned int xfer_dir:2;
  54         unsigned int src_select:4;
  55         unsigned int zero_result:1;
  56         unsigned int block_fill_en:1;
  57         unsigned int crc_gen_en:1;
  58         unsigned int crc_xfer_dis:1;
  59         unsigned int crc_seed_fetch_dis:1;
  60         unsigned int status_write_back_en:1;
  61         unsigned int endian_swap_en:1;
  62         unsigned int reserved0:2;
  63         unsigned int pq_update_xfer_en:1;
  64         unsigned int dual_xor_en:1;
  65         unsigned int pq_xfer_en:1;
  66         unsigned int p_xfer_dis:1;
  67         unsigned int reserved1:10;
  68         unsigned int relax_order_en:1;
  69         unsigned int no_snoop_en:1;
  70 };
  71
  72 struct iop13xx_adma_byte_count {
  73         unsigned int byte_count:24;
  74         unsigned int host_if:3;
  75         unsigned int reserved:2;
  76         unsigned int zero_result_err_q:1;
  77         unsigned int zero_result_err:1;
  78         unsigned int tx_complete:1;
  79 };
  80
  81 struct iop13xx_adma_desc_hw {
  82         u32 next_desc;
  83         union {
  84                 u32 desc_ctrl;
  85                 struct iop13xx_adma_desc_ctrl desc_ctrl_field;
  86         };
  87         union {
  88                 u32 crc_addr;
  89                 u32 block_fill_data;
  90                 u32 q_dest_addr;
  91         };
  92         union {
  93                 u32 byte_count;
  94                 struct iop13xx_adma_byte_count byte_count_field;
  95         };
  96         union {
  97                 u32 dest_addr;
  98                 u32 p_dest_addr;
  99         };
 100         union {
 101                 u32 upper_dest_addr;
 102                 u32 pq_upper_dest_addr;
 103         };
 104         struct iop13xx_adma_src src[1];
 105 };
 106
 107 struct iop13xx_adma_desc_dual_xor {
 108         u32 next_desc;
 109         u32 desc_ctrl;
 110         u32 reserved;
 111         u32 byte_count;
 112         u32 h_dest_addr;
 113         u32 h_upper_dest_addr;
 114         u32 src0_addr;
 115         u32 upper_src0_addr;
 116         u32 src1_addr;
 117         u32 upper_src1_addr;
 118         u32 h_src_addr;
 119         u32 h_upper_src_addr;
 120         u32 d_src_addr;
 121         u32 d_upper_src_addr;
 122         u32 d_dest_addr;
 123         u32 d_upper_dest_addr;
 124 };
 125
 126 struct iop13xx_adma_desc_pq_update {
 127         u32 next_desc;
 128         u32 desc_ctrl;
 129         u32 reserved;
 130         u32 byte_count;
 131         u32 p_dest_addr;
 132         u32 p_upper_dest_addr;
 133         u32 src0_addr;
 134         u32 upper_src0_addr;
 135         u32 src1_addr;
 136         u32 upper_src1_addr;
 137         u32 p_src_addr;
 138         u32 p_upper_src_addr;
 139         u32 q_src_addr;
 140         struct {
 141                 unsigned int q_upper_src_addr:24;
 142                 unsigned int q_dmlt:8;
 143         };
 144         u32 q_dest_addr;
 145         u32 q_upper_dest_addr;
 146 };
 147
 148 static inline int iop_adma_get_max_xor(void)
 149 {
 150         return 16;
 151 }
 152
 153 static inline u32 iop_chan_get_current_descriptor(struct iop_adma_chan *chan)
 154 {
 155         return __raw_readl(ADMA_ADAR(chan));
 156 }
 157
 158 static inline void iop_chan_set_next_descriptor(struct iop_adma_chan *chan,
 159                                                 u32 next_desc_addr)
 160 {
 161         __raw_writel(next_desc_addr, ADMA_ANDAR(chan));
 162 }
 163
 164 #define ADMA_STATUS_BUSY (1 << 13)
 165
 166 static inline char iop_chan_is_busy(struct iop_adma_chan *chan)
 167 {
 168         if (__raw_readl(ADMA_ACSR(chan)) &
 169                 ADMA_STATUS_BUSY)
 170                 return 1;
 171         else
 172                 return 0;
 173 }
 174
 175 static inline int
 176 iop_chan_get_desc_align(struct iop_adma_chan *chan, int num_slots)
 177 {
 178         return 1;
 179 }
 180 #define iop_desc_is_aligned(x, y) 1
 181
 182 static inline int
 183 iop_chan_memcpy_slot_count(size_t len, int *slots_per_op)
 184 {
 185         *slots_per_op = 1;
 186         return 1;
 187 }
 188
 189 #define iop_chan_interrupt_slot_count(s, c) iop_chan_memcpy_slot_count(0, s)
 190
 191 static inline int
 192 iop_chan_memset_slot_count(size_t len, int *slots_per_op)
 193 {
 194         *slots_per_op = 1;
 195         return 1;
 196 }
 197
 198 static inline int
 199 iop_chan_xor_slot_count(size_t len, int src_cnt, int *slots_per_op)
 200 {
 201         int num_slots;
 202         /* slots_to_find = 1 for basic descriptor + 1 per 4 sources above 1
 203          * (1 source => 8 bytes) (1 slot => 32 bytes)
 204          */
 205         num_slots = 1 + (((src_cnt - 1) << 3) >> 5);
 206         if (((src_cnt - 1) << 3) & 0x1f)
 207                 num_slots++;
 208
 209         *slots_per_op = num_slots;
 210
 211         return num_slots;
 212 }
 213
 214 #define ADMA_MAX_BYTE_COUNT     (16 * 1024 * 1024)
 215 #define IOP_ADMA_MAX_BYTE_COUNT ADMA_MAX_BYTE_COUNT
 216 #define IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT ADMA_MAX_BYTE_COUNT
 217 #define IOP_ADMA_XOR_MAX_BYTE_COUNT ADMA_MAX_BYTE_COUNT
 218 #define iop_chan_zero_sum_slot_count(l, s, o) iop_chan_xor_slot_count(l, s, o)
 219
 220 static inline u32 iop_desc_get_dest_addr(struct iop_adma_desc_slot *desc,
 221                                         struct iop_adma_chan *chan)
 222 {
 223         struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
 224         return hw_desc->dest_addr;
 225 }
 226
 227 static inline u32 iop_desc_get_byte_count(struct iop_adma_desc_slot *desc,
 228                                         struct iop_adma_chan *chan)
 229 {
 230         struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
 231         return hw_desc->byte_count_field.byte_count;
 232 }
 233
 234 static inline u32 iop_desc_get_src_addr(struct iop_adma_desc_slot *desc,
 235                                         struct iop_adma_chan *chan,
 236                                         int src_idx)
 237 {
 238         struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
 239         return hw_desc->src[src_idx].src_addr;
 240 }
 241
 242 static inline u32 iop_desc_get_src_count(struct iop_adma_desc_slot *desc,
 243                                         struct iop_adma_chan *chan)
 244 {
 245         struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
 246         return hw_desc->desc_ctrl_field.src_select + 1;
 247 }
 248
 249 static inline void
 250 iop_desc_init_memcpy(struct iop_adma_desc_slot *desc, unsigned long flags)
 251 {
 252         struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
 253         union {
 254                 u32 value;
 255                 struct iop13xx_adma_desc_ctrl field;
 256         } u_desc_ctrl;
 257
 258         u_desc_ctrl.value = 0;
 259         u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */
 260         u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT;
 261         hw_desc->desc_ctrl = u_desc_ctrl.value;
 262         hw_desc->crc_addr = 0;
 263 }
 264
 265 static inline void
 266 iop_desc_init_memset(struct iop_adma_desc_slot *desc, unsigned long flags)
 267 {
 268         struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
 269         union {
 270                 u32 value;
 271                 struct iop13xx_adma_desc_ctrl field;
 272         } u_desc_ctrl;
 273
 274         u_desc_ctrl.value = 0;
 275         u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */
 276         u_desc_ctrl.field.block_fill_en = 1;
 277         u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT;
 278         hw_desc->desc_ctrl = u_desc_ctrl.value;
 279         hw_desc->crc_addr = 0;
 280 }
 281
 282 /* to do: support buffers larger than ADMA_MAX_BYTE_COUNT */
 283 static inline void
 284 iop_desc_init_xor(struct iop_adma_desc_slot *desc, int src_cnt,
 285                   unsigned long flags)
 286 {
 287         struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
 288         union {
 289                 u32 value;
 290                 struct iop13xx_adma_desc_ctrl field;
 291         } u_desc_ctrl;
 292
 293         u_desc_ctrl.value = 0;
 294         u_desc_ctrl.field.src_select = src_cnt - 1;
 295         u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */
 296         u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT;
 297         hw_desc->desc_ctrl = u_desc_ctrl.value;
 298         hw_desc->crc_addr = 0;
 299
 300 }
 301 #define iop_desc_init_null_xor(d, s, i) iop_desc_init_xor(d, s, i)
 302
 303 /* to do: support buffers larger than ADMA_MAX_BYTE_COUNT */
 304 static inline int
 305 iop_desc_init_zero_sum(struct iop_adma_desc_slot *desc, int src_cnt,
 306                        unsigned long flags)
 307 {
 308         struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
 309         union {
 310                 u32 value;
 311                 struct iop13xx_adma_desc_ctrl field;
 312         } u_desc_ctrl;
 313
 314         u_desc_ctrl.value = 0;
 315         u_desc_ctrl.field.src_select = src_cnt - 1;
 316         u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */
 317         u_desc_ctrl.field.zero_result = 1;
 318         u_desc_ctrl.field.status_write_back_en = 1;
 319         u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT;
 320         hw_desc->desc_ctrl = u_desc_ctrl.value;
 321         hw_desc->crc_addr = 0;
 322
 323         return 1;
 324 }
 325
 326 static inline void iop_desc_set_byte_count(struct iop_adma_desc_slot *desc,
 327                                         struct iop_adma_chan *chan,
 328                                         u32 byte_count)
 329 {
 330         struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
 331         hw_desc->byte_count = byte_count;
 332 }
 333
 334 static inline void
 335 iop_desc_set_zero_sum_byte_count(struct iop_adma_desc_slot *desc, u32 len)
 336 {
 337         int slots_per_op = desc->slots_per_op;
 338         struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc, *iter;
 339         int i = 0;
 340
 341         if (len <= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT) {
 342                 hw_desc->byte_count = len;
 343         } else {
 344                 do {
 345                         iter = iop_hw_desc_slot_idx(hw_desc, i);
 346                         iter->byte_count = IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT;
 347                         len -= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT;
 348                         i += slots_per_op;
 349                 } while (len > IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT);
 350
 351                 if (len) {
 352                         iter = iop_hw_desc_slot_idx(hw_desc, i);
 353                         iter->byte_count = len;
 354                 }
 355         }
 356 }
 357
 358
 359 static inline void iop_desc_set_dest_addr(struct iop_adma_desc_slot *desc,
 360                                         struct iop_adma_chan *chan,
 361                                         dma_addr_t addr)
 362 {
 363         struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
 364         hw_desc->dest_addr = addr;
 365         hw_desc->upper_dest_addr = 0;
 366 }
 367
 368 static inline void iop_desc_set_memcpy_src_addr(struct iop_adma_desc_slot *desc,
 369                                         dma_addr_t addr)
 370 {
 371         struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
 372         hw_desc->src[0].src_addr = addr;
 373         hw_desc->src[0].upper_src_addr = 0;
 374 }
 375
 376 static inline void iop_desc_set_xor_src_addr(struct iop_adma_desc_slot *desc,
 377                                         int src_idx, dma_addr_t addr)
 378 {
 379         int slot_cnt = desc->slot_cnt, slots_per_op = desc->slots_per_op;
 380         struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc, *iter;
 381         int i = 0;
 382
 383         do {
 384                 iter = iop_hw_desc_slot_idx(hw_desc, i);
 385                 iter->src[src_idx].src_addr = addr;
 386                 iter->src[src_idx].upper_src_addr = 0;
 387                 slot_cnt -= slots_per_op;
 388                 if (slot_cnt) {
 389                         i += slots_per_op;
 390                         addr += IOP_ADMA_XOR_MAX_BYTE_COUNT;
 391                 }
 392         } while (slot_cnt);
 393 }
 394
 395 static inline void
 396 iop_desc_init_interrupt(struct iop_adma_desc_slot *desc,
 397         struct iop_adma_chan *chan)
 398 {
 399         iop_desc_init_memcpy(desc, 1);
 400         iop_desc_set_byte_count(desc, chan, 0);
 401         iop_desc_set_dest_addr(desc, chan, 0);
 402         iop_desc_set_memcpy_src_addr(desc, 0);
 403 }
 404
 405 #define iop_desc_set_zero_sum_src_addr iop_desc_set_xor_src_addr
 406
 407 static inline void iop_desc_set_next_desc(struct iop_adma_desc_slot *desc,
 408                                         u32 next_desc_addr)
 409 {
 410         struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
 411         BUG_ON(hw_desc->next_desc);
 412         hw_desc->next_desc = next_desc_addr;
 413 }
 414
 415 static inline u32 iop_desc_get_next_desc(struct iop_adma_desc_slot *desc)
 416 {
 417         struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
 418         return hw_desc->next_desc;
 419 }
 420
 421 static inline void iop_desc_clear_next_desc(struct iop_adma_desc_slot *desc)
 422 {
 423         struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
 424         hw_desc->next_desc = 0;
 425 }
 426
 427 static inline void iop_desc_set_block_fill_val(struct iop_adma_desc_slot *desc,
 428                                                 u32 val)
 429 {
 430         struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
 431         hw_desc->block_fill_data = val;
 432 }
 433
 434 static inline int iop_desc_get_zero_result(struct iop_adma_desc_slot *desc)
 435 {
 436         struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
 437         struct iop13xx_adma_desc_ctrl desc_ctrl = hw_desc->desc_ctrl_field;
 438         struct iop13xx_adma_byte_count byte_count = hw_desc->byte_count_field;
 439
 440         BUG_ON(!(byte_count.tx_complete && desc_ctrl.zero_result));
 441
 442         if (desc_ctrl.pq_xfer_en)
 443                 return byte_count.zero_result_err_q;
 444         else
 445                 return byte_count.zero_result_err;
 446 }
 447
 448 static inline void iop_chan_append(struct iop_adma_chan *chan)
 449 {
 450         u32 adma_accr;
 451
 452         adma_accr = __raw_readl(ADMA_ACCR(chan));
 453         adma_accr |= 0x2;
 454         __raw_writel(adma_accr, ADMA_ACCR(chan));
 455 }
 456
 457 static inline u32 iop_chan_get_status(struct iop_adma_chan *chan)
 458 {
 459         return __raw_readl(ADMA_ACSR(chan));
 460 }
 461
 462 static inline void iop_chan_disable(struct iop_adma_chan *chan)
 463 {
 464         u32 adma_chan_ctrl = __raw_readl(ADMA_ACCR(chan));
 465         adma_chan_ctrl &= ~0x1;
 466         __raw_writel(adma_chan_ctrl, ADMA_ACCR(chan));
 467 }
 468
 469 static inline void iop_chan_enable(struct iop_adma_chan *chan)
 470 {
 471         u32 adma_chan_ctrl;
 472
 473         adma_chan_ctrl = __raw_readl(ADMA_ACCR(chan));
 474         adma_chan_ctrl |= 0x1;
 475         __raw_writel(adma_chan_ctrl, ADMA_ACCR(chan));
 476 }
 477
 478 static inline void iop_adma_device_clear_eot_status(struct iop_adma_chan *chan)
 479 {
 480         u32 status = __raw_readl(ADMA_ACSR(chan));
 481         status &= (1 << 12);
 482         __raw_writel(status, ADMA_ACSR(chan));
 483 }
 484
 485 static inline void iop_adma_device_clear_eoc_status(struct iop_adma_chan *chan)
 486 {
 487         u32 status = __raw_readl(ADMA_ACSR(chan));
 488         status &= (1 << 11);
 489         __raw_writel(status, ADMA_ACSR(chan));
 490 }
 491
 492 static inline void iop_adma_device_clear_err_status(struct iop_adma_chan *chan)
 493 {
 494         u32 status = __raw_readl(ADMA_ACSR(chan));
 495         status &= (1 << 9) | (1 << 5) | (1 << 4) | (1 << 3);
 496         __raw_writel(status, ADMA_ACSR(chan));
 497 }
 498
 499 static inline int
 500 iop_is_err_int_parity(unsigned long status, struct iop_adma_chan *chan)
 501 {
 502         return test_bit(9, &status);
 503 }
 504
 505 static inline int
 506 iop_is_err_mcu_abort(unsigned long status, struct iop_adma_chan *chan)
 507 {
 508         return test_bit(5, &status);
 509 }
 510
 511 static inline int
 512 iop_is_err_int_tabort(unsigned long status, struct iop_adma_chan *chan)
 513 {
 514         return test_bit(4, &status);
 515 }
 516
 517 static inline int
 518 iop_is_err_int_mabort(unsigned long status, struct iop_adma_chan *chan)
 519 {
 520         return test_bit(3, &status);
 521 }
 522
 523 static inline int
 524 iop_is_err_pci_tabort(unsigned long status, struct iop_adma_chan *chan)
 525 {
 526         return 0;
 527 }
 528
 529 static inline int
 530 iop_is_err_pci_mabort(unsigned long status, struct iop_adma_chan *chan)
 531 {
 532         return 0;
 533 }
 534
 535 static inline int
 536 iop_is_err_split_tx(unsigned long status, struct iop_adma_chan *chan)
 537 {
 538         return 0;
 539 }
 540
 541 #endif /* _ADMA_H */