2 * ahci.c - AHCI SATA support
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/sched.h>
43 #include <linux/dma-mapping.h>
45 #include <scsi/scsi_host.h>
46 #include <linux/libata.h>
49 #define DRV_NAME "ahci"
50 #define DRV_VERSION "1.01"
55 AHCI_MAX_SG = 168, /* hardware max is 64K */
56 AHCI_DMA_BOUNDARY = 0xffffffff,
57 AHCI_USE_CLUSTERING = 0,
58 AHCI_CMD_SLOT_SZ = 32 * 32,
60 AHCI_CMD_TBL_HDR = 0x80,
61 AHCI_CMD_TBL_CDB = 0x40,
62 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR + (AHCI_MAX_SG * 16),
63 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_SZ +
65 AHCI_IRQ_ON_SG = (1 << 31),
66 AHCI_CMD_ATAPI = (1 << 5),
67 AHCI_CMD_WRITE = (1 << 6),
69 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
73 /* global controller registers */
74 HOST_CAP = 0x00, /* host capabilities */
75 HOST_CTL = 0x04, /* global host control */
76 HOST_IRQ_STAT = 0x08, /* interrupt status */
77 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
78 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
81 HOST_RESET = (1 << 0), /* reset controller; self-clear */
82 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
83 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
86 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
88 /* registers for each SATA port */
89 PORT_LST_ADDR = 0x00, /* command list DMA addr */
90 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
91 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
92 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
93 PORT_IRQ_STAT = 0x10, /* interrupt status */
94 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
95 PORT_CMD = 0x18, /* port command */
96 PORT_TFDATA = 0x20, /* taskfile data */
97 PORT_SIG = 0x24, /* device TF signature */
98 PORT_CMD_ISSUE = 0x38, /* command issue */
99 PORT_SCR = 0x28, /* SATA phy register block */
100 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
101 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
102 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
103 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
105 /* PORT_IRQ_{STAT,MASK} bits */
106 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
107 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
108 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
109 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
110 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
111 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
112 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
113 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
115 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
116 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
117 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
118 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
119 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
120 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
121 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
122 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
123 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
125 PORT_IRQ_FATAL = PORT_IRQ_TF_ERR |
127 PORT_IRQ_HBUS_DATA_ERR |
129 DEF_PORT_IRQ = PORT_IRQ_FATAL | PORT_IRQ_PHYRDY |
130 PORT_IRQ_CONNECT | PORT_IRQ_SG_DONE |
131 PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_FIS |
132 PORT_IRQ_DMAS_FIS | PORT_IRQ_PIOS_FIS |
133 PORT_IRQ_D2H_REG_FIS,
136 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
137 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
138 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
139 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
140 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
141 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
143 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
144 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
145 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
147 /* hpriv->flags bits */
148 AHCI_FLAG_MSI = (1 << 0),
151 struct ahci_cmd_hdr {
166 struct ahci_host_priv {
168 u32 cap; /* cache of HOST_CAP register */
169 u32 port_map; /* cache of HOST_PORTS_IMPL reg */
172 struct ahci_port_priv {
173 struct ahci_cmd_hdr *cmd_slot;
174 dma_addr_t cmd_slot_dma;
176 dma_addr_t cmd_tbl_dma;
177 struct ahci_sg *cmd_tbl_sg;
179 dma_addr_t rx_fis_dma;
182 static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg);
183 static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
184 static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
185 static int ahci_qc_issue(struct ata_queued_cmd *qc);
186 static irqreturn_t ahci_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
187 static void ahci_phy_reset(struct ata_port *ap);
188 static void ahci_irq_clear(struct ata_port *ap);
189 static void ahci_eng_timeout(struct ata_port *ap);
190 static int ahci_port_start(struct ata_port *ap);
191 static void ahci_port_stop(struct ata_port *ap);
192 static void ahci_host_stop(struct ata_host_set *host_set);
193 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
194 static void ahci_qc_prep(struct ata_queued_cmd *qc);
195 static u8 ahci_check_status(struct ata_port *ap);
196 static u8 ahci_check_err(struct ata_port *ap);
197 static inline int ahci_host_intr(struct ata_port *ap, struct ata_queued_cmd *qc);
198 static void ahci_remove_one (struct pci_dev *pdev);
200 static Scsi_Host_Template ahci_sht = {
201 .module = THIS_MODULE,
203 .ioctl = ata_scsi_ioctl,
204 .queuecommand = ata_scsi_queuecmd,
205 .eh_strategy_handler = ata_scsi_error,
206 .can_queue = ATA_DEF_QUEUE,
207 .this_id = ATA_SHT_THIS_ID,
208 .sg_tablesize = AHCI_MAX_SG,
209 .max_sectors = ATA_MAX_SECTORS,
210 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
211 .emulated = ATA_SHT_EMULATED,
212 .use_clustering = AHCI_USE_CLUSTERING,
213 .proc_name = DRV_NAME,
214 .dma_boundary = AHCI_DMA_BOUNDARY,
215 .slave_configure = ata_scsi_slave_config,
216 .bios_param = ata_std_bios_param,
220 static struct ata_port_operations ahci_ops = {
221 .port_disable = ata_port_disable,
223 .check_status = ahci_check_status,
224 .check_altstatus = ahci_check_status,
225 .check_err = ahci_check_err,
226 .dev_select = ata_noop_dev_select,
228 .tf_read = ahci_tf_read,
230 .phy_reset = ahci_phy_reset,
232 .qc_prep = ahci_qc_prep,
233 .qc_issue = ahci_qc_issue,
235 .eng_timeout = ahci_eng_timeout,
237 .irq_handler = ahci_interrupt,
238 .irq_clear = ahci_irq_clear,
240 .scr_read = ahci_scr_read,
241 .scr_write = ahci_scr_write,
243 .port_start = ahci_port_start,
244 .port_stop = ahci_port_stop,
245 .host_stop = ahci_host_stop,
248 static struct ata_port_info ahci_port_info[] = {
252 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
253 ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO |
255 .pio_mask = 0x03, /* pio3-4 */
256 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
257 .port_ops = &ahci_ops,
261 static struct pci_device_id ahci_pci_tbl[] = {
262 { PCI_VENDOR_ID_INTEL, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
263 board_ahci }, /* ICH6 */
264 { PCI_VENDOR_ID_INTEL, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
265 board_ahci }, /* ICH6M */
266 { PCI_VENDOR_ID_INTEL, 0x27c1, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
267 board_ahci }, /* ICH7 */
268 { PCI_VENDOR_ID_INTEL, 0x27c5, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
269 board_ahci }, /* ICH7M */
270 { PCI_VENDOR_ID_INTEL, 0x27c3, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
271 board_ahci }, /* ICH7R */
272 { PCI_VENDOR_ID_AL, 0x5288, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
273 board_ahci }, /* ULi M5288 */
274 { PCI_VENDOR_ID_INTEL, 0x2681, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
275 board_ahci }, /* ESB2 */
276 { PCI_VENDOR_ID_INTEL, 0x2682, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
277 board_ahci }, /* ESB2 */
278 { PCI_VENDOR_ID_INTEL, 0x2683, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
279 board_ahci }, /* ESB2 */
280 { PCI_VENDOR_ID_INTEL, 0x27c6, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
281 board_ahci }, /* ICH7-M DH */
282 { } /* terminate list */
286 static struct pci_driver ahci_pci_driver = {
288 .id_table = ahci_pci_tbl,
289 .probe = ahci_init_one,
290 .remove = ahci_remove_one,
294 static inline unsigned long ahci_port_base_ul (unsigned long base, unsigned int port)
296 return base + 0x100 + (port * 0x80);
299 static inline void *ahci_port_base (void *base, unsigned int port)
301 return (void *) ahci_port_base_ul((unsigned long)base, port);
304 static void ahci_host_stop(struct ata_host_set *host_set)
306 struct ahci_host_priv *hpriv = host_set->private_data;
309 ata_host_stop(host_set);
312 static int ahci_port_start(struct ata_port *ap)
314 struct device *dev = ap->host_set->dev;
315 struct ahci_host_priv *hpriv = ap->host_set->private_data;
316 struct ahci_port_priv *pp;
317 void *mem, *mmio = ap->host_set->mmio_base;
318 void *port_mmio = ahci_port_base(mmio, ap->port_no);
321 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
324 memset(pp, 0, sizeof(*pp));
326 mem = dma_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma, GFP_KERNEL);
331 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
334 * First item in chunk of DMA memory: 32-slot command table,
335 * 32 bytes each in size
338 pp->cmd_slot_dma = mem_dma;
340 mem += AHCI_CMD_SLOT_SZ;
341 mem_dma += AHCI_CMD_SLOT_SZ;
344 * Second item: Received-FIS area
347 pp->rx_fis_dma = mem_dma;
349 mem += AHCI_RX_FIS_SZ;
350 mem_dma += AHCI_RX_FIS_SZ;
353 * Third item: data area for storing a single command
354 * and its scatter-gather table
357 pp->cmd_tbl_dma = mem_dma;
359 pp->cmd_tbl_sg = mem + AHCI_CMD_TBL_HDR;
361 ap->private_data = pp;
363 if (hpriv->cap & HOST_CAP_64)
364 writel((pp->cmd_slot_dma >> 16) >> 16, port_mmio + PORT_LST_ADDR_HI);
365 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
366 readl(port_mmio + PORT_LST_ADDR); /* flush */
368 if (hpriv->cap & HOST_CAP_64)
369 writel((pp->rx_fis_dma >> 16) >> 16, port_mmio + PORT_FIS_ADDR_HI);
370 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
371 readl(port_mmio + PORT_FIS_ADDR); /* flush */
373 writel(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
374 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
375 PORT_CMD_START, port_mmio + PORT_CMD);
376 readl(port_mmio + PORT_CMD); /* flush */
382 static void ahci_port_stop(struct ata_port *ap)
384 struct device *dev = ap->host_set->dev;
385 struct ahci_port_priv *pp = ap->private_data;
386 void *mmio = ap->host_set->mmio_base;
387 void *port_mmio = ahci_port_base(mmio, ap->port_no);
390 tmp = readl(port_mmio + PORT_CMD);
391 tmp &= ~(PORT_CMD_START | PORT_CMD_FIS_RX);
392 writel(tmp, port_mmio + PORT_CMD);
393 readl(port_mmio + PORT_CMD); /* flush */
395 /* spec says 500 msecs for each PORT_CMD_{START,FIS_RX} bit, so
396 * this is slightly incorrect.
400 ap->private_data = NULL;
401 dma_free_coherent(dev, AHCI_PORT_PRIV_DMA_SZ,
402 pp->cmd_slot, pp->cmd_slot_dma);
406 static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg_in)
411 case SCR_STATUS: sc_reg = 0; break;
412 case SCR_CONTROL: sc_reg = 1; break;
413 case SCR_ERROR: sc_reg = 2; break;
414 case SCR_ACTIVE: sc_reg = 3; break;
419 return readl((void *) ap->ioaddr.scr_addr + (sc_reg * 4));
423 static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg_in,
429 case SCR_STATUS: sc_reg = 0; break;
430 case SCR_CONTROL: sc_reg = 1; break;
431 case SCR_ERROR: sc_reg = 2; break;
432 case SCR_ACTIVE: sc_reg = 3; break;
437 writel(val, (void *) ap->ioaddr.scr_addr + (sc_reg * 4));
440 static void ahci_phy_reset(struct ata_port *ap)
442 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
443 struct ata_taskfile tf;
444 struct ata_device *dev = &ap->device[0];
447 __sata_phy_reset(ap);
449 if (ap->flags & ATA_FLAG_PORT_DISABLED)
452 tmp = readl(port_mmio + PORT_SIG);
453 tf.lbah = (tmp >> 24) & 0xff;
454 tf.lbam = (tmp >> 16) & 0xff;
455 tf.lbal = (tmp >> 8) & 0xff;
456 tf.nsect = (tmp) & 0xff;
458 dev->class = ata_dev_classify(&tf);
459 if (!ata_dev_present(dev))
460 ata_port_disable(ap);
463 static u8 ahci_check_status(struct ata_port *ap)
465 void *mmio = (void *) ap->ioaddr.cmd_addr;
467 return readl(mmio + PORT_TFDATA) & 0xFF;
470 static u8 ahci_check_err(struct ata_port *ap)
472 void *mmio = (void *) ap->ioaddr.cmd_addr;
474 return (readl(mmio + PORT_TFDATA) >> 8) & 0xFF;
477 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
479 struct ahci_port_priv *pp = ap->private_data;
480 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
482 ata_tf_from_fis(d2h_fis, tf);
485 static void ahci_fill_sg(struct ata_queued_cmd *qc)
487 struct ahci_port_priv *pp = qc->ap->private_data;
493 * Next, the S/G list.
495 for (i = 0; i < qc->n_elem; i++) {
499 addr = sg_dma_address(&qc->sg[i]);
500 sg_len = sg_dma_len(&qc->sg[i]);
502 pp->cmd_tbl_sg[i].addr = cpu_to_le32(addr & 0xffffffff);
503 pp->cmd_tbl_sg[i].addr_hi = cpu_to_le32((addr >> 16) >> 16);
504 pp->cmd_tbl_sg[i].flags_size = cpu_to_le32(sg_len - 1);
508 static void ahci_qc_prep(struct ata_queued_cmd *qc)
510 struct ata_port *ap = qc->ap;
511 struct ahci_port_priv *pp = ap->private_data;
513 const u32 cmd_fis_len = 5; /* five dwords */
516 * Fill in command slot information (currently only one slot,
517 * slot 0, is currently since we don't do queueing)
520 opts = (qc->n_elem << 16) | cmd_fis_len;
521 if (qc->tf.flags & ATA_TFLAG_WRITE)
522 opts |= AHCI_CMD_WRITE;
523 if (is_atapi_taskfile(&qc->tf))
524 opts |= AHCI_CMD_ATAPI;
526 pp->cmd_slot[0].opts = cpu_to_le32(opts);
527 pp->cmd_slot[0].status = 0;
528 pp->cmd_slot[0].tbl_addr = cpu_to_le32(pp->cmd_tbl_dma & 0xffffffff);
529 pp->cmd_slot[0].tbl_addr_hi = cpu_to_le32((pp->cmd_tbl_dma >> 16) >> 16);
532 * Fill in command table information. First, the header,
533 * a SATA Register - Host to Device command FIS.
535 ata_tf_to_fis(&qc->tf, pp->cmd_tbl, 0);
536 if (opts & AHCI_CMD_ATAPI) {
537 memset(pp->cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
538 memcpy(pp->cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, ap->cdb_len);
541 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
547 static void ahci_intr_error(struct ata_port *ap, u32 irq_stat)
549 void *mmio = ap->host_set->mmio_base;
550 void *port_mmio = ahci_port_base(mmio, ap->port_no);
555 tmp = readl(port_mmio + PORT_CMD);
556 tmp &= ~PORT_CMD_START;
557 writel(tmp, port_mmio + PORT_CMD);
559 /* wait for engine to stop. TODO: this could be
560 * as long as 500 msec
564 tmp = readl(port_mmio + PORT_CMD);
565 if ((tmp & PORT_CMD_LIST_ON) == 0)
570 /* clear SATA phy error, if any */
571 tmp = readl(port_mmio + PORT_SCR_ERR);
572 writel(tmp, port_mmio + PORT_SCR_ERR);
574 /* if DRQ/BSY is set, device needs to be reset.
575 * if so, issue COMRESET
577 tmp = readl(port_mmio + PORT_TFDATA);
578 if (tmp & (ATA_BUSY | ATA_DRQ)) {
579 writel(0x301, port_mmio + PORT_SCR_CTL);
580 readl(port_mmio + PORT_SCR_CTL); /* flush */
582 writel(0x300, port_mmio + PORT_SCR_CTL);
583 readl(port_mmio + PORT_SCR_CTL); /* flush */
587 tmp = readl(port_mmio + PORT_CMD);
588 tmp |= PORT_CMD_START;
589 writel(tmp, port_mmio + PORT_CMD);
590 readl(port_mmio + PORT_CMD); /* flush */
592 printk(KERN_WARNING "ata%u: error occurred, port reset\n", ap->id);
595 static void ahci_eng_timeout(struct ata_port *ap)
597 struct ata_host_set *host_set = ap->host_set;
598 void *mmio = host_set->mmio_base;
599 void *port_mmio = ahci_port_base(mmio, ap->port_no);
600 struct ata_queued_cmd *qc;
605 spin_lock_irqsave(&host_set->lock, flags);
607 ahci_intr_error(ap, readl(port_mmio + PORT_IRQ_STAT));
609 qc = ata_qc_from_tag(ap, ap->active_tag);
611 printk(KERN_ERR "ata%u: BUG: timeout without command\n",
614 /* hack alert! We cannot use the supplied completion
615 * function from inside the ->eh_strategy_handler() thread.
616 * libata is the only user of ->eh_strategy_handler() in
617 * any kernel, so the default scsi_done() assumes it is
618 * not being called from the SCSI EH.
620 qc->scsidone = scsi_finish_command;
621 ata_qc_complete(qc, ATA_ERR);
624 spin_unlock_irqrestore(&host_set->lock, flags);
627 static inline int ahci_host_intr(struct ata_port *ap, struct ata_queued_cmd *qc)
629 void *mmio = ap->host_set->mmio_base;
630 void *port_mmio = ahci_port_base(mmio, ap->port_no);
631 u32 status, serr, ci;
633 serr = readl(port_mmio + PORT_SCR_ERR);
634 writel(serr, port_mmio + PORT_SCR_ERR);
636 status = readl(port_mmio + PORT_IRQ_STAT);
637 writel(status, port_mmio + PORT_IRQ_STAT);
639 ci = readl(port_mmio + PORT_CMD_ISSUE);
640 if (likely((ci & 0x1) == 0)) {
642 ata_qc_complete(qc, 0);
647 if (status & PORT_IRQ_FATAL) {
648 ahci_intr_error(ap, status);
650 ata_qc_complete(qc, ATA_ERR);
656 static void ahci_irq_clear(struct ata_port *ap)
661 static irqreturn_t ahci_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
663 struct ata_host_set *host_set = dev_instance;
664 struct ahci_host_priv *hpriv;
665 unsigned int i, handled = 0;
667 u32 irq_stat, irq_ack = 0;
671 hpriv = host_set->private_data;
672 mmio = host_set->mmio_base;
674 /* sigh. 0xffffffff is a valid return from h/w */
675 irq_stat = readl(mmio + HOST_IRQ_STAT);
676 irq_stat &= hpriv->port_map;
680 spin_lock(&host_set->lock);
682 for (i = 0; i < host_set->n_ports; i++) {
686 VPRINTK("port %u\n", i);
687 ap = host_set->ports[i];
688 tmp = irq_stat & (1 << i);
690 struct ata_queued_cmd *qc;
691 qc = ata_qc_from_tag(ap, ap->active_tag);
692 if (ahci_host_intr(ap, qc))
698 writel(irq_ack, mmio + HOST_IRQ_STAT);
702 spin_unlock(&host_set->lock);
706 return IRQ_RETVAL(handled);
709 static int ahci_qc_issue(struct ata_queued_cmd *qc)
711 struct ata_port *ap = qc->ap;
712 void *port_mmio = (void *) ap->ioaddr.cmd_addr;
714 writel(1, port_mmio + PORT_CMD_ISSUE);
715 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
720 static void ahci_setup_port(struct ata_ioports *port, unsigned long base,
721 unsigned int port_idx)
723 VPRINTK("ENTER, base==0x%lx, port_idx %u\n", base, port_idx);
724 base = ahci_port_base_ul(base, port_idx);
725 VPRINTK("base now==0x%lx\n", base);
727 port->cmd_addr = base;
728 port->scr_addr = base + PORT_SCR;
733 static int ahci_host_init(struct ata_probe_ent *probe_ent)
735 struct ahci_host_priv *hpriv = probe_ent->private_data;
736 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
737 void __iomem *mmio = probe_ent->mmio_base;
740 unsigned int i, j, using_dac;
742 void __iomem *port_mmio;
744 cap_save = readl(mmio + HOST_CAP);
745 cap_save &= ( (1<<28) | (1<<17) );
746 cap_save |= (1 << 27);
748 /* global controller reset */
749 tmp = readl(mmio + HOST_CTL);
750 if ((tmp & HOST_RESET) == 0) {
751 writel(tmp | HOST_RESET, mmio + HOST_CTL);
752 readl(mmio + HOST_CTL); /* flush */
755 /* reset must complete within 1 second, or
756 * the hardware should be considered fried.
760 tmp = readl(mmio + HOST_CTL);
761 if (tmp & HOST_RESET) {
762 printk(KERN_ERR DRV_NAME "(%s): controller reset failed (0x%x)\n",
763 pci_name(pdev), tmp);
767 writel(HOST_AHCI_EN, mmio + HOST_CTL);
768 (void) readl(mmio + HOST_CTL); /* flush */
769 writel(cap_save, mmio + HOST_CAP);
770 writel(0xf, mmio + HOST_PORTS_IMPL);
771 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
773 pci_read_config_word(pdev, 0x92, &tmp16);
775 pci_write_config_word(pdev, 0x92, tmp16);
777 hpriv->cap = readl(mmio + HOST_CAP);
778 hpriv->port_map = readl(mmio + HOST_PORTS_IMPL);
779 probe_ent->n_ports = (hpriv->cap & 0x1f) + 1;
781 VPRINTK("cap 0x%x port_map 0x%x n_ports %d\n",
782 hpriv->cap, hpriv->port_map, probe_ent->n_ports);
784 using_dac = hpriv->cap & HOST_CAP_64;
786 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
787 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
789 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
791 printk(KERN_ERR DRV_NAME "(%s): 64-bit DMA enable failed\n",
797 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
799 printk(KERN_ERR DRV_NAME "(%s): 32-bit DMA enable failed\n",
803 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
805 printk(KERN_ERR DRV_NAME "(%s): 32-bit consistent DMA enable failed\n",
811 for (i = 0; i < probe_ent->n_ports; i++) {
812 #if 0 /* BIOSen initialize this incorrectly */
813 if (!(hpriv->port_map & (1 << i)))
817 port_mmio = ahci_port_base(mmio, i);
818 VPRINTK("mmio %p port_mmio %p\n", mmio, port_mmio);
820 ahci_setup_port(&probe_ent->port[i],
821 (unsigned long) mmio, i);
823 /* make sure port is not active */
824 tmp = readl(port_mmio + PORT_CMD);
825 VPRINTK("PORT_CMD 0x%x\n", tmp);
826 if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
827 PORT_CMD_FIS_RX | PORT_CMD_START)) {
828 tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
829 PORT_CMD_FIS_RX | PORT_CMD_START);
830 writel(tmp, port_mmio + PORT_CMD);
831 readl(port_mmio + PORT_CMD); /* flush */
833 /* spec says 500 msecs for each bit, so
834 * this is slightly incorrect.
839 writel(PORT_CMD_SPIN_UP, port_mmio + PORT_CMD);
844 tmp = readl(port_mmio + PORT_SCR_STAT);
845 if ((tmp & 0xf) == 0x3)
850 tmp = readl(port_mmio + PORT_SCR_ERR);
851 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
852 writel(tmp, port_mmio + PORT_SCR_ERR);
854 /* ack any pending irq events for this port */
855 tmp = readl(port_mmio + PORT_IRQ_STAT);
856 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
858 writel(tmp, port_mmio + PORT_IRQ_STAT);
860 writel(1 << i, mmio + HOST_IRQ_STAT);
862 /* set irq mask (enables interrupts) */
863 writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
866 tmp = readl(mmio + HOST_CTL);
867 VPRINTK("HOST_CTL 0x%x\n", tmp);
868 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
869 tmp = readl(mmio + HOST_CTL);
870 VPRINTK("HOST_CTL 0x%x\n", tmp);
872 pci_set_master(pdev);
877 /* move to PCI layer, integrate w/ MSI stuff */
878 static void pci_intx(struct pci_dev *pdev, int enable)
880 u16 pci_command, new;
882 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
885 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
887 new = pci_command | PCI_COMMAND_INTX_DISABLE;
889 if (new != pci_command)
890 pci_write_config_word(pdev, PCI_COMMAND, pci_command);
893 static void ahci_print_info(struct ata_probe_ent *probe_ent)
895 struct ahci_host_priv *hpriv = probe_ent->private_data;
896 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
897 void *mmio = probe_ent->mmio_base;
898 u32 vers, cap, impl, speed;
903 vers = readl(mmio + HOST_VERSION);
905 impl = hpriv->port_map;
907 speed = (cap >> 20) & 0xf;
915 pci_read_config_word(pdev, 0x0a, &cc);
918 else if (cc == 0x0106)
920 else if (cc == 0x0104)
925 printk(KERN_INFO DRV_NAME "(%s) AHCI %02x%02x.%02x%02x "
926 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
935 ((cap >> 8) & 0x1f) + 1,
941 printk(KERN_INFO DRV_NAME "(%s) flags: "
947 cap & (1 << 31) ? "64bit " : "",
948 cap & (1 << 30) ? "ncq " : "",
949 cap & (1 << 28) ? "ilck " : "",
950 cap & (1 << 27) ? "stag " : "",
951 cap & (1 << 26) ? "pm " : "",
952 cap & (1 << 25) ? "led " : "",
954 cap & (1 << 24) ? "clo " : "",
955 cap & (1 << 19) ? "nz " : "",
956 cap & (1 << 18) ? "only " : "",
957 cap & (1 << 17) ? "pmp " : "",
958 cap & (1 << 15) ? "pio " : "",
959 cap & (1 << 14) ? "slum " : "",
960 cap & (1 << 13) ? "part " : ""
964 static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
966 static int printed_version;
967 struct ata_probe_ent *probe_ent = NULL;
968 struct ahci_host_priv *hpriv;
971 unsigned int board_idx = (unsigned int) ent->driver_data;
972 int have_msi, pci_dev_busy = 0;
977 if (!printed_version++)
978 printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");
980 rc = pci_enable_device(pdev);
984 rc = pci_request_regions(pdev, DRV_NAME);
990 if (pci_enable_msi(pdev) == 0)
997 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
998 if (probe_ent == NULL) {
1003 memset(probe_ent, 0, sizeof(*probe_ent));
1004 probe_ent->dev = pci_dev_to_dev(pdev);
1005 INIT_LIST_HEAD(&probe_ent->node);
1007 mmio_base = ioremap(pci_resource_start(pdev, AHCI_PCI_BAR),
1008 pci_resource_len(pdev, AHCI_PCI_BAR));
1009 if (mmio_base == NULL) {
1011 goto err_out_free_ent;
1013 base = (unsigned long) mmio_base;
1015 hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
1018 goto err_out_iounmap;
1020 memset(hpriv, 0, sizeof(*hpriv));
1022 probe_ent->sht = ahci_port_info[board_idx].sht;
1023 probe_ent->host_flags = ahci_port_info[board_idx].host_flags;
1024 probe_ent->pio_mask = ahci_port_info[board_idx].pio_mask;
1025 probe_ent->udma_mask = ahci_port_info[board_idx].udma_mask;
1026 probe_ent->port_ops = ahci_port_info[board_idx].port_ops;
1028 probe_ent->irq = pdev->irq;
1029 probe_ent->irq_flags = SA_SHIRQ;
1030 probe_ent->mmio_base = mmio_base;
1031 probe_ent->private_data = hpriv;
1034 hpriv->flags |= AHCI_FLAG_MSI;
1036 /* initialize adapter */
1037 rc = ahci_host_init(probe_ent);
1041 ahci_print_info(probe_ent);
1043 /* FIXME: check ata_device_add return value */
1044 ata_device_add(probe_ent);
1057 pci_disable_msi(pdev);
1060 pci_release_regions(pdev);
1063 pci_disable_device(pdev);
1067 static void ahci_remove_one (struct pci_dev *pdev)
1069 struct device *dev = pci_dev_to_dev(pdev);
1070 struct ata_host_set *host_set = dev_get_drvdata(dev);
1071 struct ahci_host_priv *hpriv = host_set->private_data;
1072 struct ata_port *ap;
1076 for (i = 0; i < host_set->n_ports; i++) {
1077 ap = host_set->ports[i];
1079 scsi_remove_host(ap->host);
1082 have_msi = hpriv->flags & AHCI_FLAG_MSI;
1083 free_irq(host_set->irq, host_set);
1085 for (i = 0; i < host_set->n_ports; i++) {
1086 ap = host_set->ports[i];
1088 ata_scsi_release(ap->host);
1089 scsi_host_put(ap->host);
1092 host_set->ops->host_stop(host_set);
1096 pci_disable_msi(pdev);
1099 pci_release_regions(pdev);
1100 pci_disable_device(pdev);
1101 dev_set_drvdata(dev, NULL);
1104 static int __init ahci_init(void)
1106 return pci_module_init(&ahci_pci_driver);
1110 static void __exit ahci_exit(void)
1112 pci_unregister_driver(&ahci_pci_driver);
1116 MODULE_AUTHOR("Jeff Garzik");
1117 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1118 MODULE_LICENSE("GPL");
1119 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1120 MODULE_VERSION(DRV_VERSION);
1122 module_init(ahci_init);
1123 module_exit(ahci_exit);