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   1 /* sunsab.c: ASYNC Driver for the SIEMENS SAB82532 DUSCC.
   2  *
   3  * Copyright (C) 1997  Eddie C. Dost  (ecd@skynet.be)
   4  * Copyright (C) 2002, 2006  David S. Miller (davem@davemloft.net)
   5  *
   6  * Rewrote buffer handling to use CIRC(Circular Buffer) macros.
   7  *   Maxim Krasnyanskiy <maxk@qualcomm.com>
   8  *
   9  * Fixed to use tty_get_baud_rate, and to allow for arbitrary baud
  10  * rates to be programmed into the UART.  Also eliminated a lot of
  11  * duplicated code in the console setup.
  12  *   Theodore Ts'o <tytso@mit.edu>, 2001-Oct-12
  13  *
  14  * Ported to new 2.5.x UART layer.
  15  *   David S. Miller <davem@davemloft.net>
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/kernel.h>
  20 #include <linux/sched.h>
  21 #include <linux/errno.h>
  22 #include <linux/tty.h>
  23 #include <linux/tty_flip.h>
  24 #include <linux/major.h>
  25 #include <linux/string.h>
  26 #include <linux/ptrace.h>
  27 #include <linux/ioport.h>
  28 #include <linux/circ_buf.h>
  29 #include <linux/serial.h>
  30 #include <linux/sysrq.h>
  31 #include <linux/console.h>
  32 #include <linux/spinlock.h>
  33 #include <linux/slab.h>
  34 #include <linux/delay.h>
  35 #include <linux/init.h>
  36
  37 #include <asm/io.h>
  38 #include <asm/irq.h>
  39 #include <asm/prom.h>
  40 #include <asm/of_device.h>
  41
  42 #if defined(CONFIG_SERIAL_SUNZILOG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  43 #define SUPPORT_SYSRQ
  44 #endif
  45
  46 #include <linux/serial_core.h>
  47
  48 #include "suncore.h"
  49 #include "sunsab.h"
  50
  51 struct uart_sunsab_port {
  52         struct uart_port                port;           /* Generic UART port    */
  53         union sab82532_async_regs       __iomem *regs;  /* Chip registers       */
  54         unsigned long                   irqflags;       /* IRQ state flags      */
  55         int                             dsr;            /* Current DSR state    */
  56         unsigned int                    cec_timeout;    /* Chip poll timeout... */
  57         unsigned int                    tec_timeout;    /* likewise             */
  58         unsigned char                   interrupt_mask0;/* ISR0 masking         */
  59         unsigned char                   interrupt_mask1;/* ISR1 masking         */
  60         unsigned char                   pvr_dtr_bit;    /* Which PVR bit is DTR */
  61         unsigned char                   pvr_dsr_bit;    /* Which PVR bit is DSR */
  62         int                             type;           /* SAB82532 version     */
  63
  64         /* Setting configuration bits while the transmitter is active
  65          * can cause garbage characters to get emitted by the chip.
  66          * Therefore, we cache such writes here and do the real register
  67          * write the next time the transmitter becomes idle.
  68          */
  69         unsigned int                    cached_ebrg;
  70         unsigned char                   cached_mode;
  71         unsigned char                   cached_pvr;
  72         unsigned char                   cached_dafo;
  73 };
  74
  75 /*
  76  * This assumes you have a 29.4912 MHz clock for your UART.
  77  */
  78 #define SAB_BASE_BAUD ( 29491200 / 16 )
  79
  80 static char *sab82532_version[16] = {
  81         "V1.0", "V2.0", "V3.2", "V(0x03)",
  82         "V(0x04)", "V(0x05)", "V(0x06)", "V(0x07)",
  83         "V(0x08)", "V(0x09)", "V(0x0a)", "V(0x0b)",
  84         "V(0x0c)", "V(0x0d)", "V(0x0e)", "V(0x0f)"
  85 };
  86
  87 #define SAB82532_MAX_TEC_TIMEOUT 200000 /* 1 character time (at 50 baud) */
  88 #define SAB82532_MAX_CEC_TIMEOUT  50000 /* 2.5 TX CLKs (at 50 baud) */
  89
  90 #define SAB82532_RECV_FIFO_SIZE 32      /* Standard async fifo sizes */
  91 #define SAB82532_XMIT_FIFO_SIZE 32
  92
  93 static __inline__ void sunsab_tec_wait(struct uart_sunsab_port *up)
  94 {
  95         int timeout = up->tec_timeout;
  96
  97         while ((readb(&up->regs->r.star) & SAB82532_STAR_TEC) && --timeout)
  98                 udelay(1);
  99 }
 100
 101 static __inline__ void sunsab_cec_wait(struct uart_sunsab_port *up)
 102 {
 103         int timeout = up->cec_timeout;
 104
 105         while ((readb(&up->regs->r.star) & SAB82532_STAR_CEC) && --timeout)
 106                 udelay(1);
 107 }
 108
 109 static struct tty_struct *
 110 receive_chars(struct uart_sunsab_port *up,
 111               union sab82532_irq_status *stat)
 112 {
 113         struct tty_struct *tty = NULL;
 114         unsigned char buf[32];
 115         int saw_console_brk = 0;
 116         int free_fifo = 0;
 117         int count = 0;
 118         int i;
 119
 120         if (up->port.info != NULL)              /* Unopened serial console */
 121                 tty = up->port.info->tty;
 122
 123         /* Read number of BYTES (Character + Status) available. */
 124         if (stat->sreg.isr0 & SAB82532_ISR0_RPF) {
 125                 count = SAB82532_RECV_FIFO_SIZE;
 126                 free_fifo++;
 127         }
 128
 129         if (stat->sreg.isr0 & SAB82532_ISR0_TCD) {
 130                 count = readb(&up->regs->r.rbcl) & (SAB82532_RECV_FIFO_SIZE - 1);
 131                 free_fifo++;
 132         }
 133
 134         /* Issue a FIFO read command in case we where idle. */
 135         if (stat->sreg.isr0 & SAB82532_ISR0_TIME) {
 136                 sunsab_cec_wait(up);
 137                 writeb(SAB82532_CMDR_RFRD, &up->regs->w.cmdr);
 138                 return tty;
 139         }
 140
 141         if (stat->sreg.isr0 & SAB82532_ISR0_RFO)
 142                 free_fifo++;
 143
 144         /* Read the FIFO. */
 145         for (i = 0; i < count; i++)
 146                 buf[i] = readb(&up->regs->r.rfifo[i]);
 147
 148         /* Issue Receive Message Complete command. */
 149         if (free_fifo) {
 150                 sunsab_cec_wait(up);
 151                 writeb(SAB82532_CMDR_RMC, &up->regs->w.cmdr);
 152         }
 153
 154         /* Count may be zero for BRK, so we check for it here */
 155         if ((stat->sreg.isr1 & SAB82532_ISR1_BRK) &&
 156             (up->port.line == up->port.cons->index))
 157                 saw_console_brk = 1;
 158
 159         for (i = 0; i < count; i++) {
 160                 unsigned char ch = buf[i], flag;
 161
 162                 if (tty == NULL) {
 163                         uart_handle_sysrq_char(&up->port, ch);
 164                         continue;
 165                 }
 166
 167                 flag = TTY_NORMAL;
 168                 up->port.icount.rx++;
 169
 170                 if (unlikely(stat->sreg.isr0 & (SAB82532_ISR0_PERR |
 171                                                 SAB82532_ISR0_FERR |
 172                                                 SAB82532_ISR0_RFO)) ||
 173                     unlikely(stat->sreg.isr1 & SAB82532_ISR1_BRK)) {
 174                         /*
 175                          * For statistics only
 176                          */
 177                         if (stat->sreg.isr1 & SAB82532_ISR1_BRK) {
 178                                 stat->sreg.isr0 &= ~(SAB82532_ISR0_PERR |
 179                                                      SAB82532_ISR0_FERR);
 180                                 up->port.icount.brk++;
 181                                 /*
 182                                  * We do the SysRQ and SAK checking
 183                                  * here because otherwise the break
 184                                  * may get masked by ignore_status_mask
 185                                  * or read_status_mask.
 186                                  */
 187                                 if (uart_handle_break(&up->port))
 188                                         continue;
 189                         } else if (stat->sreg.isr0 & SAB82532_ISR0_PERR)
 190                                 up->port.icount.parity++;
 191                         else if (stat->sreg.isr0 & SAB82532_ISR0_FERR)
 192                                 up->port.icount.frame++;
 193                         if (stat->sreg.isr0 & SAB82532_ISR0_RFO)
 194                                 up->port.icount.overrun++;
 195
 196                         /*
 197                          * Mask off conditions which should be ingored.
 198                          */
 199                         stat->sreg.isr0 &= (up->port.read_status_mask & 0xff);
 200                         stat->sreg.isr1 &= ((up->port.read_status_mask >> 8) & 0xff);
 201
 202                         if (stat->sreg.isr1 & SAB82532_ISR1_BRK) {
 203                                 flag = TTY_BREAK;
 204                         } else if (stat->sreg.isr0 & SAB82532_ISR0_PERR)
 205                                 flag = TTY_PARITY;
 206                         else if (stat->sreg.isr0 & SAB82532_ISR0_FERR)
 207                                 flag = TTY_FRAME;
 208                 }
 209
 210                 if (uart_handle_sysrq_char(&up->port, ch))
 211                         continue;
 212
 213                 if ((stat->sreg.isr0 & (up->port.ignore_status_mask & 0xff)) == 0 &&
 214                     (stat->sreg.isr1 & ((up->port.ignore_status_mask >> 8) & 0xff)) == 0)
 215                         tty_insert_flip_char(tty, ch, flag);
 216                 if (stat->sreg.isr0 & SAB82532_ISR0_RFO)
 217                         tty_insert_flip_char(tty, 0, TTY_OVERRUN);
 218         }
 219
 220         if (saw_console_brk)
 221                 sun_do_break();
 222
 223         return tty;
 224 }
 225
 226 static void sunsab_stop_tx(struct uart_port *);
 227 static void sunsab_tx_idle(struct uart_sunsab_port *);
 228
 229 static void transmit_chars(struct uart_sunsab_port *up,
 230                            union sab82532_irq_status *stat)
 231 {
 232         struct circ_buf *xmit = &up->port.info->xmit;
 233         int i;
 234
 235         if (stat->sreg.isr1 & SAB82532_ISR1_ALLS) {
 236                 up->interrupt_mask1 |= SAB82532_IMR1_ALLS;
 237                 writeb(up->interrupt_mask1, &up->regs->w.imr1);
 238                 set_bit(SAB82532_ALLS, &up->irqflags);
 239         }
 240
 241 #if 0 /* bde@nwlink.com says this check causes problems */
 242         if (!(stat->sreg.isr1 & SAB82532_ISR1_XPR))
 243                 return;
 244 #endif
 245
 246         if (!(readb(&up->regs->r.star) & SAB82532_STAR_XFW))
 247                 return;
 248
 249         set_bit(SAB82532_XPR, &up->irqflags);
 250         sunsab_tx_idle(up);
 251
 252         if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
 253                 up->interrupt_mask1 |= SAB82532_IMR1_XPR;
 254                 writeb(up->interrupt_mask1, &up->regs->w.imr1);
 255                 return;
 256         }
 257
 258         up->interrupt_mask1 &= ~(SAB82532_IMR1_ALLS|SAB82532_IMR1_XPR);
 259         writeb(up->interrupt_mask1, &up->regs->w.imr1);
 260         clear_bit(SAB82532_ALLS, &up->irqflags);
 261
 262         /* Stuff 32 bytes into Transmit FIFO. */
 263         clear_bit(SAB82532_XPR, &up->irqflags);
 264         for (i = 0; i < up->port.fifosize; i++) {
 265                 writeb(xmit->buf[xmit->tail],
 266                        &up->regs->w.xfifo[i]);
 267                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 268                 up->port.icount.tx++;
 269                 if (uart_circ_empty(xmit))
 270                         break;
 271         }
 272
 273         /* Issue a Transmit Frame command. */
 274         sunsab_cec_wait(up);
 275         writeb(SAB82532_CMDR_XF, &up->regs->w.cmdr);
 276
 277         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 278                 uart_write_wakeup(&up->port);
 279
 280         if (uart_circ_empty(xmit))
 281                 sunsab_stop_tx(&up->port);
 282 }
 283
 284 static void check_status(struct uart_sunsab_port *up,
 285                          union sab82532_irq_status *stat)
 286 {
 287         if (stat->sreg.isr0 & SAB82532_ISR0_CDSC)
 288                 uart_handle_dcd_change(&up->port,
 289                                        !(readb(&up->regs->r.vstr) & SAB82532_VSTR_CD));
 290
 291         if (stat->sreg.isr1 & SAB82532_ISR1_CSC)
 292                 uart_handle_cts_change(&up->port,
 293                                        (readb(&up->regs->r.star) & SAB82532_STAR_CTS));
 294
 295         if ((readb(&up->regs->r.pvr) & up->pvr_dsr_bit) ^ up->dsr) {
 296                 up->dsr = (readb(&up->regs->r.pvr) & up->pvr_dsr_bit) ? 0 : 1;
 297                 up->port.icount.dsr++;
 298         }
 299
 300         wake_up_interruptible(&up->port.info->delta_msr_wait);
 301 }
 302
 303 static irqreturn_t sunsab_interrupt(int irq, void *dev_id)
 304 {
 305         struct uart_sunsab_port *up = dev_id;
 306         struct tty_struct *tty;
 307         union sab82532_irq_status status;
 308         unsigned long flags;
 309
 310         spin_lock_irqsave(&up->port.lock, flags);
 311
 312         status.stat = 0;
 313         if (readb(&up->regs->r.gis) & SAB82532_GIS_ISA0)
 314                 status.sreg.isr0 = readb(&up->regs->r.isr0);
 315         if (readb(&up->regs->r.gis) & SAB82532_GIS_ISA1)
 316                 status.sreg.isr1 = readb(&up->regs->r.isr1);
 317
 318         tty = NULL;
 319         if (status.stat) {
 320                 if ((status.sreg.isr0 & (SAB82532_ISR0_TCD | SAB82532_ISR0_TIME |
 321                                          SAB82532_ISR0_RFO | SAB82532_ISR0_RPF)) ||
 322                     (status.sreg.isr1 & SAB82532_ISR1_BRK))
 323                         tty = receive_chars(up, &status);
 324                 if ((status.sreg.isr0 & SAB82532_ISR0_CDSC) ||
 325                     (status.sreg.isr1 & SAB82532_ISR1_CSC))
 326                         check_status(up, &status);
 327                 if (status.sreg.isr1 & (SAB82532_ISR1_ALLS | SAB82532_ISR1_XPR))
 328                         transmit_chars(up, &status);
 329         }
 330
 331         spin_unlock(&up->port.lock);
 332
 333         if (tty)
 334                 tty_flip_buffer_push(tty);
 335
 336         up++;
 337
 338         spin_lock(&up->port.lock);
 339
 340         status.stat = 0;
 341         if (readb(&up->regs->r.gis) & SAB82532_GIS_ISB0)
 342                 status.sreg.isr0 = readb(&up->regs->r.isr0);
 343         if (readb(&up->regs->r.gis) & SAB82532_GIS_ISB1)
 344                 status.sreg.isr1 = readb(&up->regs->r.isr1);
 345
 346         tty = NULL;
 347         if (status.stat) {
 348                 if ((status.sreg.isr0 & (SAB82532_ISR0_TCD | SAB82532_ISR0_TIME |
 349                                          SAB82532_ISR0_RFO | SAB82532_ISR0_RPF)) ||
 350                     (status.sreg.isr1 & SAB82532_ISR1_BRK))
 351
 352                         tty = receive_chars(up, &status);
 353                 if ((status.sreg.isr0 & SAB82532_ISR0_CDSC) ||
 354                     (status.sreg.isr1 & (SAB82532_ISR1_BRK | SAB82532_ISR1_CSC)))
 355                         check_status(up, &status);
 356                 if (status.sreg.isr1 & (SAB82532_ISR1_ALLS | SAB82532_ISR1_XPR))
 357                         transmit_chars(up, &status);
 358         }
 359
 360         spin_unlock_irqrestore(&up->port.lock, flags);
 361
 362         if (tty)
 363                 tty_flip_buffer_push(tty);
 364
 365         return IRQ_HANDLED;
 366 }
 367
 368 /* port->lock is not held.  */
 369 static unsigned int sunsab_tx_empty(struct uart_port *port)
 370 {
 371         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
 372         int ret;
 373
 374         /* Do not need a lock for a state test like this.  */
 375         if (test_bit(SAB82532_ALLS, &up->irqflags))
 376                 ret = TIOCSER_TEMT;
 377         else
 378                 ret = 0;
 379
 380         return ret;
 381 }
 382
 383 /* port->lock held by caller.  */
 384 static void sunsab_set_mctrl(struct uart_port *port, unsigned int mctrl)
 385 {
 386         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
 387
 388         if (mctrl & TIOCM_RTS) {
 389                 up->cached_mode &= ~SAB82532_MODE_FRTS;
 390                 up->cached_mode |= SAB82532_MODE_RTS;
 391         } else {
 392                 up->cached_mode |= (SAB82532_MODE_FRTS |
 393                                     SAB82532_MODE_RTS);
 394         }
 395         if (mctrl & TIOCM_DTR) {
 396                 up->cached_pvr &= ~(up->pvr_dtr_bit);
 397         } else {
 398                 up->cached_pvr |= up->pvr_dtr_bit;
 399         }
 400
 401         set_bit(SAB82532_REGS_PENDING, &up->irqflags);
 402         if (test_bit(SAB82532_XPR, &up->irqflags))
 403                 sunsab_tx_idle(up);
 404 }
 405
 406 /* port->lock is held by caller and interrupts are disabled.  */
 407 static unsigned int sunsab_get_mctrl(struct uart_port *port)
 408 {
 409         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
 410         unsigned char val;
 411         unsigned int result;
 412
 413         result = 0;
 414
 415         val = readb(&up->regs->r.pvr);
 416         result |= (val & up->pvr_dsr_bit) ? 0 : TIOCM_DSR;
 417
 418         val = readb(&up->regs->r.vstr);
 419         result |= (val & SAB82532_VSTR_CD) ? 0 : TIOCM_CAR;
 420
 421         val = readb(&up->regs->r.star);
 422         result |= (val & SAB82532_STAR_CTS) ? TIOCM_CTS : 0;
 423
 424         return result;
 425 }
 426
 427 /* port->lock held by caller.  */
 428 static void sunsab_stop_tx(struct uart_port *port)
 429 {
 430         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
 431
 432         up->interrupt_mask1 |= SAB82532_IMR1_XPR;
 433         writeb(up->interrupt_mask1, &up->regs->w.imr1);
 434 }
 435
 436 /* port->lock held by caller.  */
 437 static void sunsab_tx_idle(struct uart_sunsab_port *up)
 438 {
 439         if (test_bit(SAB82532_REGS_PENDING, &up->irqflags)) {
 440                 u8 tmp;
 441
 442                 clear_bit(SAB82532_REGS_PENDING, &up->irqflags);
 443                 writeb(up->cached_mode, &up->regs->rw.mode);
 444                 writeb(up->cached_pvr, &up->regs->rw.pvr);
 445                 writeb(up->cached_dafo, &up->regs->w.dafo);
 446
 447                 writeb(up->cached_ebrg & 0xff, &up->regs->w.bgr);
 448                 tmp = readb(&up->regs->rw.ccr2);
 449                 tmp &= ~0xc0;
 450                 tmp |= (up->cached_ebrg >> 2) & 0xc0;
 451                 writeb(tmp, &up->regs->rw.ccr2);
 452         }
 453 }
 454
 455 /* port->lock held by caller.  */
 456 static void sunsab_start_tx(struct uart_port *port)
 457 {
 458         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
 459         struct circ_buf *xmit = &up->port.info->xmit;
 460         int i;
 461
 462         up->interrupt_mask1 &= ~(SAB82532_IMR1_ALLS|SAB82532_IMR1_XPR);
 463         writeb(up->interrupt_mask1, &up->regs->w.imr1);
 464
 465         if (!test_bit(SAB82532_XPR, &up->irqflags))
 466                 return;
 467
 468         clear_bit(SAB82532_ALLS, &up->irqflags);
 469         clear_bit(SAB82532_XPR, &up->irqflags);
 470
 471         for (i = 0; i < up->port.fifosize; i++) {
 472                 writeb(xmit->buf[xmit->tail],
 473                        &up->regs->w.xfifo[i]);
 474                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 475                 up->port.icount.tx++;
 476                 if (uart_circ_empty(xmit))
 477                         break;
 478         }
 479
 480         /* Issue a Transmit Frame command.  */
 481         sunsab_cec_wait(up);
 482         writeb(SAB82532_CMDR_XF, &up->regs->w.cmdr);
 483 }
 484
 485 /* port->lock is not held.  */
 486 static void sunsab_send_xchar(struct uart_port *port, char ch)
 487 {
 488         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
 489         unsigned long flags;
 490
 491         spin_lock_irqsave(&up->port.lock, flags);
 492
 493         sunsab_tec_wait(up);
 494         writeb(ch, &up->regs->w.tic);
 495
 496         spin_unlock_irqrestore(&up->port.lock, flags);
 497 }
 498
 499 /* port->lock held by caller.  */
 500 static void sunsab_stop_rx(struct uart_port *port)
 501 {
 502         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
 503
 504         up->interrupt_mask0 |= SAB82532_ISR0_TCD;
 505         writeb(up->interrupt_mask1, &up->regs->w.imr0);
 506 }
 507
 508 /* port->lock held by caller.  */
 509 static void sunsab_enable_ms(struct uart_port *port)
 510 {
 511         /* For now we always receive these interrupts.  */
 512 }
 513
 514 /* port->lock is not held.  */
 515 static void sunsab_break_ctl(struct uart_port *port, int break_state)
 516 {
 517         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
 518         unsigned long flags;
 519         unsigned char val;
 520
 521         spin_lock_irqsave(&up->port.lock, flags);
 522
 523         val = up->cached_dafo;
 524         if (break_state)
 525                 val |= SAB82532_DAFO_XBRK;
 526         else
 527                 val &= ~SAB82532_DAFO_XBRK;
 528         up->cached_dafo = val;
 529
 530         set_bit(SAB82532_REGS_PENDING, &up->irqflags);
 531         if (test_bit(SAB82532_XPR, &up->irqflags))
 532                 sunsab_tx_idle(up);
 533
 534         spin_unlock_irqrestore(&up->port.lock, flags);
 535 }
 536
 537 /* port->lock is not held.  */
 538 static int sunsab_startup(struct uart_port *port)
 539 {
 540         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
 541         unsigned long flags;
 542         unsigned char tmp;
 543
 544         spin_lock_irqsave(&up->port.lock, flags);
 545
 546         /*
 547          * Wait for any commands or immediate characters
 548          */
 549         sunsab_cec_wait(up);
 550         sunsab_tec_wait(up);
 551
 552         /*
 553          * Clear the FIFO buffers.
 554          */
 555         writeb(SAB82532_CMDR_RRES, &up->regs->w.cmdr);
 556         sunsab_cec_wait(up);
 557         writeb(SAB82532_CMDR_XRES, &up->regs->w.cmdr);
 558
 559         /*
 560          * Clear the interrupt registers.
 561          */
 562         (void) readb(&up->regs->r.isr0);
 563         (void) readb(&up->regs->r.isr1);
 564
 565         /*
 566          * Now, initialize the UART
 567          */
 568         writeb(0, &up->regs->w.ccr0);                           /* power-down */
 569         writeb(SAB82532_CCR0_MCE | SAB82532_CCR0_SC_NRZ |
 570                SAB82532_CCR0_SM_ASYNC, &up->regs->w.ccr0);
 571         writeb(SAB82532_CCR1_ODS | SAB82532_CCR1_BCR | 7, &up->regs->w.ccr1);
 572         writeb(SAB82532_CCR2_BDF | SAB82532_CCR2_SSEL |
 573                SAB82532_CCR2_TOE, &up->regs->w.ccr2);
 574         writeb(0, &up->regs->w.ccr3);
 575         writeb(SAB82532_CCR4_MCK4 | SAB82532_CCR4_EBRG, &up->regs->w.ccr4);
 576         up->cached_mode = (SAB82532_MODE_RTS | SAB82532_MODE_FCTS |
 577                            SAB82532_MODE_RAC);
 578         writeb(up->cached_mode, &up->regs->w.mode);
 579         writeb(SAB82532_RFC_DPS|SAB82532_RFC_RFTH_32, &up->regs->w.rfc);
 580
 581         tmp = readb(&up->regs->rw.ccr0);
 582         tmp |= SAB82532_CCR0_PU;        /* power-up */
 583         writeb(tmp, &up->regs->rw.ccr0);
 584
 585         /*
 586          * Finally, enable interrupts
 587          */
 588         up->interrupt_mask0 = (SAB82532_IMR0_PERR | SAB82532_IMR0_FERR |
 589                                SAB82532_IMR0_PLLA);
 590         writeb(up->interrupt_mask0, &up->regs->w.imr0);
 591         up->interrupt_mask1 = (SAB82532_IMR1_BRKT | SAB82532_IMR1_ALLS |
 592                                SAB82532_IMR1_XOFF | SAB82532_IMR1_TIN |
 593                                SAB82532_IMR1_CSC | SAB82532_IMR1_XON |
 594                                SAB82532_IMR1_XPR);
 595         writeb(up->interrupt_mask1, &up->regs->w.imr1);
 596         set_bit(SAB82532_ALLS, &up->irqflags);
 597         set_bit(SAB82532_XPR, &up->irqflags);
 598
 599         spin_unlock_irqrestore(&up->port.lock, flags);
 600
 601         return 0;
 602 }
 603
 604 /* port->lock is not held.  */
 605 static void sunsab_shutdown(struct uart_port *port)
 606 {
 607         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
 608         unsigned long flags;
 609
 610         spin_lock_irqsave(&up->port.lock, flags);
 611
 612         /* Disable Interrupts */
 613         up->interrupt_mask0 = 0xff;
 614         writeb(up->interrupt_mask0, &up->regs->w.imr0);
 615         up->interrupt_mask1 = 0xff;
 616         writeb(up->interrupt_mask1, &up->regs->w.imr1);
 617
 618         /* Disable break condition */
 619         up->cached_dafo = readb(&up->regs->rw.dafo);
 620         up->cached_dafo &= ~SAB82532_DAFO_XBRK;
 621         writeb(up->cached_dafo, &up->regs->rw.dafo);
 622
 623         /* Disable Receiver */
 624         up->cached_mode &= ~SAB82532_MODE_RAC;
 625         writeb(up->cached_mode, &up->regs->rw.mode);
 626
 627         /*
 628          * XXX FIXME
 629          *
 630          * If the chip is powered down here the system hangs/crashes during
 631          * reboot or shutdown.  This needs to be investigated further,
 632          * similar behaviour occurs in 2.4 when the driver is configured
 633          * as a module only.  One hint may be that data is sometimes
 634          * transmitted at 9600 baud during shutdown (regardless of the
 635          * speed the chip was configured for when the port was open).
 636          */
 637 #if 0
 638         /* Power Down */
 639         tmp = readb(&up->regs->rw.ccr0);
 640         tmp &= ~SAB82532_CCR0_PU;
 641         writeb(tmp, &up->regs->rw.ccr0);
 642 #endif
 643
 644         spin_unlock_irqrestore(&up->port.lock, flags);
 645 }
 646
 647 /*
 648  * This is used to figure out the divisor speeds.
 649  *
 650  * The formula is:    Baud = SAB_BASE_BAUD / ((N + 1) * (1 << M)),
 651  *
 652  * with               0 <= N < 64 and 0 <= M < 16
 653  */
 654
 655 static void calc_ebrg(int baud, int *n_ret, int *m_ret)
 656 {
 657         int     n, m;
 658
 659         if (baud == 0) {
 660                 *n_ret = 0;
 661                 *m_ret = 0;
 662                 return;
 663         }
 664
 665         /*
 666          * We scale numbers by 10 so that we get better accuracy
 667          * without having to use floating point.  Here we increment m
 668          * until n is within the valid range.
 669          */
 670         n = (SAB_BASE_BAUD * 10) / baud;
 671         m = 0;
 672         while (n >= 640) {
 673                 n = n / 2;
 674                 m++;
 675         }
 676         n = (n+5) / 10;
 677         /*
 678          * We try very hard to avoid speeds with M == 0 since they may
 679          * not work correctly for XTAL frequences above 10 MHz.
 680          */
 681         if ((m == 0) && ((n & 1) == 0)) {
 682                 n = n / 2;
 683                 m++;
 684         }
 685         *n_ret = n - 1;
 686         *m_ret = m;
 687 }
 688
 689 /* Internal routine, port->lock is held and local interrupts are disabled.  */
 690 static void sunsab_convert_to_sab(struct uart_sunsab_port *up, unsigned int cflag,
 691                                   unsigned int iflag, unsigned int baud,
 692                                   unsigned int quot)
 693 {
 694         unsigned char dafo;
 695         int bits, n, m;
 696
 697         /* Byte size and parity */
 698         switch (cflag & CSIZE) {
 699               case CS5: dafo = SAB82532_DAFO_CHL5; bits = 7; break;
 700               case CS6: dafo = SAB82532_DAFO_CHL6; bits = 8; break;
 701               case CS7: dafo = SAB82532_DAFO_CHL7; bits = 9; break;
 702               case CS8: dafo = SAB82532_DAFO_CHL8; bits = 10; break;
 703               /* Never happens, but GCC is too dumb to figure it out */
 704               default:  dafo = SAB82532_DAFO_CHL5; bits = 7; break;
 705         }
 706
 707         if (cflag & CSTOPB) {
 708                 dafo |= SAB82532_DAFO_STOP;
 709                 bits++;
 710         }
 711
 712         if (cflag & PARENB) {
 713                 dafo |= SAB82532_DAFO_PARE;
 714                 bits++;
 715         }
 716
 717         if (cflag & PARODD) {
 718                 dafo |= SAB82532_DAFO_PAR_ODD;
 719         } else {
 720                 dafo |= SAB82532_DAFO_PAR_EVEN;
 721         }
 722         up->cached_dafo = dafo;
 723
 724         calc_ebrg(baud, &n, &m);
 725
 726         up->cached_ebrg = n | (m << 6);
 727
 728         up->tec_timeout = (10 * 1000000) / baud;
 729         up->cec_timeout = up->tec_timeout >> 2;
 730
 731         /* CTS flow control flags */
 732         /* We encode read_status_mask and ignore_status_mask like so:
 733          *
 734          * ---------------------
 735          * | ... | ISR1 | ISR0 |
 736          * ---------------------
 737          *  ..    15   8 7    0
 738          */
 739
 740         up->port.read_status_mask = (SAB82532_ISR0_TCD | SAB82532_ISR0_TIME |
 741                                      SAB82532_ISR0_RFO | SAB82532_ISR0_RPF |
 742                                      SAB82532_ISR0_CDSC);
 743         up->port.read_status_mask |= (SAB82532_ISR1_CSC |
 744                                       SAB82532_ISR1_ALLS |
 745                                       SAB82532_ISR1_XPR) << 8;
 746         if (iflag & INPCK)
 747                 up->port.read_status_mask |= (SAB82532_ISR0_PERR |
 748                                               SAB82532_ISR0_FERR);
 749         if (iflag & (BRKINT | PARMRK))
 750                 up->port.read_status_mask |= (SAB82532_ISR1_BRK << 8);
 751
 752         /*
 753          * Characteres to ignore
 754          */
 755         up->port.ignore_status_mask = 0;
 756         if (iflag & IGNPAR)
 757                 up->port.ignore_status_mask |= (SAB82532_ISR0_PERR |
 758                                                 SAB82532_ISR0_FERR);
 759         if (iflag & IGNBRK) {
 760                 up->port.ignore_status_mask |= (SAB82532_ISR1_BRK << 8);
 761                 /*
 762                  * If we're ignoring parity and break indicators,
 763                  * ignore overruns too (for real raw support).
 764                  */
 765                 if (iflag & IGNPAR)
 766                         up->port.ignore_status_mask |= SAB82532_ISR0_RFO;
 767         }
 768
 769         /*
 770          * ignore all characters if CREAD is not set
 771          */
 772         if ((cflag & CREAD) == 0)
 773                 up->port.ignore_status_mask |= (SAB82532_ISR0_RPF |
 774                                                 SAB82532_ISR0_TCD);
 775
 776         uart_update_timeout(&up->port, cflag,
 777                             (up->port.uartclk / (16 * quot)));
 778
 779         /* Now schedule a register update when the chip's
 780          * transmitter is idle.
 781          */
 782         up->cached_mode |= SAB82532_MODE_RAC;
 783         set_bit(SAB82532_REGS_PENDING, &up->irqflags);
 784         if (test_bit(SAB82532_XPR, &up->irqflags))
 785                 sunsab_tx_idle(up);
 786 }
 787
 788 /* port->lock is not held.  */
 789 static void sunsab_set_termios(struct uart_port *port, struct termios *termios,
 790                                struct termios *old)
 791 {
 792         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
 793         unsigned long flags;
 794         unsigned int baud = uart_get_baud_rate(port, termios, old, 0, 4000000);
 795         unsigned int quot = uart_get_divisor(port, baud);
 796
 797         spin_lock_irqsave(&up->port.lock, flags);
 798         sunsab_convert_to_sab(up, termios->c_cflag, termios->c_iflag, baud, quot);
 799         spin_unlock_irqrestore(&up->port.lock, flags);
 800 }
 801
 802 static const char *sunsab_type(struct uart_port *port)
 803 {
 804         struct uart_sunsab_port *up = (void *)port;
 805         static char buf[36];
 806
 807         sprintf(buf, "SAB82532 %s", sab82532_version[up->type]);
 808         return buf;
 809 }
 810
 811 static void sunsab_release_port(struct uart_port *port)
 812 {
 813 }
 814
 815 static int sunsab_request_port(struct uart_port *port)
 816 {
 817         return 0;
 818 }
 819
 820 static void sunsab_config_port(struct uart_port *port, int flags)
 821 {
 822 }
 823
 824 static int sunsab_verify_port(struct uart_port *port, struct serial_struct *ser)
 825 {
 826         return -EINVAL;
 827 }
 828
 829 static struct uart_ops sunsab_pops = {
 830         .tx_empty       = sunsab_tx_empty,
 831         .set_mctrl      = sunsab_set_mctrl,
 832         .get_mctrl      = sunsab_get_mctrl,
 833         .stop_tx        = sunsab_stop_tx,
 834         .start_tx       = sunsab_start_tx,
 835         .send_xchar     = sunsab_send_xchar,
 836         .stop_rx        = sunsab_stop_rx,
 837         .enable_ms      = sunsab_enable_ms,
 838         .break_ctl      = sunsab_break_ctl,
 839         .startup        = sunsab_startup,
 840         .shutdown       = sunsab_shutdown,
 841         .set_termios    = sunsab_set_termios,
 842         .type           = sunsab_type,
 843         .release_port   = sunsab_release_port,
 844         .request_port   = sunsab_request_port,
 845         .config_port    = sunsab_config_port,
 846         .verify_port    = sunsab_verify_port,
 847 };
 848
 849 static struct uart_driver sunsab_reg = {
 850         .owner                  = THIS_MODULE,
 851         .driver_name            = "serial",
 852         .dev_name               = "ttyS",
 853         .major                  = TTY_MAJOR,
 854 };
 855
 856 static struct uart_sunsab_port *sunsab_ports;
 857 static int num_channels;
 858
 859 #ifdef CONFIG_SERIAL_SUNSAB_CONSOLE
 860
 861 static void sunsab_console_putchar(struct uart_port *port, int c)
 862 {
 863         struct uart_sunsab_port *up = (struct uart_sunsab_port *)port;
 864         unsigned long flags;
 865
 866         spin_lock_irqsave(&up->port.lock, flags);
 867
 868         sunsab_tec_wait(up);
 869         writeb(c, &up->regs->w.tic);
 870
 871         spin_unlock_irqrestore(&up->port.lock, flags);
 872 }
 873
 874 static void sunsab_console_write(struct console *con, const char *s, unsigned n)
 875 {
 876         struct uart_sunsab_port *up = &sunsab_ports[con->index];
 877
 878         uart_console_write(&up->port, s, n, sunsab_console_putchar);
 879         sunsab_tec_wait(up);
 880 }
 881
 882 static int sunsab_console_setup(struct console *con, char *options)
 883 {
 884         struct uart_sunsab_port *up = &sunsab_ports[con->index];
 885         unsigned long flags;
 886         unsigned int baud, quot;
 887
 888         /*
 889          * The console framework calls us for each and every port
 890          * registered. Defer the console setup until the requested
 891          * port has been properly discovered. A bit of a hack,
 892          * though...
 893          */
 894         if (up->port.type != PORT_SUNSAB)
 895                 return -1;
 896
 897         printk("Console: ttyS%d (SAB82532)\n",
 898                (sunsab_reg.minor - 64) + con->index);
 899
 900         sunserial_console_termios(con);
 901
 902         switch (con->cflag & CBAUD) {
 903         case B150: baud = 150; break;
 904         case B300: baud = 300; break;
 905         case B600: baud = 600; break;
 906         case B1200: baud = 1200; break;
 907         case B2400: baud = 2400; break;
 908         case B4800: baud = 4800; break;
 909         default: case B9600: baud = 9600; break;
 910         case B19200: baud = 19200; break;
 911         case B38400: baud = 38400; break;
 912         case B57600: baud = 57600; break;
 913         case B115200: baud = 115200; break;
 914         case B230400: baud = 230400; break;
 915         case B460800: baud = 460800; break;
 916         };
 917
 918         /*
 919          * Temporary fix.
 920          */
 921         spin_lock_init(&up->port.lock);
 922
 923         /*
 924          * Initialize the hardware
 925          */
 926         sunsab_startup(&up->port);
 927
 928         spin_lock_irqsave(&up->port.lock, flags);
 929
 930         /*
 931          * Finally, enable interrupts
 932          */
 933         up->interrupt_mask0 = SAB82532_IMR0_PERR | SAB82532_IMR0_FERR |
 934                                 SAB82532_IMR0_PLLA | SAB82532_IMR0_CDSC;
 935         writeb(up->interrupt_mask0, &up->regs->w.imr0);
 936         up->interrupt_mask1 = SAB82532_IMR1_BRKT | SAB82532_IMR1_ALLS |
 937                                 SAB82532_IMR1_XOFF | SAB82532_IMR1_TIN |
 938                                 SAB82532_IMR1_CSC | SAB82532_IMR1_XON |
 939                                 SAB82532_IMR1_XPR;
 940         writeb(up->interrupt_mask1, &up->regs->w.imr1);
 941
 942         quot = uart_get_divisor(&up->port, baud);
 943         sunsab_convert_to_sab(up, con->cflag, 0, baud, quot);
 944         sunsab_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS);
 945
 946         spin_unlock_irqrestore(&up->port.lock, flags);
 947
 948         return 0;
 949 }
 950
 951 static struct console sunsab_console = {
 952         .name   =       "ttyS",
 953         .write  =       sunsab_console_write,
 954         .device =       uart_console_device,
 955         .setup  =       sunsab_console_setup,
 956         .flags  =       CON_PRINTBUFFER,
 957         .index  =       -1,
 958         .data   =       &sunsab_reg,
 959 };
 960
 961 static inline struct console *SUNSAB_CONSOLE(void)
 962 {
 963         int i;
 964
 965         if (con_is_present())
 966                 return NULL;
 967
 968         for (i = 0; i < num_channels; i++) {
 969                 int this_minor = sunsab_reg.minor + i;
 970
 971                 if ((this_minor - 64) == (serial_console - 1))
 972                         break;
 973         }
 974         if (i == num_channels)
 975                 return NULL;
 976
 977         sunsab_console.index = i;
 978
 979         return &sunsab_console;
 980 }
 981 #else
 982 #define SUNSAB_CONSOLE()        (NULL)
 983 #define sunsab_console_init()   do { } while (0)
 984 #endif
 985
 986 static int __devinit sunsab_init_one(struct uart_sunsab_port *up,
 987                                      struct of_device *op,
 988                                      unsigned long offset,
 989                                      int line)
 990 {
 991         up->port.line = line;
 992         up->port.dev = &op->dev;
 993
 994         up->port.mapbase = op->resource[0].start + offset;
 995         up->port.membase = of_ioremap(&op->resource[0], offset,
 996                                       sizeof(union sab82532_async_regs),
 997                                       "sab");
 998         if (!up->port.membase)
 999                 return -ENOMEM;
1000         up->regs = (union sab82532_async_regs __iomem *) up->port.membase;
1001
1002         up->port.irq = op->irqs[0];
1003
1004         up->port.fifosize = SAB82532_XMIT_FIFO_SIZE;
1005         up->port.iotype = UPIO_MEM;
1006
1007         writeb(SAB82532_IPC_IC_ACT_LOW, &up->regs->w.ipc);
1008
1009         up->port.ops = &sunsab_pops;
1010         up->port.type = PORT_SUNSAB;
1011         up->port.uartclk = SAB_BASE_BAUD;
1012
1013         up->type = readb(&up->regs->r.vstr) & 0x0f;
1014         writeb(~((1 << 1) | (1 << 2) | (1 << 4)), &up->regs->w.pcr);
1015         writeb(0xff, &up->regs->w.pim);
1016         if ((up->port.line & 0x1) == 0) {
1017                 up->pvr_dsr_bit = (1 << 0);
1018                 up->pvr_dtr_bit = (1 << 1);
1019         } else {
1020                 up->pvr_dsr_bit = (1 << 3);
1021                 up->pvr_dtr_bit = (1 << 2);
1022         }
1023         up->cached_pvr = (1 << 1) | (1 << 2) | (1 << 4);
1024         writeb(up->cached_pvr, &up->regs->w.pvr);
1025         up->cached_mode = readb(&up->regs->rw.mode);
1026         up->cached_mode |= SAB82532_MODE_FRTS;
1027         writeb(up->cached_mode, &up->regs->rw.mode);
1028         up->cached_mode |= SAB82532_MODE_RTS;
1029         writeb(up->cached_mode, &up->regs->rw.mode);
1030
1031         up->tec_timeout = SAB82532_MAX_TEC_TIMEOUT;
1032         up->cec_timeout = SAB82532_MAX_CEC_TIMEOUT;
1033
1034         if (!(up->port.line & 0x01)) {
1035                 int err;
1036
1037                 err = request_irq(up->port.irq, sunsab_interrupt,
1038                                   IRQF_SHARED, "sab", up);
1039                 if (err) {
1040                         of_iounmap(up->port.membase,
1041                                    sizeof(union sab82532_async_regs));
1042                         return err;
1043                 }
1044         }
1045
1046         return 0;
1047 }
1048
1049 static int __devinit sab_probe(struct of_device *op, const struct of_device_id *match)
1050 {
1051         static int inst;
1052         struct uart_sunsab_port *up;
1053         int err;
1054
1055         up = &sunsab_ports[inst * 2];
1056
1057         err = sunsab_init_one(&up[0], op,
1058                               0,
1059                               (inst * 2) + 0);
1060         if (err)
1061                 return err;
1062
1063         err = sunsab_init_one(&up[1], op,
1064                               sizeof(union sab82532_async_regs),
1065                               (inst * 2) + 1);
1066         if (err) {
1067                 of_iounmap(up[0].port.membase,
1068                            sizeof(union sab82532_async_regs));
1069                 free_irq(up[0].port.irq, &up[0]);
1070                 return err;
1071         }
1072
1073         uart_add_one_port(&sunsab_reg, &up[0].port);
1074         uart_add_one_port(&sunsab_reg, &up[1].port);
1075
1076         dev_set_drvdata(&op->dev, &up[0]);
1077
1078         inst++;
1079
1080         return 0;
1081 }
1082
1083 static void __devexit sab_remove_one(struct uart_sunsab_port *up)
1084 {
1085         uart_remove_one_port(&sunsab_reg, &up->port);
1086         if (!(up->port.line & 1))
1087                 free_irq(up->port.irq, up);
1088         of_iounmap(up->port.membase,
1089                    sizeof(union sab82532_async_regs));
1090 }
1091
1092 static int __devexit sab_remove(struct of_device *op)
1093 {
1094         struct uart_sunsab_port *up = dev_get_drvdata(&op->dev);
1095
1096         sab_remove_one(&up[0]);
1097         sab_remove_one(&up[1]);
1098
1099         dev_set_drvdata(&op->dev, NULL);
1100
1101         return 0;
1102 }
1103
1104 static struct of_device_id sab_match[] = {
1105         {
1106                 .name = "se",
1107         },
1108         {
1109                 .name = "serial",
1110                 .compatible = "sab82532",
1111         },
1112         {},
1113 };
1114 MODULE_DEVICE_TABLE(of, sab_match);
1115
1116 static struct of_platform_driver sab_driver = {
1117         .name           = "sab",
1118         .match_table    = sab_match,
1119         .probe          = sab_probe,
1120         .remove         = __devexit_p(sab_remove),
1121 };
1122
1123 static int __init sunsab_init(void)
1124 {
1125         struct device_node *dp;
1126         int err;
1127
1128         num_channels = 0;
1129         for_each_node_by_name(dp, "se")
1130                 num_channels += 2;
1131         for_each_node_by_name(dp, "serial") {
1132                 if (of_device_is_compatible(dp, "sab82532"))
1133                         num_channels += 2;
1134         }
1135
1136         if (num_channels) {
1137                 sunsab_ports = kzalloc(sizeof(struct uart_sunsab_port) *
1138                                        num_channels, GFP_KERNEL);
1139                 if (!sunsab_ports)
1140                         return -ENOMEM;
1141
1142                 sunsab_reg.minor = sunserial_current_minor;
1143                 sunsab_reg.nr = num_channels;
1144
1145                 err = uart_register_driver(&sunsab_reg);
1146                 if (err) {
1147                         kfree(sunsab_ports);
1148                         sunsab_ports = NULL;
1149
1150                         return err;
1151                 }
1152
1153                 sunsab_reg.tty_driver->name_base = sunsab_reg.minor - 64;
1154                 sunsab_reg.cons = SUNSAB_CONSOLE();
1155                 sunserial_current_minor += num_channels;
1156         }
1157
1158         return of_register_driver(&sab_driver, &of_bus_type);
1159 }
1160
1161 static void __exit sunsab_exit(void)
1162 {
1163         of_unregister_driver(&sab_driver);
1164         if (num_channels) {
1165                 sunserial_current_minor -= num_channels;
1166                 uart_unregister_driver(&sunsab_reg);
1167         }
1168
1169         kfree(sunsab_ports);
1170         sunsab_ports = NULL;
1171 }
1172
1173 module_init(sunsab_init);
1174 module_exit(sunsab_exit);
1175
1176 MODULE_AUTHOR("Eddie C. Dost and David S. Miller");
1177 MODULE_DESCRIPTION("Sun SAB82532 serial port driver");
1178 MODULE_LICENSE("GPL");