git.oblomov.eu Git - linux-2.6/blob - drivers/video/aty/atyfb_base.c

   1 /*
   2  *  ATI Frame Buffer Device Driver Core
   3  *
   4  *      Copyright (C) 2004  Alex Kern <alex.kern@gmx.de>
   5  *      Copyright (C) 1997-2001  Geert Uytterhoeven
   6  *      Copyright (C) 1998  Bernd Harries
   7  *      Copyright (C) 1998  Eddie C. Dost  (ecd@skynet.be)
   8  *
   9  *  This driver supports the following ATI graphics chips:
  10  *    - ATI Mach64
  11  *
  12  *  To do: add support for
  13  *    - ATI Rage128 (from aty128fb.c)
  14  *    - ATI Radeon (from radeonfb.c)
  15  *
  16  *  This driver is partly based on the PowerMac console driver:
  17  *
  18  *      Copyright (C) 1996 Paul Mackerras
  19  *
  20  *  and on the PowerMac ATI/mach64 display driver:
  21  *
  22  *      Copyright (C) 1997 Michael AK Tesch
  23  *
  24  *            with work by Jon Howell
  25  *                         Harry AC Eaton
  26  *                         Anthony Tong <atong@uiuc.edu>
  27  *
  28  *  Generic LCD support written by Daniel Mantione, ported from 2.4.20 by Alex Kern
  29  *  Many Thanks to Ville Syrjälä for patches and fixing nasting 16 bit color bug.
  30  *
  31  *  This file is subject to the terms and conditions of the GNU General Public
  32  *  License. See the file COPYING in the main directory of this archive for
  33  *  more details.
  34  *
  35  *  Many thanks to Nitya from ATI devrel for support and patience !
  36  */
  37
  38 /******************************************************************************
  39
  40   TODO:
  41
  42     - cursor support on all cards and all ramdacs.
  43     - cursor parameters controlable via ioctl()s.
  44     - guess PLL and MCLK based on the original PLL register values initialized
  45       by Open Firmware (if they are initialized). BIOS is done
  46
  47     (Anyone with Mac to help with this?)
  48
  49 ******************************************************************************/
  50
  51
  52 #include <linux/config.h>
  53 #include <linux/module.h>
  54 #include <linux/moduleparam.h>
  55 #include <linux/kernel.h>
  56 #include <linux/errno.h>
  57 #include <linux/string.h>
  58 #include <linux/mm.h>
  59 #include <linux/slab.h>
  60 #include <linux/vmalloc.h>
  61 #include <linux/delay.h>
  62 #include <linux/console.h>
  63 #include <linux/fb.h>
  64 #include <linux/init.h>
  65 #include <linux/pci.h>
  66 #include <linux/interrupt.h>
  67 #include <linux/spinlock.h>
  68 #include <linux/wait.h>
  69
  70 #include <asm/io.h>
  71 #include <asm/uaccess.h>
  72
  73 #include <video/mach64.h>
  74 #include "atyfb.h"
  75 #include "ati_ids.h"
  76
  77 #ifdef __powerpc__
  78 #include <asm/prom.h>
  79 #include "../macmodes.h"
  80 #endif
  81 #ifdef __sparc__
  82 #include <asm/pbm.h>
  83 #include <asm/fbio.h>
  84 #endif
  85
  86 #ifdef CONFIG_ADB_PMU
  87 #include <linux/adb.h>
  88 #include <linux/pmu.h>
  89 #endif
  90 #ifdef CONFIG_BOOTX_TEXT
  91 #include <asm/btext.h>
  92 #endif
  93 #ifdef CONFIG_PMAC_BACKLIGHT
  94 #include <asm/backlight.h>
  95 #endif
  96 #ifdef CONFIG_MTRR
  97 #include <asm/mtrr.h>
  98 #endif
  99
 100 /*
 101  * Debug flags.
 102  */
 103 #undef DEBUG
 104 /*#define DEBUG*/
 105
 106 /* Make sure n * PAGE_SIZE is protected at end of Aperture for GUI-regs */
 107 /*  - must be large enough to catch all GUI-Regs   */
 108 /*  - must be aligned to a PAGE boundary           */
 109 #define GUI_RESERVE     (1 * PAGE_SIZE)
 110
 111 /* FIXME: remove the FAIL definition */
 112 #define FAIL(msg) do { \
 113         if (!(var->activate & FB_ACTIVATE_TEST)) \
 114                 printk(KERN_CRIT "atyfb: " msg "\n"); \
 115         return -EINVAL; \
 116 } while (0)
 117 #define FAIL_MAX(msg, x, _max_) do { \
 118         if (x > _max_) { \
 119                 if (!(var->activate & FB_ACTIVATE_TEST)) \
 120                         printk(KERN_CRIT "atyfb: " msg " %x(%x)\n", x, _max_); \
 121                 return -EINVAL; \
 122         } \
 123 } while (0)
 124 #ifdef DEBUG
 125 #define DPRINTK(fmt, args...)   printk(KERN_DEBUG "atyfb: " fmt, ## args)
 126 #else
 127 #define DPRINTK(fmt, args...)
 128 #endif
 129
 130 #define PRINTKI(fmt, args...)   printk(KERN_INFO "atyfb: " fmt, ## args)
 131 #define PRINTKE(fmt, args...)    printk(KERN_ERR "atyfb: " fmt, ## args)
 132
 133 #if defined(CONFIG_PM) || defined(CONFIG_PMAC_BACKLIGHT) || defined (CONFIG_FB_ATY_GENERIC_LCD)
 134 static const u32 lt_lcd_regs[] = {
 135         CONFIG_PANEL_LG,
 136         LCD_GEN_CNTL_LG,
 137         DSTN_CONTROL_LG,
 138         HFB_PITCH_ADDR_LG,
 139         HORZ_STRETCHING_LG,
 140         VERT_STRETCHING_LG,
 141         0, /* EXT_VERT_STRETCH */
 142         LT_GIO_LG,
 143         POWER_MANAGEMENT_LG
 144 };
 145
 146 void aty_st_lcd(int index, u32 val, const struct atyfb_par *par)
 147 {
 148         if (M64_HAS(LT_LCD_REGS)) {
 149                 aty_st_le32(lt_lcd_regs[index], val, par);
 150         } else {
 151                 unsigned long temp;
 152
 153                 /* write addr byte */
 154                 temp = aty_ld_le32(LCD_INDEX, par);
 155                 aty_st_le32(LCD_INDEX, (temp & ~LCD_INDEX_MASK) | index, par);
 156                 /* write the register value */
 157                 aty_st_le32(LCD_DATA, val, par);
 158         }
 159 }
 160
 161 u32 aty_ld_lcd(int index, const struct atyfb_par *par)
 162 {
 163         if (M64_HAS(LT_LCD_REGS)) {
 164                 return aty_ld_le32(lt_lcd_regs[index], par);
 165         } else {
 166                 unsigned long temp;
 167
 168                 /* write addr byte */
 169                 temp = aty_ld_le32(LCD_INDEX, par);
 170                 aty_st_le32(LCD_INDEX, (temp & ~LCD_INDEX_MASK) | index, par);
 171                 /* read the register value */
 172                 return aty_ld_le32(LCD_DATA, par);
 173         }
 174 }
 175 #endif /* defined(CONFIG_PM) || defined(CONFIG_PMAC_BACKLIGHT) || defined (CONFIG_FB_ATY_GENERIC_LCD) */
 176
 177 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 178 /*
 179  * ATIReduceRatio --
 180  *
 181  * Reduce a fraction by factoring out the largest common divider of the
 182  * fraction's numerator and denominator.
 183  */
 184 static void ATIReduceRatio(int *Numerator, int *Denominator)
 185 {
 186     int Multiplier, Divider, Remainder;
 187
 188     Multiplier = *Numerator;
 189     Divider = *Denominator;
 190
 191     while ((Remainder = Multiplier % Divider))
 192     {
 193         Multiplier = Divider;
 194         Divider = Remainder;
 195     }
 196
 197     *Numerator /= Divider;
 198     *Denominator /= Divider;
 199 }
 200 #endif
 201     /*
 202      *  The Hardware parameters for each card
 203      */
 204
 205 struct aty_cmap_regs {
 206         u8 windex;
 207         u8 lut;
 208         u8 mask;
 209         u8 rindex;
 210         u8 cntl;
 211 };
 212
 213 struct pci_mmap_map {
 214         unsigned long voff;
 215         unsigned long poff;
 216         unsigned long size;
 217         unsigned long prot_flag;
 218         unsigned long prot_mask;
 219 };
 220
 221 static struct fb_fix_screeninfo atyfb_fix __devinitdata = {
 222         .id             = "ATY Mach64",
 223         .type           = FB_TYPE_PACKED_PIXELS,
 224         .visual         = FB_VISUAL_PSEUDOCOLOR,
 225         .xpanstep       = 8,
 226         .ypanstep       = 1,
 227 };
 228
 229     /*
 230      *  Frame buffer device API
 231      */
 232
 233 static int atyfb_open(struct fb_info *info, int user);
 234 static int atyfb_release(struct fb_info *info, int user);
 235 static int atyfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info);
 236 static int atyfb_set_par(struct fb_info *info);
 237 static int atyfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
 238         u_int transp, struct fb_info *info);
 239 static int atyfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info);
 240 static int atyfb_blank(int blank, struct fb_info *info);
 241 static int atyfb_ioctl(struct inode *inode, struct file *file, u_int cmd,
 242         u_long arg, struct fb_info *info);
 243 extern void atyfb_fillrect(struct fb_info *info, const struct fb_fillrect *rect);
 244 extern void atyfb_copyarea(struct fb_info *info, const struct fb_copyarea *area);
 245 extern void atyfb_imageblit(struct fb_info *info, const struct fb_image *image);
 246 #ifdef __sparc__
 247 static int atyfb_mmap(struct fb_info *info, struct file *file, struct vm_area_struct *vma);
 248 #endif
 249 static int atyfb_sync(struct fb_info *info);
 250
 251     /*
 252      *  Internal routines
 253      */
 254
 255 static int aty_init(struct fb_info *info, const char *name);
 256 #ifdef CONFIG_ATARI
 257 static int store_video_par(char *videopar, unsigned char m64_num);
 258 #endif
 259
 260 static struct crtc saved_crtc;
 261 static union aty_pll saved_pll;
 262 static void aty_get_crtc(const struct atyfb_par *par, struct crtc *crtc);
 263
 264 static void aty_set_crtc(const struct atyfb_par *par, const struct crtc *crtc);
 265 static int aty_var_to_crtc(const struct fb_info *info, const struct fb_var_screeninfo *var, struct crtc *crtc);
 266 static int aty_crtc_to_var(const struct crtc *crtc, struct fb_var_screeninfo *var);
 267 static void set_off_pitch(struct atyfb_par *par, const struct fb_info *info);
 268 #ifdef CONFIG_PPC
 269 static int read_aty_sense(const struct atyfb_par *par);
 270 #endif
 271
 272
 273     /*
 274      *  Interface used by the world
 275      */
 276
 277 static struct fb_var_screeninfo default_var = {
 278         /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
 279         640, 480, 640, 480, 0, 0, 8, 0,
 280         {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
 281         0, 0, -1, -1, 0, 39722, 48, 16, 33, 10, 96, 2,
 282         0, FB_VMODE_NONINTERLACED
 283 };
 284
 285 static struct fb_videomode defmode = {
 286         /* 640x480 @ 60 Hz, 31.5 kHz hsync */
 287         NULL, 60, 640, 480, 39721, 40, 24, 32, 11, 96, 2,
 288         0, FB_VMODE_NONINTERLACED
 289 };
 290
 291 static struct fb_ops atyfb_ops = {
 292         .owner          = THIS_MODULE,
 293         .fb_open        = atyfb_open,
 294         .fb_release     = atyfb_release,
 295         .fb_check_var   = atyfb_check_var,
 296         .fb_set_par     = atyfb_set_par,
 297         .fb_setcolreg   = atyfb_setcolreg,
 298         .fb_pan_display = atyfb_pan_display,
 299         .fb_blank       = atyfb_blank,
 300         .fb_ioctl       = atyfb_ioctl,
 301         .fb_fillrect    = atyfb_fillrect,
 302         .fb_copyarea    = atyfb_copyarea,
 303         .fb_imageblit   = atyfb_imageblit,
 304 #ifdef __sparc__
 305         .fb_mmap        = atyfb_mmap,
 306 #endif
 307         .fb_sync        = atyfb_sync,
 308 };
 309
 310 static int noaccel;
 311 #ifdef CONFIG_MTRR
 312 static int nomtrr;
 313 #endif
 314 static int vram;
 315 static int pll;
 316 static int mclk;
 317 static int xclk;
 318 static int comp_sync __initdata = -1;
 319 static char *mode;
 320
 321 #ifdef CONFIG_PPC
 322 static int default_vmode __initdata = VMODE_CHOOSE;
 323 static int default_cmode __initdata = CMODE_CHOOSE;
 324
 325 module_param_named(vmode, default_vmode, int, 0);
 326 MODULE_PARM_DESC(vmode, "int: video mode for mac");
 327 module_param_named(cmode, default_cmode, int, 0);
 328 MODULE_PARM_DESC(cmode, "int: color mode for mac");
 329 #endif
 330
 331 #ifdef CONFIG_ATARI
 332 static unsigned int mach64_count __initdata = 0;
 333 static unsigned long phys_vmembase[FB_MAX] __initdata = { 0, };
 334 static unsigned long phys_size[FB_MAX] __initdata = { 0, };
 335 static unsigned long phys_guiregbase[FB_MAX] __initdata = { 0, };
 336 #endif
 337
 338 /* top -> down is an evolution of mach64 chipset, any corrections? */
 339 #define ATI_CHIP_88800GX   (M64F_GX)
 340 #define ATI_CHIP_88800CX   (M64F_GX)
 341
 342 #define ATI_CHIP_264CT     (M64F_CT | M64F_INTEGRATED | M64F_CT_BUS | M64F_MAGIC_FIFO)
 343 #define ATI_CHIP_264ET     (M64F_CT | M64F_INTEGRATED | M64F_CT_BUS | M64F_MAGIC_FIFO)
 344
 345 #define ATI_CHIP_264VT     (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_MAGIC_FIFO)
 346 #define ATI_CHIP_264GT     (M64F_GT | M64F_INTEGRATED               | M64F_MAGIC_FIFO | M64F_EXTRA_BRIGHT)
 347
 348 #define ATI_CHIP_264VTB    (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_GTB_DSP)
 349 #define ATI_CHIP_264VT3    (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_GTB_DSP | M64F_SDRAM_MAGIC_PLL)
 350 #define ATI_CHIP_264VT4    (M64F_VT | M64F_INTEGRATED               | M64F_GTB_DSP)
 351
 352 /* FIXME what is this chip? */
 353 #define ATI_CHIP_264LT     (M64F_GT | M64F_INTEGRATED               | M64F_GTB_DSP)
 354
 355 /* make sets shorter */
 356 #define ATI_MODERN_SET     (M64F_GT | M64F_INTEGRATED               | M64F_GTB_DSP | M64F_EXTRA_BRIGHT)
 357
 358 #define ATI_CHIP_264GTB    (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL)
 359 /*#define ATI_CHIP_264GTDVD  ?*/
 360 #define ATI_CHIP_264LTG    (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL)
 361
 362 #define ATI_CHIP_264GT2C   (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL | M64F_HW_TRIPLE)
 363 #define ATI_CHIP_264GTPRO  (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D)
 364 #define ATI_CHIP_264LTPRO  (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D)
 365
 366 #define ATI_CHIP_264XL     (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D | M64F_XL_DLL | M64F_MFB_FORCE_4)
 367 #define ATI_CHIP_MOBILITY  (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D | M64F_XL_DLL | M64F_MFB_FORCE_4 | M64F_MOBIL_BUS)
 368
 369 static struct {
 370         u16 pci_id;
 371         const char *name;
 372         int pll, mclk, xclk, ecp_max;
 373         u32 features;
 374 } aty_chips[] __devinitdata = {
 375 #ifdef CONFIG_FB_ATY_GX
 376         /* Mach64 GX */
 377         { PCI_CHIP_MACH64GX, "ATI888GX00 (Mach64 GX)", 135, 50, 50, 0, ATI_CHIP_88800GX },
 378         { PCI_CHIP_MACH64CX, "ATI888CX00 (Mach64 CX)", 135, 50, 50, 0, ATI_CHIP_88800CX },
 379 #endif /* CONFIG_FB_ATY_GX */
 380
 381 #ifdef CONFIG_FB_ATY_CT
 382         { PCI_CHIP_MACH64CT, "ATI264CT (Mach64 CT)", 135, 60, 60, 0, ATI_CHIP_264CT },
 383         { PCI_CHIP_MACH64ET, "ATI264ET (Mach64 ET)", 135, 60, 60, 0, ATI_CHIP_264ET },
 384
 385         /* FIXME what is this chip? */
 386         { PCI_CHIP_MACH64LT, "ATI264LT (Mach64 LT)", 135, 63, 63, 0, ATI_CHIP_264LT },
 387
 388         { PCI_CHIP_MACH64VT, "ATI264VT (Mach64 VT)", 170, 67, 67, 80, ATI_CHIP_264VT },
 389         { PCI_CHIP_MACH64GT, "3D RAGE (Mach64 GT)", 135, 63, 63, 80, ATI_CHIP_264GT },
 390
 391         { PCI_CHIP_MACH64VU, "ATI264VT3 (Mach64 VU)", 200, 67, 67, 80, ATI_CHIP_264VT3 },
 392         { PCI_CHIP_MACH64GU, "3D RAGE II+ (Mach64 GU)", 200, 67, 67, 100, ATI_CHIP_264GTB },
 393
 394         { PCI_CHIP_MACH64LG, "3D RAGE LT (Mach64 LG)", 230, 63, 63, 100, ATI_CHIP_264LTG | M64F_LT_LCD_REGS | M64F_G3_PB_1024x768 },
 395
 396         { PCI_CHIP_MACH64VV, "ATI264VT4 (Mach64 VV)", 230, 83, 83, 100, ATI_CHIP_264VT4 },
 397
 398         { PCI_CHIP_MACH64GV, "3D RAGE IIC (Mach64 GV, PCI)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
 399         { PCI_CHIP_MACH64GW, "3D RAGE IIC (Mach64 GW, AGP)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
 400         { PCI_CHIP_MACH64GY, "3D RAGE IIC (Mach64 GY, PCI)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
 401         { PCI_CHIP_MACH64GZ, "3D RAGE IIC (Mach64 GZ, AGP)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
 402
 403         { PCI_CHIP_MACH64GB, "3D RAGE PRO (Mach64 GB, BGA, AGP)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
 404         { PCI_CHIP_MACH64GD, "3D RAGE PRO (Mach64 GD, BGA, AGP 1x)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
 405         { PCI_CHIP_MACH64GI, "3D RAGE PRO (Mach64 GI, BGA, PCI)", 230, 100, 100, 125, ATI_CHIP_264GTPRO | M64F_MAGIC_VRAM_SIZE },
 406         { PCI_CHIP_MACH64GP, "3D RAGE PRO (Mach64 GP, PQFP, PCI)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
 407         { PCI_CHIP_MACH64GQ, "3D RAGE PRO (Mach64 GQ, PQFP, PCI, limited 3D)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
 408
 409         { PCI_CHIP_MACH64LB, "3D RAGE LT PRO (Mach64 LB, AGP)", 236, 75, 100, 135, ATI_CHIP_264LTPRO },
 410         { PCI_CHIP_MACH64LD, "3D RAGE LT PRO (Mach64 LD, AGP)", 230, 100, 100, 135, ATI_CHIP_264LTPRO },
 411         { PCI_CHIP_MACH64LI, "3D RAGE LT PRO (Mach64 LI, PCI)", 230, 100, 100, 135, ATI_CHIP_264LTPRO | M64F_G3_PB_1_1 | M64F_G3_PB_1024x768 },
 412         { PCI_CHIP_MACH64LP, "3D RAGE LT PRO (Mach64 LP, PCI)", 230, 100, 100, 135, ATI_CHIP_264LTPRO },
 413         { PCI_CHIP_MACH64LQ, "3D RAGE LT PRO (Mach64 LQ, PCI)", 230, 100, 100, 135, ATI_CHIP_264LTPRO },
 414
 415         { PCI_CHIP_MACH64GM, "3D RAGE XL (Mach64 GM, AGP 2x)", 230, 83, 63, 135, ATI_CHIP_264XL },
 416         { PCI_CHIP_MACH64GN, "3D RAGE XC (Mach64 GN, AGP 2x)", 230, 83, 63, 135, ATI_CHIP_264XL },
 417         { PCI_CHIP_MACH64GO, "3D RAGE XL (Mach64 GO, PCI-66)", 230, 83, 63, 135, ATI_CHIP_264XL },
 418         { PCI_CHIP_MACH64GL, "3D RAGE XC (Mach64 GL, PCI-66)", 230, 83, 63, 135, ATI_CHIP_264XL },
 419         { PCI_CHIP_MACH64GR, "3D RAGE XL (Mach64 GR, PCI-33)", 230, 83, 63, 135, ATI_CHIP_264XL | M64F_SDRAM_MAGIC_PLL },
 420         { PCI_CHIP_MACH64GS, "3D RAGE XC (Mach64 GS, PCI-33)", 230, 83, 63, 135, ATI_CHIP_264XL },
 421
 422         { PCI_CHIP_MACH64LM, "3D RAGE Mobility P/M (Mach64 LM, AGP 2x)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
 423         { PCI_CHIP_MACH64LN, "3D RAGE Mobility L (Mach64 LN, AGP 2x)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
 424         { PCI_CHIP_MACH64LR, "3D RAGE Mobility P/M (Mach64 LR, PCI)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
 425         { PCI_CHIP_MACH64LS, "3D RAGE Mobility L (Mach64 LS, PCI)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
 426 #endif /* CONFIG_FB_ATY_CT */
 427 };
 428
 429 /* can not fail */
 430 static int __devinit correct_chipset(struct atyfb_par *par)
 431 {
 432         u8 rev;
 433         u16 type;
 434         u32 chip_id;
 435         const char *name;
 436         int i;
 437
 438         for (i = sizeof(aty_chips) / sizeof(*aty_chips) - 1; i >= 0; i--)
 439                 if (par->pci_id == aty_chips[i].pci_id)
 440                         break;
 441
 442         name = aty_chips[i].name;
 443         par->pll_limits.pll_max = aty_chips[i].pll;
 444         par->pll_limits.mclk = aty_chips[i].mclk;
 445         par->pll_limits.xclk = aty_chips[i].xclk;
 446         par->pll_limits.ecp_max = aty_chips[i].ecp_max;
 447         par->features = aty_chips[i].features;
 448
 449         chip_id = aty_ld_le32(CONFIG_CHIP_ID, par);
 450         type = chip_id & CFG_CHIP_TYPE;
 451         rev = (chip_id & CFG_CHIP_REV) >> 24;
 452
 453         switch(par->pci_id) {
 454 #ifdef CONFIG_FB_ATY_GX
 455         case PCI_CHIP_MACH64GX:
 456                 if(type != 0x00d7)
 457                         return -ENODEV;
 458                 break;
 459         case PCI_CHIP_MACH64CX:
 460                 if(type != 0x0057)
 461                         return -ENODEV;
 462                 break;
 463 #endif
 464 #ifdef CONFIG_FB_ATY_CT
 465         case PCI_CHIP_MACH64VT:
 466                 switch (rev & 0x07) {
 467                 case 0x00:
 468                         switch (rev & 0xc0) {
 469                         case 0x00:
 470                                 name = "ATI264VT (A3) (Mach64 VT)";
 471                                 par->pll_limits.pll_max = 170;
 472                                 par->pll_limits.mclk = 67;
 473                                 par->pll_limits.xclk = 67;
 474                                 par->pll_limits.ecp_max = 80;
 475                                 par->features = ATI_CHIP_264VT;
 476                                 break;
 477                         case 0x40:
 478                                 name = "ATI264VT2 (A4) (Mach64 VT)";
 479                                 par->pll_limits.pll_max = 200;
 480                                 par->pll_limits.mclk = 67;
 481                                 par->pll_limits.xclk = 67;
 482                                 par->pll_limits.ecp_max = 80;
 483                                 par->features = ATI_CHIP_264VT | M64F_MAGIC_POSTDIV;
 484                                 break;
 485                         }
 486                         break;
 487                 case 0x01:
 488                         name = "ATI264VT3 (B1) (Mach64 VT)";
 489                         par->pll_limits.pll_max = 200;
 490                         par->pll_limits.mclk = 67;
 491                         par->pll_limits.xclk = 67;
 492                         par->pll_limits.ecp_max = 80;
 493                         par->features = ATI_CHIP_264VTB;
 494                         break;
 495                 case 0x02:
 496                         name = "ATI264VT3 (B2) (Mach64 VT)";
 497                         par->pll_limits.pll_max = 200;
 498                         par->pll_limits.mclk = 67;
 499                         par->pll_limits.xclk = 67;
 500                         par->pll_limits.ecp_max = 80;
 501                         par->features = ATI_CHIP_264VT3;
 502                         break;
 503                 }
 504                 break;
 505         case PCI_CHIP_MACH64GT:
 506                 switch (rev & 0x07) {
 507                 case 0x01:
 508                         name = "3D RAGE II (Mach64 GT)";
 509                         par->pll_limits.pll_max = 170;
 510                         par->pll_limits.mclk = 67;
 511                         par->pll_limits.xclk = 67;
 512                         par->pll_limits.ecp_max = 80;
 513                         par->features = ATI_CHIP_264GTB;
 514                         break;
 515                 case 0x02:
 516                         name = "3D RAGE II+ (Mach64 GT)";
 517                         par->pll_limits.pll_max = 200;
 518                         par->pll_limits.mclk = 67;
 519                         par->pll_limits.xclk = 67;
 520                         par->pll_limits.ecp_max = 100;
 521                         par->features = ATI_CHIP_264GTB;
 522                         break;
 523                 }
 524                 break;
 525 #endif
 526         }
 527
 528         PRINTKI("%s [0x%04x rev 0x%02x]\n", name, type, rev);
 529         return 0;
 530 }
 531
 532 static char ram_dram[] __devinitdata = "DRAM";
 533 static char ram_resv[] __devinitdata = "RESV";
 534 #ifdef CONFIG_FB_ATY_GX
 535 static char ram_vram[] __devinitdata = "VRAM";
 536 #endif /* CONFIG_FB_ATY_GX */
 537 #ifdef CONFIG_FB_ATY_CT
 538 static char ram_edo[] __devinitdata = "EDO";
 539 static char ram_sdram[] __devinitdata = "SDRAM (1:1)";
 540 static char ram_sgram[] __devinitdata = "SGRAM (1:1)";
 541 static char ram_sdram32[] __devinitdata = "SDRAM (2:1) (32-bit)";
 542 static char ram_off[] __devinitdata = "OFF";
 543 #endif /* CONFIG_FB_ATY_CT */
 544
 545
 546 static u32 pseudo_palette[17];
 547
 548 #ifdef CONFIG_FB_ATY_GX
 549 static char *aty_gx_ram[8] __devinitdata = {
 550         ram_dram, ram_vram, ram_vram, ram_dram,
 551         ram_dram, ram_vram, ram_vram, ram_resv
 552 };
 553 #endif /* CONFIG_FB_ATY_GX */
 554
 555 #ifdef CONFIG_FB_ATY_CT
 556 static char *aty_ct_ram[8] __devinitdata = {
 557         ram_off, ram_dram, ram_edo, ram_edo,
 558         ram_sdram, ram_sgram, ram_sdram32, ram_resv
 559 };
 560 #endif /* CONFIG_FB_ATY_CT */
 561
 562 static u32 atyfb_get_pixclock(struct fb_var_screeninfo *var, struct atyfb_par *par)
 563 {
 564         u32 pixclock = var->pixclock;
 565 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 566         u32 lcd_on_off;
 567         par->pll.ct.xres = 0;
 568         if (par->lcd_table != 0) {
 569                 lcd_on_off = aty_ld_lcd(LCD_GEN_CNTL, par);
 570                 if(lcd_on_off & LCD_ON) {
 571                         par->pll.ct.xres = var->xres;
 572                         pixclock = par->lcd_pixclock;
 573                 }
 574         }
 575 #endif
 576         return pixclock;
 577 }
 578
 579 #if defined(CONFIG_PPC)
 580
 581 /*
 582  *  Apple monitor sense
 583  */
 584
 585 static int __init read_aty_sense(const struct atyfb_par *par)
 586 {
 587         int sense, i;
 588
 589         aty_st_le32(GP_IO, 0x31003100, par); /* drive outputs high */
 590         __delay(200);
 591         aty_st_le32(GP_IO, 0, par); /* turn off outputs */
 592         __delay(2000);
 593         i = aty_ld_le32(GP_IO, par); /* get primary sense value */
 594         sense = ((i & 0x3000) >> 3) | (i & 0x100);
 595
 596         /* drive each sense line low in turn and collect the other 2 */
 597         aty_st_le32(GP_IO, 0x20000000, par); /* drive A low */
 598         __delay(2000);
 599         i = aty_ld_le32(GP_IO, par);
 600         sense |= ((i & 0x1000) >> 7) | ((i & 0x100) >> 4);
 601         aty_st_le32(GP_IO, 0x20002000, par); /* drive A high again */
 602         __delay(200);
 603
 604         aty_st_le32(GP_IO, 0x10000000, par); /* drive B low */
 605         __delay(2000);
 606         i = aty_ld_le32(GP_IO, par);
 607         sense |= ((i & 0x2000) >> 10) | ((i & 0x100) >> 6);
 608         aty_st_le32(GP_IO, 0x10001000, par); /* drive B high again */
 609         __delay(200);
 610
 611         aty_st_le32(GP_IO, 0x01000000, par); /* drive C low */
 612         __delay(2000);
 613         sense |= (aty_ld_le32(GP_IO, par) & 0x3000) >> 12;
 614         aty_st_le32(GP_IO, 0, par); /* turn off outputs */
 615         return sense;
 616 }
 617
 618 #endif /* defined(CONFIG_PPC) */
 619
 620 /* ------------------------------------------------------------------------- */
 621
 622 /*
 623  *  CRTC programming
 624  */
 625
 626 static void aty_get_crtc(const struct atyfb_par *par, struct crtc *crtc)
 627 {
 628 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 629         if (par->lcd_table != 0) {
 630                 if(!M64_HAS(LT_LCD_REGS)) {
 631                     crtc->lcd_index = aty_ld_le32(LCD_INDEX, par);
 632                     aty_st_le32(LCD_INDEX, crtc->lcd_index, par);
 633                 }
 634                 crtc->lcd_config_panel = aty_ld_lcd(CONFIG_PANEL, par);
 635                 crtc->lcd_gen_cntl = aty_ld_lcd(LCD_GEN_CNTL, par);
 636
 637
 638                 /* switch to non shadow registers */
 639                 aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl &
 640                     ~(CRTC_RW_SELECT | SHADOW_EN | SHADOW_RW_EN), par);
 641
 642                 /* save stretching */
 643                 crtc->horz_stretching = aty_ld_lcd(HORZ_STRETCHING, par);
 644                 crtc->vert_stretching = aty_ld_lcd(VERT_STRETCHING, par);
 645                 if (!M64_HAS(LT_LCD_REGS))
 646                         crtc->ext_vert_stretch = aty_ld_lcd(EXT_VERT_STRETCH, par);
 647         }
 648 #endif
 649         crtc->h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
 650         crtc->h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
 651         crtc->v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
 652         crtc->v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
 653         crtc->vline_crnt_vline = aty_ld_le32(CRTC_VLINE_CRNT_VLINE, par);
 654         crtc->off_pitch = aty_ld_le32(CRTC_OFF_PITCH, par);
 655         crtc->gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
 656
 657 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 658         if (par->lcd_table != 0) {
 659                 /* switch to shadow registers */
 660                 aty_st_lcd(LCD_GEN_CNTL, (crtc->lcd_gen_cntl & ~CRTC_RW_SELECT) |
 661                         SHADOW_EN | SHADOW_RW_EN, par);
 662
 663                 crtc->shadow_h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
 664                 crtc->shadow_h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
 665                 crtc->shadow_v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
 666                 crtc->shadow_v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
 667
 668                 aty_st_le32(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);
 669         }
 670 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
 671 }
 672
 673 static void aty_set_crtc(const struct atyfb_par *par, const struct crtc *crtc)
 674 {
 675 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 676         if (par->lcd_table != 0) {
 677                 /* stop CRTC */
 678                 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl & ~(CRTC_EXT_DISP_EN | CRTC_EN), par);
 679
 680                 /* update non-shadow registers first */
 681                 aty_st_lcd(CONFIG_PANEL, crtc->lcd_config_panel, par);
 682                 aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl &
 683                         ~(CRTC_RW_SELECT | SHADOW_EN | SHADOW_RW_EN), par);
 684
 685                 /* temporarily disable stretching */
 686                 aty_st_lcd(HORZ_STRETCHING,
 687                         crtc->horz_stretching &
 688                         ~(HORZ_STRETCH_MODE | HORZ_STRETCH_EN), par);
 689                 aty_st_lcd(VERT_STRETCHING,
 690                         crtc->vert_stretching &
 691                         ~(VERT_STRETCH_RATIO1 | VERT_STRETCH_RATIO2 |
 692                         VERT_STRETCH_USE0 | VERT_STRETCH_EN), par);
 693         }
 694 #endif
 695         /* turn off CRT */
 696         aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl & ~CRTC_EN, par);
 697
 698         DPRINTK("setting up CRTC\n");
 699         DPRINTK("set primary CRT to %ix%i %c%c composite %c\n",
 700             ((((crtc->h_tot_disp>>16) & 0xff) + 1)<<3), (((crtc->v_tot_disp>>16) & 0x7ff) + 1),
 701             (crtc->h_sync_strt_wid & 0x200000)?'N':'P', (crtc->v_sync_strt_wid & 0x200000)?'N':'P',
 702             (crtc->gen_cntl & CRTC_CSYNC_EN)?'P':'N');
 703
 704         DPRINTK("CRTC_H_TOTAL_DISP: %x\n",crtc->h_tot_disp);
 705         DPRINTK("CRTC_H_SYNC_STRT_WID: %x\n",crtc->h_sync_strt_wid);
 706         DPRINTK("CRTC_V_TOTAL_DISP: %x\n",crtc->v_tot_disp);
 707         DPRINTK("CRTC_V_SYNC_STRT_WID: %x\n",crtc->v_sync_strt_wid);
 708         DPRINTK("CRTC_OFF_PITCH: %x\n", crtc->off_pitch);
 709         DPRINTK("CRTC_VLINE_CRNT_VLINE: %x\n", crtc->vline_crnt_vline);
 710         DPRINTK("CRTC_GEN_CNTL: %x\n",crtc->gen_cntl);
 711
 712         aty_st_le32(CRTC_H_TOTAL_DISP, crtc->h_tot_disp, par);
 713         aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid, par);
 714         aty_st_le32(CRTC_V_TOTAL_DISP, crtc->v_tot_disp, par);
 715         aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid, par);
 716         aty_st_le32(CRTC_OFF_PITCH, crtc->off_pitch, par);
 717         aty_st_le32(CRTC_VLINE_CRNT_VLINE, crtc->vline_crnt_vline, par);
 718
 719         aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl, par);
 720 #if 0
 721         FIXME
 722         if (par->accel_flags & FB_ACCELF_TEXT)
 723                 aty_init_engine(par, info);
 724 #endif
 725 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 726         /* after setting the CRTC registers we should set the LCD registers. */
 727         if (par->lcd_table != 0) {
 728                 /* switch to shadow registers */
 729                 aty_st_lcd(LCD_GEN_CNTL, (crtc->lcd_gen_cntl & ~CRTC_RW_SELECT) |
 730                         (SHADOW_EN | SHADOW_RW_EN), par);
 731
 732                 DPRINTK("set shadow CRT to %ix%i %c%c\n",
 733                     ((((crtc->shadow_h_tot_disp>>16) & 0xff) + 1)<<3), (((crtc->shadow_v_tot_disp>>16) & 0x7ff) + 1),
 734                     (crtc->shadow_h_sync_strt_wid & 0x200000)?'N':'P', (crtc->shadow_v_sync_strt_wid & 0x200000)?'N':'P');
 735
 736                 DPRINTK("SHADOW CRTC_H_TOTAL_DISP: %x\n", crtc->shadow_h_tot_disp);
 737                 DPRINTK("SHADOW CRTC_H_SYNC_STRT_WID: %x\n", crtc->shadow_h_sync_strt_wid);
 738                 DPRINTK("SHADOW CRTC_V_TOTAL_DISP: %x\n", crtc->shadow_v_tot_disp);
 739                 DPRINTK("SHADOW CRTC_V_SYNC_STRT_WID: %x\n", crtc->shadow_v_sync_strt_wid);
 740
 741                 aty_st_le32(CRTC_H_TOTAL_DISP, crtc->shadow_h_tot_disp, par);
 742                 aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->shadow_h_sync_strt_wid, par);
 743                 aty_st_le32(CRTC_V_TOTAL_DISP, crtc->shadow_v_tot_disp, par);
 744                 aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->shadow_v_sync_strt_wid, par);
 745
 746                 /* restore CRTC selection & shadow state and enable stretching */
 747                 DPRINTK("LCD_GEN_CNTL: %x\n", crtc->lcd_gen_cntl);
 748                 DPRINTK("HORZ_STRETCHING: %x\n", crtc->horz_stretching);
 749                 DPRINTK("VERT_STRETCHING: %x\n", crtc->vert_stretching);
 750                 if(!M64_HAS(LT_LCD_REGS))
 751                     DPRINTK("EXT_VERT_STRETCH: %x\n", crtc->ext_vert_stretch);
 752
 753                 aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);
 754                 aty_st_lcd(HORZ_STRETCHING, crtc->horz_stretching, par);
 755                 aty_st_lcd(VERT_STRETCHING, crtc->vert_stretching, par);
 756                 if(!M64_HAS(LT_LCD_REGS)) {
 757                     aty_st_lcd(EXT_VERT_STRETCH, crtc->ext_vert_stretch, par);
 758                     aty_ld_le32(LCD_INDEX, par);
 759                     aty_st_le32(LCD_INDEX, crtc->lcd_index, par);
 760                 }
 761         }
 762 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
 763 }
 764
 765 static int aty_var_to_crtc(const struct fb_info *info,
 766         const struct fb_var_screeninfo *var, struct crtc *crtc)
 767 {
 768         struct atyfb_par *par = (struct atyfb_par *) info->par;
 769         u32 xres, yres, vxres, vyres, xoffset, yoffset, bpp;
 770         u32 sync, vmode, vdisplay;
 771         u32 h_total, h_disp, h_sync_strt, h_sync_end, h_sync_dly, h_sync_wid, h_sync_pol;
 772         u32 v_total, v_disp, v_sync_strt, v_sync_end, v_sync_wid, v_sync_pol, c_sync;
 773         u32 pix_width, dp_pix_width, dp_chain_mask;
 774
 775         /* input */
 776         xres = var->xres;
 777         yres = var->yres;
 778         vxres = var->xres_virtual;
 779         vyres = var->yres_virtual;
 780         xoffset = var->xoffset;
 781         yoffset = var->yoffset;
 782         bpp = var->bits_per_pixel;
 783         if (bpp == 16)
 784                 bpp = (var->green.length == 5) ? 15 : 16;
 785         sync = var->sync;
 786         vmode = var->vmode;
 787
 788         /* convert (and round up) and validate */
 789         if (vxres < xres + xoffset)
 790                 vxres = xres + xoffset;
 791         h_disp = xres;
 792
 793         if (vyres < yres + yoffset)
 794                 vyres = yres + yoffset;
 795         v_disp = yres;
 796
 797         if (bpp <= 8) {
 798                 bpp = 8;
 799                 pix_width = CRTC_PIX_WIDTH_8BPP;
 800                 dp_pix_width =
 801                     HOST_8BPP | SRC_8BPP | DST_8BPP |
 802                     BYTE_ORDER_LSB_TO_MSB;
 803                 dp_chain_mask = DP_CHAIN_8BPP;
 804         } else if (bpp <= 15) {
 805                 bpp = 16;
 806                 pix_width = CRTC_PIX_WIDTH_15BPP;
 807                 dp_pix_width = HOST_15BPP | SRC_15BPP | DST_15BPP |
 808                     BYTE_ORDER_LSB_TO_MSB;
 809                 dp_chain_mask = DP_CHAIN_15BPP;
 810         } else if (bpp <= 16) {
 811                 bpp = 16;
 812                 pix_width = CRTC_PIX_WIDTH_16BPP;
 813                 dp_pix_width = HOST_16BPP | SRC_16BPP | DST_16BPP |
 814                     BYTE_ORDER_LSB_TO_MSB;
 815                 dp_chain_mask = DP_CHAIN_16BPP;
 816         } else if (bpp <= 24 && M64_HAS(INTEGRATED)) {
 817                 bpp = 24;
 818                 pix_width = CRTC_PIX_WIDTH_24BPP;
 819                 dp_pix_width =
 820                     HOST_8BPP | SRC_8BPP | DST_8BPP |
 821                     BYTE_ORDER_LSB_TO_MSB;
 822                 dp_chain_mask = DP_CHAIN_24BPP;
 823         } else if (bpp <= 32) {
 824                 bpp = 32;
 825                 pix_width = CRTC_PIX_WIDTH_32BPP;
 826                 dp_pix_width = HOST_32BPP | SRC_32BPP | DST_32BPP |
 827                     BYTE_ORDER_LSB_TO_MSB;
 828                 dp_chain_mask = DP_CHAIN_32BPP;
 829         } else
 830                 FAIL("invalid bpp");
 831
 832         if (vxres * vyres * bpp / 8 > info->fix.smem_len)
 833                 FAIL("not enough video RAM");
 834
 835         h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
 836         v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
 837
 838         if((xres > 1600) || (yres > 1200)) {
 839                 FAIL("MACH64 chips are designed for max 1600x1200\n"
 840                 "select anoter resolution.");
 841         }
 842         h_sync_strt = h_disp + var->right_margin;
 843         h_sync_end = h_sync_strt + var->hsync_len;
 844         h_sync_dly  = var->right_margin & 7;
 845         h_total = h_sync_end + h_sync_dly + var->left_margin;
 846
 847         v_sync_strt = v_disp + var->lower_margin;
 848         v_sync_end = v_sync_strt + var->vsync_len;
 849         v_total = v_sync_end + var->upper_margin;
 850
 851 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 852         if (par->lcd_table != 0) {
 853                 if(!M64_HAS(LT_LCD_REGS)) {
 854                     u32 lcd_index = aty_ld_le32(LCD_INDEX, par);
 855                     crtc->lcd_index = lcd_index &
 856                         ~(LCD_INDEX_MASK | LCD_DISPLAY_DIS | LCD_SRC_SEL | CRTC2_DISPLAY_DIS);
 857                     aty_st_le32(LCD_INDEX, lcd_index, par);
 858                 }
 859
 860                 if (!M64_HAS(MOBIL_BUS))
 861                         crtc->lcd_index |= CRTC2_DISPLAY_DIS;
 862
 863                 crtc->lcd_config_panel = aty_ld_lcd(CONFIG_PANEL, par) | 0x4000;
 864                 crtc->lcd_gen_cntl = aty_ld_lcd(LCD_GEN_CNTL, par) & ~CRTC_RW_SELECT;
 865
 866                 crtc->lcd_gen_cntl &=
 867                         ~(HORZ_DIVBY2_EN | DIS_HOR_CRT_DIVBY2 | TVCLK_PM_EN |
 868                         /*VCLK_DAC_PM_EN | USE_SHADOWED_VEND |*/
 869                         USE_SHADOWED_ROWCUR | SHADOW_EN | SHADOW_RW_EN);
 870                 crtc->lcd_gen_cntl |= DONT_SHADOW_VPAR | LOCK_8DOT;
 871
 872                 if((crtc->lcd_gen_cntl & LCD_ON) &&
 873                         ((xres > par->lcd_width) || (yres > par->lcd_height))) {
 874                         /* We cannot display the mode on the LCD. If the CRT is enabled
 875                            we can turn off the LCD.
 876                            If the CRT is off, it isn't a good idea to switch it on; we don't
 877                            know if one is connected. So it's better to fail then.
 878                          */
 879                         if (crtc->lcd_gen_cntl & CRT_ON) {
 880                                 if (!(var->activate & FB_ACTIVATE_TEST))
 881                                         PRINTKI("Disable LCD panel, because video mode does not fit.\n");
 882                                 crtc->lcd_gen_cntl &= ~LCD_ON;
 883                                 /*aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);*/
 884                         } else {
 885                                 if (!(var->activate & FB_ACTIVATE_TEST))
 886                                         PRINTKE("Video mode exceeds size of LCD panel.\nConnect this computer to a conventional monitor if you really need this mode.\n");
 887                                 return -EINVAL;
 888                         }
 889                 }
 890         }
 891
 892         if ((par->lcd_table != 0) && (crtc->lcd_gen_cntl & LCD_ON)) {
 893                 int VScan = 1;
 894                 /* bpp -> bytespp, 1,4 -> 0; 8 -> 2; 15,16 -> 1; 24 -> 6; 32 -> 5
 895                 const u8 DFP_h_sync_dly_LT[] = { 0, 2, 1, 6, 5 };
 896                 const u8 ADD_to_strt_wid_and_dly_LT_DAC[] = { 0, 5, 6, 9, 9, 12, 12 };  */
 897
 898                 vmode &= ~(FB_VMODE_DOUBLE | FB_VMODE_INTERLACED);
 899
 900                 /* This is horror! When we simulate, say 640x480 on an 800x600
 901                    LCD monitor, the CRTC should be programmed 800x600 values for
 902                    the non visible part, but 640x480 for the visible part.
 903                    This code has been tested on a laptop with it's 1400x1050 LCD
 904                    monitor and a conventional monitor both switched on.
 905                    Tested modes: 1280x1024, 1152x864, 1024x768, 800x600,
 906                     works with little glitches also with DOUBLESCAN modes
 907                  */
 908                 if (yres < par->lcd_height) {
 909                         VScan = par->lcd_height / yres;
 910                         if(VScan > 1) {
 911                                 VScan = 2;
 912                                 vmode |= FB_VMODE_DOUBLE;
 913                         }
 914                 }
 915
 916                 h_sync_strt = h_disp + par->lcd_right_margin;
 917                 h_sync_end = h_sync_strt + par->lcd_hsync_len;
 918                 h_sync_dly = /*DFP_h_sync_dly[ ( bpp + 1 ) / 3 ]; */par->lcd_hsync_dly;
 919                 h_total = h_disp + par->lcd_hblank_len;
 920
 921                 v_sync_strt = v_disp + par->lcd_lower_margin / VScan;
 922                 v_sync_end = v_sync_strt + par->lcd_vsync_len / VScan;
 923                 v_total = v_disp + par->lcd_vblank_len / VScan;
 924         }
 925 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
 926
 927         h_disp = (h_disp >> 3) - 1;
 928         h_sync_strt = (h_sync_strt >> 3) - 1;
 929         h_sync_end = (h_sync_end >> 3) - 1;
 930         h_total = (h_total >> 3) - 1;
 931         h_sync_wid = h_sync_end - h_sync_strt;
 932
 933         FAIL_MAX("h_disp too large", h_disp, 0xff);
 934         FAIL_MAX("h_sync_strt too large", h_sync_strt, 0x1ff);
 935         /*FAIL_MAX("h_sync_wid too large", h_sync_wid, 0x1f);*/
 936         if(h_sync_wid > 0x1f)
 937                 h_sync_wid = 0x1f;
 938         FAIL_MAX("h_total too large", h_total, 0x1ff);
 939
 940         if (vmode & FB_VMODE_DOUBLE) {
 941                 v_disp <<= 1;
 942                 v_sync_strt <<= 1;
 943                 v_sync_end <<= 1;
 944                 v_total <<= 1;
 945         }
 946
 947         vdisplay = yres;
 948 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 949         if ((par->lcd_table != 0) && (crtc->lcd_gen_cntl & LCD_ON))
 950                 vdisplay  = par->lcd_height;
 951 #endif
 952
 953         v_disp--;
 954         v_sync_strt--;
 955         v_sync_end--;
 956         v_total--;
 957         v_sync_wid = v_sync_end - v_sync_strt;
 958
 959         FAIL_MAX("v_disp too large", v_disp, 0x7ff);
 960         FAIL_MAX("v_sync_stsrt too large", v_sync_strt, 0x7ff);
 961         /*FAIL_MAX("v_sync_wid too large", v_sync_wid, 0x1f);*/
 962         if(v_sync_wid > 0x1f)
 963                 v_sync_wid = 0x1f;
 964         FAIL_MAX("v_total too large", v_total, 0x7ff);
 965
 966         c_sync = sync & FB_SYNC_COMP_HIGH_ACT ? CRTC_CSYNC_EN : 0;
 967
 968         /* output */
 969         crtc->vxres = vxres;
 970         crtc->vyres = vyres;
 971         crtc->xoffset = xoffset;
 972         crtc->yoffset = yoffset;
 973         crtc->bpp = bpp;
 974         crtc->off_pitch = ((yoffset*vxres+xoffset)*bpp/64) | (vxres<<19);
 975         crtc->vline_crnt_vline = 0;
 976
 977         crtc->h_tot_disp = h_total | (h_disp<<16);
 978         crtc->h_sync_strt_wid = (h_sync_strt & 0xff) | (h_sync_dly<<8) |
 979                 ((h_sync_strt & 0x100)<<4) | (h_sync_wid<<16) | (h_sync_pol<<21);
 980         crtc->v_tot_disp = v_total | (v_disp<<16);
 981         crtc->v_sync_strt_wid = v_sync_strt | (v_sync_wid<<16) | (v_sync_pol<<21);
 982
 983         /* crtc->gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC_PRESERVED_MASK; */
 984         crtc->gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN | pix_width | c_sync;
 985         crtc->gen_cntl |= CRTC_VGA_LINEAR;
 986
 987         /* Enable doublescan mode if requested */
 988         if (vmode & FB_VMODE_DOUBLE)
 989                 crtc->gen_cntl |= CRTC_DBL_SCAN_EN;
 990         /* Enable interlaced mode if requested */
 991         if (vmode & FB_VMODE_INTERLACED)
 992                 crtc->gen_cntl |= CRTC_INTERLACE_EN;
 993 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 994         if (par->lcd_table != 0) {
 995                 vdisplay = yres;
 996                 if(vmode & FB_VMODE_DOUBLE)
 997                         vdisplay <<= 1;
 998                 crtc->gen_cntl &= ~(CRTC2_EN | CRTC2_PIX_WIDTH);
 999                 crtc->lcd_gen_cntl &= ~(HORZ_DIVBY2_EN | DIS_HOR_CRT_DIVBY2 |
1000                         /*TVCLK_PM_EN | VCLK_DAC_PM_EN |*/
1001                         USE_SHADOWED_VEND | USE_SHADOWED_ROWCUR | SHADOW_EN | SHADOW_RW_EN);
1002                 crtc->lcd_gen_cntl |= (DONT_SHADOW_VPAR/* | LOCK_8DOT*/);
1003
1004                 /* MOBILITY M1 tested, FIXME: LT */
1005                 crtc->horz_stretching = aty_ld_lcd(HORZ_STRETCHING, par);
1006                 if (!M64_HAS(LT_LCD_REGS))
1007                         crtc->ext_vert_stretch = aty_ld_lcd(EXT_VERT_STRETCH, par) &
1008                                 ~(AUTO_VERT_RATIO | VERT_STRETCH_MODE | VERT_STRETCH_RATIO3);
1009
1010                 crtc->horz_stretching &=
1011                         ~(HORZ_STRETCH_RATIO | HORZ_STRETCH_LOOP | AUTO_HORZ_RATIO |
1012                         HORZ_STRETCH_MODE | HORZ_STRETCH_EN);
1013                 if (xres < par->lcd_width && crtc->lcd_gen_cntl & LCD_ON) {
1014                         do {
1015                                 /*
1016                                 * The horizontal blender misbehaves when HDisplay is less than a
1017                                 * a certain threshold (440 for a 1024-wide panel).  It doesn't
1018                                 * stretch such modes enough.  Use pixel replication instead of
1019                                 * blending to stretch modes that can be made to exactly fit the
1020                                 * panel width.  The undocumented "NoLCDBlend" option allows the
1021                                 * pixel-replicated mode to be slightly wider or narrower than the
1022                                 * panel width.  It also causes a mode that is exactly half as wide
1023                                 * as the panel to be pixel-replicated, rather than blended.
1024                                 */
1025                                 int HDisplay  = xres & ~7;
1026                                 int nStretch  = par->lcd_width / HDisplay;
1027                                 int Remainder = par->lcd_width % HDisplay;
1028
1029                                 if ((!Remainder && ((nStretch > 2))) ||
1030                                         (((HDisplay * 16) / par->lcd_width) < 7)) {
1031                                         static const char StretchLoops[] = {10, 12, 13, 15, 16};
1032                                         int horz_stretch_loop = -1, BestRemainder;
1033                                         int Numerator = HDisplay, Denominator = par->lcd_width;
1034                                         int Index = 5;
1035                                         ATIReduceRatio(&Numerator, &Denominator);
1036
1037                                         BestRemainder = (Numerator * 16) / Denominator;
1038                                         while (--Index >= 0) {
1039                                                 Remainder = ((Denominator - Numerator) * StretchLoops[Index]) %
1040                                                         Denominator;
1041                                                 if (Remainder < BestRemainder) {
1042                                                         horz_stretch_loop = Index;
1043                                                         if (!(BestRemainder = Remainder))
1044                                                                 break;
1045                                                 }
1046                                         }
1047
1048                                         if ((horz_stretch_loop >= 0) && !BestRemainder) {
1049                                                 int horz_stretch_ratio = 0, Accumulator = 0;
1050                                                 int reuse_previous = 1;
1051
1052                                                 Index = StretchLoops[horz_stretch_loop];
1053
1054                                                 while (--Index >= 0) {
1055                                                         if (Accumulator > 0)
1056                                                                 horz_stretch_ratio |= reuse_previous;
1057                                                         else
1058                                                                 Accumulator += Denominator;
1059                                                         Accumulator -= Numerator;
1060                                                         reuse_previous <<= 1;
1061                                                 }
1062
1063                                                 crtc->horz_stretching |= (HORZ_STRETCH_EN |
1064                                                         ((horz_stretch_loop & HORZ_STRETCH_LOOP) << 16) |
1065                                                         (horz_stretch_ratio & HORZ_STRETCH_RATIO));
1066                                                 break;      /* Out of the do { ... } while (0) */
1067                                         }
1068                                 }
1069
1070                                 crtc->horz_stretching |= (HORZ_STRETCH_MODE | HORZ_STRETCH_EN |
1071                                         (((HDisplay * (HORZ_STRETCH_BLEND + 1)) / par->lcd_width) & HORZ_STRETCH_BLEND));
1072                         } while (0);
1073                 }
1074
1075                 if (vdisplay < par->lcd_height && crtc->lcd_gen_cntl & LCD_ON) {
1076                         crtc->vert_stretching = (VERT_STRETCH_USE0 | VERT_STRETCH_EN |
1077                                 (((vdisplay * (VERT_STRETCH_RATIO0 + 1)) / par->lcd_height) & VERT_STRETCH_RATIO0));
1078
1079                         if (!M64_HAS(LT_LCD_REGS) &&
1080                             xres <= (M64_HAS(MOBIL_BUS)?1024:800))
1081                                 crtc->ext_vert_stretch |= VERT_STRETCH_MODE;
1082                 } else {
1083                         /*
1084                          * Don't use vertical blending if the mode is too wide or not
1085                          * vertically stretched.
1086                          */
1087                         crtc->vert_stretching = 0;
1088                 }
1089                 /* copy to shadow crtc */
1090                 crtc->shadow_h_tot_disp = crtc->h_tot_disp;
1091                 crtc->shadow_h_sync_strt_wid = crtc->h_sync_strt_wid;
1092                 crtc->shadow_v_tot_disp = crtc->v_tot_disp;
1093                 crtc->shadow_v_sync_strt_wid = crtc->v_sync_strt_wid;
1094         }
1095 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
1096
1097         if (M64_HAS(MAGIC_FIFO)) {
1098                 /* FIXME: display FIFO low watermark values */
1099                 crtc->gen_cntl |= (aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC_FIFO_LWM);
1100         }
1101         crtc->dp_pix_width = dp_pix_width;
1102         crtc->dp_chain_mask = dp_chain_mask;
1103
1104         return 0;
1105 }
1106
1107 static int aty_crtc_to_var(const struct crtc *crtc, struct fb_var_screeninfo *var)
1108 {
1109         u32 xres, yres, bpp, left, right, upper, lower, hslen, vslen, sync;
1110         u32 h_total, h_disp, h_sync_strt, h_sync_dly, h_sync_wid,
1111             h_sync_pol;
1112         u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
1113         u32 pix_width;
1114         u32 double_scan, interlace;
1115
1116         /* input */
1117         h_total = crtc->h_tot_disp & 0x1ff;
1118         h_disp = (crtc->h_tot_disp >> 16) & 0xff;
1119         h_sync_strt = (crtc->h_sync_strt_wid & 0xff) | ((crtc->h_sync_strt_wid >> 4) & 0x100);
1120         h_sync_dly = (crtc->h_sync_strt_wid >> 8) & 0x7;
1121         h_sync_wid = (crtc->h_sync_strt_wid >> 16) & 0x1f;
1122         h_sync_pol = (crtc->h_sync_strt_wid >> 21) & 0x1;
1123         v_total = crtc->v_tot_disp & 0x7ff;
1124         v_disp = (crtc->v_tot_disp >> 16) & 0x7ff;
1125         v_sync_strt = crtc->v_sync_strt_wid & 0x7ff;
1126         v_sync_wid = (crtc->v_sync_strt_wid >> 16) & 0x1f;
1127         v_sync_pol = (crtc->v_sync_strt_wid >> 21) & 0x1;
1128         c_sync = crtc->gen_cntl & CRTC_CSYNC_EN ? 1 : 0;
1129         pix_width = crtc->gen_cntl & CRTC_PIX_WIDTH_MASK;
1130         double_scan = crtc->gen_cntl & CRTC_DBL_SCAN_EN;
1131         interlace = crtc->gen_cntl & CRTC_INTERLACE_EN;
1132
1133         /* convert */
1134         xres = (h_disp + 1) * 8;
1135         yres = v_disp + 1;
1136         left = (h_total - h_sync_strt - h_sync_wid) * 8 - h_sync_dly;
1137         right = (h_sync_strt - h_disp) * 8 + h_sync_dly;
1138         hslen = h_sync_wid * 8;
1139         upper = v_total - v_sync_strt - v_sync_wid;
1140         lower = v_sync_strt - v_disp;
1141         vslen = v_sync_wid;
1142         sync = (h_sync_pol ? 0 : FB_SYNC_HOR_HIGH_ACT) |
1143             (v_sync_pol ? 0 : FB_SYNC_VERT_HIGH_ACT) |
1144             (c_sync ? FB_SYNC_COMP_HIGH_ACT : 0);
1145
1146         switch (pix_width) {
1147 #if 0
1148         case CRTC_PIX_WIDTH_4BPP:
1149                 bpp = 4;
1150                 var->red.offset = 0;
1151                 var->red.length = 8;
1152                 var->green.offset = 0;
1153                 var->green.length = 8;
1154                 var->blue.offset = 0;
1155                 var->blue.length = 8;
1156                 var->transp.offset = 0;
1157                 var->transp.length = 0;
1158                 break;
1159 #endif
1160         case CRTC_PIX_WIDTH_8BPP:
1161                 bpp = 8;
1162                 var->red.offset = 0;
1163                 var->red.length = 8;
1164                 var->green.offset = 0;
1165                 var->green.length = 8;
1166                 var->blue.offset = 0;
1167                 var->blue.length = 8;
1168                 var->transp.offset = 0;
1169                 var->transp.length = 0;
1170                 break;
1171         case CRTC_PIX_WIDTH_15BPP:      /* RGB 555 */
1172                 bpp = 16;
1173                 var->red.offset = 10;
1174                 var->red.length = 5;
1175                 var->green.offset = 5;
1176                 var->green.length = 5;
1177                 var->blue.offset = 0;
1178                 var->blue.length = 5;
1179                 var->transp.offset = 0;
1180                 var->transp.length = 0;
1181                 break;
1182         case CRTC_PIX_WIDTH_16BPP:      /* RGB 565 */
1183                 bpp = 16;
1184                 var->red.offset = 11;
1185                 var->red.length = 5;
1186                 var->green.offset = 5;
1187                 var->green.length = 6;
1188                 var->blue.offset = 0;
1189                 var->blue.length = 5;
1190                 var->transp.offset = 0;
1191                 var->transp.length = 0;
1192                 break;
1193         case CRTC_PIX_WIDTH_24BPP:      /* RGB 888 */
1194                 bpp = 24;
1195                 var->red.offset = 16;
1196                 var->red.length = 8;
1197                 var->green.offset = 8;
1198                 var->green.length = 8;
1199                 var->blue.offset = 0;
1200                 var->blue.length = 8;
1201                 var->transp.offset = 0;
1202                 var->transp.length = 0;
1203                 break;
1204         case CRTC_PIX_WIDTH_32BPP:      /* ARGB 8888 */
1205                 bpp = 32;
1206                 var->red.offset = 16;
1207                 var->red.length = 8;
1208                 var->green.offset = 8;
1209                 var->green.length = 8;
1210                 var->blue.offset = 0;
1211                 var->blue.length = 8;
1212                 var->transp.offset = 24;
1213                 var->transp.length = 8;
1214                 break;
1215         default:
1216                 PRINTKE("Invalid pixel width\n");
1217                 return -EINVAL;
1218         }
1219
1220         /* output */
1221         var->xres = xres;
1222         var->yres = yres;
1223         var->xres_virtual = crtc->vxres;
1224         var->yres_virtual = crtc->vyres;
1225         var->bits_per_pixel = bpp;
1226         var->left_margin = left;
1227         var->right_margin = right;
1228         var->upper_margin = upper;
1229         var->lower_margin = lower;
1230         var->hsync_len = hslen;
1231         var->vsync_len = vslen;
1232         var->sync = sync;
1233         var->vmode = FB_VMODE_NONINTERLACED;
1234         /* In double scan mode, the vertical parameters are doubled, so we need to
1235            half them to get the right values.
1236            In interlaced mode the values are already correct, so no correction is
1237            necessary.
1238          */
1239         if (interlace)
1240                 var->vmode = FB_VMODE_INTERLACED;
1241
1242         if (double_scan) {
1243                 var->vmode = FB_VMODE_DOUBLE;
1244                 var->yres>>=1;
1245                 var->upper_margin>>=1;
1246                 var->lower_margin>>=1;
1247                 var->vsync_len>>=1;
1248         }
1249
1250         return 0;
1251 }
1252
1253 /* ------------------------------------------------------------------------- */
1254
1255 static int atyfb_set_par(struct fb_info *info)
1256 {
1257         struct atyfb_par *par = (struct atyfb_par *) info->par;
1258         struct fb_var_screeninfo *var = &info->var;
1259         u32 tmp, pixclock;
1260         int err;
1261 #ifdef DEBUG
1262         struct fb_var_screeninfo debug;
1263         u32 pixclock_in_ps;
1264 #endif
1265         if (par->asleep)
1266                 return 0;
1267
1268         if ((err = aty_var_to_crtc(info, var, &par->crtc)))
1269                 return err;
1270
1271         pixclock = atyfb_get_pixclock(var, par);
1272
1273         if (pixclock == 0) {
1274                 PRINTKE("Invalid pixclock\n");
1275                 return -EINVAL;
1276         } else {
1277                 if((err = par->pll_ops->var_to_pll(info, pixclock, var->bits_per_pixel, &par->pll)))
1278                         return err;
1279         }
1280
1281         par->accel_flags = var->accel_flags; /* hack */
1282
1283         if (par->blitter_may_be_busy)
1284                 wait_for_idle(par);
1285
1286         aty_set_crtc(par, &par->crtc);
1287         par->dac_ops->set_dac(info, &par->pll, var->bits_per_pixel, par->accel_flags);
1288         par->pll_ops->set_pll(info, &par->pll);
1289
1290 #ifdef DEBUG
1291         if(par->pll_ops && par->pll_ops->pll_to_var)
1292                 pixclock_in_ps = par->pll_ops->pll_to_var(info, &(par->pll));
1293         else
1294                 pixclock_in_ps = 0;
1295
1296         if(0 == pixclock_in_ps) {
1297                 PRINTKE("ALERT ops->pll_to_var get 0\n");
1298                 pixclock_in_ps = pixclock;
1299         }
1300
1301         memset(&debug, 0, sizeof(debug));
1302         if(!aty_crtc_to_var(&(par->crtc), &debug)) {
1303                 u32 hSync, vRefresh;
1304                 u32 h_disp, h_sync_strt, h_sync_end, h_total;
1305                 u32 v_disp, v_sync_strt, v_sync_end, v_total;
1306
1307                 h_disp = debug.xres;
1308                 h_sync_strt = h_disp + debug.right_margin;
1309                 h_sync_end = h_sync_strt + debug.hsync_len;
1310                 h_total = h_sync_end + debug.left_margin;
1311                 v_disp = debug.yres;
1312                 v_sync_strt = v_disp + debug.lower_margin;
1313                 v_sync_end = v_sync_strt + debug.vsync_len;
1314                 v_total = v_sync_end + debug.upper_margin;
1315
1316                 hSync = 1000000000 / (pixclock_in_ps * h_total);
1317                 vRefresh = (hSync * 1000) / v_total;
1318                 if (par->crtc.gen_cntl & CRTC_INTERLACE_EN)
1319                 vRefresh *= 2;
1320                 if (par->crtc.gen_cntl & CRTC_DBL_SCAN_EN)
1321                 vRefresh /= 2;
1322
1323                 DPRINTK("atyfb_set_par\n");
1324                 DPRINTK(" Set Visible Mode to %ix%i-%i\n", var->xres, var->yres, var->bits_per_pixel);
1325                 DPRINTK(" Virtual resolution %ix%i, pixclock_in_ps %i (calculated %i)\n",
1326                         var->xres_virtual, var->yres_virtual, pixclock, pixclock_in_ps);
1327                 DPRINTK(" Dot clock:           %i MHz\n", 1000000 / pixclock_in_ps);
1328                 DPRINTK(" Horizontal sync:     %i kHz\n", hSync);
1329                 DPRINTK(" Vertical refresh:    %i Hz\n", vRefresh);
1330                 DPRINTK(" x  style: %i.%03i %i %i %i %i   %i %i %i %i\n",
1331                         1000000 / pixclock_in_ps, 1000000 % pixclock_in_ps,
1332                         h_disp, h_sync_strt, h_sync_end, h_total,
1333                         v_disp, v_sync_strt, v_sync_end, v_total);
1334                 DPRINTK(" fb style: %i  %i %i %i %i %i %i %i %i\n",
1335                         pixclock_in_ps,
1336                         debug.left_margin, h_disp, debug.right_margin, debug.hsync_len,
1337                         debug.upper_margin, v_disp, debug.lower_margin, debug.vsync_len);
1338         }
1339 #endif /* DEBUG */
1340
1341         if (!M64_HAS(INTEGRATED)) {
1342                 /* Don't forget MEM_CNTL */
1343                 tmp = aty_ld_le32(MEM_CNTL, par) & 0xf0ffffff;
1344                 switch (var->bits_per_pixel) {
1345                 case 8:
1346                         tmp |= 0x02000000;
1347                         break;
1348                 case 16:
1349                         tmp |= 0x03000000;
1350                         break;
1351                 case 32:
1352                         tmp |= 0x06000000;
1353                         break;
1354                 }
1355                 aty_st_le32(MEM_CNTL, tmp, par);
1356         } else {
1357                 tmp = aty_ld_le32(MEM_CNTL, par) & 0xf00fffff;
1358                 if (!M64_HAS(MAGIC_POSTDIV))
1359                         tmp |= par->mem_refresh_rate << 20;
1360                 switch (var->bits_per_pixel) {
1361                 case 8:
1362                 case 24:
1363                         tmp |= 0x00000000;
1364                         break;
1365                 case 16:
1366                         tmp |= 0x04000000;
1367                         break;
1368                 case 32:
1369                         tmp |= 0x08000000;
1370                         break;
1371                 }
1372                 if (M64_HAS(CT_BUS)) {
1373                         aty_st_le32(DAC_CNTL, 0x87010184, par);
1374                         aty_st_le32(BUS_CNTL, 0x680000f9, par);
1375                 } else if (M64_HAS(VT_BUS)) {
1376                         aty_st_le32(DAC_CNTL, 0x87010184, par);
1377                         aty_st_le32(BUS_CNTL, 0x680000f9, par);
1378                 } else if (M64_HAS(MOBIL_BUS)) {
1379                         aty_st_le32(DAC_CNTL, 0x80010102, par);
1380                         aty_st_le32(BUS_CNTL, 0x7b33a040 | (par->aux_start ? BUS_APER_REG_DIS : 0), par);
1381                 } else {
1382                         /* GT */
1383                         aty_st_le32(DAC_CNTL, 0x86010102, par);
1384                         aty_st_le32(BUS_CNTL, 0x7b23a040 | (par->aux_start ? BUS_APER_REG_DIS : 0), par);
1385                         aty_st_le32(EXT_MEM_CNTL, aty_ld_le32(EXT_MEM_CNTL, par) | 0x5000001, par);
1386                 }
1387                 aty_st_le32(MEM_CNTL, tmp, par);
1388         }
1389         aty_st_8(DAC_MASK, 0xff, par);
1390
1391         info->fix.line_length = var->xres_virtual * var->bits_per_pixel/8;
1392         info->fix.visual = var->bits_per_pixel <= 8 ?
1393                 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1394
1395         /* Initialize the graphics engine */
1396         if (par->accel_flags & FB_ACCELF_TEXT)
1397                 aty_init_engine(par, info);
1398
1399 #ifdef CONFIG_BOOTX_TEXT
1400         btext_update_display(info->fix.smem_start,
1401                 (((par->crtc.h_tot_disp >> 16) & 0xff) + 1) * 8,
1402                 ((par->crtc.v_tot_disp >> 16) & 0x7ff) + 1,
1403                 var->bits_per_pixel,
1404                 par->crtc.vxres * var->bits_per_pixel / 8);
1405 #endif /* CONFIG_BOOTX_TEXT */
1406 #if 0
1407         /* switch to accelerator mode */
1408         if (!(par->crtc.gen_cntl & CRTC_EXT_DISP_EN))
1409                 aty_st_le32(CRTC_GEN_CNTL, par->crtc.gen_cntl | CRTC_EXT_DISP_EN, par);
1410 #endif
1411 #ifdef DEBUG
1412 {
1413         /* dump non shadow CRTC, pll, LCD registers */
1414         int i; u32 base;
1415
1416         /* CRTC registers */
1417         base = 0x2000;
1418         printk("debug atyfb: Mach64 non-shadow register values:");
1419         for (i = 0; i < 256; i = i+4) {
1420                 if(i%16 == 0) printk("\ndebug atyfb: 0x%04X: ", base + i);
1421                 printk(" %08X", aty_ld_le32(i, par));
1422         }
1423         printk("\n\n");
1424
1425 #ifdef CONFIG_FB_ATY_CT
1426         /* PLL registers */
1427         base = 0x00;
1428         printk("debug atyfb: Mach64 PLL register values:");
1429         for (i = 0; i < 64; i++) {
1430                 if(i%16 == 0) printk("\ndebug atyfb: 0x%02X: ", base + i);
1431                 if(i%4 == 0)  printk(" ");
1432                 printk("%02X", aty_ld_pll_ct(i, par));
1433         }
1434         printk("\n\n");
1435 #endif  /* CONFIG_FB_ATY_CT */
1436
1437 #ifdef CONFIG_FB_ATY_GENERIC_LCD
1438         if (par->lcd_table != 0) {
1439                 /* LCD registers */
1440                 base = 0x00;
1441                 printk("debug atyfb: LCD register values:");
1442                 if(M64_HAS(LT_LCD_REGS)) {
1443                     for(i = 0; i <= POWER_MANAGEMENT; i++) {
1444                         if(i == EXT_VERT_STRETCH)
1445                             continue;
1446                         printk("\ndebug atyfb: 0x%04X: ", lt_lcd_regs[i]);
1447                         printk(" %08X", aty_ld_lcd(i, par));
1448                     }
1449
1450                 } else {
1451                     for (i = 0; i < 64; i++) {
1452                         if(i%4 == 0) printk("\ndebug atyfb: 0x%02X: ", base + i);
1453                         printk(" %08X", aty_ld_lcd(i, par));
1454                     }
1455                 }
1456                 printk("\n\n");
1457         }
1458 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
1459 }
1460 #endif /* DEBUG */
1461         return 0;
1462 }
1463
1464 static int atyfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
1465 {
1466         struct atyfb_par *par = (struct atyfb_par *) info->par;
1467         int err;
1468         struct crtc crtc;
1469         union aty_pll pll;
1470         u32 pixclock;
1471
1472         memcpy(&pll, &(par->pll), sizeof(pll));
1473
1474         if((err = aty_var_to_crtc(info, var, &crtc)))
1475                 return err;
1476
1477         pixclock = atyfb_get_pixclock(var, par);
1478
1479         if (pixclock == 0) {
1480                 if (!(var->activate & FB_ACTIVATE_TEST))
1481                         PRINTKE("Invalid pixclock\n");
1482                 return -EINVAL;
1483         } else {
1484                 if((err = par->pll_ops->var_to_pll(info, pixclock, var->bits_per_pixel, &pll)))
1485                         return err;
1486         }
1487
1488         if (var->accel_flags & FB_ACCELF_TEXT)
1489                 info->var.accel_flags = FB_ACCELF_TEXT;
1490         else
1491                 info->var.accel_flags = 0;
1492
1493 #if 0 /* fbmon is not done. uncomment for 2.5.x -brad */
1494         if (!fbmon_valid_timings(pixclock, htotal, vtotal, info))
1495                 return -EINVAL;
1496 #endif
1497         aty_crtc_to_var(&crtc, var);
1498         var->pixclock = par->pll_ops->pll_to_var(info, &pll);
1499         return 0;
1500 }
1501
1502 static void set_off_pitch(struct atyfb_par *par, const struct fb_info *info)
1503 {
1504         u32 xoffset = info->var.xoffset;
1505         u32 yoffset = info->var.yoffset;
1506         u32 vxres = par->crtc.vxres;
1507         u32 bpp = info->var.bits_per_pixel;
1508
1509         par->crtc.off_pitch = ((yoffset * vxres + xoffset) * bpp / 64) | (vxres << 19);
1510 }
1511
1512
1513     /*
1514      *  Open/Release the frame buffer device
1515      */
1516
1517 static int atyfb_open(struct fb_info *info, int user)
1518 {
1519         struct atyfb_par *par = (struct atyfb_par *) info->par;
1520
1521         if (user) {
1522                 par->open++;
1523 #ifdef __sparc__
1524                 par->mmaped = 0;
1525 #endif
1526         }
1527         return (0);
1528 }
1529
1530 static irqreturn_t aty_irq(int irq, void *dev_id, struct pt_regs *fp)
1531 {
1532         struct atyfb_par *par = dev_id;
1533         int handled = 0;
1534         u32 int_cntl;
1535
1536         spin_lock(&par->int_lock);
1537
1538         int_cntl = aty_ld_le32(CRTC_INT_CNTL, par);
1539
1540         if (int_cntl & CRTC_VBLANK_INT) {
1541                 /* clear interrupt */
1542                 aty_st_le32(CRTC_INT_CNTL, (int_cntl & CRTC_INT_EN_MASK) | CRTC_VBLANK_INT_AK, par);
1543                 par->vblank.count++;
1544                 if (par->vblank.pan_display) {
1545                         par->vblank.pan_display = 0;
1546                         aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1547                 }
1548                 wake_up_interruptible(&par->vblank.wait);
1549                 handled = 1;
1550         }
1551
1552         spin_unlock(&par->int_lock);
1553
1554         return IRQ_RETVAL(handled);
1555 }
1556
1557 static int aty_enable_irq(struct atyfb_par *par, int reenable)
1558 {
1559         u32 int_cntl;
1560
1561         if (!test_and_set_bit(0, &par->irq_flags)) {
1562                 if (request_irq(par->irq, aty_irq, SA_SHIRQ, "atyfb", par)) {
1563                         clear_bit(0, &par->irq_flags);
1564                         return -EINVAL;
1565                 }
1566                 spin_lock_irq(&par->int_lock);
1567                 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK;
1568                 /* clear interrupt */
1569                 aty_st_le32(CRTC_INT_CNTL, int_cntl | CRTC_VBLANK_INT_AK, par);
1570                 /* enable interrupt */
1571                 aty_st_le32(CRTC_INT_CNTL, int_cntl | CRTC_VBLANK_INT_EN, par);
1572                 spin_unlock_irq(&par->int_lock);
1573         } else if (reenable) {
1574                 spin_lock_irq(&par->int_lock);
1575                 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK;
1576                 if (!(int_cntl & CRTC_VBLANK_INT_EN)) {
1577                         printk("atyfb: someone disabled IRQ [%08x]\n", int_cntl);
1578                         /* re-enable interrupt */
1579                         aty_st_le32(CRTC_INT_CNTL, int_cntl | CRTC_VBLANK_INT_EN, par );
1580                 }
1581                 spin_unlock_irq(&par->int_lock);
1582         }
1583
1584         return 0;
1585 }
1586
1587 static int aty_disable_irq(struct atyfb_par *par)
1588 {
1589         u32 int_cntl;
1590
1591         if (test_and_clear_bit(0, &par->irq_flags)) {
1592                 if (par->vblank.pan_display) {
1593                         par->vblank.pan_display = 0;
1594                         aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1595                 }
1596                 spin_lock_irq(&par->int_lock);
1597                 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK;
1598                 /* disable interrupt */
1599                 aty_st_le32(CRTC_INT_CNTL, int_cntl & ~CRTC_VBLANK_INT_EN, par );
1600                 spin_unlock_irq(&par->int_lock);
1601                 free_irq(par->irq, par);
1602         }
1603
1604         return 0;
1605 }
1606
1607 static int atyfb_release(struct fb_info *info, int user)
1608 {
1609         struct atyfb_par *par = (struct atyfb_par *) info->par;
1610         if (user) {
1611                 par->open--;
1612                 mdelay(1);
1613                 wait_for_idle(par);
1614                 if (!par->open) {
1615 #ifdef __sparc__
1616                         int was_mmaped = par->mmaped;
1617
1618                         par->mmaped = 0;
1619
1620                         if (was_mmaped) {
1621                                 struct fb_var_screeninfo var;
1622
1623                                 /* Now reset the default display config, we have no
1624                                  * idea what the program(s) which mmap'd the chip did
1625                                  * to the configuration, nor whether it restored it
1626                                  * correctly.
1627                                  */
1628                                 var = default_var;
1629                                 if (noaccel)
1630                                         var.accel_flags &= ~FB_ACCELF_TEXT;
1631                                 else
1632                                         var.accel_flags |= FB_ACCELF_TEXT;
1633                                 if (var.yres == var.yres_virtual) {
1634                                         u32 videoram = (info->fix.smem_len - (PAGE_SIZE << 2));
1635                                         var.yres_virtual = ((videoram * 8) / var.bits_per_pixel) / var.xres_virtual;
1636                                         if (var.yres_virtual < var.yres)
1637                                                 var.yres_virtual = var.yres;
1638                                 }
1639                         }
1640 #endif
1641                         aty_disable_irq(par);
1642                 }
1643         }
1644         return (0);
1645 }
1646
1647     /*
1648      *  Pan or Wrap the Display
1649      *
1650      *  This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag
1651      */
1652
1653 static int atyfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
1654 {
1655         struct atyfb_par *par = (struct atyfb_par *) info->par;
1656         u32 xres, yres, xoffset, yoffset;
1657
1658         xres = (((par->crtc.h_tot_disp >> 16) & 0xff) + 1) * 8;
1659         yres = ((par->crtc.v_tot_disp >> 16) & 0x7ff) + 1;
1660         if (par->crtc.gen_cntl & CRTC_DBL_SCAN_EN)
1661                 yres >>= 1;
1662         xoffset = (var->xoffset + 7) & ~7;
1663         yoffset = var->yoffset;
1664         if (xoffset + xres > par->crtc.vxres || yoffset + yres > par->crtc.vyres)
1665                 return -EINVAL;
1666         info->var.xoffset = xoffset;
1667         info->var.yoffset = yoffset;
1668         if (par->asleep)
1669                 return 0;
1670
1671         set_off_pitch(par, info);
1672         if ((var->activate & FB_ACTIVATE_VBL) && !aty_enable_irq(par, 0)) {
1673                 par->vblank.pan_display = 1;
1674         } else {
1675                 par->vblank.pan_display = 0;
1676                 aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1677         }
1678
1679         return 0;
1680 }
1681
1682 static int aty_waitforvblank(struct atyfb_par *par, u32 crtc)
1683 {
1684         struct aty_interrupt *vbl;
1685         unsigned int count;
1686         int ret;
1687
1688         switch (crtc) {
1689         case 0:
1690                 vbl = &par->vblank;
1691                 break;
1692         default:
1693                 return -ENODEV;
1694         }
1695
1696         ret = aty_enable_irq(par, 0);
1697         if (ret)
1698                 return ret;
1699
1700         count = vbl->count;
1701         ret = wait_event_interruptible_timeout(vbl->wait, count != vbl->count, HZ/10);
1702         if (ret < 0) {
1703                 return ret;
1704         }
1705         if (ret == 0) {
1706                 aty_enable_irq(par, 1);
1707                 return -ETIMEDOUT;
1708         }
1709
1710         return 0;
1711 }
1712
1713
1714 #ifdef DEBUG
1715 #define ATYIO_CLKR              0x41545900      /* ATY\00 */
1716 #define ATYIO_CLKW              0x41545901      /* ATY\01 */
1717
1718 struct atyclk {
1719         u32 ref_clk_per;
1720         u8 pll_ref_div;
1721         u8 mclk_fb_div;
1722         u8 mclk_post_div;       /* 1,2,3,4,8 */
1723         u8 mclk_fb_mult;        /* 2 or 4 */
1724         u8 xclk_post_div;       /* 1,2,3,4,8 */
1725         u8 vclk_fb_div;
1726         u8 vclk_post_div;       /* 1,2,3,4,6,8,12 */
1727         u32 dsp_xclks_per_row;  /* 0-16383 */
1728         u32 dsp_loop_latency;   /* 0-15 */
1729         u32 dsp_precision;      /* 0-7 */
1730         u32 dsp_on;             /* 0-2047 */
1731         u32 dsp_off;            /* 0-2047 */
1732 };
1733
1734 #define ATYIO_FEATR             0x41545902      /* ATY\02 */
1735 #define ATYIO_FEATW             0x41545903      /* ATY\03 */
1736 #endif
1737
1738 #ifndef FBIO_WAITFORVSYNC
1739 #define FBIO_WAITFORVSYNC _IOW('F', 0x20, __u32)
1740 #endif
1741
1742 static int atyfb_ioctl(struct inode *inode, struct file *file, u_int cmd,
1743         u_long arg, struct fb_info *info)
1744 {
1745         struct atyfb_par *par = (struct atyfb_par *) info->par;
1746 #ifdef __sparc__
1747         struct fbtype fbtyp;
1748 #endif
1749
1750         switch (cmd) {
1751 #ifdef __sparc__
1752         case FBIOGTYPE:
1753                 fbtyp.fb_type = FBTYPE_PCI_GENERIC;
1754                 fbtyp.fb_width = par->crtc.vxres;
1755                 fbtyp.fb_height = par->crtc.vyres;
1756                 fbtyp.fb_depth = info->var.bits_per_pixel;
1757                 fbtyp.fb_cmsize = info->cmap.len;
1758                 fbtyp.fb_size = info->fix.smem_len;
1759                 if (copy_to_user((struct fbtype __user *) arg, &fbtyp, sizeof(fbtyp)))
1760                         return -EFAULT;
1761                 break;
1762 #endif /* __sparc__ */
1763
1764         case FBIO_WAITFORVSYNC:
1765                 {
1766                         u32 crtc;
1767
1768                         if (get_user(crtc, (__u32 __user *) arg))
1769                                 return -EFAULT;
1770
1771                         return aty_waitforvblank(par, crtc);
1772                 }
1773                 break;
1774
1775 #if defined(DEBUG) && defined(CONFIG_FB_ATY_CT)
1776         case ATYIO_CLKR:
1777                 if (M64_HAS(INTEGRATED)) {
1778                         struct atyclk clk;
1779                         union aty_pll *pll = &(par->pll);
1780                         u32 dsp_config = pll->ct.dsp_config;
1781                         u32 dsp_on_off = pll->ct.dsp_on_off;
1782                         clk.ref_clk_per = par->ref_clk_per;
1783                         clk.pll_ref_div = pll->ct.pll_ref_div;
1784                         clk.mclk_fb_div = pll->ct.mclk_fb_div;
1785                         clk.mclk_post_div = pll->ct.mclk_post_div_real;
1786                         clk.mclk_fb_mult = pll->ct.mclk_fb_mult;
1787                         clk.xclk_post_div = pll->ct.xclk_post_div_real;
1788                         clk.vclk_fb_div = pll->ct.vclk_fb_div;
1789                         clk.vclk_post_div = pll->ct.vclk_post_div_real;
1790                         clk.dsp_xclks_per_row = dsp_config & 0x3fff;
1791                         clk.dsp_loop_latency = (dsp_config >> 16) & 0xf;
1792                         clk.dsp_precision = (dsp_config >> 20) & 7;
1793                         clk.dsp_off = dsp_on_off & 0x7ff;
1794                         clk.dsp_on = (dsp_on_off >> 16) & 0x7ff;
1795                         if (copy_to_user((struct atyclk __user *) arg, &clk,
1796                                          sizeof(clk)))
1797                                 return -EFAULT;
1798                 } else
1799                         return -EINVAL;
1800                 break;
1801         case ATYIO_CLKW:
1802                 if (M64_HAS(INTEGRATED)) {
1803                         struct atyclk clk;
1804                         union aty_pll *pll = &(par->pll);
1805                         if (copy_from_user(&clk, (struct atyclk __user *) arg, sizeof(clk)))
1806                                 return -EFAULT;
1807                         par->ref_clk_per = clk.ref_clk_per;
1808                         pll->ct.pll_ref_div = clk.pll_ref_div;
1809                         pll->ct.mclk_fb_div = clk.mclk_fb_div;
1810                         pll->ct.mclk_post_div_real = clk.mclk_post_div;
1811                         pll->ct.mclk_fb_mult = clk.mclk_fb_mult;
1812                         pll->ct.xclk_post_div_real = clk.xclk_post_div;
1813                         pll->ct.vclk_fb_div = clk.vclk_fb_div;
1814                         pll->ct.vclk_post_div_real = clk.vclk_post_div;
1815                         pll->ct.dsp_config = (clk.dsp_xclks_per_row & 0x3fff) |
1816                                 ((clk.dsp_loop_latency & 0xf)<<16)| ((clk.dsp_precision & 7)<<20);
1817                         pll->ct.dsp_on_off = (clk.dsp_off & 0x7ff) | ((clk.dsp_on & 0x7ff)<<16);
1818                         /*aty_calc_pll_ct(info, &pll->ct);*/
1819                         aty_set_pll_ct(info, pll);
1820                 } else
1821                         return -EINVAL;
1822                 break;
1823         case ATYIO_FEATR:
1824                 if (get_user(par->features, (u32 __user *) arg))
1825                         return -EFAULT;
1826                 break;
1827         case ATYIO_FEATW:
1828                 if (put_user(par->features, (u32 __user *) arg))
1829                         return -EFAULT;
1830                 break;
1831 #endif /* DEBUG && CONFIG_FB_ATY_CT */
1832         default:
1833                 return -EINVAL;
1834         }
1835         return 0;
1836 }
1837
1838 static int atyfb_sync(struct fb_info *info)
1839 {
1840         struct atyfb_par *par = (struct atyfb_par *) info->par;
1841
1842         if (par->blitter_may_be_busy)
1843                 wait_for_idle(par);
1844         return 0;
1845 }
1846
1847 #ifdef __sparc__
1848 static int atyfb_mmap(struct fb_info *info, struct file *file, struct vm_area_struct *vma)
1849 {
1850         struct atyfb_par *par = (struct atyfb_par *) info->par;
1851         unsigned int size, page, map_size = 0;
1852         unsigned long map_offset = 0;
1853         unsigned long off;
1854         int i;
1855
1856         if (!par->mmap_map)
1857                 return -ENXIO;
1858
1859         if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT))
1860                 return -EINVAL;
1861
1862         off = vma->vm_pgoff << PAGE_SHIFT;
1863         size = vma->vm_end - vma->vm_start;
1864
1865         /* To stop the swapper from even considering these pages. */
1866         vma->vm_flags |= (VM_IO | VM_RESERVED);
1867
1868         if (((vma->vm_pgoff == 0) && (size == info->fix.smem_len)) ||
1869             ((off == info->fix.smem_len) && (size == PAGE_SIZE)))
1870                 off += 0x8000000000000000UL;
1871
1872         vma->vm_pgoff = off >> PAGE_SHIFT;      /* propagate off changes */
1873
1874         /* Each page, see which map applies */
1875         for (page = 0; page < size;) {
1876                 map_size = 0;
1877                 for (i = 0; par->mmap_map[i].size; i++) {
1878                         unsigned long start = par->mmap_map[i].voff;
1879                         unsigned long end = start + par->mmap_map[i].size;
1880                         unsigned long offset = off + page;
1881
1882                         if (start > offset)
1883                                 continue;
1884                         if (offset >= end)
1885                                 continue;
1886
1887                         map_size = par->mmap_map[i].size - (offset - start);
1888                         map_offset =
1889                             par->mmap_map[i].poff + (offset - start);
1890                         break;
1891                 }
1892                 if (!map_size) {
1893                         page += PAGE_SIZE;
1894                         continue;
1895                 }
1896                 if (page + map_size > size)
1897                         map_size = size - page;
1898
1899                 pgprot_val(vma->vm_page_prot) &=
1900                     ~(par->mmap_map[i].prot_mask);
1901                 pgprot_val(vma->vm_page_prot) |= par->mmap_map[i].prot_flag;
1902
1903                 if (remap_pfn_range(vma, vma->vm_start + page,
1904                         map_offset >> PAGE_SHIFT, map_size, vma->vm_page_prot))
1905                         return -EAGAIN;
1906
1907                 page += map_size;
1908         }
1909
1910         if (!map_size)
1911                 return -EINVAL;
1912
1913         if (!par->mmaped)
1914                 par->mmaped = 1;
1915         return 0;
1916 }
1917
1918 static struct {
1919         u32 yoffset;
1920         u8 r[2][256];
1921         u8 g[2][256];
1922         u8 b[2][256];
1923 } atyfb_save;
1924
1925 static void atyfb_save_palette(struct atyfb_par *par, int enter)
1926 {
1927         int i, tmp;
1928
1929         for (i = 0; i < 256; i++) {
1930                 tmp = aty_ld_8(DAC_CNTL, par) & 0xfc;
1931                 if (M64_HAS(EXTRA_BRIGHT))
1932                         tmp |= 0x2;
1933                 aty_st_8(DAC_CNTL, tmp, par);
1934                 aty_st_8(DAC_MASK, 0xff, par);
1935
1936                 writeb(i, &par->aty_cmap_regs->rindex);
1937                 atyfb_save.r[enter][i] = readb(&par->aty_cmap_regs->lut);
1938                 atyfb_save.g[enter][i] = readb(&par->aty_cmap_regs->lut);
1939                 atyfb_save.b[enter][i] = readb(&par->aty_cmap_regs->lut);
1940                 writeb(i, &par->aty_cmap_regs->windex);
1941                 writeb(atyfb_save.r[1 - enter][i],
1942                        &par->aty_cmap_regs->lut);
1943                 writeb(atyfb_save.g[1 - enter][i],
1944                        &par->aty_cmap_regs->lut);
1945                 writeb(atyfb_save.b[1 - enter][i],
1946                        &par->aty_cmap_regs->lut);
1947         }
1948 }
1949
1950 static void atyfb_palette(int enter)
1951 {
1952         struct atyfb_par *par;
1953         struct fb_info *info;
1954         int i;
1955
1956         for (i = 0; i < FB_MAX; i++) {
1957                 info = registered_fb[i];
1958                 if (info && info->fbops == &atyfb_ops) {
1959                         par = (struct atyfb_par *) info->par;
1960
1961                         atyfb_save_palette(par, enter);
1962                         if (enter) {
1963                                 atyfb_save.yoffset = info->var.yoffset;
1964                                 info->var.yoffset = 0;
1965                                 set_off_pitch(par, info);
1966                         } else {
1967                                 info->var.yoffset = atyfb_save.yoffset;
1968                                 set_off_pitch(par, info);
1969                         }
1970                         aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1971                         break;
1972                 }
1973         }
1974 }
1975 #endif /* __sparc__ */
1976
1977
1978
1979 #if defined(CONFIG_PM) && defined(CONFIG_PCI)
1980
1981 /* Power management routines. Those are used for PowerBook sleep.
1982  */
1983 static int aty_power_mgmt(int sleep, struct atyfb_par *par)
1984 {
1985         u32 pm;
1986         int timeout;
1987
1988         pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1989         pm = (pm & ~PWR_MGT_MODE_MASK) | PWR_MGT_MODE_REG;
1990         aty_st_lcd(POWER_MANAGEMENT, pm, par);
1991         pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1992
1993         timeout = 2000;
1994         if (sleep) {
1995                 /* Sleep */
1996                 pm &= ~PWR_MGT_ON;
1997                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
1998                 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1999                 udelay(10);
2000                 pm &= ~(PWR_BLON | AUTO_PWR_UP);
2001                 pm |= SUSPEND_NOW;
2002                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2003                 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2004                 udelay(10);
2005                 pm |= PWR_MGT_ON;
2006                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2007                 do {
2008                         pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2009                         mdelay(1);
2010                         if ((--timeout) == 0)
2011                                 break;
2012                 } while ((pm & PWR_MGT_STATUS_MASK) != PWR_MGT_STATUS_SUSPEND);
2013         } else {
2014                 /* Wakeup */
2015                 pm &= ~PWR_MGT_ON;
2016                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2017                 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2018                 udelay(10);
2019                 pm &= ~SUSPEND_NOW;
2020                 pm |= (PWR_BLON | AUTO_PWR_UP);
2021                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2022                 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2023                 udelay(10);
2024                 pm |= PWR_MGT_ON;
2025                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2026                 do {
2027                         pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2028                         mdelay(1);
2029                         if ((--timeout) == 0)
2030                                 break;
2031                 } while ((pm & PWR_MGT_STATUS_MASK) != 0);
2032         }
2033         mdelay(500);
2034
2035         return timeout ? 0 : -EIO;
2036 }
2037
2038 static int atyfb_pci_suspend(struct pci_dev *pdev, pm_message_t state)
2039 {
2040         struct fb_info *info = pci_get_drvdata(pdev);
2041         struct atyfb_par *par = (struct atyfb_par *) info->par;
2042
2043 #ifndef CONFIG_PPC_PMAC
2044         /* HACK ALERT ! Once I find a proper way to say to each driver
2045          * individually what will happen with it's PCI slot, I'll change
2046          * that. On laptops, the AGP slot is just unclocked, so D2 is
2047          * expected, while on desktops, the card is powered off
2048          */
2049         return 0;
2050 #endif /* CONFIG_PPC_PMAC */
2051
2052         if (state.event == pdev->dev.power.power_state.event)
2053                 return 0;
2054
2055         acquire_console_sem();
2056
2057         fb_set_suspend(info, 1);
2058
2059         /* Idle & reset engine */
2060         wait_for_idle(par);
2061         aty_reset_engine(par);
2062
2063         /* Blank display and LCD */
2064         atyfb_blank(FB_BLANK_POWERDOWN, info);
2065
2066         par->asleep = 1;
2067         par->lock_blank = 1;
2068
2069         /* Set chip to "suspend" mode */
2070         if (aty_power_mgmt(1, par)) {
2071                 par->asleep = 0;
2072                 par->lock_blank = 0;
2073                 atyfb_blank(FB_BLANK_UNBLANK, info);
2074                 fb_set_suspend(info, 0);
2075                 release_console_sem();
2076                 return -EIO;
2077         }
2078
2079         release_console_sem();
2080
2081         pdev->dev.power.power_state = state;
2082
2083         return 0;
2084 }
2085
2086 static int atyfb_pci_resume(struct pci_dev *pdev)
2087 {
2088         struct fb_info *info = pci_get_drvdata(pdev);
2089         struct atyfb_par *par = (struct atyfb_par *) info->par;
2090
2091         if (pdev->dev.power.power_state.event == PM_EVENT_ON)
2092                 return 0;
2093
2094         acquire_console_sem();
2095
2096         if (pdev->dev.power.power_state.event == 2)
2097                 aty_power_mgmt(0, par);
2098         par->asleep = 0;
2099
2100         /* Restore display */
2101         atyfb_set_par(info);
2102
2103         /* Refresh */
2104         fb_set_suspend(info, 0);
2105
2106         /* Unblank */
2107         par->lock_blank = 0;
2108         atyfb_blank(FB_BLANK_UNBLANK, info);
2109
2110         release_console_sem();
2111
2112         pdev->dev.power.power_state = PMSG_ON;
2113
2114         return 0;
2115 }
2116
2117 #endif /*  defined(CONFIG_PM) && defined(CONFIG_PCI) */
2118
2119 #ifdef CONFIG_PMAC_BACKLIGHT
2120
2121     /*
2122      *   LCD backlight control
2123      */
2124
2125 static int backlight_conv[] = {
2126         0x00, 0x3f, 0x4c, 0x59, 0x66, 0x73, 0x80, 0x8d,
2127         0x9a, 0xa7, 0xb4, 0xc1, 0xcf, 0xdc, 0xe9, 0xff
2128 };
2129
2130 static int aty_set_backlight_enable(int on, int level, void *data)
2131 {
2132         struct fb_info *info = (struct fb_info *) data;
2133         struct atyfb_par *par = (struct atyfb_par *) info->par;
2134         unsigned int reg = aty_ld_lcd(LCD_MISC_CNTL, par);
2135
2136         reg |= (BLMOD_EN | BIASMOD_EN);
2137         if (on && level > BACKLIGHT_OFF) {
2138                 reg &= ~BIAS_MOD_LEVEL_MASK;
2139                 reg |= (backlight_conv[level] << BIAS_MOD_LEVEL_SHIFT);
2140         } else {
2141                 reg &= ~BIAS_MOD_LEVEL_MASK;
2142                 reg |= (backlight_conv[0] << BIAS_MOD_LEVEL_SHIFT);
2143         }
2144         aty_st_lcd(LCD_MISC_CNTL, reg, par);
2145         return 0;
2146 }
2147
2148 static int aty_set_backlight_level(int level, void *data)
2149 {
2150         return aty_set_backlight_enable(1, level, data);
2151 }
2152
2153 static struct backlight_controller aty_backlight_controller = {
2154         aty_set_backlight_enable,
2155         aty_set_backlight_level
2156 };
2157 #endif /* CONFIG_PMAC_BACKLIGHT */
2158
2159 static void __init aty_calc_mem_refresh(struct atyfb_par *par, int xclk)
2160 {
2161         const int ragepro_tbl[] = {
2162                 44, 50, 55, 66, 75, 80, 100
2163         };
2164         const int ragexl_tbl[] = {
2165                 50, 66, 75, 83, 90, 95, 100, 105,
2166                 110, 115, 120, 125, 133, 143, 166
2167         };
2168         const int *refresh_tbl;
2169         int i, size;
2170
2171         if (IS_XL(par->pci_id) || IS_MOBILITY(par->pci_id)) {
2172                 refresh_tbl = ragexl_tbl;
2173                 size = sizeof(ragexl_tbl)/sizeof(int);
2174         } else {
2175                 refresh_tbl = ragepro_tbl;
2176                 size = sizeof(ragepro_tbl)/sizeof(int);
2177         }
2178
2179         for (i=0; i < size; i++) {
2180                 if (xclk < refresh_tbl[i])
2181                 break;
2182         }
2183         par->mem_refresh_rate = i;
2184 }
2185
2186     /*
2187      *  Initialisation
2188      */
2189
2190 static struct fb_info *fb_list = NULL;
2191
2192 #if defined(__i386__) && defined(CONFIG_FB_ATY_GENERIC_LCD)
2193 static int __devinit atyfb_get_timings_from_lcd(struct atyfb_par *par,
2194                                                 struct fb_var_screeninfo *var)
2195 {
2196         int ret = -EINVAL;
2197
2198         if (par->lcd_table != 0 && (aty_ld_lcd(LCD_GEN_CNTL, par) & LCD_ON)) {
2199                 *var = default_var;
2200                 var->xres = var->xres_virtual = par->lcd_hdisp;
2201                 var->right_margin = par->lcd_right_margin;
2202                 var->left_margin = par->lcd_hblank_len -
2203                         (par->lcd_right_margin + par->lcd_hsync_dly +
2204                          par->lcd_hsync_len);
2205                 var->hsync_len = par->lcd_hsync_len + par->lcd_hsync_dly;
2206                 var->yres = var->yres_virtual = par->lcd_vdisp;
2207                 var->lower_margin = par->lcd_lower_margin;
2208                 var->upper_margin = par->lcd_vblank_len -
2209                         (par->lcd_lower_margin + par->lcd_vsync_len);
2210                 var->vsync_len = par->lcd_vsync_len;
2211                 var->pixclock = par->lcd_pixclock;
2212                 ret = 0;
2213         }
2214
2215         return ret;
2216 }
2217 #endif /* defined(__i386__) && defined(CONFIG_FB_ATY_GENERIC_LCD) */
2218
2219 static int __init aty_init(struct fb_info *info, const char *name)
2220 {
2221         struct atyfb_par *par = (struct atyfb_par *) info->par;
2222         const char *ramname = NULL, *xtal;
2223         int gtb_memsize, has_var = 0;
2224         struct fb_var_screeninfo var;
2225         u8 pll_ref_div;
2226         u32 i;
2227 #if defined(CONFIG_PPC)
2228         int sense;
2229 #endif
2230
2231         init_waitqueue_head(&par->vblank.wait);
2232         spin_lock_init(&par->int_lock);
2233
2234         par->aty_cmap_regs =
2235             (struct aty_cmap_regs __iomem *) (par->ati_regbase + 0xc0);
2236
2237 #ifdef CONFIG_PPC_PMAC
2238         /* The Apple iBook1 uses non-standard memory frequencies. We detect it
2239          * and set the frequency manually. */
2240         if (machine_is_compatible("PowerBook2,1")) {
2241                 par->pll_limits.mclk = 70;
2242                 par->pll_limits.xclk = 53;
2243         }
2244 #endif
2245         if (pll)
2246                 par->pll_limits.pll_max = pll;
2247         if (mclk)
2248                 par->pll_limits.mclk = mclk;
2249         if (xclk)
2250                 par->pll_limits.xclk = xclk;
2251
2252         aty_calc_mem_refresh(par, par->pll_limits.xclk);
2253         par->pll_per = 1000000/par->pll_limits.pll_max;
2254         par->mclk_per = 1000000/par->pll_limits.mclk;
2255         par->xclk_per = 1000000/par->pll_limits.xclk;
2256
2257         par->ref_clk_per = 1000000000000ULL / 14318180;
2258         xtal = "14.31818";
2259
2260 #ifdef CONFIG_FB_ATY_GX
2261         if (!M64_HAS(INTEGRATED)) {
2262                 u32 stat0;
2263                 u8 dac_type, dac_subtype, clk_type;
2264                 stat0 = aty_ld_le32(CONFIG_STAT0, par);
2265                 par->bus_type = (stat0 >> 0) & 0x07;
2266                 par->ram_type = (stat0 >> 3) & 0x07;
2267                 ramname = aty_gx_ram[par->ram_type];
2268                 /* FIXME: clockchip/RAMDAC probing? */
2269                 dac_type = (aty_ld_le32(DAC_CNTL, par) >> 16) & 0x07;
2270 #ifdef CONFIG_ATARI
2271                 clk_type = CLK_ATI18818_1;
2272                 dac_type = (stat0 >> 9) & 0x07;
2273                 if (dac_type == 0x07)
2274                         dac_subtype = DAC_ATT20C408;
2275                 else
2276                         dac_subtype = (aty_ld_8(SCRATCH_REG1 + 1, par) & 0xF0) | dac_type;
2277 #else
2278                 dac_type = DAC_IBMRGB514;
2279                 dac_subtype = DAC_IBMRGB514;
2280                 clk_type = CLK_IBMRGB514;
2281 #endif
2282                 switch (dac_subtype) {
2283                 case DAC_IBMRGB514:
2284                         par->dac_ops = &aty_dac_ibm514;
2285                         break;
2286                 case DAC_ATI68860_B:
2287                 case DAC_ATI68860_C:
2288                         par->dac_ops = &aty_dac_ati68860b;
2289                         break;
2290                 case DAC_ATT20C408:
2291                 case DAC_ATT21C498:
2292                         par->dac_ops = &aty_dac_att21c498;
2293                         break;
2294                 default:
2295                         PRINTKI("aty_init: DAC type not implemented yet!\n");
2296                         par->dac_ops = &aty_dac_unsupported;
2297                         break;
2298                 }
2299                 switch (clk_type) {
2300                 case CLK_ATI18818_1:
2301                         par->pll_ops = &aty_pll_ati18818_1;
2302                         break;
2303                 case CLK_STG1703:
2304                         par->pll_ops = &aty_pll_stg1703;
2305                         break;
2306                 case CLK_CH8398:
2307                         par->pll_ops = &aty_pll_ch8398;
2308                         break;
2309                 case CLK_ATT20C408:
2310                         par->pll_ops = &aty_pll_att20c408;
2311                         break;
2312                 case CLK_IBMRGB514:
2313                         par->pll_ops = &aty_pll_ibm514;
2314                         break;
2315                 default:
2316                         PRINTKI("aty_init: CLK type not implemented yet!");
2317                         par->pll_ops = &aty_pll_unsupported;
2318                         break;
2319                 }
2320         }
2321 #endif /* CONFIG_FB_ATY_GX */
2322 #ifdef CONFIG_FB_ATY_CT
2323         if (M64_HAS(INTEGRATED)) {
2324                 par->dac_ops = &aty_dac_ct;
2325                 par->pll_ops = &aty_pll_ct;
2326                 par->bus_type = PCI;
2327                 par->ram_type = (aty_ld_le32(CONFIG_STAT0, par) & 0x07);
2328                 ramname = aty_ct_ram[par->ram_type];
2329                 /* for many chips, the mclk is 67 MHz for SDRAM, 63 MHz otherwise */
2330                 if (par->pll_limits.mclk == 67 && par->ram_type < SDRAM)
2331                         par->pll_limits.mclk = 63;
2332         }
2333
2334         if (M64_HAS(GTB_DSP)
2335             && (pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par))) {
2336                 int diff1, diff2;
2337                 diff1 = 510 * 14 / pll_ref_div - par->pll_limits.pll_max;
2338                 diff2 = 510 * 29 / pll_ref_div - par->pll_limits.pll_max;
2339                 if (diff1 < 0)
2340                         diff1 = -diff1;
2341                 if (diff2 < 0)
2342                         diff2 = -diff2;
2343                 if (diff2 < diff1) {
2344                         par->ref_clk_per = 1000000000000ULL / 29498928;
2345                         xtal = "29.498928";
2346                 }
2347         }
2348 #endif /* CONFIG_FB_ATY_CT */
2349
2350         /* save previous video mode */
2351         aty_get_crtc(par, &saved_crtc);
2352         if(par->pll_ops->get_pll)
2353                 par->pll_ops->get_pll(info, &saved_pll);
2354
2355         i = aty_ld_le32(MEM_CNTL, par);
2356         gtb_memsize = M64_HAS(GTB_DSP);
2357         if (gtb_memsize)
2358                 switch (i & 0xF) {      /* 0xF used instead of MEM_SIZE_ALIAS */
2359                 case MEM_SIZE_512K:
2360                         info->fix.smem_len = 0x80000;
2361                         break;
2362                 case MEM_SIZE_1M:
2363                         info->fix.smem_len = 0x100000;
2364                         break;
2365                 case MEM_SIZE_2M_GTB:
2366                         info->fix.smem_len = 0x200000;
2367                         break;
2368                 case MEM_SIZE_4M_GTB:
2369                         info->fix.smem_len = 0x400000;
2370                         break;
2371                 case MEM_SIZE_6M_GTB:
2372                         info->fix.smem_len = 0x600000;
2373                         break;
2374                 case MEM_SIZE_8M_GTB:
2375                         info->fix.smem_len = 0x800000;
2376                         break;
2377                 default:
2378                         info->fix.smem_len = 0x80000;
2379         } else
2380                 switch (i & MEM_SIZE_ALIAS) {
2381                 case MEM_SIZE_512K:
2382                         info->fix.smem_len = 0x80000;
2383                         break;
2384                 case MEM_SIZE_1M:
2385                         info->fix.smem_len = 0x100000;
2386                         break;
2387                 case MEM_SIZE_2M:
2388                         info->fix.smem_len = 0x200000;
2389                         break;
2390                 case MEM_SIZE_4M:
2391                         info->fix.smem_len = 0x400000;
2392                         break;
2393                 case MEM_SIZE_6M:
2394                         info->fix.smem_len = 0x600000;
2395                         break;
2396                 case MEM_SIZE_8M:
2397                         info->fix.smem_len = 0x800000;
2398                         break;
2399                 default:
2400                         info->fix.smem_len = 0x80000;
2401                 }
2402
2403         if (M64_HAS(MAGIC_VRAM_SIZE)) {
2404                 if (aty_ld_le32(CONFIG_STAT1, par) & 0x40000000)
2405                         info->fix.smem_len += 0x400000;
2406         }
2407
2408         if (vram) {
2409                 info->fix.smem_len = vram * 1024;
2410                 i = i & ~(gtb_memsize ? 0xF : MEM_SIZE_ALIAS);
2411                 if (info->fix.smem_len <= 0x80000)
2412                         i |= MEM_SIZE_512K;
2413                 else if (info->fix.smem_len <= 0x100000)
2414                         i |= MEM_SIZE_1M;
2415                 else if (info->fix.smem_len <= 0x200000)
2416                         i |= gtb_memsize ? MEM_SIZE_2M_GTB : MEM_SIZE_2M;
2417                 else if (info->fix.smem_len <= 0x400000)
2418                         i |= gtb_memsize ? MEM_SIZE_4M_GTB : MEM_SIZE_4M;
2419                 else if (info->fix.smem_len <= 0x600000)
2420                         i |= gtb_memsize ? MEM_SIZE_6M_GTB : MEM_SIZE_6M;
2421                 else
2422                         i |= gtb_memsize ? MEM_SIZE_8M_GTB : MEM_SIZE_8M;
2423                 aty_st_le32(MEM_CNTL, i, par);
2424         }
2425
2426         /*
2427          *  Reg Block 0 (CT-compatible block) is at mmio_start
2428          *  Reg Block 1 (multimedia extensions) is at mmio_start - 0x400
2429          */
2430         if (M64_HAS(GX)) {
2431                 info->fix.mmio_len = 0x400;
2432                 info->fix.accel = FB_ACCEL_ATI_MACH64GX;
2433         } else if (M64_HAS(CT)) {
2434                 info->fix.mmio_len = 0x400;
2435                 info->fix.accel = FB_ACCEL_ATI_MACH64CT;
2436         } else if (M64_HAS(VT)) {
2437                 info->fix.mmio_start -= 0x400;
2438                 info->fix.mmio_len = 0x800;
2439                 info->fix.accel = FB_ACCEL_ATI_MACH64VT;
2440         } else {/* GT */
2441                 info->fix.mmio_start -= 0x400;
2442                 info->fix.mmio_len = 0x800;
2443                 info->fix.accel = FB_ACCEL_ATI_MACH64GT;
2444         }
2445
2446         PRINTKI("%d%c %s, %s MHz XTAL, %d MHz PLL, %d Mhz MCLK, %d MHz XCLK\n",
2447                info->fix.smem_len == 0x80000 ? 512 : (info->fix.smem_len >> 20),
2448                info->fix.smem_len == 0x80000 ? 'K' : 'M', ramname, xtal, par->pll_limits.pll_max,
2449                par->pll_limits.mclk, par->pll_limits.xclk);
2450
2451 #if defined(DEBUG) && defined(CONFIG_ATY_CT)
2452         if (M64_HAS(INTEGRATED)) {
2453                 int i;
2454                 printk("debug atyfb: BUS_CNTL DAC_CNTL MEM_CNTL EXT_MEM_CNTL CRTC_GEN_CNTL "
2455                        "DSP_CONFIG DSP_ON_OFF CLOCK_CNTL\n"
2456                        "debug atyfb: %08x %08x %08x %08x     %08x      %08x   %08x   %08x\n"
2457                        "debug atyfb: PLL",
2458                         aty_ld_le32(BUS_CNTL, par), aty_ld_le32(DAC_CNTL, par),
2459                         aty_ld_le32(MEM_CNTL, par), aty_ld_le32(EXT_MEM_CNTL, par),
2460                         aty_ld_le32(CRTC_GEN_CNTL, par), aty_ld_le32(DSP_CONFIG, par),
2461                         aty_ld_le32(DSP_ON_OFF, par), aty_ld_le32(CLOCK_CNTL, par));
2462                 for (i = 0; i < 40; i++)
2463                         printk(" %02x", aty_ld_pll_ct(i, par));
2464                 printk("\n");
2465         }
2466 #endif
2467         if(par->pll_ops->init_pll)
2468                 par->pll_ops->init_pll(info, &par->pll);
2469
2470         /*
2471          *  Last page of 8 MB (4 MB on ISA) aperture is MMIO
2472          *  FIXME: we should use the auxiliary aperture instead so we can access
2473          *  the full 8 MB of video RAM on 8 MB boards
2474          */
2475
2476         if (!par->aux_start &&
2477                 (info->fix.smem_len == 0x800000 || (par->bus_type == ISA && info->fix.smem_len == 0x400000)))
2478                 info->fix.smem_len -= GUI_RESERVE;
2479
2480         /*
2481          *  Disable register access through the linear aperture
2482          *  if the auxiliary aperture is used so we can access
2483          *  the full 8 MB of video RAM on 8 MB boards.
2484          */
2485         if (par->aux_start)
2486                 aty_st_le32(BUS_CNTL, aty_ld_le32(BUS_CNTL, par) | BUS_APER_REG_DIS, par);
2487
2488 #ifdef CONFIG_MTRR
2489         par->mtrr_aper = -1;
2490         par->mtrr_reg = -1;
2491         if (!nomtrr) {
2492                 /* Cover the whole resource. */
2493                  par->mtrr_aper = mtrr_add(par->res_start, par->res_size, MTRR_TYPE_WRCOMB, 1);
2494                  if (par->mtrr_aper >= 0 && !par->aux_start) {
2495                         /* Make a hole for mmio. */
2496                         par->mtrr_reg = mtrr_add(par->res_start + 0x800000 - GUI_RESERVE,
2497                                 GUI_RESERVE, MTRR_TYPE_UNCACHABLE, 1);
2498                         if (par->mtrr_reg < 0) {
2499                                 mtrr_del(par->mtrr_aper, 0, 0);
2500                                 par->mtrr_aper = -1;
2501                         }
2502                  }
2503         }
2504 #endif
2505
2506         info->fbops = &atyfb_ops;
2507         info->pseudo_palette = pseudo_palette;
2508         info->flags = FBINFO_FLAG_DEFAULT;
2509
2510 #ifdef CONFIG_PMAC_BACKLIGHT
2511         if (M64_HAS(G3_PB_1_1) && machine_is_compatible("PowerBook1,1")) {
2512                 /* these bits let the 101 powerbook wake up from sleep -- paulus */
2513                 aty_st_lcd(POWER_MANAGEMENT, aty_ld_lcd(POWER_MANAGEMENT, par)
2514                            | (USE_F32KHZ | TRISTATE_MEM_EN), par);
2515         } else if (M64_HAS(MOBIL_BUS))
2516                 register_backlight_controller(&aty_backlight_controller, info, "ati");
2517 #endif /* CONFIG_PMAC_BACKLIGHT */
2518
2519         memset(&var, 0, sizeof(var));
2520 #ifdef CONFIG_PPC
2521         if (_machine == _MACH_Pmac) {
2522                 /*
2523                  *  FIXME: The NVRAM stuff should be put in a Mac-specific file, as it
2524                  *         applies to all Mac video cards
2525                  */
2526                 if (mode) {
2527                         if (mac_find_mode(&var, info, mode, 8))
2528                                 has_var = 1;
2529                 } else {
2530                         if (default_vmode == VMODE_CHOOSE) {
2531                                 if (M64_HAS(G3_PB_1024x768))
2532                                         /* G3 PowerBook with 1024x768 LCD */
2533                                         default_vmode = VMODE_1024_768_60;
2534                                 else if (machine_is_compatible("iMac"))
2535                                         default_vmode = VMODE_1024_768_75;
2536                                 else if (machine_is_compatible
2537                                          ("PowerBook2,1"))
2538                                         /* iBook with 800x600 LCD */
2539                                         default_vmode = VMODE_800_600_60;
2540                                 else
2541                                         default_vmode = VMODE_640_480_67;
2542                                 sense = read_aty_sense(par);
2543                                 PRINTKI("monitor sense=%x, mode %d\n",
2544                                         sense,  mac_map_monitor_sense(sense));
2545                         }
2546                         if (default_vmode <= 0 || default_vmode > VMODE_MAX)
2547                                 default_vmode = VMODE_640_480_60;
2548                         if (default_cmode < CMODE_8 || default_cmode > CMODE_32)
2549                                 default_cmode = CMODE_8;
2550                         if (!mac_vmode_to_var(default_vmode, default_cmode,
2551                                                &var))
2552                                 has_var = 1;
2553                 }
2554         }
2555
2556 #endif /* !CONFIG_PPC */
2557
2558 #if defined(__i386__) && defined(CONFIG_FB_ATY_GENERIC_LCD)
2559         if (!atyfb_get_timings_from_lcd(par, &var))
2560                 has_var = 1;
2561 #endif
2562
2563         if (mode && fb_find_mode(&var, info, mode, NULL, 0, &defmode, 8))
2564                 has_var = 1;
2565
2566         if (!has_var)
2567                 var = default_var;
2568
2569         if (noaccel)
2570                 var.accel_flags &= ~FB_ACCELF_TEXT;
2571         else
2572                 var.accel_flags |= FB_ACCELF_TEXT;
2573
2574         if (comp_sync != -1) {
2575                 if (!comp_sync)
2576                         var.sync &= ~FB_SYNC_COMP_HIGH_ACT;
2577                 else
2578                         var.sync |= FB_SYNC_COMP_HIGH_ACT;
2579         }
2580
2581         if (var.yres == var.yres_virtual) {
2582                 u32 videoram = (info->fix.smem_len - (PAGE_SIZE << 2));
2583                 var.yres_virtual = ((videoram * 8) / var.bits_per_pixel) / var.xres_virtual;
2584                 if (var.yres_virtual < var.yres)
2585                         var.yres_virtual = var.yres;
2586         }
2587
2588         if (atyfb_check_var(&var, info)) {
2589                 PRINTKE("can't set default video mode\n");
2590                 goto aty_init_exit;
2591         }
2592
2593 #ifdef __sparc__
2594         atyfb_save_palette(par, 0);
2595 #endif
2596
2597 #ifdef CONFIG_FB_ATY_CT
2598         if (!noaccel && M64_HAS(INTEGRATED))
2599                 aty_init_cursor(info);
2600 #endif /* CONFIG_FB_ATY_CT */
2601         info->var = var;
2602
2603         fb_alloc_cmap(&info->cmap, 256, 0);
2604
2605         if (register_framebuffer(info) < 0)
2606                 goto aty_init_exit;
2607
2608         fb_list = info;
2609
2610         PRINTKI("fb%d: %s frame buffer device on %s\n",
2611                info->node, info->fix.id, name);
2612         return 0;
2613
2614 aty_init_exit:
2615         /* restore video mode */
2616         aty_set_crtc(par, &saved_crtc);
2617         par->pll_ops->set_pll(info, &saved_pll);
2618
2619 #ifdef CONFIG_MTRR
2620         if (par->mtrr_reg >= 0) {
2621             mtrr_del(par->mtrr_reg, 0, 0);
2622             par->mtrr_reg = -1;
2623         }
2624         if (par->mtrr_aper >= 0) {
2625             mtrr_del(par->mtrr_aper, 0, 0);
2626             par->mtrr_aper = -1;
2627         }
2628 #endif
2629         return -1;
2630 }
2631
2632 #ifdef CONFIG_ATARI
2633 static int __init store_video_par(char *video_str, unsigned char m64_num)
2634 {
2635         char *p;
2636         unsigned long vmembase, size, guiregbase;
2637
2638         PRINTKI("store_video_par() '%s' \n", video_str);
2639
2640         if (!(p = strsep(&video_str, ";")) || !*p)
2641                 goto mach64_invalid;
2642         vmembase = simple_strtoul(p, NULL, 0);
2643         if (!(p = strsep(&video_str, ";")) || !*p)
2644                 goto mach64_invalid;
2645         size = simple_strtoul(p, NULL, 0);
2646         if (!(p = strsep(&video_str, ";")) || !*p)
2647                 goto mach64_invalid;
2648         guiregbase = simple_strtoul(p, NULL, 0);
2649
2650         phys_vmembase[m64_num] = vmembase;
2651         phys_size[m64_num] = size;
2652         phys_guiregbase[m64_num] = guiregbase;
2653         PRINTKI("stored them all: $%08lX $%08lX $%08lX \n", vmembase, size,
2654                guiregbase);
2655         return 0;
2656
2657       mach64_invalid:
2658         phys_vmembase[m64_num] = 0;
2659         return -1;
2660 }
2661 #endif /* CONFIG_ATARI */
2662
2663     /*
2664      *  Blank the display.
2665      */
2666
2667 static int atyfb_blank(int blank, struct fb_info *info)
2668 {
2669         struct atyfb_par *par = (struct atyfb_par *) info->par;
2670         u32 gen_cntl;
2671
2672         if (par->lock_blank || par->asleep)
2673                 return 0;
2674
2675 #ifdef CONFIG_PMAC_BACKLIGHT
2676         if ((_machine == _MACH_Pmac) && blank > FB_BLANK_NORMAL)
2677                 set_backlight_enable(0);
2678 #elif defined(CONFIG_FB_ATY_GENERIC_LCD)
2679         if (par->lcd_table && blank > FB_BLANK_NORMAL &&
2680             (aty_ld_lcd(LCD_GEN_CNTL, par) & LCD_ON)) {
2681                 u32 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2682                 pm &= ~PWR_BLON;
2683                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2684         }
2685 #endif
2686
2687         gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
2688         switch (blank) {
2689                 case FB_BLANK_UNBLANK:
2690                         gen_cntl &= ~0x400004c;
2691                         break;
2692                 case FB_BLANK_NORMAL:
2693                         gen_cntl |= 0x4000040;
2694                         break;
2695                 case FB_BLANK_VSYNC_SUSPEND:
2696                         gen_cntl |= 0x4000048;
2697                         break;
2698                 case FB_BLANK_HSYNC_SUSPEND:
2699                         gen_cntl |= 0x4000044;
2700                         break;
2701                 case FB_BLANK_POWERDOWN:
2702                         gen_cntl |= 0x400004c;
2703                         break;
2704         }
2705         aty_st_le32(CRTC_GEN_CNTL, gen_cntl, par);
2706
2707 #ifdef CONFIG_PMAC_BACKLIGHT
2708         if ((_machine == _MACH_Pmac) && blank <= FB_BLANK_NORMAL)
2709                 set_backlight_enable(1);
2710 #elif defined(CONFIG_FB_ATY_GENERIC_LCD)
2711         if (par->lcd_table && blank <= FB_BLANK_NORMAL &&
2712             (aty_ld_lcd(LCD_GEN_CNTL, par) & LCD_ON)) {
2713                 u32 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2714                 pm |= PWR_BLON;
2715                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2716         }
2717 #endif
2718
2719         return 0;
2720 }
2721
2722 static void aty_st_pal(u_int regno, u_int red, u_int green, u_int blue,
2723                        const struct atyfb_par *par)
2724 {
2725 #ifdef CONFIG_ATARI
2726         out_8(&par->aty_cmap_regs->windex, regno);
2727         out_8(&par->aty_cmap_regs->lut, red);
2728         out_8(&par->aty_cmap_regs->lut, green);
2729         out_8(&par->aty_cmap_regs->lut, blue);
2730 #else
2731         writeb(regno, &par->aty_cmap_regs->windex);
2732         writeb(red, &par->aty_cmap_regs->lut);
2733         writeb(green, &par->aty_cmap_regs->lut);
2734         writeb(blue, &par->aty_cmap_regs->lut);
2735 #endif
2736 }
2737
2738     /*
2739      *  Set a single color register. The values supplied are already
2740      *  rounded down to the hardware's capabilities (according to the
2741      *  entries in the var structure). Return != 0 for invalid regno.
2742      *  !! 4 & 8 =  PSEUDO, > 8 = DIRECTCOLOR
2743      */
2744
2745 static int atyfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
2746         u_int transp, struct fb_info *info)
2747 {
2748         struct atyfb_par *par = (struct atyfb_par *) info->par;
2749         int i, depth;
2750         u32 *pal = info->pseudo_palette;
2751
2752         depth = info->var.bits_per_pixel;
2753         if (depth == 16)
2754                 depth = (info->var.green.length == 5) ? 15 : 16;
2755
2756         if (par->asleep)
2757                 return 0;
2758
2759         if (regno > 255 ||
2760             (depth == 16 && regno > 63) ||
2761             (depth == 15 && regno > 31))
2762                 return 1;
2763
2764         red >>= 8;
2765         green >>= 8;
2766         blue >>= 8;
2767
2768         par->palette[regno].red = red;
2769         par->palette[regno].green = green;
2770         par->palette[regno].blue = blue;
2771
2772         if (regno < 16) {
2773                 switch (depth) {
2774                 case 15:
2775                         pal[regno] = (regno << 10) | (regno << 5) | regno;
2776                         break;
2777                 case 16:
2778                         pal[regno] = (regno << 11) | (regno << 5) | regno;
2779                         break;
2780                 case 24:
2781                         pal[regno] = (regno << 16) | (regno << 8) | regno;
2782                         break;
2783                 case 32:
2784                         i = (regno << 8) | regno;
2785                         pal[regno] = (i << 16) | i;
2786                         break;
2787                 }
2788         }
2789
2790         i = aty_ld_8(DAC_CNTL, par) & 0xfc;
2791         if (M64_HAS(EXTRA_BRIGHT))
2792                 i |= 0x2; /* DAC_CNTL | 0x2 turns off the extra brightness for gt */
2793         aty_st_8(DAC_CNTL, i, par);
2794         aty_st_8(DAC_MASK, 0xff, par);
2795
2796         if (M64_HAS(INTEGRATED)) {
2797                 if (depth == 16) {
2798                         if (regno < 32)
2799                                 aty_st_pal(regno << 3, red,
2800                                            par->palette[regno<<1].green,
2801                                            blue, par);
2802                         red = par->palette[regno>>1].red;
2803                         blue = par->palette[regno>>1].blue;
2804                         regno <<= 2;
2805                 } else if (depth == 15) {
2806                         regno <<= 3;
2807                         for(i = 0; i < 8; i++) {
2808                             aty_st_pal(regno + i, red, green, blue, par);
2809                         }
2810                 }
2811         }
2812         aty_st_pal(regno, red, green, blue, par);
2813
2814         return 0;
2815 }
2816
2817 #ifdef CONFIG_PCI
2818
2819 #ifdef __sparc__
2820
2821 extern void (*prom_palette) (int);
2822
2823 static int __devinit atyfb_setup_sparc(struct pci_dev *pdev,
2824                         struct fb_info *info, unsigned long addr)
2825 {
2826         extern int con_is_present(void);
2827
2828         struct atyfb_par *par = info->par;
2829         struct pcidev_cookie *pcp;
2830         char prop[128];
2831         int node, len, i, j, ret;
2832         u32 mem, chip_id;
2833
2834         /* Do not attach when we have a serial console. */
2835         if (!con_is_present())
2836                 return -ENXIO;
2837
2838         /*
2839          * Map memory-mapped registers.
2840          */
2841         par->ati_regbase = (void *)addr + 0x7ffc00UL;
2842         info->fix.mmio_start = addr + 0x7ffc00UL;
2843
2844         /*
2845          * Map in big-endian aperture.
2846          */
2847         info->screen_base = (char *) (addr + 0x800000UL);
2848         info->fix.smem_start = addr + 0x800000UL;
2849
2850         /*
2851          * Figure mmap addresses from PCI config space.
2852          * Split Framebuffer in big- and little-endian halfs.
2853          */
2854         for (i = 0; i < 6 && pdev->resource[i].start; i++)
2855                 /* nothing */ ;
2856         j = i + 4;
2857
2858         par->mmap_map = kmalloc(j * sizeof(*par->mmap_map), GFP_ATOMIC);
2859         if (!par->mmap_map) {
2860                 PRINTKE("atyfb_setup_sparc() can't alloc mmap_map\n");
2861                 return -ENOMEM;
2862         }
2863         memset(par->mmap_map, 0, j * sizeof(*par->mmap_map));
2864
2865         for (i = 0, j = 2; i < 6 && pdev->resource[i].start; i++) {
2866                 struct resource *rp = &pdev->resource[i];
2867                 int io, breg = PCI_BASE_ADDRESS_0 + (i << 2);
2868                 unsigned long base;
2869                 u32 size, pbase;
2870
2871                 base = rp->start;
2872
2873                 io = (rp->flags & IORESOURCE_IO);
2874
2875                 size = rp->end - base + 1;
2876
2877                 pci_read_config_dword(pdev, breg, &pbase);
2878
2879                 if (io)
2880                         size &= ~1;
2881
2882                 /*
2883                  * Map the framebuffer a second time, this time without
2884                  * the braindead _PAGE_IE setting. This is used by the
2885                  * fixed Xserver, but we need to maintain the old mapping
2886                  * to stay compatible with older ones...
2887                  */
2888                 if (base == addr) {
2889                         par->mmap_map[j].voff = (pbase + 0x10000000) & PAGE_MASK;
2890                         par->mmap_map[j].poff = base & PAGE_MASK;
2891                         par->mmap_map[j].size = (size + ~PAGE_MASK) & PAGE_MASK;
2892                         par->mmap_map[j].prot_mask = _PAGE_CACHE;
2893                         par->mmap_map[j].prot_flag = _PAGE_E;
2894                         j++;
2895                 }
2896
2897                 /*
2898                  * Here comes the old framebuffer mapping with _PAGE_IE
2899                  * set for the big endian half of the framebuffer...
2900                  */
2901                 if (base == addr) {
2902                         par->mmap_map[j].voff = (pbase + 0x800000) & PAGE_MASK;
2903                         par->mmap_map[j].poff = (base + 0x800000) & PAGE_MASK;
2904                         par->mmap_map[j].size = 0x800000;
2905                         par->mmap_map[j].prot_mask = _PAGE_CACHE;
2906                         par->mmap_map[j].prot_flag = _PAGE_E | _PAGE_IE;
2907                         size -= 0x800000;
2908                         j++;
2909                 }
2910
2911                 par->mmap_map[j].voff = pbase & PAGE_MASK;
2912                 par->mmap_map[j].poff = base & PAGE_MASK;
2913                 par->mmap_map[j].size = (size + ~PAGE_MASK) & PAGE_MASK;
2914                 par->mmap_map[j].prot_mask = _PAGE_CACHE;
2915                 par->mmap_map[j].prot_flag = _PAGE_E;
2916                 j++;
2917         }
2918
2919         if((ret = correct_chipset(par)))
2920                 return ret;
2921
2922         if (IS_XL(pdev->device)) {
2923                 /*
2924                  * Fix PROMs idea of MEM_CNTL settings...
2925                  */
2926                 mem = aty_ld_le32(MEM_CNTL, par);
2927                 chip_id = aty_ld_le32(CONFIG_CHIP_ID, par);
2928                 if (((chip_id & CFG_CHIP_TYPE) == VT_CHIP_ID) && !((chip_id >> 24) & 1)) {
2929                         switch (mem & 0x0f) {
2930                         case 3:
2931                                 mem = (mem & ~(0x0f)) | 2;
2932                                 break;
2933                         case 7:
2934                                 mem = (mem & ~(0x0f)) | 3;
2935                                 break;
2936                         case 9:
2937                                 mem = (mem & ~(0x0f)) | 4;
2938                                 break;
2939                         case 11:
2940                                 mem = (mem & ~(0x0f)) | 5;
2941                                 break;
2942                         default:
2943                                 break;
2944                         }
2945                         if ((aty_ld_le32(CONFIG_STAT0, par) & 7) >= SDRAM)
2946                                 mem &= ~(0x00700000);
2947                 }
2948                 mem &= ~(0xcf80e000);   /* Turn off all undocumented bits. */
2949                 aty_st_le32(MEM_CNTL, mem, par);
2950         }
2951
2952         /*
2953          * If this is the console device, we will set default video
2954          * settings to what the PROM left us with.
2955          */
2956         node = prom_getchild(prom_root_node);
2957         node = prom_searchsiblings(node, "aliases");
2958         if (node) {
2959                 len = prom_getproperty(node, "screen", prop, sizeof(prop));
2960                 if (len > 0) {
2961                         prop[len] = '\0';
2962                         node = prom_finddevice(prop);
2963                 } else
2964                         node = 0;
2965         }
2966
2967         pcp = pdev->sysdata;
2968         if (node == pcp->prom_node) {
2969                 struct fb_var_screeninfo *var = &default_var;
2970                 unsigned int N, P, Q, M, T, R;
2971                 u32 v_total, h_total;
2972                 struct crtc crtc;
2973                 u8 pll_regs[16];
2974                 u8 clock_cntl;
2975
2976                 crtc.vxres = prom_getintdefault(node, "width", 1024);
2977                 crtc.vyres = prom_getintdefault(node, "height", 768);
2978                 var->bits_per_pixel = prom_getintdefault(node, "depth", 8);
2979                 var->xoffset = var->yoffset = 0;
2980                 crtc.h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
2981                 crtc.h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
2982                 crtc.v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
2983                 crtc.v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
2984                 crtc.gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
2985                 aty_crtc_to_var(&crtc, var);
2986
2987                 h_total = var->xres + var->right_margin + var->hsync_len + var->left_margin;
2988                 v_total = var->yres + var->lower_margin + var->vsync_len + var->upper_margin;
2989
2990                 /*
2991                  * Read the PLL to figure actual Refresh Rate.
2992                  */
2993                 clock_cntl = aty_ld_8(CLOCK_CNTL, par);
2994                 /* DPRINTK("CLOCK_CNTL %02x\n", clock_cntl); */
2995                 for (i = 0; i < 16; i++)
2996                         pll_regs[i] = aty_ld_pll_ct(i, par);
2997
2998                 /*
2999                  * PLL Reference Divider M:
3000                  */
3001                 M = pll_regs[2];
3002
3003                 /*
3004                  * PLL Feedback Divider N (Dependant on CLOCK_CNTL):
3005                  */
3006                 N = pll_regs[7 + (clock_cntl & 3)];
3007
3008                 /*
3009                  * PLL Post Divider P (Dependant on CLOCK_CNTL):
3010                  */
3011                 P = 1 << (pll_regs[6] >> ((clock_cntl & 3) << 1));
3012
3013                 /*
3014                  * PLL Divider Q:
3015                  */
3016                 Q = N / P;
3017
3018                 /*
3019                  * Target Frequency:
3020                  *
3021                  *      T * M
3022                  * Q = -------
3023                  *      2 * R
3024                  *
3025                  * where R is XTALIN (= 14318 or 29498 kHz).
3026                  */
3027                 if (IS_XL(pdev->device))
3028                         R = 29498;
3029                 else
3030                         R = 14318;
3031
3032                 T = 2 * Q * R / M;
3033
3034                 default_var.pixclock = 1000000000 / T;
3035         }
3036
3037         return 0;
3038 }
3039
3040 #else /* __sparc__ */
3041
3042 #ifdef __i386__
3043 #ifdef CONFIG_FB_ATY_GENERIC_LCD
3044 static void aty_init_lcd(struct atyfb_par *par, u32 bios_base)
3045 {
3046         u32 driv_inf_tab, sig;
3047         u16 lcd_ofs;
3048
3049         /* To support an LCD panel, we should know it's dimensions and
3050          *  it's desired pixel clock.
3051          * There are two ways to do it:
3052          *  - Check the startup video mode and calculate the panel
3053          *    size from it. This is unreliable.
3054          *  - Read it from the driver information table in the video BIOS.
3055         */
3056         /* Address of driver information table is at offset 0x78. */
3057         driv_inf_tab = bios_base + *((u16 *)(bios_base+0x78));
3058
3059         /* Check for the driver information table signature. */
3060         sig = (*(u32 *)driv_inf_tab);
3061         if ((sig == 0x54504c24) || /* Rage LT pro */
3062                 (sig == 0x544d5224) || /* Rage mobility */
3063                 (sig == 0x54435824) || /* Rage XC */
3064                 (sig == 0x544c5824)) { /* Rage XL */
3065                 PRINTKI("BIOS contains driver information table.\n");
3066                 lcd_ofs = (*(u16 *)(driv_inf_tab + 10));
3067                 par->lcd_table = 0;
3068                 if (lcd_ofs != 0) {
3069                         par->lcd_table = bios_base + lcd_ofs;
3070                 }
3071         }
3072
3073         if (par->lcd_table != 0) {
3074                 char model[24];
3075                 char strbuf[16];
3076                 char refresh_rates_buf[100];
3077                 int id, tech, f, i, m, default_refresh_rate;
3078                 char *txtcolour;
3079                 char *txtmonitor;
3080                 char *txtdual;
3081                 char *txtformat;
3082                 u16 width, height, panel_type, refresh_rates;
3083                 u16 *lcdmodeptr;
3084                 u32 format;
3085                 u8 lcd_refresh_rates[16] = {50,56,60,67,70,72,75,76,85,90,100,120,140,150,160,200};
3086                 /* The most important information is the panel size at
3087                  * offset 25 and 27, but there's some other nice information
3088                  * which we print to the screen.
3089                  */
3090                 id = *(u8 *)par->lcd_table;
3091                 strncpy(model,(char *)par->lcd_table+1,24);
3092                 model[23]=0;
3093
3094                 width = par->lcd_width = *(u16 *)(par->lcd_table+25);
3095                 height = par->lcd_height = *(u16 *)(par->lcd_table+27);
3096                 panel_type = *(u16 *)(par->lcd_table+29);
3097                 if (panel_type & 1)
3098                         txtcolour = "colour";
3099                 else
3100                         txtcolour = "monochrome";
3101                 if (panel_type & 2)
3102                         txtdual = "dual (split) ";
3103                 else
3104                         txtdual = "";
3105                 tech = (panel_type>>2) & 63;
3106                 switch (tech) {
3107                 case 0:
3108                         txtmonitor = "passive matrix";
3109                         break;
3110                 case 1:
3111                         txtmonitor = "active matrix";
3112                         break;
3113                 case 2:
3114                         txtmonitor = "active addressed STN";
3115                         break;
3116                 case 3:
3117                         txtmonitor = "EL";
3118                         break;
3119                 case 4:
3120                         txtmonitor = "plasma";
3121                         break;
3122                 default:
3123                         txtmonitor = "unknown";
3124                 }
3125                 format = *(u32 *)(par->lcd_table+57);
3126                 if (tech == 0 || tech == 2) {
3127                         switch (format & 7) {
3128                         case 0:
3129                                 txtformat = "12 bit interface";
3130                                 break;
3131                         case 1:
3132                                 txtformat = "16 bit interface";
3133                                 break;
3134                         case 2:
3135                                 txtformat = "24 bit interface";
3136                                 break;
3137                         default:
3138                                 txtformat = "unkown format";
3139                         }
3140                 } else {
3141                         switch (format & 7) {
3142                         case 0:
3143                                 txtformat = "8 colours";
3144                                 break;
3145                         case 1:
3146                                 txtformat = "512 colours";
3147                                 break;
3148                         case 2:
3149                                 txtformat = "4096 colours";
3150                                 break;
3151                         case 4:
3152                                 txtformat = "262144 colours (LT mode)";
3153                                 break;
3154                         case 5:
3155                                 txtformat = "16777216 colours";
3156                                 break;
3157                         case 6:
3158                                 txtformat = "262144 colours (FDPI-2 mode)";
3159                                 break;
3160                         default:
3161                                 txtformat = "unkown format";
3162                         }
3163                 }
3164                 PRINTKI("%s%s %s monitor detected: %s\n",
3165                         txtdual ,txtcolour, txtmonitor, model);
3166                 PRINTKI("       id=%d, %dx%d pixels, %s\n",
3167                         id, width, height, txtformat);
3168                 refresh_rates_buf[0] = 0;
3169                 refresh_rates = *(u16 *)(par->lcd_table+62);
3170                 m = 1;
3171                 f = 0;
3172                 for (i=0;i<16;i++) {
3173                         if (refresh_rates & m) {
3174                                 if (f == 0) {
3175                                         sprintf(strbuf, "%d", lcd_refresh_rates[i]);
3176                                         f++;
3177                                 } else {
3178                                         sprintf(strbuf, ",%d", lcd_refresh_rates[i]);
3179                                 }
3180                                 strcat(refresh_rates_buf,strbuf);
3181                         }
3182                         m = m << 1;
3183                 }
3184                 default_refresh_rate = (*(u8 *)(par->lcd_table+61) & 0xf0) >> 4;
3185                 PRINTKI("       supports refresh rates [%s], default %d Hz\n",
3186                         refresh_rates_buf, lcd_refresh_rates[default_refresh_rate]);
3187                 par->lcd_refreshrate = lcd_refresh_rates[default_refresh_rate];
3188                 /* We now need to determine the crtc parameters for the
3189                  * LCD monitor. This is tricky, because they are not stored
3190                  * individually in the BIOS. Instead, the BIOS contains a
3191                  * table of display modes that work for this monitor.
3192                  *
3193                  * The idea is that we search for a mode of the same dimensions
3194                  * as the dimensions of the LCD monitor. Say our LCD monitor
3195                  * is 800x600 pixels, we search for a 800x600 monitor.
3196                  * The CRTC parameters we find here are the ones that we need
3197                  * to use to simulate other resolutions on the LCD screen.
3198                  */
3199                 lcdmodeptr = (u16 *)(par->lcd_table + 64);
3200                 while (*lcdmodeptr != 0) {
3201                         u32 modeptr;
3202                         u16 mwidth, mheight, lcd_hsync_start, lcd_vsync_start;
3203                         modeptr = bios_base + *lcdmodeptr;
3204
3205                         mwidth = *((u16 *)(modeptr+0));
3206                         mheight = *((u16 *)(modeptr+2));
3207
3208                         if (mwidth == width && mheight == height) {
3209                                 par->lcd_pixclock = 100000000 / *((u16 *)(modeptr+9));
3210                                 par->lcd_htotal = *((u16 *)(modeptr+17)) & 511;
3211                                 par->lcd_hdisp = *((u16 *)(modeptr+19)) & 511;
3212                                 lcd_hsync_start = *((u16 *)(modeptr+21)) & 511;
3213                                 par->lcd_hsync_dly = (*((u16 *)(modeptr+21)) >> 9) & 7;
3214                                 par->lcd_hsync_len = *((u8 *)(modeptr+23)) & 63;
3215
3216                                 par->lcd_vtotal = *((u16 *)(modeptr+24)) & 2047;
3217                                 par->lcd_vdisp = *((u16 *)(modeptr+26)) & 2047;
3218                                 lcd_vsync_start = *((u16 *)(modeptr+28)) & 2047;
3219                                 par->lcd_vsync_len = (*((u16 *)(modeptr+28)) >> 11) & 31;
3220
3221                                 par->lcd_htotal = (par->lcd_htotal + 1) * 8;
3222                                 par->lcd_hdisp = (par->lcd_hdisp + 1) * 8;
3223                                 lcd_hsync_start = (lcd_hsync_start + 1) * 8;
3224                                 par->lcd_hsync_len = par->lcd_hsync_len * 8;
3225
3226                                 par->lcd_vtotal++;
3227                                 par->lcd_vdisp++;
3228                                 lcd_vsync_start++;
3229
3230                                 par->lcd_right_margin = lcd_hsync_start - par->lcd_hdisp;
3231                                 par->lcd_lower_margin = lcd_vsync_start - par->lcd_vdisp;
3232                                 par->lcd_hblank_len = par->lcd_htotal - par->lcd_hdisp;
3233                                 par->lcd_vblank_len = par->lcd_vtotal - par->lcd_vdisp;
3234                                 break;
3235                         }
3236
3237                         lcdmodeptr++;
3238                 }
3239                 if (*lcdmodeptr == 0) {
3240                         PRINTKE("LCD monitor CRTC parameters not found!!!\n");
3241                         /* To do: Switch to CRT if possible. */
3242                 } else {
3243                         PRINTKI("       LCD CRTC parameters: %d.%d  %d %d %d %d  %d %d %d %d\n",
3244                                 1000000 / par->lcd_pixclock, 1000000 % par->lcd_pixclock,
3245                                 par->lcd_hdisp,
3246                                 par->lcd_hdisp + par->lcd_right_margin,
3247                                 par->lcd_hdisp + par->lcd_right_margin
3248                                         + par->lcd_hsync_dly + par->lcd_hsync_len,
3249                                 par->lcd_htotal,
3250                                 par->lcd_vdisp,
3251                                 par->lcd_vdisp + par->lcd_lower_margin,
3252                                 par->lcd_vdisp + par->lcd_lower_margin + par->lcd_vsync_len,
3253                                 par->lcd_vtotal);
3254                         PRINTKI("                          : %d %d %d %d %d %d %d %d %d\n",
3255                                 par->lcd_pixclock,
3256                                 par->lcd_hblank_len - (par->lcd_right_margin +
3257                                         par->lcd_hsync_dly + par->lcd_hsync_len),
3258                                 par->lcd_hdisp,
3259                                 par->lcd_right_margin,
3260                                 par->lcd_hsync_len,
3261                                 par->lcd_vblank_len - (par->lcd_lower_margin + par->lcd_vsync_len),
3262                                 par->lcd_vdisp,
3263                                 par->lcd_lower_margin,
3264                                 par->lcd_vsync_len);
3265                 }
3266         }
3267 }
3268 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
3269
3270 static int __devinit init_from_bios(struct atyfb_par *par)
3271 {
3272         u32 bios_base, rom_addr;
3273         int ret;
3274
3275         rom_addr = 0xc0000 + ((aty_ld_le32(SCRATCH_REG1, par) & 0x7f) << 11);
3276         bios_base = (unsigned long)ioremap(rom_addr, 0x10000);
3277
3278         /* The BIOS starts with 0xaa55. */
3279         if (*((u16 *)bios_base) == 0xaa55) {
3280
3281                 u8 *bios_ptr;
3282                 u16 rom_table_offset, freq_table_offset;
3283                 PLL_BLOCK_MACH64 pll_block;
3284
3285                 PRINTKI("Mach64 BIOS is located at %x, mapped at %x.\n", rom_addr, bios_base);
3286
3287                 /* check for frequncy table */
3288                 bios_ptr = (u8*)bios_base;
3289                 rom_table_offset = (u16)(bios_ptr[0x48] | (bios_ptr[0x49] << 8));
3290                 freq_table_offset = bios_ptr[rom_table_offset + 16] | (bios_ptr[rom_table_offset + 17] << 8);
3291                 memcpy(&pll_block, bios_ptr + freq_table_offset, sizeof(PLL_BLOCK_MACH64));
3292
3293                 PRINTKI("BIOS frequency table:\n");
3294                 PRINTKI("PCLK_min_freq %d, PCLK_max_freq %d, ref_freq %d, ref_divider %d\n",
3295                         pll_block.PCLK_min_freq, pll_block.PCLK_max_freq,
3296                         pll_block.ref_freq, pll_block.ref_divider);
3297                 PRINTKI("MCLK_pwd %d, MCLK_max_freq %d, XCLK_max_freq %d, SCLK_freq %d\n",
3298                         pll_block.MCLK_pwd, pll_block.MCLK_max_freq,
3299                         pll_block.XCLK_max_freq, pll_block.SCLK_freq);
3300
3301                 par->pll_limits.pll_min = pll_block.PCLK_min_freq/100;
3302                 par->pll_limits.pll_max = pll_block.PCLK_max_freq/100;
3303                 par->pll_limits.ref_clk = pll_block.ref_freq/100;
3304                 par->pll_limits.ref_div = pll_block.ref_divider;
3305                 par->pll_limits.sclk = pll_block.SCLK_freq/100;
3306                 par->pll_limits.mclk = pll_block.MCLK_max_freq/100;
3307                 par->pll_limits.mclk_pm = pll_block.MCLK_pwd/100;
3308                 par->pll_limits.xclk = pll_block.XCLK_max_freq/100;
3309 #ifdef CONFIG_FB_ATY_GENERIC_LCD
3310                 aty_init_lcd(par, bios_base);
3311 #endif
3312                 ret = 0;
3313         } else {
3314                 PRINTKE("no BIOS frequency table found, use parameters\n");
3315                 ret = -ENXIO;
3316         }
3317         iounmap((void* __iomem )bios_base);
3318
3319         return ret;
3320 }
3321 #endif /* __i386__ */
3322
3323 static int __devinit atyfb_setup_generic(struct pci_dev *pdev, struct fb_info *info, unsigned long addr)
3324 {
3325         struct atyfb_par *par = info->par;
3326         u16 tmp;
3327         unsigned long raddr;
3328         struct resource *rrp;
3329         int ret = 0;
3330
3331         raddr = addr + 0x7ff000UL;
3332         rrp = &pdev->resource[2];
3333         if ((rrp->flags & IORESOURCE_MEM) && request_mem_region(rrp->start, rrp->end - rrp->start + 1, "atyfb")) {
3334                 par->aux_start = rrp->start;
3335                 par->aux_size = rrp->end - rrp->start + 1;
3336                 raddr = rrp->start;
3337                 PRINTKI("using auxiliary register aperture\n");
3338         }
3339
3340         info->fix.mmio_start = raddr;
3341         par->ati_regbase = ioremap(info->fix.mmio_start, 0x1000);
3342         if (par->ati_regbase == 0)
3343                 return -ENOMEM;
3344
3345         info->fix.mmio_start += par->aux_start ? 0x400 : 0xc00;
3346         par->ati_regbase += par->aux_start ? 0x400 : 0xc00;
3347
3348         /*
3349          * Enable memory-space accesses using config-space
3350          * command register.
3351          */
3352         pci_read_config_word(pdev, PCI_COMMAND, &tmp);
3353         if (!(tmp & PCI_COMMAND_MEMORY)) {
3354                 tmp |= PCI_COMMAND_MEMORY;
3355                 pci_write_config_word(pdev, PCI_COMMAND, tmp);
3356         }
3357 #ifdef __BIG_ENDIAN
3358         /* Use the big-endian aperture */
3359         addr += 0x800000;
3360 #endif
3361
3362         /* Map in frame buffer */
3363         info->fix.smem_start = addr;
3364         info->screen_base = ioremap(addr, 0x800000);
3365         if (info->screen_base == NULL) {
3366                 ret = -ENOMEM;
3367                 goto atyfb_setup_generic_fail;
3368         }
3369
3370         if((ret = correct_chipset(par)))
3371                 goto atyfb_setup_generic_fail;
3372 #ifdef __i386__
3373         if((ret = init_from_bios(par)))
3374                 goto atyfb_setup_generic_fail;
3375 #endif
3376         if (!(aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC_EXT_DISP_EN))
3377                 par->clk_wr_offset = (inb(R_GENMO) & 0x0CU) >> 2;
3378         else
3379                 par->clk_wr_offset = aty_ld_8(CLOCK_CNTL, par) & 0x03U;
3380
3381         /* according to ATI, we should use clock 3 for acelerated mode */
3382         par->clk_wr_offset = 3;
3383
3384         return 0;
3385
3386 atyfb_setup_generic_fail:
3387         iounmap(par->ati_regbase);
3388         par->ati_regbase = NULL;
3389         return ret;
3390 }
3391
3392 #endif /* !__sparc__ */
3393
3394 static int __devinit atyfb_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3395 {
3396         unsigned long addr, res_start, res_size;
3397         struct fb_info *info;
3398         struct resource *rp;
3399         struct atyfb_par *par;
3400         int i, rc = -ENOMEM;
3401
3402         for (i = sizeof(aty_chips) / sizeof(*aty_chips) - 1; i >= 0; i--)
3403                 if (pdev->device == aty_chips[i].pci_id)
3404                         break;
3405
3406         if (i < 0)
3407                 return -ENODEV;
3408
3409         /* Enable device in PCI config */
3410         if (pci_enable_device(pdev)) {
3411                 PRINTKE("Cannot enable PCI device\n");
3412                 return -ENXIO;
3413         }
3414
3415         /* Find which resource to use */
3416         rp = &pdev->resource[0];
3417         if (rp->flags & IORESOURCE_IO)
3418                 rp = &pdev->resource[1];
3419         addr = rp->start;
3420         if (!addr)
3421                 return -ENXIO;
3422
3423         /* Reserve space */
3424         res_start = rp->start;
3425         res_size = rp->end - rp->start + 1;
3426         if (!request_mem_region (res_start, res_size, "atyfb"))
3427                 return -EBUSY;
3428
3429         /* Allocate framebuffer */
3430         info = framebuffer_alloc(sizeof(struct atyfb_par), &pdev->dev);
3431         if (!info) {
3432                 PRINTKE("atyfb_pci_probe() can't alloc fb_info\n");
3433                 return -ENOMEM;
3434         }
3435         par = info->par;
3436         info->fix = atyfb_fix;
3437         info->device = &pdev->dev;
3438         par->pci_id = aty_chips[i].pci_id;
3439         par->res_start = res_start;
3440         par->res_size = res_size;
3441         par->irq = pdev->irq;
3442
3443         /* Setup "info" structure */
3444 #ifdef __sparc__
3445         rc = atyfb_setup_sparc(pdev, info, addr);
3446 #else
3447         rc = atyfb_setup_generic(pdev, info, addr);
3448 #endif
3449         if (rc)
3450                 goto err_release_mem;
3451
3452         pci_set_drvdata(pdev, info);
3453
3454         /* Init chip & register framebuffer */
3455         if (aty_init(info, "PCI"))
3456                 goto err_release_io;
3457
3458 #ifdef __sparc__
3459         if (!prom_palette)
3460                 prom_palette = atyfb_palette;
3461
3462         /*
3463          * Add /dev/fb mmap values.
3464          */
3465         par->mmap_map[0].voff = 0x8000000000000000UL;
3466         par->mmap_map[0].poff = (unsigned long) info->screen_base & PAGE_MASK;
3467         par->mmap_map[0].size = info->fix.smem_len;
3468         par->mmap_map[0].prot_mask = _PAGE_CACHE;
3469         par->mmap_map[0].prot_flag = _PAGE_E;
3470         par->mmap_map[1].voff = par->mmap_map[0].voff + info->fix.smem_len;
3471         par->mmap_map[1].poff = (long)par->ati_regbase & PAGE_MASK;
3472         par->mmap_map[1].size = PAGE_SIZE;
3473         par->mmap_map[1].prot_mask = _PAGE_CACHE;
3474         par->mmap_map[1].prot_flag = _PAGE_E;
3475 #endif /* __sparc__ */
3476
3477         return 0;
3478
3479 err_release_io:
3480 #ifdef __sparc__
3481         kfree(par->mmap_map);
3482 #else
3483         if (par->ati_regbase)
3484                 iounmap(par->ati_regbase);
3485         if (info->screen_base)
3486                 iounmap(info->screen_base);
3487 #endif
3488 err_release_mem:
3489         if (par->aux_start)
3490                 release_mem_region(par->aux_start, par->aux_size);
3491
3492         release_mem_region(par->res_start, par->res_size);
3493         framebuffer_release(info);
3494
3495         return rc;
3496 }
3497
3498 #endif /* CONFIG_PCI */
3499
3500 #ifdef CONFIG_ATARI
3501
3502 static int __devinit atyfb_atari_probe(void)
3503 {
3504         struct atyfb_par *par;
3505         struct fb_info *info;
3506         int m64_num;
3507         u32 clock_r;
3508
3509         for (m64_num = 0; m64_num < mach64_count; m64_num++) {
3510                 if (!phys_vmembase[m64_num] || !phys_size[m64_num] ||
3511                     !phys_guiregbase[m64_num]) {
3512                     PRINTKI("phys_*[%d] parameters not set => returning early. \n", m64_num);
3513                         continue;
3514                 }
3515
3516                 info = framebuffer_alloc(sizeof(struct atyfb_par), NULL);
3517                 if (!info) {
3518                         PRINTKE("atyfb_atari_probe() can't alloc fb_info\n");
3519                         return -ENOMEM;
3520                 }
3521                 par = info->par;
3522
3523                 info->fix = atyfb_fix;
3524
3525                 par->irq = (unsigned int) -1; /* something invalid */
3526
3527                 /*
3528                  *  Map the video memory (physical address given) to somewhere in the
3529                  *  kernel address space.
3530                  */
3531                 info->screen_base = ioremap(phys_vmembase[m64_num], phys_size[m64_num]);
3532                 info->fix.smem_start = (unsigned long)info->screen_base; /* Fake! */
3533                 par->ati_regbase = ioremap(phys_guiregbase[m64_num], 0x10000) +
3534                                                 0xFC00ul;
3535                 info->fix.mmio_start = (unsigned long)par->ati_regbase; /* Fake! */
3536
3537                 aty_st_le32(CLOCK_CNTL, 0x12345678, par);
3538                 clock_r = aty_ld_le32(CLOCK_CNTL, par);
3539
3540                 switch (clock_r & 0x003F) {
3541                 case 0x12:
3542                         par->clk_wr_offset = 3; /*  */
3543                         break;
3544                 case 0x34:
3545                         par->clk_wr_offset = 2; /* Medusa ST-IO ISA Adapter etc. */
3546                         break;
3547                 case 0x16:
3548                         par->clk_wr_offset = 1; /*  */
3549                         break;
3550                 case 0x38:
3551                         par->clk_wr_offset = 0; /* Panther 1 ISA Adapter (Gerald) */
3552                         break;
3553                 }
3554
3555                 if (aty_init(info, "ISA bus")) {
3556                         framebuffer_release(info);
3557                         /* This is insufficient! kernel_map has added two large chunks!! */
3558                         return -ENXIO;
3559                 }
3560         }
3561 }
3562
3563 #endif /* CONFIG_ATARI */
3564
3565 static void __devexit atyfb_remove(struct fb_info *info)
3566 {
3567         struct atyfb_par *par = (struct atyfb_par *) info->par;
3568
3569         /* restore video mode */
3570         aty_set_crtc(par, &saved_crtc);
3571         par->pll_ops->set_pll(info, &saved_pll);
3572
3573         unregister_framebuffer(info);
3574
3575 #ifdef CONFIG_MTRR
3576         if (par->mtrr_reg >= 0) {
3577             mtrr_del(par->mtrr_reg, 0, 0);
3578             par->mtrr_reg = -1;
3579         }
3580         if (par->mtrr_aper >= 0) {
3581             mtrr_del(par->mtrr_aper, 0, 0);
3582             par->mtrr_aper = -1;
3583         }
3584 #endif
3585 #ifndef __sparc__
3586         if (par->ati_regbase)
3587                 iounmap(par->ati_regbase);
3588         if (info->screen_base)
3589                 iounmap(info->screen_base);
3590 #ifdef __BIG_ENDIAN
3591         if (info->sprite.addr)
3592                 iounmap(info->sprite.addr);
3593 #endif
3594 #endif
3595 #ifdef __sparc__
3596         kfree(par->mmap_map);
3597 #endif
3598         if (par->aux_start)
3599                 release_mem_region(par->aux_start, par->aux_size);
3600
3601         if (par->res_start)
3602                 release_mem_region(par->res_start, par->res_size);
3603
3604         framebuffer_release(info);
3605 }
3606
3607 #ifdef CONFIG_PCI
3608
3609 static void __devexit atyfb_pci_remove(struct pci_dev *pdev)
3610 {
3611         struct fb_info *info = pci_get_drvdata(pdev);
3612
3613         atyfb_remove(info);
3614 }
3615
3616 /*
3617  * This driver uses its own matching table. That will be more difficult
3618  * to fix, so for now, we just match against any ATI ID and let the
3619  * probe() function find out what's up. That also mean we don't have
3620  * a module ID table though.
3621  */
3622 static struct pci_device_id atyfb_pci_tbl[] = {
3623         { PCI_VENDOR_ID_ATI, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
3624           PCI_BASE_CLASS_DISPLAY << 16, 0xff0000, 0 },
3625         { 0, }
3626 };
3627
3628 static struct pci_driver atyfb_driver = {
3629         .name           = "atyfb",
3630         .id_table       = atyfb_pci_tbl,
3631         .probe          = atyfb_pci_probe,
3632         .remove         = __devexit_p(atyfb_pci_remove),
3633 #ifdef CONFIG_PM
3634         .suspend        = atyfb_pci_suspend,
3635         .resume         = atyfb_pci_resume,
3636 #endif /* CONFIG_PM */
3637 };
3638
3639 #endif /* CONFIG_PCI */
3640
3641 #ifndef MODULE
3642 static int __init atyfb_setup(char *options)
3643 {
3644         char *this_opt;
3645
3646         if (!options || !*options)
3647                 return 0;
3648
3649         while ((this_opt = strsep(&options, ",")) != NULL) {
3650                 if (!strncmp(this_opt, "noaccel", 7)) {
3651                         noaccel = 1;
3652 #ifdef CONFIG_MTRR
3653                 } else if (!strncmp(this_opt, "nomtrr", 6)) {
3654                         nomtrr = 1;
3655 #endif
3656                 } else if (!strncmp(this_opt, "vram:", 5))
3657                         vram = simple_strtoul(this_opt + 5, NULL, 0);
3658                 else if (!strncmp(this_opt, "pll:", 4))
3659                         pll = simple_strtoul(this_opt + 4, NULL, 0);
3660                 else if (!strncmp(this_opt, "mclk:", 5))
3661                         mclk = simple_strtoul(this_opt + 5, NULL, 0);
3662                 else if (!strncmp(this_opt, "xclk:", 5))
3663                         xclk = simple_strtoul(this_opt+5, NULL, 0);
3664                 else if (!strncmp(this_opt, "comp_sync:", 10))
3665                         comp_sync = simple_strtoul(this_opt+10, NULL, 0);
3666 #ifdef CONFIG_PPC
3667                 else if (!strncmp(this_opt, "vmode:", 6)) {
3668                         unsigned int vmode =
3669                             simple_strtoul(this_opt + 6, NULL, 0);
3670                         if (vmode > 0 && vmode <= VMODE_MAX)
3671                                 default_vmode = vmode;
3672                 } else if (!strncmp(this_opt, "cmode:", 6)) {
3673                         unsigned int cmode =
3674                             simple_strtoul(this_opt + 6, NULL, 0);
3675                         switch (cmode) {
3676                         case 0:
3677                         case 8:
3678                                 default_cmode = CMODE_8;
3679                                 break;
3680                         case 15:
3681                         case 16:
3682                                 default_cmode = CMODE_16;
3683                                 break;
3684                         case 24:
3685                         case 32:
3686                                 default_cmode = CMODE_32;
3687                                 break;
3688                         }
3689                 }
3690 #endif
3691 #ifdef CONFIG_ATARI
3692                 /*
3693                  * Why do we need this silly Mach64 argument?
3694                  * We are already here because of mach64= so its redundant.
3695                  */
3696                 else if (MACH_IS_ATARI
3697                          && (!strncmp(this_opt, "Mach64:", 7))) {
3698                         static unsigned char m64_num;
3699                         static char mach64_str[80];
3700                         strlcpy(mach64_str, this_opt + 7, sizeof(mach64_str));
3701                         if (!store_video_par(mach64_str, m64_num)) {
3702                                 m64_num++;
3703                                 mach64_count = m64_num;
3704                         }
3705                 }
3706 #endif
3707                 else
3708                         mode = this_opt;
3709         }
3710         return 0;
3711 }
3712 #endif  /*  MODULE  */
3713
3714 static int __init atyfb_init(void)
3715 {
3716 #ifndef MODULE
3717     char *option = NULL;
3718
3719     if (fb_get_options("atyfb", &option))
3720         return -ENODEV;
3721     atyfb_setup(option);
3722 #endif
3723
3724     pci_register_driver(&atyfb_driver);
3725 #ifdef CONFIG_ATARI
3726     atyfb_atari_probe();
3727 #endif
3728     return 0;
3729 }
3730
3731 static void __exit atyfb_exit(void)
3732 {
3733         pci_unregister_driver(&atyfb_driver);
3734 }
3735
3736 module_init(atyfb_init);
3737 module_exit(atyfb_exit);
3738
3739 MODULE_DESCRIPTION("FBDev driver for ATI Mach64 cards");
3740 MODULE_LICENSE("GPL");
3741 module_param(noaccel, bool, 0);
3742 MODULE_PARM_DESC(noaccel, "bool: disable acceleration");
3743 module_param(vram, int, 0);
3744 MODULE_PARM_DESC(vram, "int: override size of video ram");
3745 module_param(pll, int, 0);
3746 MODULE_PARM_DESC(pll, "int: override video clock");
3747 module_param(mclk, int, 0);
3748 MODULE_PARM_DESC(mclk, "int: override memory clock");
3749 module_param(xclk, int, 0);
3750 MODULE_PARM_DESC(xclk, "int: override accelerated engine clock");
3751 module_param(comp_sync, int, 0);
3752 MODULE_PARM_DESC(comp_sync,
3753                  "Set composite sync signal to low (0) or high (1)");
3754 module_param(mode, charp, 0);
3755 MODULE_PARM_DESC(mode, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
3756 #ifdef CONFIG_MTRR
3757 module_param(nomtrr, bool, 0);
3758 MODULE_PARM_DESC(nomtrr, "bool: disable use of MTRR registers");
3759 #endif