2 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #ifndef _IPATH_REGISTERS_H
34 #define _IPATH_REGISTERS_H
37 * This file should only be included by kernel source, and by the diags.
38 * It defines the registers, and their contents, for the InfiniPath HT-400 chip
42 * These are the InfiniPath register and buffer bit definitions,
43 * that are visible to software, and needed only by the kernel
44 * and diag code. A few, that are visible to protocol and user
45 * code are in ipath_common.h. Some bits are specific
46 * to a given chip implementation, and have been moved to the
47 * chip-specific source file
50 /* kr_revision bits */
51 #define INFINIPATH_R_CHIPREVMINOR_MASK 0xFF
52 #define INFINIPATH_R_CHIPREVMINOR_SHIFT 0
53 #define INFINIPATH_R_CHIPREVMAJOR_MASK 0xFF
54 #define INFINIPATH_R_CHIPREVMAJOR_SHIFT 8
55 #define INFINIPATH_R_ARCH_MASK 0xFF
56 #define INFINIPATH_R_ARCH_SHIFT 16
57 #define INFINIPATH_R_SOFTWARE_MASK 0xFF
58 #define INFINIPATH_R_SOFTWARE_SHIFT 24
59 #define INFINIPATH_R_BOARDID_MASK 0xFF
60 #define INFINIPATH_R_BOARDID_SHIFT 32
63 #define INFINIPATH_C_FREEZEMODE 0x00000002
64 #define INFINIPATH_C_LINKENABLE 0x00000004
65 #define INFINIPATH_C_RESET 0x00000001
67 /* kr_sendctrl bits */
68 #define INFINIPATH_S_DISARMPIOBUF_SHIFT 16
70 #define IPATH_S_ABORT 0
71 #define IPATH_S_PIOINTBUFAVAIL 1
72 #define IPATH_S_PIOBUFAVAILUPD 2
73 #define IPATH_S_PIOENABLE 3
74 #define IPATH_S_DISARM 31
76 #define INFINIPATH_S_ABORT (1U << IPATH_S_ABORT)
77 #define INFINIPATH_S_PIOINTBUFAVAIL (1U << IPATH_S_PIOINTBUFAVAIL)
78 #define INFINIPATH_S_PIOBUFAVAILUPD (1U << IPATH_S_PIOBUFAVAILUPD)
79 #define INFINIPATH_S_PIOENABLE (1U << IPATH_S_PIOENABLE)
80 #define INFINIPATH_S_DISARM (1U << IPATH_S_DISARM)
83 #define INFINIPATH_R_PORTENABLE_SHIFT 0
84 #define INFINIPATH_R_INTRAVAIL_SHIFT 16
85 #define INFINIPATH_R_TAILUPD 0x80000000
87 /* kr_intstatus, kr_intclear, kr_intmask bits */
88 #define INFINIPATH_I_RCVURG_SHIFT 0
89 #define INFINIPATH_I_RCVAVAIL_SHIFT 12
90 #define INFINIPATH_I_ERROR 0x80000000
91 #define INFINIPATH_I_SPIOSENT 0x40000000
92 #define INFINIPATH_I_SPIOBUFAVAIL 0x20000000
93 #define INFINIPATH_I_GPIO 0x10000000
95 /* kr_errorstatus, kr_errorclear, kr_errormask bits */
96 #define INFINIPATH_E_RFORMATERR 0x0000000000000001ULL
97 #define INFINIPATH_E_RVCRC 0x0000000000000002ULL
98 #define INFINIPATH_E_RICRC 0x0000000000000004ULL
99 #define INFINIPATH_E_RMINPKTLEN 0x0000000000000008ULL
100 #define INFINIPATH_E_RMAXPKTLEN 0x0000000000000010ULL
101 #define INFINIPATH_E_RLONGPKTLEN 0x0000000000000020ULL
102 #define INFINIPATH_E_RSHORTPKTLEN 0x0000000000000040ULL
103 #define INFINIPATH_E_RUNEXPCHAR 0x0000000000000080ULL
104 #define INFINIPATH_E_RUNSUPVL 0x0000000000000100ULL
105 #define INFINIPATH_E_REBP 0x0000000000000200ULL
106 #define INFINIPATH_E_RIBFLOW 0x0000000000000400ULL
107 #define INFINIPATH_E_RBADVERSION 0x0000000000000800ULL
108 #define INFINIPATH_E_RRCVEGRFULL 0x0000000000001000ULL
109 #define INFINIPATH_E_RRCVHDRFULL 0x0000000000002000ULL
110 #define INFINIPATH_E_RBADTID 0x0000000000004000ULL
111 #define INFINIPATH_E_RHDRLEN 0x0000000000008000ULL
112 #define INFINIPATH_E_RHDR 0x0000000000010000ULL
113 #define INFINIPATH_E_RIBLOSTLINK 0x0000000000020000ULL
114 #define INFINIPATH_E_SMINPKTLEN 0x0000000020000000ULL
115 #define INFINIPATH_E_SMAXPKTLEN 0x0000000040000000ULL
116 #define INFINIPATH_E_SUNDERRUN 0x0000000080000000ULL
117 #define INFINIPATH_E_SPKTLEN 0x0000000100000000ULL
118 #define INFINIPATH_E_SDROPPEDSMPPKT 0x0000000200000000ULL
119 #define INFINIPATH_E_SDROPPEDDATAPKT 0x0000000400000000ULL
120 #define INFINIPATH_E_SPIOARMLAUNCH 0x0000000800000000ULL
121 #define INFINIPATH_E_SUNEXPERRPKTNUM 0x0000001000000000ULL
122 #define INFINIPATH_E_SUNSUPVL 0x0000002000000000ULL
123 #define INFINIPATH_E_IBSTATUSCHANGED 0x0001000000000000ULL
124 #define INFINIPATH_E_INVALIDADDR 0x0002000000000000ULL
125 #define INFINIPATH_E_RESET 0x0004000000000000ULL
126 #define INFINIPATH_E_HARDWARE 0x0008000000000000ULL
128 /* kr_hwerrclear, kr_hwerrmask, kr_hwerrstatus, bits */
129 /* TXEMEMPARITYERR bit 0: PIObuf, 1: PIOpbc, 2: launchfifo
130 * RXEMEMPARITYERR bit 0: rcvbuf, 1: lookupq, 2: eagerTID, 3: expTID
131 * bit 4: flag buffer, 5: datainfo, 6: header info */
132 #define INFINIPATH_HWE_TXEMEMPARITYERR_MASK 0xFULL
133 #define INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT 40
134 #define INFINIPATH_HWE_RXEMEMPARITYERR_MASK 0x7FULL
135 #define INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT 44
136 #define INFINIPATH_HWE_RXDSYNCMEMPARITYERR 0x0000000400000000ULL
137 #define INFINIPATH_HWE_MEMBISTFAILED 0x0040000000000000ULL
138 #define INFINIPATH_HWE_IBCBUSTOSPCPARITYERR 0x4000000000000000ULL
139 #define INFINIPATH_HWE_IBCBUSFRSPCPARITYERR 0x8000000000000000ULL
141 /* kr_hwdiagctrl bits */
142 #define INFINIPATH_DC_FORCETXEMEMPARITYERR_MASK 0xFULL
143 #define INFINIPATH_DC_FORCETXEMEMPARITYERR_SHIFT 40
144 #define INFINIPATH_DC_FORCERXEMEMPARITYERR_MASK 0x7FULL
145 #define INFINIPATH_DC_FORCERXEMEMPARITYERR_SHIFT 44
146 #define INFINIPATH_DC_FORCERXDSYNCMEMPARITYERR 0x0000000400000000ULL
147 #define INFINIPATH_DC_COUNTERDISABLE 0x1000000000000000ULL
148 #define INFINIPATH_DC_COUNTERWREN 0x2000000000000000ULL
149 #define INFINIPATH_DC_FORCEIBCBUSTOSPCPARITYERR 0x4000000000000000ULL
150 #define INFINIPATH_DC_FORCEIBCBUSFRSPCPARITYERR 0x8000000000000000ULL
152 /* kr_ibcctrl bits */
153 #define INFINIPATH_IBCC_FLOWCTRLPERIOD_MASK 0xFFULL
154 #define INFINIPATH_IBCC_FLOWCTRLPERIOD_SHIFT 0
155 #define INFINIPATH_IBCC_FLOWCTRLWATERMARK_MASK 0xFFULL
156 #define INFINIPATH_IBCC_FLOWCTRLWATERMARK_SHIFT 8
157 #define INFINIPATH_IBCC_LINKINITCMD_MASK 0x3ULL
158 #define INFINIPATH_IBCC_LINKINITCMD_DISABLE 1
159 #define INFINIPATH_IBCC_LINKINITCMD_POLL 2 /* cycle through TS1/TS2 till OK */
160 #define INFINIPATH_IBCC_LINKINITCMD_SLEEP 3 /* wait for TS1, then go on */
161 #define INFINIPATH_IBCC_LINKINITCMD_SHIFT 16
162 #define INFINIPATH_IBCC_LINKCMD_MASK 0x3ULL
163 #define INFINIPATH_IBCC_LINKCMD_INIT 1 /* move to 0x11 */
164 #define INFINIPATH_IBCC_LINKCMD_ARMED 2 /* move to 0x21 */
165 #define INFINIPATH_IBCC_LINKCMD_ACTIVE 3 /* move to 0x31 */
166 #define INFINIPATH_IBCC_LINKCMD_SHIFT 18
167 #define INFINIPATH_IBCC_MAXPKTLEN_MASK 0x7FFULL
168 #define INFINIPATH_IBCC_MAXPKTLEN_SHIFT 20
169 #define INFINIPATH_IBCC_PHYERRTHRESHOLD_MASK 0xFULL
170 #define INFINIPATH_IBCC_PHYERRTHRESHOLD_SHIFT 32
171 #define INFINIPATH_IBCC_OVERRUNTHRESHOLD_MASK 0xFULL
172 #define INFINIPATH_IBCC_OVERRUNTHRESHOLD_SHIFT 36
173 #define INFINIPATH_IBCC_CREDITSCALE_MASK 0x7ULL
174 #define INFINIPATH_IBCC_CREDITSCALE_SHIFT 40
175 #define INFINIPATH_IBCC_LOOPBACK 0x8000000000000000ULL
176 #define INFINIPATH_IBCC_LINKDOWNDEFAULTSTATE 0x4000000000000000ULL
178 /* kr_ibcstatus bits */
179 #define INFINIPATH_IBCS_LINKTRAININGSTATE_MASK 0xF
180 #define INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT 0
181 #define INFINIPATH_IBCS_LINKSTATE_MASK 0x7
182 #define INFINIPATH_IBCS_LINKSTATE_SHIFT 4
183 #define INFINIPATH_IBCS_TXREADY 0x40000000
184 #define INFINIPATH_IBCS_TXCREDITOK 0x80000000
185 /* link training states (shift by INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT) */
186 #define INFINIPATH_IBCS_LT_STATE_DISABLED 0x00
187 #define INFINIPATH_IBCS_LT_STATE_LINKUP 0x01
188 #define INFINIPATH_IBCS_LT_STATE_POLLACTIVE 0x02
189 #define INFINIPATH_IBCS_LT_STATE_POLLQUIET 0x03
190 #define INFINIPATH_IBCS_LT_STATE_SLEEPDELAY 0x04
191 #define INFINIPATH_IBCS_LT_STATE_SLEEPQUIET 0x05
192 #define INFINIPATH_IBCS_LT_STATE_CFGDEBOUNCE 0x08
193 #define INFINIPATH_IBCS_LT_STATE_CFGRCVFCFG 0x09
194 #define INFINIPATH_IBCS_LT_STATE_CFGWAITRMT 0x0a
195 #define INFINIPATH_IBCS_LT_STATE_CFGIDLE 0x0b
196 #define INFINIPATH_IBCS_LT_STATE_RECOVERRETRAIN 0x0c
197 #define INFINIPATH_IBCS_LT_STATE_RECOVERWAITRMT 0x0e
198 #define INFINIPATH_IBCS_LT_STATE_RECOVERIDLE 0x0f
199 /* link state machine states (shift by INFINIPATH_IBCS_LINKSTATE_SHIFT) */
200 #define INFINIPATH_IBCS_L_STATE_DOWN 0x0
201 #define INFINIPATH_IBCS_L_STATE_INIT 0x1
202 #define INFINIPATH_IBCS_L_STATE_ARM 0x2
203 #define INFINIPATH_IBCS_L_STATE_ACTIVE 0x3
204 #define INFINIPATH_IBCS_L_STATE_ACT_DEFER 0x4
206 /* combination link status states that we use with some frequency */
207 #define IPATH_IBSTATE_MASK ((INFINIPATH_IBCS_LINKTRAININGSTATE_MASK \
208 << INFINIPATH_IBCS_LINKSTATE_SHIFT) | \
209 (INFINIPATH_IBCS_LINKSTATE_MASK \
210 <<INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT))
211 #define IPATH_IBSTATE_INIT ((INFINIPATH_IBCS_L_STATE_INIT \
212 << INFINIPATH_IBCS_LINKSTATE_SHIFT) | \
213 (INFINIPATH_IBCS_LT_STATE_LINKUP \
214 <<INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT))
215 #define IPATH_IBSTATE_ARM ((INFINIPATH_IBCS_L_STATE_ARM \
216 << INFINIPATH_IBCS_LINKSTATE_SHIFT) | \
217 (INFINIPATH_IBCS_LT_STATE_LINKUP \
218 <<INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT))
219 #define IPATH_IBSTATE_ACTIVE ((INFINIPATH_IBCS_L_STATE_ACTIVE \
220 << INFINIPATH_IBCS_LINKSTATE_SHIFT) | \
221 (INFINIPATH_IBCS_LT_STATE_LINKUP \
222 <<INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT))
224 /* kr_extstatus bits */
225 #define INFINIPATH_EXTS_SERDESPLLLOCK 0x1
226 #define INFINIPATH_EXTS_GPIOIN_MASK 0xFFFFULL
227 #define INFINIPATH_EXTS_GPIOIN_SHIFT 48
229 /* kr_extctrl bits */
230 #define INFINIPATH_EXTC_GPIOINVERT_MASK 0xFFFFULL
231 #define INFINIPATH_EXTC_GPIOINVERT_SHIFT 32
232 #define INFINIPATH_EXTC_GPIOOE_MASK 0xFFFFULL
233 #define INFINIPATH_EXTC_GPIOOE_SHIFT 48
234 #define INFINIPATH_EXTC_SERDESENABLE 0x80000000ULL
235 #define INFINIPATH_EXTC_SERDESCONNECT 0x40000000ULL
236 #define INFINIPATH_EXTC_SERDESENTRUNKING 0x20000000ULL
237 #define INFINIPATH_EXTC_SERDESDISRXFIFO 0x10000000ULL
238 #define INFINIPATH_EXTC_SERDESENPLPBK1 0x08000000ULL
239 #define INFINIPATH_EXTC_SERDESENPLPBK2 0x04000000ULL
240 #define INFINIPATH_EXTC_SERDESENENCDEC 0x02000000ULL
241 #define INFINIPATH_EXTC_LED1SECPORT_ON 0x00000020ULL
242 #define INFINIPATH_EXTC_LED2SECPORT_ON 0x00000010ULL
243 #define INFINIPATH_EXTC_LED1PRIPORT_ON 0x00000008ULL
244 #define INFINIPATH_EXTC_LED2PRIPORT_ON 0x00000004ULL
245 #define INFINIPATH_EXTC_LEDGBLOK_ON 0x00000002ULL
246 #define INFINIPATH_EXTC_LEDGBLERR_OFF 0x00000001ULL
249 #define INFINIPATH_MDIO_CLKDIV_MASK 0x7FULL
250 #define INFINIPATH_MDIO_CLKDIV_SHIFT 32
251 #define INFINIPATH_MDIO_COMMAND_MASK 0x7ULL
252 #define INFINIPATH_MDIO_COMMAND_SHIFT 26
253 #define INFINIPATH_MDIO_DEVADDR_MASK 0x1FULL
254 #define INFINIPATH_MDIO_DEVADDR_SHIFT 21
255 #define INFINIPATH_MDIO_REGADDR_MASK 0x1FULL
256 #define INFINIPATH_MDIO_REGADDR_SHIFT 16
257 #define INFINIPATH_MDIO_DATA_MASK 0xFFFFULL
258 #define INFINIPATH_MDIO_DATA_SHIFT 0
259 #define INFINIPATH_MDIO_CMDVALID 0x0000000040000000ULL
260 #define INFINIPATH_MDIO_RDDATAVALID 0x0000000080000000ULL
262 /* kr_partitionkey bits */
263 #define INFINIPATH_PKEY_SIZE 16
264 #define INFINIPATH_PKEY_MASK 0xFFFF
265 #define INFINIPATH_PKEY_DEFAULT_PKEY 0xFFFF
267 /* kr_serdesconfig0 bits */
268 #define INFINIPATH_SERDC0_RESET_MASK 0xfULL /* overal reset bits */
269 #define INFINIPATH_SERDC0_RESET_PLL 0x10000000ULL /* pll reset */
270 #define INFINIPATH_SERDC0_TXIDLE 0xF000ULL /* tx idle enables (per lane) */
271 #define INFINIPATH_SERDC0_RXDETECT_EN 0xF0000ULL /* rx detect enables (per lane) */
272 #define INFINIPATH_SERDC0_L1PWR_DN 0xF0ULL /* L1 Power down; use with RXDETECT,
273 Otherwise not used on IB side */
275 /* kr_xgxsconfig bits */
276 #define INFINIPATH_XGXS_RESET 0x7ULL
277 #define INFINIPATH_XGXS_MDIOADDR_MASK 0xfULL
278 #define INFINIPATH_XGXS_MDIOADDR_SHIFT 4
280 #define INFINIPATH_RT_ADDR_MASK 0xFFFFFFFFFFULL /* 40 bits valid */
282 /* TID entries (memory), HT400-only */
283 #define INFINIPATH_RT_VALID 0x8000000000000000ULL
284 #define INFINIPATH_RT_ADDR_SHIFT 0
285 #define INFINIPATH_RT_BUFSIZE_MASK 0x3FFF
286 #define INFINIPATH_RT_BUFSIZE_SHIFT 48
289 * IPATH_PIO_MAXIBHDR is the max IB header size allowed for in our
290 * PIO send buffers. This is well beyond anything currently
291 * defined in the InfiniBand spec.
293 #define IPATH_PIO_MAXIBHDR 128
295 typedef u64 ipath_err_t;
297 /* mask of defined bits for various registers */
298 extern u64 infinipath_i_bitsextant;
299 extern ipath_err_t infinipath_e_bitsextant, infinipath_hwe_bitsextant;
301 /* masks that are different in various chips, or only exist in some chips */
302 extern u32 infinipath_i_rcvavail_mask, infinipath_i_rcvurg_mask;
305 * register bits for selecting i2c direction and values, used for I2C serial
308 extern u16 ipath_gpio_sda_num, ipath_gpio_scl_num;
309 extern u64 ipath_gpio_sda, ipath_gpio_scl;
312 * These are the infinipath general register numbers (not offsets).
313 * The kernel registers are used directly, those beyond the kernel
314 * registers are calculated from one of the base registers. The use of
315 * an integer type doesn't allow type-checking as thorough as, say,
316 * an enum but allows for better hiding of chip differences.
318 typedef const u16 ipath_kreg, /* infinipath general registers */
319 ipath_creg, /* infinipath counter registers */
320 ipath_sreg; /* kernel-only, infinipath send registers */
323 * These are the chip registers common to all infinipath chips, and
324 * used both by the kernel and the diagnostics or other user code.
325 * They are all implemented such that 64 bit accesses work.
326 * Some implement no more than 32 bits. Because 64 bit reads
327 * require 2 HT cmds on opteron, we access those with 32 bit
328 * reads for efficiency (they are written as 64 bits, since
329 * the extra 32 bits are nearly free on writes, and it slightly reduces
330 * complexity). The rest are all accessed as 64 bits.
333 /* These are the 32 bit group */
334 ipath_kreg kr_control;
335 ipath_kreg kr_counterregbase;
336 ipath_kreg kr_intmask;
337 ipath_kreg kr_intstatus;
338 ipath_kreg kr_pagealign;
339 ipath_kreg kr_portcnt;
340 ipath_kreg kr_rcvtidbase;
341 ipath_kreg kr_rcvtidcnt;
342 ipath_kreg kr_rcvegrbase;
343 ipath_kreg kr_rcvegrcnt;
344 ipath_kreg kr_scratch;
345 ipath_kreg kr_sendctrl;
346 ipath_kreg kr_sendpiobufbase;
347 ipath_kreg kr_sendpiobufcnt;
348 ipath_kreg kr_sendpiosize;
349 ipath_kreg kr_sendregbase;
350 ipath_kreg kr_userregbase;
351 /* These are the 64 bit group */
352 ipath_kreg kr_debugport;
353 ipath_kreg kr_debugportselect;
354 ipath_kreg kr_errorclear;
355 ipath_kreg kr_errormask;
356 ipath_kreg kr_errorstatus;
357 ipath_kreg kr_extctrl;
358 ipath_kreg kr_extstatus;
359 ipath_kreg kr_gpio_clear;
360 ipath_kreg kr_gpio_mask;
361 ipath_kreg kr_gpio_out;
362 ipath_kreg kr_gpio_status;
363 ipath_kreg kr_hwdiagctrl;
364 ipath_kreg kr_hwerrclear;
365 ipath_kreg kr_hwerrmask;
366 ipath_kreg kr_hwerrstatus;
367 ipath_kreg kr_ibcctrl;
368 ipath_kreg kr_ibcstatus;
369 ipath_kreg kr_intblocked;
370 ipath_kreg kr_intclear;
371 ipath_kreg kr_interruptconfig;
373 ipath_kreg kr_partitionkey;
374 ipath_kreg kr_rcvbthqp;
375 ipath_kreg kr_rcvbufbase;
376 ipath_kreg kr_rcvbufsize;
377 ipath_kreg kr_rcvctrl;
378 ipath_kreg kr_rcvhdrcnt;
379 ipath_kreg kr_rcvhdrentsize;
380 ipath_kreg kr_rcvhdrsize;
381 ipath_kreg kr_rcvintmembase;
382 ipath_kreg kr_rcvintmemsize;
383 ipath_kreg kr_revision;
384 ipath_kreg kr_sendbuffererror;
385 ipath_kreg kr_sendpioavailaddr;
386 ipath_kreg kr_serdesconfig0;
387 ipath_kreg kr_serdesconfig1;
388 ipath_kreg kr_serdesstatus;
389 ipath_kreg kr_txintmembase;
390 ipath_kreg kr_txintmemsize;
391 ipath_kreg kr_xgxsconfig;
392 ipath_kreg kr_ibpllcfg;
393 /* use these two (and the following N ports) only with ipath_k*_kreg64_port();
395 ipath_kreg kr_rcvhdraddr;
396 ipath_kreg kr_rcvhdrtailaddr;
398 /* remaining registers are not present on all types of infinipath chips */
399 ipath_kreg kr_rcvpktledcnt;
400 ipath_kreg kr_pcierbuftestreg0;
401 ipath_kreg kr_pcierbuftestreg1;
402 ipath_kreg kr_pcieq0serdesconfig0;
403 ipath_kreg kr_pcieq0serdesconfig1;
404 ipath_kreg kr_pcieq0serdesstatus;
405 ipath_kreg kr_pcieq1serdesconfig0;
406 ipath_kreg kr_pcieq1serdesconfig1;
407 ipath_kreg kr_pcieq1serdesstatus;
411 ipath_creg cr_badformatcnt;
412 ipath_creg cr_erricrccnt;
413 ipath_creg cr_errlinkcnt;
414 ipath_creg cr_errlpcrccnt;
415 ipath_creg cr_errpkey;
416 ipath_creg cr_errrcvflowctrlcnt;
417 ipath_creg cr_err_rlencnt;
418 ipath_creg cr_errslencnt;
419 ipath_creg cr_errtidfull;
420 ipath_creg cr_errtidvalid;
421 ipath_creg cr_errvcrccnt;
422 ipath_creg cr_ibstatuschange;
423 ipath_creg cr_intcnt;
424 ipath_creg cr_invalidrlencnt;
425 ipath_creg cr_invalidslencnt;
426 ipath_creg cr_lbflowstallcnt;
427 ipath_creg cr_iblinkdowncnt;
428 ipath_creg cr_iblinkerrrecovcnt;
429 ipath_creg cr_ibsymbolerrcnt;
430 ipath_creg cr_pktrcvcnt;
431 ipath_creg cr_pktrcvflowctrlcnt;
432 ipath_creg cr_pktsendcnt;
433 ipath_creg cr_pktsendflowcnt;
434 ipath_creg cr_portovflcnt;
435 ipath_creg cr_rcvebpcnt;
436 ipath_creg cr_rcvovflcnt;
437 ipath_creg cr_rxdroppktcnt;
438 ipath_creg cr_senddropped;
439 ipath_creg cr_sendstallcnt;
440 ipath_creg cr_sendunderruncnt;
441 ipath_creg cr_unsupvlcnt;
442 ipath_creg cr_wordrcvcnt;
443 ipath_creg cr_wordsendcnt;
446 #endif /* _IPATH_REGISTERS_H */