1 # Put here option for CPU selection and depending optimization
5 prompt "Processor family"
12 This is the processor type of your CPU. This information is used for
13 optimizing purposes. In order to compile a kernel that can run on
14 all x86 CPU types (albeit not optimally fast), you can specify
17 The kernel will not necessarily run on earlier architectures than
18 the one you have chosen, e.g. a Pentium optimized kernel will run on
19 a PPro, but not necessarily on a i486.
21 Here are the settings recommended for greatest speed:
22 - "386" for the AMD/Cyrix/Intel 386DX/DXL/SL/SLC/SX, Cyrix/TI
23 486DLC/DLC2, UMC 486SX-S and NexGen Nx586. Only "386" kernels
24 will run on a 386 class machine.
25 - "486" for the AMD/Cyrix/IBM/Intel 486DX/DX2/DX4 or
26 SL/SLC/SLC2/SLC3/SX/SX2 and UMC U5D or U5S.
27 - "586" for generic Pentium CPUs lacking the TSC
28 (time stamp counter) register.
29 - "Pentium-Classic" for the Intel Pentium.
30 - "Pentium-MMX" for the Intel Pentium MMX.
31 - "Pentium-Pro" for the Intel Pentium Pro.
32 - "Pentium-II" for the Intel Pentium II or pre-Coppermine Celeron.
33 - "Pentium-III" for the Intel Pentium III or Coppermine Celeron.
34 - "Pentium-4" for the Intel Pentium 4 or P4-based Celeron.
35 - "K6" for the AMD K6, K6-II and K6-III (aka K6-3D).
36 - "Athlon" for the AMD K7 family (Athlon/Duron/Thunderbird).
37 - "Crusoe" for the Transmeta Crusoe series.
38 - "Efficeon" for the Transmeta Efficeon series.
39 - "Winchip-C6" for original IDT Winchip.
40 - "Winchip-2" for IDT Winchip 2.
41 - "Winchip-2A" for IDT Winchips with 3dNow! capabilities.
42 - "GeodeGX1" for Geode GX1 (Cyrix MediaGX).
43 - "Geode GX/LX" For AMD Geode GX and LX processors.
44 - "CyrixIII/VIA C3" for VIA Cyrix III or VIA C3.
45 - "VIA C3-2" for VIA C3-2 "Nehemiah" (model 9 and above).
47 If you don't know what to do, choose "386".
52 Select this for a 486 series processor, either Intel or one of the
53 compatible processors from AMD, Cyrix, IBM, or Intel. Includes DX,
54 DX2, and DX4 variants; also SL/SLC/SLC2/SLC3/SX/SX2 and UMC U5D or
58 bool "586/K5/5x86/6x86/6x86MX"
60 Select this for an 586 or 686 series processor such as the AMD K5,
61 the Cyrix 5x86, 6x86 and 6x86MX. This choice does not
62 assume the RDTSC (Read Time Stamp Counter) instruction.
65 bool "Pentium-Classic"
67 Select this for a Pentium Classic processor with the RDTSC (Read
68 Time Stamp Counter) instruction for benchmarking.
73 Select this for a Pentium with the MMX graphics/multimedia
74 extended instructions.
79 Select this for Intel Pentium Pro chips. This enables the use of
80 Pentium Pro extended instructions, and disables the init-time guard
81 against the f00f bug found in earlier Pentiums.
84 bool "Pentium-II/Celeron(pre-Coppermine)"
86 Select this for Intel chips based on the Pentium-II and
87 pre-Coppermine Celeron core. This option enables an unaligned
88 copy optimization, compiles the kernel with optimization flags
89 tailored for the chip, and applies any applicable Pentium Pro
93 bool "Pentium-III/Celeron(Coppermine)/Pentium-III Xeon"
95 Select this for Intel chips based on the Pentium-III and
96 Celeron-Coppermine core. This option enables use of some
97 extended prefetch instructions in addition to the Pentium II
103 Select this for Intel Pentium M (not Pentium-4 M)
107 bool "Pentium-4/Celeron(P4-based)/Pentium-4 M/Xeon"
109 Select this for Intel Pentium 4 chips. This includes the
110 Pentium 4, P4-based Celeron and Xeon, and Pentium-4 M
111 (not Pentium M) chips. This option enables compile flags
112 optimized for the chip, uses the correct cache shift, and
113 applies any applicable Pentium III optimizations.
116 bool "K6/K6-II/K6-III"
118 Select this for an AMD K6-family processor. Enables use of
119 some extended instructions, and passes appropriate optimization
123 bool "Athlon/Duron/K7"
125 Select this for an AMD Athlon K7-family processor. Enables use of
126 some extended instructions, and passes appropriate optimization
130 bool "Opteron/Athlon64/Hammer/K8"
132 Select this for an AMD Opteron or Athlon64 Hammer-family processor. Enables
133 use of some extended instructions, and passes appropriate optimization
139 Select this for a Transmeta Crusoe processor. Treats the processor
140 like a 586 with TSC, and sets some GCC optimization flags (like a
141 Pentium Pro with no alignment requirements).
146 Select this for a Transmeta Efficeon processor.
151 Select this for an IDT Winchip C6 chip. Linux and GCC
152 treat this chip as a 586TSC with some extended instructions
153 and alignment requirements.
158 Select this for an IDT Winchip-2. Linux and GCC
159 treat this chip as a 586TSC with some extended instructions
160 and alignment requirements.
163 bool "Winchip-2A/Winchip-3"
165 Select this for an IDT Winchip-2A or 3. Linux and GCC
166 treat this chip as a 586TSC with some extended instructions
167 and alignment reqirements. Also enable out of order memory
168 stores for this CPU, which can increase performance of some
174 Select this for a Geode GX1 (Cyrix MediaGX) chip.
179 Select this for AMD Geode GX and LX processors.
182 bool "CyrixIII/VIA-C3"
184 Select this for a Cyrix III or C3 chip. Presently Linux and GCC
185 treat this chip as a generic 586. Whilst the CPU is 686 class,
186 it lacks the cmov extension which gcc assumes is present when
188 Note that Nehemiah (Model 9) and above will not boot with this
189 kernel due to them lacking the 3DNow! instructions used in earlier
190 incarnations of the CPU.
193 bool "VIA C3-2 (Nehemiah)"
195 Select this for a VIA C3 "Nehemiah". Selecting this enables usage
196 of SSE and tells gcc to treat the CPU as a 686.
197 Note, this kernel will not boot on older (pre model 9) C3s.
202 bool "Generic x86 support"
204 Instead of just including optimizations for the selected
205 x86 variant (e.g. PII, Crusoe or Athlon), include some more
206 generic optimizations as well. This will make the kernel
207 perform better on x86 CPUs other than that selected.
209 This is really intended for distributors who need more
210 generic optimizations.
215 # Define implied options from the CPU selection here
227 config X86_L1_CACHE_SHIFT
229 default "7" if MPENTIUM4 || X86_GENERIC
230 default "4" if X86_ELAN || M486 || M386 || MGEODEGX1
231 default "5" if MWINCHIP3D || MWINCHIP2 || MWINCHIPC6 || MCRUSOE || MEFFICEON || MCYRIXIII || MK6 || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || M586 || MVIAC3_2 || MGEODE_LX
232 default "6" if MK7 || MK8 || MPENTIUMM
234 config RWSEM_GENERIC_SPINLOCK
239 config RWSEM_XCHGADD_ALGORITHM
244 config GENERIC_CALIBRATE_DELAY
248 config X86_PPRO_FENCE
250 depends on M686 || M586MMX || M586TSC || M586 || M486 || M386 || MGEODEGX1
255 depends on M586MMX || M586TSC || M586 || M486 || M386
258 config X86_WP_WORKS_OK
280 depends on !M386 && !M486
283 config X86_ALIGNMENT_16
285 depends on MWINCHIP3D || MWINCHIP2 || MWINCHIPC6 || MCYRIXIII || X86_ELAN || MK6 || M586MMX || M586TSC || M586 || M486 || MVIAC3_2 || MGEODEGX1
290 depends on MK7 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || MK8 || MEFFICEON
293 config X86_INTEL_USERCOPY
295 depends on MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M586MMX || X86_GENERIC || MK8 || MK7 || MEFFICEON
298 config X86_USE_PPRO_CHECKSUM
300 depends on MWINCHIP3D || MWINCHIP2 || MWINCHIPC6 || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MK8 || MVIAC3_2 || MEFFICEON || MGEODE_LX
305 depends on (MCYRIXIII || MK7 || MGEODE_LX) && !UML
310 depends on (MWINCHIP3D || MWINCHIP2 || MWINCHIPC6) && MTRR
315 depends on (MWINCHIP3D || MWINCHIP2 || MCRUSOE || MEFFICEON || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || MK8 || MVIAC3_2 || MGEODEGX1 || MGEODE_LX) && !X86_NUMAQ