1 /* tsb.S: Sparc64 TSB table handling.
3 * Copyright (C) 2006 David S. Miller <davem@davemloft.net>
7 #include <asm/hypervisor.h>
12 /* Invoked from TLB miss handler, we are in the
13 * MMU global registers and they are setup like
16 * %g1: TSB entry pointer
17 * %g2: available temporary
18 * %g3: FAULT_CODE_{D,I}TLB
19 * %g4: available temporary
20 * %g5: available temporary
22 * %g7: available temporary, will be loaded by us with
23 * the physical address base of the linux page
24 * tables for the current address space
27 mov TLB_TAG_ACCESS, %g4
28 ldxa [%g4] ASI_DMMU, %g4
29 ba,pt %xcc, tsb_miss_page_table_walk
33 mov TLB_TAG_ACCESS, %g4
34 ldxa [%g4] ASI_IMMU, %g4
35 ba,pt %xcc, tsb_miss_page_table_walk
38 /* The sun4v TLB miss handlers jump directly here instead
39 * of tsb_miss_{d,i}tlb with registers setup as follows:
41 * %g4: missing virtual address
42 * %g1: TSB entry address loaded
43 * %g6: TAG TARGET ((vaddr >> 22) | (ctx << 48))
45 tsb_miss_page_table_walk:
46 TRAP_LOAD_PGD_PHYS(%g7, %g5)
48 USER_PGTABLE_WALK_TL1(%g4, %g7, %g5, %g2, tsb_do_fault)
51 TSB_LOCK_TAG(%g1, %g2, %g7)
53 /* Load and check PTE. */
54 ldxa [%g5] ASI_PHYS_USE_EC, %g5
55 brgez,a,pn %g5, tsb_do_fault
58 /* If it is larger than the base page size, don't
59 * bother putting it into the TSB.
62 sethi %hi(_PAGE_ALL_SZ_BITS >> 32), %g7
64 sethi %hi(_PAGE_SZBITS >> 32), %g7
66 bne,a,pn %xcc, tsb_tlb_reload
69 TSB_WRITE(%g1, %g5, %g6)
71 /* Finally, load TLB and return from trap. */
73 cmp %g3, FAULT_CODE_DTLB
74 bne,pn %xcc, tsb_itlb_load
79 661: stxa %g5, [%g0] ASI_DTLB_DATA_IN
81 .section .sun4v_2insn_patch, "ax"
87 /* For sun4v the ASI_DTLB_DATA_IN store and the retry
88 * instruction get nop'd out and we get here to branch
89 * to the sun4v tlb load code. The registers are setup
96 * The sun4v TLB load wants the PTE in %g3 so we fix that
99 ba,pt %xcc, sun4v_dtlb_load
104 661: stxa %g5, [%g0] ASI_ITLB_DATA_IN
106 .section .sun4v_2insn_patch, "ax"
112 /* For sun4v the ASI_ITLB_DATA_IN store and the retry
113 * instruction get nop'd out and we get here to branch
114 * to the sun4v tlb load code. The registers are setup
121 * The sun4v TLB load wants the PTE in %g3 so we fix that
124 ba,pt %xcc, sun4v_itlb_load
127 /* No valid entry in the page tables, do full fault
133 cmp %g3, FAULT_CODE_DTLB
135 661: rdpr %pstate, %g5
136 wrpr %g5, PSTATE_AG | PSTATE_MG, %pstate
137 .section .sun4v_2insn_patch, "ax"
143 bne,pn %xcc, tsb_do_itlb_fault
150 661: mov TLB_TAG_ACCESS, %g4
151 ldxa [%g4] ASI_DMMU, %g5
152 .section .sun4v_2insn_patch, "ax"
158 be,pt %xcc, sparc64_realfault_common
159 mov FAULT_CODE_DTLB, %g4
160 ba,pt %xcc, winfix_trampoline
165 ba,pt %xcc, sparc64_realfault_common
166 mov FAULT_CODE_ITLB, %g4
168 .globl sparc64_realfault_common
169 sparc64_realfault_common:
170 /* fault code in %g4, fault address in %g5, etrap will
171 * preserve these two values in %l4 and %l5 respectively
173 ba,pt %xcc, etrap ! Save trap state
175 stb %l4, [%g6 + TI_FAULT_CODE] ! Save fault code
176 stx %l5, [%g6 + TI_FAULT_ADDR] ! Save fault address
177 call do_sparc64_fault ! Call fault handler
178 add %sp, PTREGS_OFF, %o0 ! Compute pt_regs arg
179 ba,pt %xcc, rtrap_clr_l6 ! Restore cpu state
180 nop ! Delay slot (fill me)
183 rdpr %tpc, %g3 ! Prepare winfixup TNPC
184 or %g3, 0x7c, %g3 ! Compute branch offset
185 wrpr %g3, %tnpc ! Write it into TNPC
188 /* Insert an entry into the TSB.
190 * %o0: TSB entry pointer (virt or phys address)
198 wrpr %o5, PSTATE_IE, %pstate
199 TSB_LOCK_TAG(%o0, %g2, %g3)
200 TSB_WRITE(%o0, %o2, %o1)
205 /* Flush the given TSB entry if it has the matching
208 * %o0: TSB entry pointer (virt or phys address)
214 sethi %hi(TSB_TAG_LOCK_HIGH), %g2
215 1: TSB_LOAD_TAG(%o0, %g1)
223 TSB_CAS_TAG(%o0, %g1, %o3)
230 /* Reload MMU related context switch state at
233 * %o0: page table physical address
234 * %o1: TSB register value
235 * %o2: TSB virtual address
236 * %o3: TSB mapping locked PTE
237 * %o4: Hypervisor TSB descriptor physical address
239 * We have to run this whole thing with interrupts
240 * disabled so that the current cpu doesn't change
244 .globl __tsb_context_switch
245 __tsb_context_switch:
247 wrpr %o5, PSTATE_IE, %pstate
249 ldub [%g6 + TI_CPU], %g1
250 sethi %hi(trap_block), %g2
251 sllx %g1, TRAP_BLOCK_SZ_SHIFT, %g1
252 or %g2, %lo(trap_block), %g2
254 stx %o0, [%g2 + TRAP_PER_CPU_PGD_PADDR]
256 sethi %hi(tlb_type), %g1
257 lduw [%g1 + %lo(tlb_type)], %g1
262 /* Hypervisor TSB switch. */
263 mov SCRATCHPAD_UTSBREG1, %g1
264 stxa %o1, [%g1] ASI_SCRATCHPAD
266 mov SCRATCHPAD_UTSBREG2, %g1
267 stxa %g2, [%g1] ASI_SCRATCHPAD
269 mov HV_FAST_MMU_TSB_CTXNON0, %o5
277 /* SUN4U TSB switch. */
279 stxa %o1, [%g1] ASI_DMMU
281 stxa %o1, [%g1] ASI_IMMU
287 sethi %hi(sparc64_highest_unlocked_tlb_ent), %g2
288 mov TLB_TAG_ACCESS, %g1
289 lduw [%g2 + %lo(sparc64_highest_unlocked_tlb_ent)], %g2
290 stxa %o2, [%g1] ASI_DMMU
293 stxa %o3, [%g2] ASI_DTLB_DATA_ACCESS