2 * 8253/8254 interval timer emulation
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 * Copyright (c) 2006 Intel Corporation
6 * Copyright (c) 2007 Keir Fraser, XenSource Inc
7 * Copyright (c) 2008 Intel Corporation
9 * Permission is hereby granted, free of charge, to any person obtaining a copy
10 * of this software and associated documentation files (the "Software"), to deal
11 * in the Software without restriction, including without limitation the rights
12 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
13 * copies of the Software, and to permit persons to whom the Software is
14 * furnished to do so, subject to the following conditions:
16 * The above copyright notice and this permission notice shall be included in
17 * all copies or substantial portions of the Software.
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
24 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
28 * Sheng Yang <sheng.yang@intel.com>
29 * Based on QEMU and Xen.
32 #include <linux/kvm_host.h>
38 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
40 #define mod_64(x, y) ((x) % (y))
43 #define RW_STATE_LSB 1
44 #define RW_STATE_MSB 2
45 #define RW_STATE_WORD0 3
46 #define RW_STATE_WORD1 4
48 /* Compute with 96 bit intermediate result: (a*b)/c */
49 static u64 muldiv64(u64 a, u32 b, u32 c)
60 rl = (u64)u.l.low * (u64)b;
61 rh = (u64)u.l.high * (u64)b;
63 res.l.high = div64_u64(rh, c);
64 res.l.low = div64_u64(((mod_64(rh, c) << 32) + (rl & 0xffffffff)), c);
68 static void pit_set_gate(struct kvm *kvm, int channel, u32 val)
70 struct kvm_kpit_channel_state *c =
71 &kvm->arch.vpit->pit_state.channels[channel];
73 WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock));
79 /* XXX: just disable/enable counting */
85 /* Restart counting on rising edge. */
87 c->count_load_time = ktime_get();
94 static int pit_get_gate(struct kvm *kvm, int channel)
96 WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock));
98 return kvm->arch.vpit->pit_state.channels[channel].gate;
101 static int pit_get_count(struct kvm *kvm, int channel)
103 struct kvm_kpit_channel_state *c =
104 &kvm->arch.vpit->pit_state.channels[channel];
108 WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock));
110 t = ktime_to_ns(ktime_sub(ktime_get(), c->count_load_time));
111 d = muldiv64(t, KVM_PIT_FREQ, NSEC_PER_SEC);
118 counter = (c->count - d) & 0xffff;
121 /* XXX: may be incorrect for odd counts */
122 counter = c->count - (mod_64((2 * d), c->count));
125 counter = c->count - mod_64(d, c->count);
131 static int pit_get_out(struct kvm *kvm, int channel)
133 struct kvm_kpit_channel_state *c =
134 &kvm->arch.vpit->pit_state.channels[channel];
138 WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock));
140 t = ktime_to_ns(ktime_sub(ktime_get(), c->count_load_time));
141 d = muldiv64(t, KVM_PIT_FREQ, NSEC_PER_SEC);
146 out = (d >= c->count);
149 out = (d < c->count);
152 out = ((mod_64(d, c->count) == 0) && (d != 0));
155 out = (mod_64(d, c->count) < ((c->count + 1) >> 1));
159 out = (d == c->count);
166 static void pit_latch_count(struct kvm *kvm, int channel)
168 struct kvm_kpit_channel_state *c =
169 &kvm->arch.vpit->pit_state.channels[channel];
171 WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock));
173 if (!c->count_latched) {
174 c->latched_count = pit_get_count(kvm, channel);
175 c->count_latched = c->rw_mode;
179 static void pit_latch_status(struct kvm *kvm, int channel)
181 struct kvm_kpit_channel_state *c =
182 &kvm->arch.vpit->pit_state.channels[channel];
184 WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock));
186 if (!c->status_latched) {
187 /* TODO: Return NULL COUNT (bit 6). */
188 c->status = ((pit_get_out(kvm, channel) << 7) |
192 c->status_latched = 1;
196 static int __pit_timer_fn(struct kvm_kpit_state *ps)
198 struct kvm_vcpu *vcpu0 = ps->pit->kvm->vcpus[0];
199 struct kvm_kpit_timer *pt = &ps->pit_timer;
201 if (!atomic_inc_and_test(&pt->pending))
202 set_bit(KVM_REQ_PENDING_TIMER, &vcpu0->requests);
205 atomic_set(&pt->pending, 1);
207 if (vcpu0 && waitqueue_active(&vcpu0->wq))
208 wake_up_interruptible(&vcpu0->wq);
210 hrtimer_add_expires_ns(&pt->timer, pt->period);
211 pt->scheduled = hrtimer_get_expires_ns(&pt->timer);
213 ps->channels[0].count_load_time = ktime_get();
215 return (pt->period == 0 ? 0 : 1);
218 int pit_has_pending_timer(struct kvm_vcpu *vcpu)
220 struct kvm_pit *pit = vcpu->kvm->arch.vpit;
222 if (pit && vcpu->vcpu_id == 0 && pit->pit_state.irq_ack)
223 return atomic_read(&pit->pit_state.pit_timer.pending);
227 static void kvm_pit_ack_irq(struct kvm_irq_ack_notifier *kian)
229 struct kvm_kpit_state *ps = container_of(kian, struct kvm_kpit_state,
231 spin_lock(&ps->inject_lock);
232 if (atomic_dec_return(&ps->pit_timer.pending) < 0)
233 atomic_inc(&ps->pit_timer.pending);
235 spin_unlock(&ps->inject_lock);
238 static enum hrtimer_restart pit_timer_fn(struct hrtimer *data)
240 struct kvm_kpit_state *ps;
241 int restart_timer = 0;
243 ps = container_of(data, struct kvm_kpit_state, pit_timer.timer);
245 restart_timer = __pit_timer_fn(ps);
248 return HRTIMER_RESTART;
250 return HRTIMER_NORESTART;
253 void __kvm_migrate_pit_timer(struct kvm_vcpu *vcpu)
255 struct kvm_pit *pit = vcpu->kvm->arch.vpit;
256 struct hrtimer *timer;
258 if (vcpu->vcpu_id != 0 || !pit)
261 timer = &pit->pit_state.pit_timer.timer;
262 if (hrtimer_cancel(timer))
263 hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
266 static void destroy_pit_timer(struct kvm_kpit_timer *pt)
268 pr_debug("pit: execute del timer!\n");
269 hrtimer_cancel(&pt->timer);
272 static void create_pit_timer(struct kvm_kpit_state *ps, u32 val, int is_period)
274 struct kvm_kpit_timer *pt = &ps->pit_timer;
277 interval = muldiv64(val, NSEC_PER_SEC, KVM_PIT_FREQ);
279 pr_debug("pit: create pit timer, interval is %llu nsec\n", interval);
281 /* TODO The new value only affected after the retriggered */
282 hrtimer_cancel(&pt->timer);
283 pt->period = (is_period == 0) ? 0 : interval;
284 pt->timer.function = pit_timer_fn;
285 atomic_set(&pt->pending, 0);
288 hrtimer_start(&pt->timer, ktime_add_ns(ktime_get(), interval),
292 static void pit_load_count(struct kvm *kvm, int channel, u32 val)
294 struct kvm_kpit_state *ps = &kvm->arch.vpit->pit_state;
296 WARN_ON(!mutex_is_locked(&ps->lock));
298 pr_debug("pit: load_count val is %d, channel is %d\n", val, channel);
301 * Though spec said the state of 8254 is undefined after power-up,
302 * seems some tricky OS like Windows XP depends on IRQ0 interrupt
304 * So here setting initialize rate for it, and not a specific number
309 ps->channels[channel].count_load_time = ktime_get();
310 ps->channels[channel].count = val;
315 /* Two types of timer
316 * mode 1 is one shot, mode 2 is period, otherwise del timer */
317 switch (ps->channels[0].mode) {
319 /* FIXME: enhance mode 4 precision */
321 create_pit_timer(ps, val, 0);
325 create_pit_timer(ps, val, 1);
328 destroy_pit_timer(&ps->pit_timer);
332 void kvm_pit_load_count(struct kvm *kvm, int channel, u32 val)
334 mutex_lock(&kvm->arch.vpit->pit_state.lock);
335 pit_load_count(kvm, channel, val);
336 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
339 static void pit_ioport_write(struct kvm_io_device *this,
340 gpa_t addr, int len, const void *data)
342 struct kvm_pit *pit = (struct kvm_pit *)this->private;
343 struct kvm_kpit_state *pit_state = &pit->pit_state;
344 struct kvm *kvm = pit->kvm;
346 struct kvm_kpit_channel_state *s;
347 u32 val = *(u32 *) data;
350 addr &= KVM_PIT_CHANNEL_MASK;
352 mutex_lock(&pit_state->lock);
355 pr_debug("pit: write addr is 0x%x, len is %d, val is 0x%x\n",
356 (unsigned int)addr, len, val);
361 /* Read-Back Command. */
362 for (channel = 0; channel < 3; channel++) {
363 s = &pit_state->channels[channel];
364 if (val & (2 << channel)) {
366 pit_latch_count(kvm, channel);
368 pit_latch_status(kvm, channel);
372 /* Select Counter <channel>. */
373 s = &pit_state->channels[channel];
374 access = (val >> 4) & KVM_PIT_CHANNEL_MASK;
376 pit_latch_count(kvm, channel);
379 s->read_state = access;
380 s->write_state = access;
381 s->mode = (val >> 1) & 7;
389 s = &pit_state->channels[addr];
390 switch (s->write_state) {
393 pit_load_count(kvm, addr, val);
396 pit_load_count(kvm, addr, val << 8);
399 s->write_latch = val;
400 s->write_state = RW_STATE_WORD1;
403 pit_load_count(kvm, addr, s->write_latch | (val << 8));
404 s->write_state = RW_STATE_WORD0;
409 mutex_unlock(&pit_state->lock);
412 static void pit_ioport_read(struct kvm_io_device *this,
413 gpa_t addr, int len, void *data)
415 struct kvm_pit *pit = (struct kvm_pit *)this->private;
416 struct kvm_kpit_state *pit_state = &pit->pit_state;
417 struct kvm *kvm = pit->kvm;
419 struct kvm_kpit_channel_state *s;
421 addr &= KVM_PIT_CHANNEL_MASK;
422 s = &pit_state->channels[addr];
424 mutex_lock(&pit_state->lock);
426 if (s->status_latched) {
427 s->status_latched = 0;
429 } else if (s->count_latched) {
430 switch (s->count_latched) {
433 ret = s->latched_count & 0xff;
434 s->count_latched = 0;
437 ret = s->latched_count >> 8;
438 s->count_latched = 0;
441 ret = s->latched_count & 0xff;
442 s->count_latched = RW_STATE_MSB;
446 switch (s->read_state) {
449 count = pit_get_count(kvm, addr);
453 count = pit_get_count(kvm, addr);
454 ret = (count >> 8) & 0xff;
457 count = pit_get_count(kvm, addr);
459 s->read_state = RW_STATE_WORD1;
462 count = pit_get_count(kvm, addr);
463 ret = (count >> 8) & 0xff;
464 s->read_state = RW_STATE_WORD0;
469 if (len > sizeof(ret))
471 memcpy(data, (char *)&ret, len);
473 mutex_unlock(&pit_state->lock);
476 static int pit_in_range(struct kvm_io_device *this, gpa_t addr,
477 int len, int is_write)
479 return ((addr >= KVM_PIT_BASE_ADDRESS) &&
480 (addr < KVM_PIT_BASE_ADDRESS + KVM_PIT_MEM_LENGTH));
483 static void speaker_ioport_write(struct kvm_io_device *this,
484 gpa_t addr, int len, const void *data)
486 struct kvm_pit *pit = (struct kvm_pit *)this->private;
487 struct kvm_kpit_state *pit_state = &pit->pit_state;
488 struct kvm *kvm = pit->kvm;
489 u32 val = *(u32 *) data;
491 mutex_lock(&pit_state->lock);
492 pit_state->speaker_data_on = (val >> 1) & 1;
493 pit_set_gate(kvm, 2, val & 1);
494 mutex_unlock(&pit_state->lock);
497 static void speaker_ioport_read(struct kvm_io_device *this,
498 gpa_t addr, int len, void *data)
500 struct kvm_pit *pit = (struct kvm_pit *)this->private;
501 struct kvm_kpit_state *pit_state = &pit->pit_state;
502 struct kvm *kvm = pit->kvm;
503 unsigned int refresh_clock;
506 /* Refresh clock toggles at about 15us. We approximate as 2^14ns. */
507 refresh_clock = ((unsigned int)ktime_to_ns(ktime_get()) >> 14) & 1;
509 mutex_lock(&pit_state->lock);
510 ret = ((pit_state->speaker_data_on << 1) | pit_get_gate(kvm, 2) |
511 (pit_get_out(kvm, 2) << 5) | (refresh_clock << 4));
512 if (len > sizeof(ret))
514 memcpy(data, (char *)&ret, len);
515 mutex_unlock(&pit_state->lock);
518 static int speaker_in_range(struct kvm_io_device *this, gpa_t addr,
519 int len, int is_write)
521 return (addr == KVM_SPEAKER_BASE_ADDRESS);
524 void kvm_pit_reset(struct kvm_pit *pit)
527 struct kvm_kpit_channel_state *c;
529 mutex_lock(&pit->pit_state.lock);
530 for (i = 0; i < 3; i++) {
531 c = &pit->pit_state.channels[i];
534 pit_load_count(pit->kvm, i, 0);
536 mutex_unlock(&pit->pit_state.lock);
538 atomic_set(&pit->pit_state.pit_timer.pending, 0);
539 pit->pit_state.irq_ack = 1;
542 static void pit_mask_notifer(struct kvm_irq_mask_notifier *kimn, bool mask)
544 struct kvm_pit *pit = container_of(kimn, struct kvm_pit, mask_notifier);
547 atomic_set(&pit->pit_state.pit_timer.pending, 0);
548 pit->pit_state.irq_ack = 1;
552 struct kvm_pit *kvm_create_pit(struct kvm *kvm)
555 struct kvm_kpit_state *pit_state;
557 pit = kzalloc(sizeof(struct kvm_pit), GFP_KERNEL);
561 pit->irq_source_id = kvm_request_irq_source_id(kvm);
562 if (pit->irq_source_id < 0) {
567 mutex_init(&pit->pit_state.lock);
568 mutex_lock(&pit->pit_state.lock);
569 spin_lock_init(&pit->pit_state.inject_lock);
571 /* Initialize PIO device */
572 pit->dev.read = pit_ioport_read;
573 pit->dev.write = pit_ioport_write;
574 pit->dev.in_range = pit_in_range;
575 pit->dev.private = pit;
576 kvm_io_bus_register_dev(&kvm->pio_bus, &pit->dev);
578 pit->speaker_dev.read = speaker_ioport_read;
579 pit->speaker_dev.write = speaker_ioport_write;
580 pit->speaker_dev.in_range = speaker_in_range;
581 pit->speaker_dev.private = pit;
582 kvm_io_bus_register_dev(&kvm->pio_bus, &pit->speaker_dev);
584 kvm->arch.vpit = pit;
587 pit_state = &pit->pit_state;
588 pit_state->pit = pit;
589 hrtimer_init(&pit_state->pit_timer.timer,
590 CLOCK_MONOTONIC, HRTIMER_MODE_ABS);
591 pit_state->irq_ack_notifier.gsi = 0;
592 pit_state->irq_ack_notifier.irq_acked = kvm_pit_ack_irq;
593 kvm_register_irq_ack_notifier(kvm, &pit_state->irq_ack_notifier);
594 pit_state->pit_timer.reinject = true;
595 mutex_unlock(&pit->pit_state.lock);
599 pit->mask_notifier.func = pit_mask_notifer;
600 kvm_register_irq_mask_notifier(kvm, 0, &pit->mask_notifier);
605 void kvm_free_pit(struct kvm *kvm)
607 struct hrtimer *timer;
609 if (kvm->arch.vpit) {
610 kvm_unregister_irq_mask_notifier(kvm, 0,
611 &kvm->arch.vpit->mask_notifier);
612 mutex_lock(&kvm->arch.vpit->pit_state.lock);
613 timer = &kvm->arch.vpit->pit_state.pit_timer.timer;
614 hrtimer_cancel(timer);
615 kvm_free_irq_source_id(kvm, kvm->arch.vpit->irq_source_id);
616 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
617 kfree(kvm->arch.vpit);
621 static void __inject_pit_timer_intr(struct kvm *kvm)
623 struct kvm_vcpu *vcpu;
626 mutex_lock(&kvm->lock);
627 kvm_set_irq(kvm, kvm->arch.vpit->irq_source_id, 0, 1);
628 kvm_set_irq(kvm, kvm->arch.vpit->irq_source_id, 0, 0);
629 mutex_unlock(&kvm->lock);
632 * Provides NMI watchdog support via Virtual Wire mode.
633 * The route is: PIT -> PIC -> LVT0 in NMI mode.
635 * Note: Our Virtual Wire implementation is simplified, only
636 * propagating PIT interrupts to all VCPUs when they have set
637 * LVT0 to NMI delivery. Other PIC interrupts are just sent to
638 * VCPU0, and only if its LVT0 is in EXTINT mode.
640 if (kvm->arch.vapics_in_nmi_mode > 0)
641 for (i = 0; i < KVM_MAX_VCPUS; ++i) {
642 vcpu = kvm->vcpus[i];
644 kvm_apic_nmi_wd_deliver(vcpu);
648 void kvm_inject_pit_timer_irqs(struct kvm_vcpu *vcpu)
650 struct kvm_pit *pit = vcpu->kvm->arch.vpit;
651 struct kvm *kvm = vcpu->kvm;
652 struct kvm_kpit_state *ps;
656 ps = &pit->pit_state;
658 /* Try to inject pending interrupts when
659 * last one has been acked.
661 spin_lock(&ps->inject_lock);
662 if (atomic_read(&ps->pit_timer.pending) && ps->irq_ack) {
666 spin_unlock(&ps->inject_lock);
668 __inject_pit_timer_intr(kvm);