git.oblomov.eu Git - linux-2.6/blob - drivers/scsi/a100u2w.c

   1 /*
   2  * Initio A100 device driver for Linux.
   3  *
   4  * Copyright (c) 1994-1998 Initio Corporation
   5  * Copyright (c) 2003-2004 Christoph Hellwig
   6  * All rights reserved.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2, or (at your option)
  11  * any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; see the file COPYING.  If not, write to
  20  * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
  21  *
  22  * --------------------------------------------------------------------------
  23  *
  24  * Redistribution and use in source and binary forms, with or without
  25  * modification, are permitted provided that the following conditions
  26  * are met:
  27  * 1. Redistributions of source code must retain the above copyright
  28  *    notice, this list of conditions, and the following disclaimer,
  29  *    without modification, immediately at the beginning of the file.
  30  * 2. Redistributions in binary form must reproduce the above copyright
  31  *    notice, this list of conditions and the following disclaimer in the
  32  *    documentation and/or other materials provided with the distribution.
  33  * 3. The name of the author may not be used to endorse or promote products
  34  *    derived from this software without specific prior written permission.
  35  *
  36  * Where this Software is combined with software released under the terms of
  37  * the GNU General Public License ("GPL") and the terms of the GPL would require the
  38  * combined work to also be released under the terms of the GPL, the terms
  39  * and conditions of this License will apply in addition to those of the
  40  * GPL with the exception of any terms or conditions of this License that
  41  * conflict with, or are expressly prohibited by, the GPL.
  42  *
  43  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  44  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  45  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  46  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
  47  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  48  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  49  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  50  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  51  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  52  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  53  * SUCH DAMAGE.
  54  */
  55
  56 /*
  57  * Revision History:
  58  * 07/02/98 hl  - v.91n Initial drivers.
  59  * 09/14/98 hl - v1.01 Support new Kernel.
  60  * 09/22/98 hl - v1.01a Support reset.
  61  * 09/24/98 hl - v1.01b Fixed reset.
  62  * 10/05/98 hl - v1.02 split the source code and release.
  63  * 12/19/98 bv - v1.02a Use spinlocks for 2.1.95 and up
  64  * 01/31/99 bv - v1.02b Use mdelay instead of waitForPause
  65  * 08/08/99 bv - v1.02c Use waitForPause again.
  66  * 06/25/02 Doug Ledford <dledford@redhat.com> - v1.02d
  67  *          - Remove limit on number of controllers
  68  *          - Port to DMA mapping API
  69  *          - Clean up interrupt handler registration
  70  *          - Fix memory leaks
  71  *          - Fix allocation of scsi host structs and private data
  72  * 11/18/03 Christoph Hellwig <hch@lst.de>
  73  *          - Port to new probing API
  74  *          - Fix some more leaks in init failure cases
  75  * 9/28/04 Christoph Hellwig <hch@lst.de>
  76  *          - merge the two source files
  77  *          - remove internal queueing code
  78  */
  79
  80 #include <linux/module.h>
  81 #include <linux/errno.h>
  82 #include <linux/delay.h>
  83 #include <linux/interrupt.h>
  84 #include <linux/pci.h>
  85 #include <linux/init.h>
  86 #include <linux/blkdev.h>
  87 #include <linux/spinlock.h>
  88 #include <linux/kernel.h>
  89 #include <linux/string.h>
  90 #include <linux/ioport.h>
  91 #include <linux/slab.h>
  92
  93 #include <asm/io.h>
  94 #include <asm/irq.h>
  95
  96 #include <scsi/scsi.h>
  97 #include <scsi/scsi_cmnd.h>
  98 #include <scsi/scsi_device.h>
  99 #include <scsi/scsi_host.h>
 100
 101 #include "a100u2w.h"
 102
 103
 104 #define JIFFIES_TO_MS(t) ((t) * 1000 / HZ)
 105 #define MS_TO_JIFFIES(j) ((j * HZ) / 1000)
 106
 107 static ORC_SCB *orc_alloc_scb(ORC_HCS * hcsp);
 108 static void inia100SCBPost(BYTE * pHcb, BYTE * pScb);
 109
 110 static NVRAM nvram, *nvramp = &nvram;
 111 static UCHAR dftNvRam[64] =
 112 {
 113 /*----------header -------------*/
 114         0x01,                   /* 0x00: Sub System Vendor ID 0 */
 115         0x11,                   /* 0x01: Sub System Vendor ID 1 */
 116         0x60,                   /* 0x02: Sub System ID 0        */
 117         0x10,                   /* 0x03: Sub System ID 1        */
 118         0x00,                   /* 0x04: SubClass               */
 119         0x01,                   /* 0x05: Vendor ID 0            */
 120         0x11,                   /* 0x06: Vendor ID 1            */
 121         0x60,                   /* 0x07: Device ID 0            */
 122         0x10,                   /* 0x08: Device ID 1            */
 123         0x00,                   /* 0x09: Reserved               */
 124         0x00,                   /* 0x0A: Reserved               */
 125         0x01,                   /* 0x0B: Revision of Data Structure     */
 126                                 /* -- Host Adapter Structure --- */
 127         0x01,                   /* 0x0C: Number Of SCSI Channel */
 128         0x01,                   /* 0x0D: BIOS Configuration 1   */
 129         0x00,                   /* 0x0E: BIOS Configuration 2   */
 130         0x00,                   /* 0x0F: BIOS Configuration 3   */
 131                                 /* --- SCSI Channel 0 Configuration --- */
 132         0x07,                   /* 0x10: H/A ID                 */
 133         0x83,                   /* 0x11: Channel Configuration  */
 134         0x20,                   /* 0x12: MAX TAG per target     */
 135         0x0A,                   /* 0x13: SCSI Reset Recovering time     */
 136         0x00,                   /* 0x14: Channel Configuration4 */
 137         0x00,                   /* 0x15: Channel Configuration5 */
 138                                 /* SCSI Channel 0 Target Configuration  */
 139                                 /* 0x16-0x25                    */
 140         0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8,
 141         0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8,
 142                                 /* --- SCSI Channel 1 Configuration --- */
 143         0x07,                   /* 0x26: H/A ID                 */
 144         0x83,                   /* 0x27: Channel Configuration  */
 145         0x20,                   /* 0x28: MAX TAG per target     */
 146         0x0A,                   /* 0x29: SCSI Reset Recovering time     */
 147         0x00,                   /* 0x2A: Channel Configuration4 */
 148         0x00,                   /* 0x2B: Channel Configuration5 */
 149                                 /* SCSI Channel 1 Target Configuration  */
 150                                 /* 0x2C-0x3B                    */
 151         0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8,
 152         0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8,
 153         0x00,                   /* 0x3C: Reserved               */
 154         0x00,                   /* 0x3D: Reserved               */
 155         0x00,                   /* 0x3E: Reserved               */
 156         0x00                    /* 0x3F: Checksum               */
 157 };
 158
 159
 160 /***************************************************************************/
 161 static void waitForPause(unsigned amount)
 162 {
 163         ULONG the_time = jiffies + MS_TO_JIFFIES(amount);
 164         while (time_before_eq(jiffies, the_time))
 165                 cpu_relax();
 166 }
 167
 168 /***************************************************************************/
 169 static UCHAR waitChipReady(ORC_HCS * hcsp)
 170 {
 171         int i;
 172
 173         for (i = 0; i < 10; i++) {      /* Wait 1 second for report timeout     */
 174                 if (ORC_RD(hcsp->HCS_Base, ORC_HCTRL) & HOSTSTOP)       /* Wait HOSTSTOP set */
 175                         return 1;
 176                 waitForPause(100);      /* wait 100ms before try again  */
 177         }
 178         return 0;
 179 }
 180
 181 /***************************************************************************/
 182 static UCHAR waitFWReady(ORC_HCS * hcsp)
 183 {
 184         int i;
 185
 186         for (i = 0; i < 10; i++) {      /* Wait 1 second for report timeout     */
 187                 if (ORC_RD(hcsp->HCS_Base, ORC_HSTUS) & RREADY)         /* Wait READY set */
 188                         return 1;
 189                 waitForPause(100);      /* wait 100ms before try again  */
 190         }
 191         return 0;
 192 }
 193
 194 /***************************************************************************/
 195 static UCHAR waitSCSIRSTdone(ORC_HCS * hcsp)
 196 {
 197         int i;
 198
 199         for (i = 0; i < 10; i++) {      /* Wait 1 second for report timeout     */
 200                 if (!(ORC_RD(hcsp->HCS_Base, ORC_HCTRL) & SCSIRST))     /* Wait SCSIRST done */
 201                         return 1;
 202                 waitForPause(100);      /* wait 100ms before try again  */
 203         }
 204         return 0;
 205 }
 206
 207 /***************************************************************************/
 208 static UCHAR waitHDOoff(ORC_HCS * hcsp)
 209 {
 210         int i;
 211
 212         for (i = 0; i < 10; i++) {      /* Wait 1 second for report timeout     */
 213                 if (!(ORC_RD(hcsp->HCS_Base, ORC_HCTRL) & HDO))         /* Wait HDO off */
 214                         return 1;
 215                 waitForPause(100);      /* wait 100ms before try again  */
 216         }
 217         return 0;
 218 }
 219
 220 /***************************************************************************/
 221 static UCHAR waitHDIset(ORC_HCS * hcsp, UCHAR * pData)
 222 {
 223         int i;
 224
 225         for (i = 0; i < 10; i++) {      /* Wait 1 second for report timeout     */
 226                 if ((*pData = ORC_RD(hcsp->HCS_Base, ORC_HSTUS)) & HDI)
 227                         return 1;       /* Wait HDI set */
 228                 waitForPause(100);      /* wait 100ms before try again  */
 229         }
 230         return 0;
 231 }
 232
 233 /***************************************************************************/
 234 static unsigned short get_FW_version(ORC_HCS * hcsp)
 235 {
 236         UCHAR bData;
 237         union {
 238                 unsigned short sVersion;
 239                 unsigned char cVersion[2];
 240         } Version;
 241
 242         ORC_WR(hcsp->HCS_Base + ORC_HDATA, ORC_CMD_VERSION);
 243         ORC_WR(hcsp->HCS_Base + ORC_HCTRL, HDO);
 244         if (waitHDOoff(hcsp) == 0)      /* Wait HDO off   */
 245                 return 0;
 246
 247         if (waitHDIset(hcsp, &bData) == 0)      /* Wait HDI set   */
 248                 return 0;
 249         Version.cVersion[0] = ORC_RD(hcsp->HCS_Base, ORC_HDATA);
 250         ORC_WR(hcsp->HCS_Base + ORC_HSTUS, bData);      /* Clear HDI            */
 251
 252         if (waitHDIset(hcsp, &bData) == 0)      /* Wait HDI set   */
 253                 return 0;
 254         Version.cVersion[1] = ORC_RD(hcsp->HCS_Base, ORC_HDATA);
 255         ORC_WR(hcsp->HCS_Base + ORC_HSTUS, bData);      /* Clear HDI            */
 256
 257         return (Version.sVersion);
 258 }
 259
 260 /***************************************************************************/
 261 static UCHAR set_NVRAM(ORC_HCS * hcsp, unsigned char address, unsigned char value)
 262 {
 263         ORC_WR(hcsp->HCS_Base + ORC_HDATA, ORC_CMD_SET_NVM);    /* Write command */
 264         ORC_WR(hcsp->HCS_Base + ORC_HCTRL, HDO);
 265         if (waitHDOoff(hcsp) == 0)      /* Wait HDO off   */
 266                 return 0;
 267
 268         ORC_WR(hcsp->HCS_Base + ORC_HDATA, address);    /* Write address */
 269         ORC_WR(hcsp->HCS_Base + ORC_HCTRL, HDO);
 270         if (waitHDOoff(hcsp) == 0)      /* Wait HDO off   */
 271                 return 0;
 272
 273         ORC_WR(hcsp->HCS_Base + ORC_HDATA, value);      /* Write value  */
 274         ORC_WR(hcsp->HCS_Base + ORC_HCTRL, HDO);
 275         if (waitHDOoff(hcsp) == 0)      /* Wait HDO off   */
 276                 return 0;
 277
 278         return 1;
 279 }
 280
 281 /***************************************************************************/
 282 static UCHAR get_NVRAM(ORC_HCS * hcsp, unsigned char address, unsigned char *pDataIn)
 283 {
 284         unsigned char bData;
 285
 286         ORC_WR(hcsp->HCS_Base + ORC_HDATA, ORC_CMD_GET_NVM);    /* Write command */
 287         ORC_WR(hcsp->HCS_Base + ORC_HCTRL, HDO);
 288         if (waitHDOoff(hcsp) == 0)      /* Wait HDO off   */
 289                 return 0;
 290
 291         ORC_WR(hcsp->HCS_Base + ORC_HDATA, address);    /* Write address */
 292         ORC_WR(hcsp->HCS_Base + ORC_HCTRL, HDO);
 293         if (waitHDOoff(hcsp) == 0)      /* Wait HDO off   */
 294                 return 0;
 295
 296         if (waitHDIset(hcsp, &bData) == 0)      /* Wait HDI set   */
 297                 return 0;
 298         *pDataIn = ORC_RD(hcsp->HCS_Base, ORC_HDATA);
 299         ORC_WR(hcsp->HCS_Base + ORC_HSTUS, bData);      /* Clear HDI    */
 300
 301         return 1;
 302 }
 303
 304 /***************************************************************************/
 305 static void orc_exec_scb(ORC_HCS * hcsp, ORC_SCB * scbp)
 306 {
 307         scbp->SCB_Status = ORCSCB_POST;
 308         ORC_WR(hcsp->HCS_Base + ORC_PQUEUE, scbp->SCB_ScbIdx);
 309         return;
 310 }
 311
 312
 313 /***********************************************************************
 314  Read SCSI H/A configuration parameters from serial EEPROM
 315 ************************************************************************/
 316 static int se2_rd_all(ORC_HCS * hcsp)
 317 {
 318         int i;
 319         UCHAR *np, chksum = 0;
 320
 321         np = (UCHAR *) nvramp;
 322         for (i = 0; i < 64; i++, np++) {        /* <01> */
 323                 if (get_NVRAM(hcsp, (unsigned char) i, np) == 0)
 324                         return -1;
 325 //      *np++ = get_NVRAM(hcsp, (unsigned char ) i);
 326         }
 327
 328 /*------ Is ckecksum ok ? ------*/
 329         np = (UCHAR *) nvramp;
 330         for (i = 0; i < 63; i++)
 331                 chksum += *np++;
 332
 333         if (nvramp->CheckSum != (UCHAR) chksum)
 334                 return -1;
 335         return 1;
 336 }
 337
 338 /************************************************************************
 339  Update SCSI H/A configuration parameters from serial EEPROM
 340 *************************************************************************/
 341 static void se2_update_all(ORC_HCS * hcsp)
 342 {                               /* setup default pattern  */
 343         int i;
 344         UCHAR *np, *np1, chksum = 0;
 345
 346         /* Calculate checksum first   */
 347         np = (UCHAR *) dftNvRam;
 348         for (i = 0; i < 63; i++)
 349                 chksum += *np++;
 350         *np = chksum;
 351
 352         np = (UCHAR *) dftNvRam;
 353         np1 = (UCHAR *) nvramp;
 354         for (i = 0; i < 64; i++, np++, np1++) {
 355                 if (*np != *np1) {
 356                         set_NVRAM(hcsp, (unsigned char) i, *np);
 357                 }
 358         }
 359         return;
 360 }
 361
 362 /*************************************************************************
 363  Function name  : read_eeprom
 364 **************************************************************************/
 365 static void read_eeprom(ORC_HCS * hcsp)
 366 {
 367         if (se2_rd_all(hcsp) != 1) {
 368                 se2_update_all(hcsp);   /* setup default pattern        */
 369                 se2_rd_all(hcsp);       /* load again                   */
 370         }
 371 }
 372
 373
 374 /***************************************************************************/
 375 static UCHAR load_FW(ORC_HCS * hcsp)
 376 {
 377         U32 dData;
 378         USHORT wBIOSAddress;
 379         USHORT i;
 380         UCHAR *pData, bData;
 381
 382
 383         bData = ORC_RD(hcsp->HCS_Base, ORC_GCFG);
 384         ORC_WR(hcsp->HCS_Base + ORC_GCFG, bData | EEPRG);       /* Enable EEPROM programming */
 385         ORC_WR(hcsp->HCS_Base + ORC_EBIOSADR2, 0x00);
 386         ORC_WRSHORT(hcsp->HCS_Base + ORC_EBIOSADR0, 0x00);
 387         if (ORC_RD(hcsp->HCS_Base, ORC_EBIOSDATA) != 0x55) {
 388                 ORC_WR(hcsp->HCS_Base + ORC_GCFG, bData);       /* Disable EEPROM programming */
 389                 return 0;
 390         }
 391         ORC_WRSHORT(hcsp->HCS_Base + ORC_EBIOSADR0, 0x01);
 392         if (ORC_RD(hcsp->HCS_Base, ORC_EBIOSDATA) != 0xAA) {
 393                 ORC_WR(hcsp->HCS_Base + ORC_GCFG, bData);       /* Disable EEPROM programming */
 394                 return 0;
 395         }
 396         ORC_WR(hcsp->HCS_Base + ORC_RISCCTL, PRGMRST | DOWNLOAD);       /* Enable SRAM programming */
 397         pData = (UCHAR *) & dData;
 398         dData = 0;              /* Initial FW address to 0 */
 399         ORC_WRSHORT(hcsp->HCS_Base + ORC_EBIOSADR0, 0x10);
 400         *pData = ORC_RD(hcsp->HCS_Base, ORC_EBIOSDATA);         /* Read from BIOS */
 401         ORC_WRSHORT(hcsp->HCS_Base + ORC_EBIOSADR0, 0x11);
 402         *(pData + 1) = ORC_RD(hcsp->HCS_Base, ORC_EBIOSDATA);   /* Read from BIOS */
 403         ORC_WRSHORT(hcsp->HCS_Base + ORC_EBIOSADR0, 0x12);
 404         *(pData + 2) = ORC_RD(hcsp->HCS_Base, ORC_EBIOSDATA);   /* Read from BIOS */
 405         ORC_WR(hcsp->HCS_Base + ORC_EBIOSADR2, *(pData + 2));
 406         ORC_WRLONG(hcsp->HCS_Base + ORC_FWBASEADR, dData);      /* Write FW address */
 407
 408         wBIOSAddress = (USHORT) dData;  /* FW code locate at BIOS address + ? */
 409         for (i = 0, pData = (UCHAR *) & dData;  /* Download the code    */
 410              i < 0x1000;        /* Firmware code size = 4K      */
 411              i++, wBIOSAddress++) {
 412                 ORC_WRSHORT(hcsp->HCS_Base + ORC_EBIOSADR0, wBIOSAddress);
 413                 *pData++ = ORC_RD(hcsp->HCS_Base, ORC_EBIOSDATA);       /* Read from BIOS */
 414                 if ((i % 4) == 3) {
 415                         ORC_WRLONG(hcsp->HCS_Base + ORC_RISCRAM, dData);        /* Write every 4 bytes */
 416                         pData = (UCHAR *) & dData;
 417                 }
 418         }
 419
 420         ORC_WR(hcsp->HCS_Base + ORC_RISCCTL, PRGMRST | DOWNLOAD);       /* Reset program count 0 */
 421         wBIOSAddress -= 0x1000; /* Reset the BIOS adddress      */
 422         for (i = 0, pData = (UCHAR *) & dData;  /* Check the code       */
 423              i < 0x1000;        /* Firmware code size = 4K      */
 424              i++, wBIOSAddress++) {
 425                 ORC_WRSHORT(hcsp->HCS_Base + ORC_EBIOSADR0, wBIOSAddress);
 426                 *pData++ = ORC_RD(hcsp->HCS_Base, ORC_EBIOSDATA);       /* Read from BIOS */
 427                 if ((i % 4) == 3) {
 428                         if (ORC_RDLONG(hcsp->HCS_Base, ORC_RISCRAM) != dData) {
 429                                 ORC_WR(hcsp->HCS_Base + ORC_RISCCTL, PRGMRST);  /* Reset program to 0 */
 430                                 ORC_WR(hcsp->HCS_Base + ORC_GCFG, bData);       /*Disable EEPROM programming */
 431                                 return 0;
 432                         }
 433                         pData = (UCHAR *) & dData;
 434                 }
 435         }
 436         ORC_WR(hcsp->HCS_Base + ORC_RISCCTL, PRGMRST);  /* Reset program to 0   */
 437         ORC_WR(hcsp->HCS_Base + ORC_GCFG, bData);       /* Disable EEPROM programming */
 438         return 1;
 439 }
 440
 441 /***************************************************************************/
 442 static void setup_SCBs(ORC_HCS * hcsp)
 443 {
 444         ORC_SCB *pVirScb;
 445         int i;
 446         ESCB *pVirEscb;
 447         dma_addr_t pPhysEscb;
 448
 449         /* Setup SCB HCS_Base and SCB Size registers */
 450         ORC_WR(hcsp->HCS_Base + ORC_SCBSIZE, ORC_MAXQUEUE);     /* Total number of SCBs */
 451         /* SCB HCS_Base address 0      */
 452         ORC_WRLONG(hcsp->HCS_Base + ORC_SCBBASE0, hcsp->HCS_physScbArray);
 453         /* SCB HCS_Base address 1      */
 454         ORC_WRLONG(hcsp->HCS_Base + ORC_SCBBASE1, hcsp->HCS_physScbArray);
 455
 456         /* setup scatter list address with one buffer */
 457         pVirScb = hcsp->HCS_virScbArray;
 458         pVirEscb = hcsp->HCS_virEscbArray;
 459
 460         for (i = 0; i < ORC_MAXQUEUE; i++) {
 461                 pPhysEscb = (hcsp->HCS_physEscbArray + (sizeof(ESCB) * i));
 462                 pVirScb->SCB_SGPAddr = (U32) pPhysEscb;
 463                 pVirScb->SCB_SensePAddr = (U32) pPhysEscb;
 464                 pVirScb->SCB_EScb = pVirEscb;
 465                 pVirScb->SCB_ScbIdx = i;
 466                 pVirScb++;
 467                 pVirEscb++;
 468         }
 469
 470         return;
 471 }
 472
 473 /***************************************************************************/
 474 static void initAFlag(ORC_HCS * hcsp)
 475 {
 476         UCHAR i, j;
 477
 478         for (i = 0; i < MAX_CHANNELS; i++) {
 479                 for (j = 0; j < 8; j++) {
 480                         hcsp->BitAllocFlag[i][j] = 0xffffffff;
 481                 }
 482         }
 483 }
 484
 485 /***************************************************************************/
 486 static int init_orchid(ORC_HCS * hcsp)
 487 {
 488         UBYTE *readBytep;
 489         USHORT revision;
 490         UCHAR i;
 491
 492         initAFlag(hcsp);
 493         ORC_WR(hcsp->HCS_Base + ORC_GIMSK, 0xFF);       /* Disable all interrupt        */
 494         if (ORC_RD(hcsp->HCS_Base, ORC_HSTUS) & RREADY) {       /* Orchid is ready              */
 495                 revision = get_FW_version(hcsp);
 496                 if (revision == 0xFFFF) {
 497                         ORC_WR(hcsp->HCS_Base + ORC_HCTRL, DEVRST);     /* Reset Host Adapter   */
 498                         if (waitChipReady(hcsp) == 0)
 499                                 return (-1);
 500                         load_FW(hcsp);  /* Download FW                  */
 501                         setup_SCBs(hcsp);       /* Setup SCB HCS_Base and SCB Size registers */
 502                         ORC_WR(hcsp->HCS_Base + ORC_HCTRL, 0);  /* clear HOSTSTOP       */
 503                         if (waitFWReady(hcsp) == 0)
 504                                 return (-1);
 505                         /* Wait for firmware ready     */
 506                 } else {
 507                         setup_SCBs(hcsp);       /* Setup SCB HCS_Base and SCB Size registers */
 508                 }
 509         } else {                /* Orchid is not Ready          */
 510                 ORC_WR(hcsp->HCS_Base + ORC_HCTRL, DEVRST);     /* Reset Host Adapter   */
 511                 if (waitChipReady(hcsp) == 0)
 512                         return (-1);
 513                 load_FW(hcsp);  /* Download FW                  */
 514                 setup_SCBs(hcsp);       /* Setup SCB HCS_Base and SCB Size registers */
 515                 ORC_WR(hcsp->HCS_Base + ORC_HCTRL, HDO);        /* Do Hardware Reset &  */
 516
 517                 /*     clear HOSTSTOP  */
 518                 if (waitFWReady(hcsp) == 0)             /* Wait for firmware ready      */
 519                         return (-1);
 520         }
 521
 522 /*------------- get serial EEProm settting -------*/
 523
 524         read_eeprom(hcsp);
 525
 526         if (nvramp->Revision != 1)
 527                 return (-1);
 528
 529         hcsp->HCS_SCSI_ID = nvramp->SCSI0Id;
 530         hcsp->HCS_BIOS = nvramp->BIOSConfig1;
 531         hcsp->HCS_MaxTar = MAX_TARGETS;
 532         readBytep = (UCHAR *) & (nvramp->Target00Config);
 533         for (i = 0; i < 16; readBytep++, i++) {
 534                 hcsp->TargetFlag[i] = *readBytep;
 535                 hcsp->MaximumTags[i] = ORC_MAXTAGS;
 536         }                       /* for                          */
 537
 538         if (nvramp->SCSI0Config & NCC_BUSRESET) {       /* Reset SCSI bus               */
 539                 hcsp->HCS_Flags |= HCF_SCSI_RESET;
 540         }
 541         ORC_WR(hcsp->HCS_Base + ORC_GIMSK, 0xFB);       /* enable RP FIFO interrupt     */
 542         return (0);
 543 }
 544
 545 /*****************************************************************************
 546  Function name  : orc_reset_scsi_bus
 547  Description    : Reset registers, reset a hanging bus and
 548                   kill active and disconnected commands for target w/o soft reset
 549  Input          : pHCB  -       Pointer to host adapter structure
 550  Output         : None.
 551  Return         : pSRB  -       Pointer to SCSI request block.
 552 *****************************************************************************/
 553 static int orc_reset_scsi_bus(ORC_HCS * pHCB)
 554 {                               /* I need Host Control Block Information */
 555         ULONG flags;
 556
 557         spin_lock_irqsave(&(pHCB->BitAllocFlagLock), flags);
 558
 559         initAFlag(pHCB);
 560         /* reset scsi bus */
 561         ORC_WR(pHCB->HCS_Base + ORC_HCTRL, SCSIRST);
 562         if (waitSCSIRSTdone(pHCB) == 0) {
 563                 spin_unlock_irqrestore(&(pHCB->BitAllocFlagLock), flags);
 564                 return FAILED;
 565         } else {
 566                 spin_unlock_irqrestore(&(pHCB->BitAllocFlagLock), flags);
 567                 return SUCCESS;
 568         }
 569 }
 570
 571 /*****************************************************************************
 572  Function name  : orc_device_reset
 573  Description    : Reset registers, reset a hanging bus and
 574                   kill active and disconnected commands for target w/o soft reset
 575  Input          : pHCB  -       Pointer to host adapter structure
 576  Output         : None.
 577  Return         : pSRB  -       Pointer to SCSI request block.
 578 *****************************************************************************/
 579 static int orc_device_reset(ORC_HCS * pHCB, struct scsi_cmnd *SCpnt, unsigned int target)
 580 {                               /* I need Host Control Block Information */
 581         ORC_SCB *pScb;
 582         ESCB *pVirEscb;
 583         ORC_SCB *pVirScb;
 584         UCHAR i;
 585         ULONG flags;
 586
 587         spin_lock_irqsave(&(pHCB->BitAllocFlagLock), flags);
 588         pScb = (ORC_SCB *) NULL;
 589         pVirEscb = (ESCB *) NULL;
 590
 591         /* setup scatter list address with one buffer */
 592         pVirScb = pHCB->HCS_virScbArray;
 593
 594         initAFlag(pHCB);
 595         /* device reset */
 596         for (i = 0; i < ORC_MAXQUEUE; i++) {
 597                 pVirEscb = pVirScb->SCB_EScb;
 598                 if ((pVirScb->SCB_Status) && (pVirEscb->SCB_Srb == SCpnt))
 599                         break;
 600                 pVirScb++;
 601         }
 602
 603         if (i == ORC_MAXQUEUE) {
 604                 printk("Unable to Reset - No SCB Found\n");
 605                 spin_unlock_irqrestore(&(pHCB->BitAllocFlagLock), flags);
 606                 return FAILED;
 607         }
 608         if ((pScb = orc_alloc_scb(pHCB)) == NULL) {
 609                 spin_unlock_irqrestore(&(pHCB->BitAllocFlagLock), flags);
 610                 return FAILED;
 611         }
 612         pScb->SCB_Opcode = ORC_BUSDEVRST;
 613         pScb->SCB_Target = target;
 614         pScb->SCB_HaStat = 0;
 615         pScb->SCB_TaStat = 0;
 616         pScb->SCB_Status = 0x0;
 617         pScb->SCB_Link = 0xFF;
 618         pScb->SCB_Reserved0 = 0;
 619         pScb->SCB_Reserved1 = 0;
 620         pScb->SCB_XferLen = 0;
 621         pScb->SCB_SGLen = 0;
 622
 623         pVirEscb->SCB_Srb = NULL;
 624         pVirEscb->SCB_Srb = SCpnt;
 625         orc_exec_scb(pHCB, pScb);       /* Start execute SCB            */
 626         spin_unlock_irqrestore(&(pHCB->BitAllocFlagLock), flags);
 627         return SUCCESS;
 628 }
 629
 630
 631 /***************************************************************************/
 632 static ORC_SCB *__orc_alloc_scb(ORC_HCS * hcsp)
 633 {
 634         ORC_SCB *pTmpScb;
 635         UCHAR Ch;
 636         ULONG idx;
 637         UCHAR index;
 638         UCHAR i;
 639
 640         Ch = hcsp->HCS_Index;
 641         for (i = 0; i < 8; i++) {
 642                 for (index = 0; index < 32; index++) {
 643                         if ((hcsp->BitAllocFlag[Ch][i] >> index) & 0x01) {
 644                                 hcsp->BitAllocFlag[Ch][i] &= ~(1 << index);
 645                                 break;
 646                         }
 647                 }
 648                 idx = index + 32 * i;
 649                 pTmpScb = (ORC_SCB *) ((ULONG) hcsp->HCS_virScbArray + (idx * sizeof(ORC_SCB)));
 650                 return (pTmpScb);
 651         }
 652         return (NULL);
 653 }
 654
 655 static ORC_SCB *orc_alloc_scb(ORC_HCS * hcsp)
 656 {
 657         ORC_SCB *pTmpScb;
 658         ULONG flags;
 659
 660         spin_lock_irqsave(&(hcsp->BitAllocFlagLock), flags);
 661         pTmpScb = __orc_alloc_scb(hcsp);
 662         spin_unlock_irqrestore(&(hcsp->BitAllocFlagLock), flags);
 663         return (pTmpScb);
 664 }
 665
 666
 667 /***************************************************************************/
 668 static void orc_release_scb(ORC_HCS * hcsp, ORC_SCB * scbp)
 669 {
 670         ULONG flags;
 671         UCHAR Index;
 672         UCHAR i;
 673         UCHAR Ch;
 674
 675         spin_lock_irqsave(&(hcsp->BitAllocFlagLock), flags);
 676         Ch = hcsp->HCS_Index;
 677         Index = scbp->SCB_ScbIdx;
 678         i = Index / 32;
 679         Index %= 32;
 680         hcsp->BitAllocFlag[Ch][i] |= (1 << Index);
 681         spin_unlock_irqrestore(&(hcsp->BitAllocFlagLock), flags);
 682 }
 683
 684 /*****************************************************************************
 685  Function name  : abort_SCB
 686  Description    : Abort a queued command.
 687                          (commands that are on the bus can't be aborted easily)
 688  Input          : pHCB  -       Pointer to host adapter structure
 689  Output         : None.
 690  Return         : pSRB  -       Pointer to SCSI request block.
 691 *****************************************************************************/
 692 static int abort_SCB(ORC_HCS * hcsp, ORC_SCB * pScb)
 693 {
 694         unsigned char bData, bStatus;
 695
 696         ORC_WR(hcsp->HCS_Base + ORC_HDATA, ORC_CMD_ABORT_SCB);  /* Write command */
 697         ORC_WR(hcsp->HCS_Base + ORC_HCTRL, HDO);
 698         if (waitHDOoff(hcsp) == 0)      /* Wait HDO off   */
 699                 return 0;
 700
 701         ORC_WR(hcsp->HCS_Base + ORC_HDATA, pScb->SCB_ScbIdx);   /* Write address */
 702         ORC_WR(hcsp->HCS_Base + ORC_HCTRL, HDO);
 703         if (waitHDOoff(hcsp) == 0)      /* Wait HDO off   */
 704                 return 0;
 705
 706         if (waitHDIset(hcsp, &bData) == 0)      /* Wait HDI set   */
 707                 return 0;
 708         bStatus = ORC_RD(hcsp->HCS_Base, ORC_HDATA);
 709         ORC_WR(hcsp->HCS_Base + ORC_HSTUS, bData);      /* Clear HDI    */
 710
 711         if (bStatus == 1)       /* 0 - Successfully               */
 712                 return 0;       /* 1 - Fail                     */
 713         return 1;
 714 }
 715
 716 /*****************************************************************************
 717  Function name  : inia100_abort
 718  Description    : Abort a queued command.
 719                          (commands that are on the bus can't be aborted easily)
 720  Input          : pHCB  -       Pointer to host adapter structure
 721  Output         : None.
 722  Return         : pSRB  -       Pointer to SCSI request block.
 723 *****************************************************************************/
 724 static int orc_abort_srb(ORC_HCS * hcsp, struct scsi_cmnd *SCpnt)
 725 {
 726         ESCB *pVirEscb;
 727         ORC_SCB *pVirScb;
 728         UCHAR i;
 729         ULONG flags;
 730
 731         spin_lock_irqsave(&(hcsp->BitAllocFlagLock), flags);
 732
 733         pVirScb = hcsp->HCS_virScbArray;
 734
 735         for (i = 0; i < ORC_MAXQUEUE; i++, pVirScb++) {
 736                 pVirEscb = pVirScb->SCB_EScb;
 737                 if ((pVirScb->SCB_Status) && (pVirEscb->SCB_Srb == SCpnt)) {
 738                         if (pVirScb->SCB_TagMsg == 0) {
 739                                 spin_unlock_irqrestore(&(hcsp->BitAllocFlagLock), flags);
 740                                 return FAILED;
 741                         } else {
 742                                 if (abort_SCB(hcsp, pVirScb)) {
 743                                         pVirEscb->SCB_Srb = NULL;
 744                                         spin_unlock_irqrestore(&(hcsp->BitAllocFlagLock), flags);
 745                                         return SUCCESS;
 746                                 } else {
 747                                         spin_unlock_irqrestore(&(hcsp->BitAllocFlagLock), flags);
 748                                         return FAILED;
 749                                 }
 750                         }
 751                 }
 752         }
 753         spin_unlock_irqrestore(&(hcsp->BitAllocFlagLock), flags);
 754         return FAILED;
 755 }
 756
 757 /***********************************************************************
 758  Routine Description:
 759           This is the interrupt service routine for the Orchid SCSI adapter.
 760           It reads the interrupt register to determine if the adapter is indeed
 761           the source of the interrupt and clears the interrupt at the device.
 762  Arguments:
 763           HwDeviceExtension - HBA miniport driver's adapter data storage
 764  Return Value:
 765 ***********************************************************************/
 766 static void orc_interrupt(
 767                           ORC_HCS * hcsp
 768 )
 769 {
 770         BYTE bScbIdx;
 771         ORC_SCB *pScb;
 772
 773         if (ORC_RD(hcsp->HCS_Base, ORC_RQUEUECNT) == 0) {
 774                 return;         // 0;
 775
 776         }
 777         do {
 778                 bScbIdx = ORC_RD(hcsp->HCS_Base, ORC_RQUEUE);
 779
 780                 pScb = (ORC_SCB *) ((ULONG) hcsp->HCS_virScbArray + (ULONG) (sizeof(ORC_SCB) * bScbIdx));
 781                 pScb->SCB_Status = 0x0;
 782
 783                 inia100SCBPost((BYTE *) hcsp, (BYTE *) pScb);
 784         } while (ORC_RD(hcsp->HCS_Base, ORC_RQUEUECNT));
 785         return;                 //1;
 786
 787 }                               /* End of I1060Interrupt() */
 788
 789 /*****************************************************************************
 790  Function name  : inia100BuildSCB
 791  Description    :
 792  Input          : pHCB  -       Pointer to host adapter structure
 793  Output         : None.
 794  Return         : pSRB  -       Pointer to SCSI request block.
 795 *****************************************************************************/
 796 static void inia100BuildSCB(ORC_HCS * pHCB, ORC_SCB * pSCB, struct scsi_cmnd * SCpnt)
 797 {                               /* Create corresponding SCB     */
 798         struct scatterlist *pSrbSG;
 799         ORC_SG *pSG;            /* Pointer to SG list           */
 800         int i, count_sg;
 801         ESCB *pEScb;
 802
 803         pEScb = pSCB->SCB_EScb;
 804         pEScb->SCB_Srb = SCpnt;
 805         pSG = NULL;
 806
 807         pSCB->SCB_Opcode = ORC_EXECSCSI;
 808         pSCB->SCB_Flags = SCF_NO_DCHK;  /* Clear done bit               */
 809         pSCB->SCB_Target = SCpnt->device->id;
 810         pSCB->SCB_Lun = SCpnt->device->lun;
 811         pSCB->SCB_Reserved0 = 0;
 812         pSCB->SCB_Reserved1 = 0;
 813         pSCB->SCB_SGLen = 0;
 814
 815         if ((pSCB->SCB_XferLen = (U32) SCpnt->request_bufflen)) {
 816                 pSG = (ORC_SG *) & pEScb->ESCB_SGList[0];
 817                 if (SCpnt->use_sg) {
 818                         pSrbSG = (struct scatterlist *) SCpnt->request_buffer;
 819                         count_sg = pci_map_sg(pHCB->pdev, pSrbSG, SCpnt->use_sg,
 820                                         SCpnt->sc_data_direction);
 821                         pSCB->SCB_SGLen = (U32) (count_sg * 8);
 822                         for (i = 0; i < count_sg; i++, pSG++, pSrbSG++) {
 823                                 pSG->SG_Ptr = (U32) sg_dma_address(pSrbSG);
 824                                 pSG->SG_Len = (U32) sg_dma_len(pSrbSG);
 825                         }
 826                 } else if (SCpnt->request_bufflen != 0) {/* Non SG */
 827                         pSCB->SCB_SGLen = 0x8;
 828                         SCpnt->SCp.dma_handle = pci_map_single(pHCB->pdev,
 829                                         SCpnt->request_buffer,
 830                                         SCpnt->request_bufflen,
 831                                         SCpnt->sc_data_direction);
 832                         pSG->SG_Ptr = (U32) SCpnt->SCp.dma_handle;
 833                         pSG->SG_Len = (U32) SCpnt->request_bufflen;
 834                 } else {
 835                         pSCB->SCB_SGLen = 0;
 836                         pSG->SG_Ptr = 0;
 837                         pSG->SG_Len = 0;
 838                 }
 839         }
 840         pSCB->SCB_SGPAddr = (U32) pSCB->SCB_SensePAddr;
 841         pSCB->SCB_HaStat = 0;
 842         pSCB->SCB_TaStat = 0;
 843         pSCB->SCB_Link = 0xFF;
 844         pSCB->SCB_SenseLen = SENSE_SIZE;
 845         pSCB->SCB_CDBLen = SCpnt->cmd_len;
 846         if (pSCB->SCB_CDBLen >= IMAX_CDB) {
 847                 printk("max cdb length= %x\b", SCpnt->cmd_len);
 848                 pSCB->SCB_CDBLen = IMAX_CDB;
 849         }
 850         pSCB->SCB_Ident = SCpnt->device->lun | DISC_ALLOW;
 851         if (SCpnt->device->tagged_supported) {  /* Tag Support                  */
 852                 pSCB->SCB_TagMsg = SIMPLE_QUEUE_TAG;    /* Do simple tag only   */
 853         } else {
 854                 pSCB->SCB_TagMsg = 0;   /* No tag support               */
 855         }
 856         memcpy(&pSCB->SCB_CDB[0], &SCpnt->cmnd, pSCB->SCB_CDBLen);
 857         return;
 858 }
 859
 860 /*****************************************************************************
 861  Function name  : inia100_queue
 862  Description    : Queue a command and setup interrupts for a free bus.
 863  Input          : pHCB  -       Pointer to host adapter structure
 864  Output         : None.
 865  Return         : pSRB  -       Pointer to SCSI request block.
 866 *****************************************************************************/
 867 static int inia100_queue(struct scsi_cmnd * SCpnt, void (*done) (struct scsi_cmnd *))
 868 {
 869         register ORC_SCB *pSCB;
 870         ORC_HCS *pHCB;          /* Point to Host adapter control block */
 871
 872         pHCB = (ORC_HCS *) SCpnt->device->host->hostdata;
 873         SCpnt->scsi_done = done;
 874         /* Get free SCSI control block  */
 875         if ((pSCB = orc_alloc_scb(pHCB)) == NULL)
 876                 return SCSI_MLQUEUE_HOST_BUSY;
 877
 878         inia100BuildSCB(pHCB, pSCB, SCpnt);
 879         orc_exec_scb(pHCB, pSCB);       /* Start execute SCB            */
 880
 881         return (0);
 882 }
 883
 884 /*****************************************************************************
 885  Function name  : inia100_abort
 886  Description    : Abort a queued command.
 887                          (commands that are on the bus can't be aborted easily)
 888  Input          : pHCB  -       Pointer to host adapter structure
 889  Output         : None.
 890  Return         : pSRB  -       Pointer to SCSI request block.
 891 *****************************************************************************/
 892 static int inia100_abort(struct scsi_cmnd * SCpnt)
 893 {
 894         ORC_HCS *hcsp;
 895
 896         hcsp = (ORC_HCS *) SCpnt->device->host->hostdata;
 897         return orc_abort_srb(hcsp, SCpnt);
 898 }
 899
 900 /*****************************************************************************
 901  Function name  : inia100_reset
 902  Description    : Reset registers, reset a hanging bus and
 903                   kill active and disconnected commands for target w/o soft reset
 904  Input          : pHCB  -       Pointer to host adapter structure
 905  Output         : None.
 906  Return         : pSRB  -       Pointer to SCSI request block.
 907 *****************************************************************************/
 908 static int inia100_bus_reset(struct scsi_cmnd * SCpnt)
 909 {                               /* I need Host Control Block Information */
 910         ORC_HCS *pHCB;
 911         pHCB = (ORC_HCS *) SCpnt->device->host->hostdata;
 912         return orc_reset_scsi_bus(pHCB);
 913 }
 914
 915 /*****************************************************************************
 916  Function name  : inia100_device_reset
 917  Description    : Reset the device
 918  Input          : pHCB  -       Pointer to host adapter structure
 919  Output         : None.
 920  Return         : pSRB  -       Pointer to SCSI request block.
 921 *****************************************************************************/
 922 static int inia100_device_reset(struct scsi_cmnd * SCpnt)
 923 {                               /* I need Host Control Block Information */
 924         ORC_HCS *pHCB;
 925         pHCB = (ORC_HCS *) SCpnt->device->host->hostdata;
 926         return orc_device_reset(pHCB, SCpnt, SCpnt->device->id);
 927
 928 }
 929
 930 /*****************************************************************************
 931  Function name  : inia100SCBPost
 932  Description    : This is callback routine be called when orc finish one
 933                         SCSI command.
 934  Input          : pHCB  -       Pointer to host adapter control block.
 935                   pSCB  -       Pointer to SCSI control block.
 936  Output         : None.
 937  Return         : None.
 938 *****************************************************************************/
 939 static void inia100SCBPost(BYTE * pHcb, BYTE * pScb)
 940 {
 941         struct scsi_cmnd *pSRB; /* Pointer to SCSI request block */
 942         ORC_HCS *pHCB;
 943         ORC_SCB *pSCB;
 944         ESCB *pEScb;
 945
 946         pHCB = (ORC_HCS *) pHcb;
 947         pSCB = (ORC_SCB *) pScb;
 948         pEScb = pSCB->SCB_EScb;
 949         if ((pSRB = (struct scsi_cmnd *) pEScb->SCB_Srb) == 0) {
 950                 printk("inia100SCBPost: SRB pointer is empty\n");
 951                 orc_release_scb(pHCB, pSCB);    /* Release SCB for current channel */
 952                 return;
 953         }
 954         pEScb->SCB_Srb = NULL;
 955
 956         switch (pSCB->SCB_HaStat) {
 957         case 0x0:
 958         case 0xa:               /* Linked command complete without error and linked normally */
 959         case 0xb:               /* Linked command complete without error interrupt generated */
 960                 pSCB->SCB_HaStat = 0;
 961                 break;
 962
 963         case 0x11:              /* Selection time out-The initiator selection or target
 964                                    reselection was not complete within the SCSI Time out period */
 965                 pSCB->SCB_HaStat = DID_TIME_OUT;
 966                 break;
 967
 968         case 0x14:              /* Target bus phase sequence failure-An invalid bus phase or bus
 969                                    phase sequence was requested by the target. The host adapter
 970                                    will generate a SCSI Reset Condition, notifying the host with
 971                                    a SCRD interrupt */
 972                 pSCB->SCB_HaStat = DID_RESET;
 973                 break;
 974
 975         case 0x1a:              /* SCB Aborted. 07/21/98 */
 976                 pSCB->SCB_HaStat = DID_ABORT;
 977                 break;
 978
 979         case 0x12:              /* Data overrun/underrun-The target attempted to transfer more data
 980                                    than was allocated by the Data Length field or the sum of the
 981                                    Scatter / Gather Data Length fields. */
 982         case 0x13:              /* Unexpected bus free-The target dropped the SCSI BSY at an unexpected time. */
 983         case 0x16:              /* Invalid CCB Operation Code-The first byte of the CCB was invalid. */
 984
 985         default:
 986                 printk("inia100: %x %x\n", pSCB->SCB_HaStat, pSCB->SCB_TaStat);
 987                 pSCB->SCB_HaStat = DID_ERROR;   /* Couldn't find any better */
 988                 break;
 989         }
 990
 991         if (pSCB->SCB_TaStat == 2) {    /* Check condition              */
 992                 memcpy((unsigned char *) &pSRB->sense_buffer[0],
 993                    (unsigned char *) &pEScb->ESCB_SGList[0], SENSE_SIZE);
 994         }
 995         pSRB->result = pSCB->SCB_TaStat | (pSCB->SCB_HaStat << 16);
 996
 997         if (pSRB->use_sg) {
 998                 pci_unmap_sg(pHCB->pdev,
 999                              (struct scatterlist *)pSRB->request_buffer,
1000                              pSRB->use_sg, pSRB->sc_data_direction);
1001         } else if (pSRB->request_bufflen != 0) {
1002                 pci_unmap_single(pHCB->pdev, pSRB->SCp.dma_handle,
1003                                  pSRB->request_bufflen,
1004                                  pSRB->sc_data_direction);
1005         }
1006
1007         pSRB->scsi_done(pSRB);  /* Notify system DONE           */
1008
1009         orc_release_scb(pHCB, pSCB);    /* Release SCB for current channel */
1010 }
1011
1012 /*
1013  * Interrupt handler (main routine of the driver)
1014  */
1015 static irqreturn_t inia100_intr(int irqno, void *devid, struct pt_regs *regs)
1016 {
1017         struct Scsi_Host *host = (struct Scsi_Host *)devid;
1018         ORC_HCS *pHcb = (ORC_HCS *)host->hostdata;
1019         unsigned long flags;
1020
1021         spin_lock_irqsave(host->host_lock, flags);
1022         orc_interrupt(pHcb);
1023         spin_unlock_irqrestore(host->host_lock, flags);
1024
1025         return IRQ_HANDLED;
1026 }
1027
1028 static struct scsi_host_template inia100_template = {
1029         .proc_name              = "inia100",
1030         .name                   = inia100_REVID,
1031         .queuecommand           = inia100_queue,
1032         .eh_abort_handler       = inia100_abort,
1033         .eh_bus_reset_handler   = inia100_bus_reset,
1034         .eh_device_reset_handler = inia100_device_reset,
1035         .can_queue              = 1,
1036         .this_id                = 1,
1037         .sg_tablesize           = SG_ALL,
1038         .cmd_per_lun            = 1,
1039         .use_clustering         = ENABLE_CLUSTERING,
1040 };
1041
1042 static int __devinit inia100_probe_one(struct pci_dev *pdev,
1043                 const struct pci_device_id *id)
1044 {
1045         struct Scsi_Host *shost;
1046         ORC_HCS *pHCB;
1047         unsigned long port, bios;
1048         int error = -ENODEV;
1049         u32 sz;
1050         unsigned long dBiosAdr;
1051         char *pbBiosAdr;
1052
1053         if (pci_enable_device(pdev))
1054                 goto out;
1055         if (pci_set_dma_mask(pdev, 0xffffffffULL)) {
1056                 printk(KERN_WARNING "Unable to set 32bit DMA "
1057                                     "on inia100 adapter, ignoring.\n");
1058                 goto out_disable_device;
1059         }
1060
1061         pci_set_master(pdev);
1062
1063         port = pci_resource_start(pdev, 0);
1064         if (!request_region(port, 256, "inia100")) {
1065                 printk(KERN_WARNING "inia100: io port 0x%lx, is busy.\n", port);
1066                 goto out_disable_device;
1067         }
1068
1069         /* <02> read from base address + 0x50 offset to get the bios balue. */
1070         bios = ORC_RDWORD(port, 0x50);
1071
1072
1073         shost = scsi_host_alloc(&inia100_template, sizeof(ORC_HCS));
1074         if (!shost)
1075                 goto out_release_region;
1076
1077         pHCB = (ORC_HCS *)shost->hostdata;
1078         pHCB->pdev = pdev;
1079         pHCB->HCS_Base = port;
1080         pHCB->HCS_BIOS = bios;
1081         spin_lock_init(&pHCB->BitAllocFlagLock);
1082
1083         /* Get total memory needed for SCB */
1084         sz = ORC_MAXQUEUE * sizeof(ORC_SCB);
1085         pHCB->HCS_virScbArray = pci_alloc_consistent(pdev, sz,
1086                         &pHCB->HCS_physScbArray);
1087         if (!pHCB->HCS_virScbArray) {
1088                 printk("inia100: SCB memory allocation error\n");
1089                 goto out_host_put;
1090         }
1091         memset(pHCB->HCS_virScbArray, 0, sz);
1092
1093         /* Get total memory needed for ESCB */
1094         sz = ORC_MAXQUEUE * sizeof(ESCB);
1095         pHCB->HCS_virEscbArray = pci_alloc_consistent(pdev, sz,
1096                         &pHCB->HCS_physEscbArray);
1097         if (!pHCB->HCS_virEscbArray) {
1098                 printk("inia100: ESCB memory allocation error\n");
1099                 goto out_free_scb_array;
1100         }
1101         memset(pHCB->HCS_virEscbArray, 0, sz);
1102
1103         dBiosAdr = pHCB->HCS_BIOS;
1104         dBiosAdr = (dBiosAdr << 4);
1105         pbBiosAdr = phys_to_virt(dBiosAdr);
1106         if (init_orchid(pHCB)) {        /* Initialize orchid chip */
1107                 printk("inia100: initial orchid fail!!\n");
1108                 goto out_free_escb_array;
1109         }
1110
1111         shost->io_port = pHCB->HCS_Base;
1112         shost->n_io_port = 0xff;
1113         shost->can_queue = ORC_MAXQUEUE;
1114         shost->unique_id = shost->io_port;
1115         shost->max_id = pHCB->HCS_MaxTar;
1116         shost->max_lun = 16;
1117         shost->irq = pHCB->HCS_Intr = pdev->irq;
1118         shost->this_id = pHCB->HCS_SCSI_ID;     /* Assign HCS index */
1119         shost->sg_tablesize = TOTAL_SG_ENTRY;
1120
1121         /* Initial orc chip           */
1122         error = request_irq(pdev->irq, inia100_intr, SA_SHIRQ,
1123                         "inia100", shost);
1124         if (error < 0) {
1125                 printk(KERN_WARNING "inia100: unable to get irq %d\n",
1126                                 pdev->irq);
1127                 goto out_free_escb_array;
1128         }
1129
1130         pci_set_drvdata(pdev, shost);
1131
1132         error = scsi_add_host(shost, &pdev->dev);
1133         if (error)
1134                 goto out_free_irq;
1135
1136         scsi_scan_host(shost);
1137         return 0;
1138
1139  out_free_irq:
1140         free_irq(shost->irq, shost);
1141  out_free_escb_array:
1142         pci_free_consistent(pdev, ORC_MAXQUEUE * sizeof(ESCB),
1143                         pHCB->HCS_virEscbArray, pHCB->HCS_physEscbArray);
1144  out_free_scb_array:
1145         pci_free_consistent(pdev, ORC_MAXQUEUE * sizeof(ORC_SCB),
1146                         pHCB->HCS_virScbArray, pHCB->HCS_physScbArray);
1147  out_host_put:
1148         scsi_host_put(shost);
1149  out_release_region:
1150         release_region(port, 256);
1151  out_disable_device:
1152         pci_disable_device(pdev);
1153  out:
1154         return error;
1155 }
1156
1157 static void __devexit inia100_remove_one(struct pci_dev *pdev)
1158 {
1159         struct Scsi_Host *shost = pci_get_drvdata(pdev);
1160         ORC_HCS *pHCB = (ORC_HCS *)shost->hostdata;
1161
1162         scsi_remove_host(shost);
1163
1164         free_irq(shost->irq, shost);
1165         pci_free_consistent(pdev, ORC_MAXQUEUE * sizeof(ESCB),
1166                         pHCB->HCS_virEscbArray, pHCB->HCS_physEscbArray);
1167         pci_free_consistent(pdev, ORC_MAXQUEUE * sizeof(ORC_SCB),
1168                         pHCB->HCS_virScbArray, pHCB->HCS_physScbArray);
1169         release_region(shost->io_port, 256);
1170
1171         scsi_host_put(shost);
1172 }
1173
1174 static struct pci_device_id inia100_pci_tbl[] = {
1175         {PCI_VENDOR_ID_INIT, 0x1060, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1176         {0,}
1177 };
1178 MODULE_DEVICE_TABLE(pci, inia100_pci_tbl);
1179
1180 static struct pci_driver inia100_pci_driver = {
1181         .name           = "inia100",
1182         .id_table       = inia100_pci_tbl,
1183         .probe          = inia100_probe_one,
1184         .remove         = __devexit_p(inia100_remove_one),
1185 };
1186
1187 static int __init inia100_init(void)
1188 {
1189         return pci_module_init(&inia100_pci_driver);
1190 }
1191
1192 static void __exit inia100_exit(void)
1193 {
1194         pci_unregister_driver(&inia100_pci_driver);
1195 }
1196
1197 MODULE_DESCRIPTION("Initio A100U2W SCSI driver");
1198 MODULE_AUTHOR("Initio Corporation");
1199 MODULE_LICENSE("Dual BSD/GPL");
1200
1201 module_init(inia100_init);
1202 module_exit(inia100_exit);