Merge master.kernel.org:/home/rmk/linux-2.6-arm
[linux-2.6] / drivers / media / dvb / frontends / dib3000mb.c
1 /*
2  * Frontend driver for mobile DVB-T demodulator DiBcom 3000M-B
3  * DiBcom (http://www.dibcom.fr/)
4  *
5  * Copyright (C) 2004-5 Patrick Boettcher (patrick.boettcher@desy.de)
6  *
7  * based on GPL code from DibCom, which has
8  *
9  * Copyright (C) 2004 Amaury Demol for DiBcom (ademol@dibcom.fr)
10  *
11  *      This program is free software; you can redistribute it and/or
12  *      modify it under the terms of the GNU General Public License as
13  *      published by the Free Software Foundation, version 2.
14  *
15  * Acknowledgements
16  *
17  *  Amaury Demol (ademol@dibcom.fr) from DiBcom for providing specs and driver
18  *  sources, on which this driver (and the dvb-dibusb) are based.
19  *
20  * see Documentation/dvb/README.dibusb for more information
21  *
22  */
23
24 #include <linux/config.h>
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/moduleparam.h>
28 #include <linux/init.h>
29 #include <linux/delay.h>
30 #include <linux/string.h>
31 #include <linux/slab.h>
32
33 #include "dib3000-common.h"
34 #include "dib3000mb_priv.h"
35 #include "dib3000.h"
36
37 /* Version information */
38 #define DRIVER_VERSION "0.1"
39 #define DRIVER_DESC "DiBcom 3000M-B DVB-T demodulator"
40 #define DRIVER_AUTHOR "Patrick Boettcher, patrick.boettcher@desy.de"
41
42 #ifdef CONFIG_DVB_DIBCOM_DEBUG
43 static int debug;
44 module_param(debug, int, 0644);
45 MODULE_PARM_DESC(debug, "set debugging level (1=info,2=xfer,4=setfe,8=getfe (|-able)).");
46 #endif
47 #define deb_info(args...) dprintk(0x01,args)
48 #define deb_xfer(args...) dprintk(0x02,args)
49 #define deb_setf(args...) dprintk(0x04,args)
50 #define deb_getf(args...) dprintk(0x08,args)
51
52 static int dib3000mb_get_frontend(struct dvb_frontend* fe,
53                                   struct dvb_frontend_parameters *fep);
54
55 static int dib3000mb_set_frontend(struct dvb_frontend* fe,
56                                   struct dvb_frontend_parameters *fep, int tuner)
57 {
58         struct dib3000_state* state = fe->demodulator_priv;
59         struct dvb_ofdm_parameters *ofdm = &fep->u.ofdm;
60         fe_code_rate_t fe_cr = FEC_NONE;
61         int search_state, seq;
62
63         if (tuner && state->config.pll_set) {
64                 state->config.pll_set(fe, fep);
65
66                 deb_setf("bandwidth: ");
67                 switch (ofdm->bandwidth) {
68                         case BANDWIDTH_8_MHZ:
69                                 deb_setf("8 MHz\n");
70                                 wr_foreach(dib3000mb_reg_timing_freq, dib3000mb_timing_freq[2]);
71                                 wr_foreach(dib3000mb_reg_bandwidth, dib3000mb_bandwidth_8mhz);
72                                 break;
73                         case BANDWIDTH_7_MHZ:
74                                 deb_setf("7 MHz\n");
75                                 wr_foreach(dib3000mb_reg_timing_freq, dib3000mb_timing_freq[1]);
76                                 wr_foreach(dib3000mb_reg_bandwidth, dib3000mb_bandwidth_7mhz);
77                                 break;
78                         case BANDWIDTH_6_MHZ:
79                                 deb_setf("6 MHz\n");
80                                 wr_foreach(dib3000mb_reg_timing_freq, dib3000mb_timing_freq[0]);
81                                 wr_foreach(dib3000mb_reg_bandwidth, dib3000mb_bandwidth_6mhz);
82                                 break;
83                         case BANDWIDTH_AUTO:
84                                 return -EOPNOTSUPP;
85                         default:
86                                 err("unkown bandwidth value.");
87                                 return -EINVAL;
88                 }
89         }
90         wr(DIB3000MB_REG_LOCK1_MASK, DIB3000MB_LOCK1_SEARCH_4);
91
92         deb_setf("transmission mode: ");
93         switch (ofdm->transmission_mode) {
94                 case TRANSMISSION_MODE_2K:
95                         deb_setf("2k\n");
96                         wr(DIB3000MB_REG_FFT, DIB3000_TRANSMISSION_MODE_2K);
97                         break;
98                 case TRANSMISSION_MODE_8K:
99                         deb_setf("8k\n");
100                         wr(DIB3000MB_REG_FFT, DIB3000_TRANSMISSION_MODE_8K);
101                         break;
102                 case TRANSMISSION_MODE_AUTO:
103                         deb_setf("auto\n");
104                         break;
105                 default:
106                         return -EINVAL;
107         }
108
109         deb_setf("guard: ");
110         switch (ofdm->guard_interval) {
111                 case GUARD_INTERVAL_1_32:
112                         deb_setf("1_32\n");
113                         wr(DIB3000MB_REG_GUARD_TIME, DIB3000_GUARD_TIME_1_32);
114                         break;
115                 case GUARD_INTERVAL_1_16:
116                         deb_setf("1_16\n");
117                         wr(DIB3000MB_REG_GUARD_TIME, DIB3000_GUARD_TIME_1_16);
118                         break;
119                 case GUARD_INTERVAL_1_8:
120                         deb_setf("1_8\n");
121                         wr(DIB3000MB_REG_GUARD_TIME, DIB3000_GUARD_TIME_1_8);
122                         break;
123                 case GUARD_INTERVAL_1_4:
124                         deb_setf("1_4\n");
125                         wr(DIB3000MB_REG_GUARD_TIME, DIB3000_GUARD_TIME_1_4);
126                         break;
127                 case GUARD_INTERVAL_AUTO:
128                         deb_setf("auto\n");
129                         break;
130                 default:
131                         return -EINVAL;
132         }
133
134         deb_setf("inversion: ");
135         switch (fep->inversion) {
136                 case INVERSION_OFF:
137                         deb_setf("off\n");
138                         wr(DIB3000MB_REG_DDS_INV, DIB3000_DDS_INVERSION_OFF);
139                         break;
140                 case INVERSION_AUTO:
141                         deb_setf("auto ");
142                         break;
143                 case INVERSION_ON:
144                         deb_setf("on\n");
145                         wr(DIB3000MB_REG_DDS_INV, DIB3000_DDS_INVERSION_ON);
146                         break;
147                 default:
148                         return -EINVAL;
149         }
150
151         deb_setf("constellation: ");
152         switch (ofdm->constellation) {
153                 case QPSK:
154                         deb_setf("qpsk\n");
155                         wr(DIB3000MB_REG_QAM, DIB3000_CONSTELLATION_QPSK);
156                         break;
157                 case QAM_16:
158                         deb_setf("qam16\n");
159                         wr(DIB3000MB_REG_QAM, DIB3000_CONSTELLATION_16QAM);
160                         break;
161                 case QAM_64:
162                         deb_setf("qam64\n");
163                         wr(DIB3000MB_REG_QAM, DIB3000_CONSTELLATION_64QAM);
164                         break;
165                 case QAM_AUTO:
166                         break;
167                 default:
168                         return -EINVAL;
169         }
170         deb_setf("hierachy: ");
171         switch (ofdm->hierarchy_information) {
172                 case HIERARCHY_NONE:
173                         deb_setf("none ");
174                         /* fall through */
175                 case HIERARCHY_1:
176                         deb_setf("alpha=1\n");
177                         wr(DIB3000MB_REG_VIT_ALPHA, DIB3000_ALPHA_1);
178                         break;
179                 case HIERARCHY_2:
180                         deb_setf("alpha=2\n");
181                         wr(DIB3000MB_REG_VIT_ALPHA, DIB3000_ALPHA_2);
182                         break;
183                 case HIERARCHY_4:
184                         deb_setf("alpha=4\n");
185                         wr(DIB3000MB_REG_VIT_ALPHA, DIB3000_ALPHA_4);
186                         break;
187                 case HIERARCHY_AUTO:
188                         deb_setf("alpha=auto\n");
189                         break;
190                 default:
191                         return -EINVAL;
192         }
193
194         deb_setf("hierarchy: ");
195         if (ofdm->hierarchy_information == HIERARCHY_NONE) {
196                 deb_setf("none\n");
197                 wr(DIB3000MB_REG_VIT_HRCH, DIB3000_HRCH_OFF);
198                 wr(DIB3000MB_REG_VIT_HP, DIB3000_SELECT_HP);
199                 fe_cr = ofdm->code_rate_HP;
200         } else if (ofdm->hierarchy_information != HIERARCHY_AUTO) {
201                 deb_setf("on\n");
202                 wr(DIB3000MB_REG_VIT_HRCH, DIB3000_HRCH_ON);
203                 wr(DIB3000MB_REG_VIT_HP, DIB3000_SELECT_LP);
204                 fe_cr = ofdm->code_rate_LP;
205         }
206         deb_setf("fec: ");
207         switch (fe_cr) {
208                 case FEC_1_2:
209                         deb_setf("1_2\n");
210                         wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_1_2);
211                         break;
212                 case FEC_2_3:
213                         deb_setf("2_3\n");
214                         wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_2_3);
215                         break;
216                 case FEC_3_4:
217                         deb_setf("3_4\n");
218                         wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_3_4);
219                         break;
220                 case FEC_5_6:
221                         deb_setf("5_6\n");
222                         wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_5_6);
223                         break;
224                 case FEC_7_8:
225                         deb_setf("7_8\n");
226                         wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_7_8);
227                         break;
228                 case FEC_NONE:
229                         deb_setf("none ");
230                         break;
231                 case FEC_AUTO:
232                         deb_setf("auto\n");
233                         break;
234                 default:
235                         return -EINVAL;
236         }
237
238         seq = dib3000_seq
239                 [ofdm->transmission_mode == TRANSMISSION_MODE_AUTO]
240                 [ofdm->guard_interval == GUARD_INTERVAL_AUTO]
241                 [fep->inversion == INVERSION_AUTO];
242
243         deb_setf("seq? %d\n", seq);
244
245         wr(DIB3000MB_REG_SEQ, seq);
246
247         wr(DIB3000MB_REG_ISI, seq ? DIB3000MB_ISI_INHIBIT : DIB3000MB_ISI_ACTIVATE);
248
249         if (ofdm->transmission_mode == TRANSMISSION_MODE_2K) {
250                 if (ofdm->guard_interval == GUARD_INTERVAL_1_8) {
251                         wr(DIB3000MB_REG_SYNC_IMPROVEMENT, DIB3000MB_SYNC_IMPROVE_2K_1_8);
252                 } else {
253                         wr(DIB3000MB_REG_SYNC_IMPROVEMENT, DIB3000MB_SYNC_IMPROVE_DEFAULT);
254                 }
255
256                 wr(DIB3000MB_REG_UNK_121, DIB3000MB_UNK_121_2K);
257         } else {
258                 wr(DIB3000MB_REG_UNK_121, DIB3000MB_UNK_121_DEFAULT);
259         }
260
261         wr(DIB3000MB_REG_MOBILE_ALGO, DIB3000MB_MOBILE_ALGO_OFF);
262         wr(DIB3000MB_REG_MOBILE_MODE_QAM, DIB3000MB_MOBILE_MODE_QAM_OFF);
263         wr(DIB3000MB_REG_MOBILE_MODE, DIB3000MB_MOBILE_MODE_OFF);
264
265         wr_foreach(dib3000mb_reg_agc_bandwidth, dib3000mb_agc_bandwidth_high);
266
267         wr(DIB3000MB_REG_ISI, DIB3000MB_ISI_ACTIVATE);
268
269         wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_AGC + DIB3000MB_RESTART_CTRL);
270         wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_OFF);
271
272         /* wait for AGC lock */
273         msleep(70);
274
275         wr_foreach(dib3000mb_reg_agc_bandwidth, dib3000mb_agc_bandwidth_low);
276
277         /* something has to be auto searched */
278         if (ofdm->constellation == QAM_AUTO ||
279                 ofdm->hierarchy_information == HIERARCHY_AUTO ||
280                 fe_cr == FEC_AUTO ||
281                 fep->inversion == INVERSION_AUTO) {
282                 int as_count=0;
283
284                 deb_setf("autosearch enabled.\n");
285
286                 wr(DIB3000MB_REG_ISI, DIB3000MB_ISI_INHIBIT);
287
288                 wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_AUTO_SEARCH);
289                 wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_OFF);
290
291                 while ((search_state =
292                                 dib3000_search_status(
293                                         rd(DIB3000MB_REG_AS_IRQ_PENDING),
294                                         rd(DIB3000MB_REG_LOCK2_VALUE))) < 0 && as_count++ < 100)
295                         msleep(1);
296
297                 deb_setf("search_state after autosearch %d after %d checks\n",search_state,as_count);
298
299                 if (search_state == 1) {
300                         struct dvb_frontend_parameters feps;
301                         if (dib3000mb_get_frontend(fe, &feps) == 0) {
302                                 deb_setf("reading tuning data from frontend succeeded.\n");
303                                 return dib3000mb_set_frontend(fe, &feps, 0);
304                         }
305                 }
306
307         } else {
308                 wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_CTRL);
309                 wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_OFF);
310         }
311
312         return 0;
313 }
314
315 static int dib3000mb_fe_init(struct dvb_frontend* fe, int mobile_mode)
316 {
317         struct dib3000_state* state = fe->demodulator_priv;
318
319         deb_info("dib3000mb is getting up.\n");
320         wr(DIB3000MB_REG_POWER_CONTROL, DIB3000MB_POWER_UP);
321
322         wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_AGC);
323
324         wr(DIB3000MB_REG_RESET_DEVICE, DIB3000MB_RESET_DEVICE);
325         wr(DIB3000MB_REG_RESET_DEVICE, DIB3000MB_RESET_DEVICE_RST);
326
327         wr(DIB3000MB_REG_CLOCK, DIB3000MB_CLOCK_DEFAULT);
328
329         wr(DIB3000MB_REG_ELECT_OUT_MODE, DIB3000MB_ELECT_OUT_MODE_ON);
330
331         wr(DIB3000MB_REG_DDS_FREQ_MSB, DIB3000MB_DDS_FREQ_MSB);
332         wr(DIB3000MB_REG_DDS_FREQ_LSB, DIB3000MB_DDS_FREQ_LSB);
333
334         wr_foreach(dib3000mb_reg_timing_freq, dib3000mb_timing_freq[2]);
335
336         wr_foreach(dib3000mb_reg_impulse_noise,
337                         dib3000mb_impulse_noise_values[DIB3000MB_IMPNOISE_OFF]);
338
339         wr_foreach(dib3000mb_reg_agc_gain, dib3000mb_default_agc_gain);
340
341         wr(DIB3000MB_REG_PHASE_NOISE, DIB3000MB_PHASE_NOISE_DEFAULT);
342
343         wr_foreach(dib3000mb_reg_phase_noise, dib3000mb_default_noise_phase);
344
345         wr_foreach(dib3000mb_reg_lock_duration, dib3000mb_default_lock_duration);
346
347         wr_foreach(dib3000mb_reg_agc_bandwidth, dib3000mb_agc_bandwidth_low);
348
349         wr(DIB3000MB_REG_LOCK0_MASK, DIB3000MB_LOCK0_DEFAULT);
350         wr(DIB3000MB_REG_LOCK1_MASK, DIB3000MB_LOCK1_SEARCH_4);
351         wr(DIB3000MB_REG_LOCK2_MASK, DIB3000MB_LOCK2_DEFAULT);
352         wr(DIB3000MB_REG_SEQ, dib3000_seq[1][1][1]);
353
354         wr_foreach(dib3000mb_reg_bandwidth, dib3000mb_bandwidth_8mhz);
355
356         wr(DIB3000MB_REG_UNK_68, DIB3000MB_UNK_68);
357         wr(DIB3000MB_REG_UNK_69, DIB3000MB_UNK_69);
358         wr(DIB3000MB_REG_UNK_71, DIB3000MB_UNK_71);
359         wr(DIB3000MB_REG_UNK_77, DIB3000MB_UNK_77);
360         wr(DIB3000MB_REG_UNK_78, DIB3000MB_UNK_78);
361         wr(DIB3000MB_REG_ISI, DIB3000MB_ISI_INHIBIT);
362         wr(DIB3000MB_REG_UNK_92, DIB3000MB_UNK_92);
363         wr(DIB3000MB_REG_UNK_96, DIB3000MB_UNK_96);
364         wr(DIB3000MB_REG_UNK_97, DIB3000MB_UNK_97);
365         wr(DIB3000MB_REG_UNK_106, DIB3000MB_UNK_106);
366         wr(DIB3000MB_REG_UNK_107, DIB3000MB_UNK_107);
367         wr(DIB3000MB_REG_UNK_108, DIB3000MB_UNK_108);
368         wr(DIB3000MB_REG_UNK_122, DIB3000MB_UNK_122);
369         wr(DIB3000MB_REG_MOBILE_MODE_QAM, DIB3000MB_MOBILE_MODE_QAM_OFF);
370         wr(DIB3000MB_REG_BERLEN, DIB3000MB_BERLEN_DEFAULT);
371
372         wr_foreach(dib3000mb_reg_filter_coeffs, dib3000mb_filter_coeffs);
373
374         wr(DIB3000MB_REG_MOBILE_ALGO, DIB3000MB_MOBILE_ALGO_ON);
375         wr(DIB3000MB_REG_MULTI_DEMOD_MSB, DIB3000MB_MULTI_DEMOD_MSB);
376         wr(DIB3000MB_REG_MULTI_DEMOD_LSB, DIB3000MB_MULTI_DEMOD_LSB);
377
378         wr(DIB3000MB_REG_OUTPUT_MODE, DIB3000MB_OUTPUT_MODE_SLAVE);
379
380         wr(DIB3000MB_REG_FIFO_142, DIB3000MB_FIFO_142);
381         wr(DIB3000MB_REG_MPEG2_OUT_MODE, DIB3000MB_MPEG2_OUT_MODE_188);
382         wr(DIB3000MB_REG_PID_PARSE, DIB3000MB_PID_PARSE_ACTIVATE);
383         wr(DIB3000MB_REG_FIFO, DIB3000MB_FIFO_INHIBIT);
384         wr(DIB3000MB_REG_FIFO_146, DIB3000MB_FIFO_146);
385         wr(DIB3000MB_REG_FIFO_147, DIB3000MB_FIFO_147);
386
387         wr(DIB3000MB_REG_DATA_IN_DIVERSITY, DIB3000MB_DATA_DIVERSITY_IN_OFF);
388
389         if (state->config.pll_init)
390                 state->config.pll_init(fe);
391
392         return 0;
393 }
394
395 static int dib3000mb_get_frontend(struct dvb_frontend* fe,
396                                   struct dvb_frontend_parameters *fep)
397 {
398         struct dib3000_state* state = fe->demodulator_priv;
399         struct dvb_ofdm_parameters *ofdm = &fep->u.ofdm;
400         fe_code_rate_t *cr;
401         u16 tps_val;
402         int inv_test1,inv_test2;
403         u32 dds_val, threshold = 0x800000;
404
405         if (!rd(DIB3000MB_REG_TPS_LOCK))
406                 return 0;
407
408         dds_val = ((rd(DIB3000MB_REG_DDS_VALUE_MSB) & 0xff) << 16) + rd(DIB3000MB_REG_DDS_VALUE_LSB);
409         deb_getf("DDS_VAL: %x %x %x",dds_val, rd(DIB3000MB_REG_DDS_VALUE_MSB), rd(DIB3000MB_REG_DDS_VALUE_LSB));
410         if (dds_val < threshold)
411                 inv_test1 = 0;
412         else if (dds_val == threshold)
413                 inv_test1 = 1;
414         else
415                 inv_test1 = 2;
416
417         dds_val = ((rd(DIB3000MB_REG_DDS_FREQ_MSB) & 0xff) << 16) + rd(DIB3000MB_REG_DDS_FREQ_LSB);
418         deb_getf("DDS_FREQ: %x %x %x",dds_val, rd(DIB3000MB_REG_DDS_FREQ_MSB), rd(DIB3000MB_REG_DDS_FREQ_LSB));
419         if (dds_val < threshold)
420                 inv_test2 = 0;
421         else if (dds_val == threshold)
422                 inv_test2 = 1;
423         else
424                 inv_test2 = 2;
425
426         fep->inversion =
427                 ((inv_test2 == 2) && (inv_test1==1 || inv_test1==0)) ||
428                 ((inv_test2 == 0) && (inv_test1==1 || inv_test1==2)) ?
429                 INVERSION_ON : INVERSION_OFF;
430
431         deb_getf("inversion %d %d, %d\n", inv_test2, inv_test1, fep->inversion);
432
433         switch ((tps_val = rd(DIB3000MB_REG_TPS_QAM))) {
434                 case DIB3000_CONSTELLATION_QPSK:
435                         deb_getf("QPSK ");
436                         ofdm->constellation = QPSK;
437                         break;
438                 case DIB3000_CONSTELLATION_16QAM:
439                         deb_getf("QAM16 ");
440                         ofdm->constellation = QAM_16;
441                         break;
442                 case DIB3000_CONSTELLATION_64QAM:
443                         deb_getf("QAM64 ");
444                         ofdm->constellation = QAM_64;
445                         break;
446                 default:
447                         err("Unexpected constellation returned by TPS (%d)", tps_val);
448                         break;
449         }
450         deb_getf("TPS: %d\n", tps_val);
451
452         if (rd(DIB3000MB_REG_TPS_HRCH)) {
453                 deb_getf("HRCH ON\n");
454                 cr = &ofdm->code_rate_LP;
455                 ofdm->code_rate_HP = FEC_NONE;
456                 switch ((tps_val = rd(DIB3000MB_REG_TPS_VIT_ALPHA))) {
457                         case DIB3000_ALPHA_0:
458                                 deb_getf("HIERARCHY_NONE ");
459                                 ofdm->hierarchy_information = HIERARCHY_NONE;
460                                 break;
461                         case DIB3000_ALPHA_1:
462                                 deb_getf("HIERARCHY_1 ");
463                                 ofdm->hierarchy_information = HIERARCHY_1;
464                                 break;
465                         case DIB3000_ALPHA_2:
466                                 deb_getf("HIERARCHY_2 ");
467                                 ofdm->hierarchy_information = HIERARCHY_2;
468                                 break;
469                         case DIB3000_ALPHA_4:
470                                 deb_getf("HIERARCHY_4 ");
471                                 ofdm->hierarchy_information = HIERARCHY_4;
472                                 break;
473                         default:
474                                 err("Unexpected ALPHA value returned by TPS (%d)", tps_val);
475                                 break;
476                 }
477                 deb_getf("TPS: %d\n", tps_val);
478
479                 tps_val = rd(DIB3000MB_REG_TPS_CODE_RATE_LP);
480         } else {
481                 deb_getf("HRCH OFF\n");
482                 cr = &ofdm->code_rate_HP;
483                 ofdm->code_rate_LP = FEC_NONE;
484                 ofdm->hierarchy_information = HIERARCHY_NONE;
485
486                 tps_val = rd(DIB3000MB_REG_TPS_CODE_RATE_HP);
487         }
488
489         switch (tps_val) {
490                 case DIB3000_FEC_1_2:
491                         deb_getf("FEC_1_2 ");
492                         *cr = FEC_1_2;
493                         break;
494                 case DIB3000_FEC_2_3:
495                         deb_getf("FEC_2_3 ");
496                         *cr = FEC_2_3;
497                         break;
498                 case DIB3000_FEC_3_4:
499                         deb_getf("FEC_3_4 ");
500                         *cr = FEC_3_4;
501                         break;
502                 case DIB3000_FEC_5_6:
503                         deb_getf("FEC_5_6 ");
504                         *cr = FEC_4_5;
505                         break;
506                 case DIB3000_FEC_7_8:
507                         deb_getf("FEC_7_8 ");
508                         *cr = FEC_7_8;
509                         break;
510                 default:
511                         err("Unexpected FEC returned by TPS (%d)", tps_val);
512                         break;
513         }
514         deb_getf("TPS: %d\n",tps_val);
515
516         switch ((tps_val = rd(DIB3000MB_REG_TPS_GUARD_TIME))) {
517                 case DIB3000_GUARD_TIME_1_32:
518                         deb_getf("GUARD_INTERVAL_1_32 ");
519                         ofdm->guard_interval = GUARD_INTERVAL_1_32;
520                         break;
521                 case DIB3000_GUARD_TIME_1_16:
522                         deb_getf("GUARD_INTERVAL_1_16 ");
523                         ofdm->guard_interval = GUARD_INTERVAL_1_16;
524                         break;
525                 case DIB3000_GUARD_TIME_1_8:
526                         deb_getf("GUARD_INTERVAL_1_8 ");
527                         ofdm->guard_interval = GUARD_INTERVAL_1_8;
528                         break;
529                 case DIB3000_GUARD_TIME_1_4:
530                         deb_getf("GUARD_INTERVAL_1_4 ");
531                         ofdm->guard_interval = GUARD_INTERVAL_1_4;
532                         break;
533                 default:
534                         err("Unexpected Guard Time returned by TPS (%d)", tps_val);
535                         break;
536         }
537         deb_getf("TPS: %d\n", tps_val);
538
539         switch ((tps_val = rd(DIB3000MB_REG_TPS_FFT))) {
540                 case DIB3000_TRANSMISSION_MODE_2K:
541                         deb_getf("TRANSMISSION_MODE_2K ");
542                         ofdm->transmission_mode = TRANSMISSION_MODE_2K;
543                         break;
544                 case DIB3000_TRANSMISSION_MODE_8K:
545                         deb_getf("TRANSMISSION_MODE_8K ");
546                         ofdm->transmission_mode = TRANSMISSION_MODE_8K;
547                         break;
548                 default:
549                         err("unexpected transmission mode return by TPS (%d)", tps_val);
550                         break;
551         }
552         deb_getf("TPS: %d\n", tps_val);
553
554         return 0;
555 }
556
557 static int dib3000mb_read_status(struct dvb_frontend* fe, fe_status_t *stat)
558 {
559         struct dib3000_state* state = fe->demodulator_priv;
560
561         *stat = 0;
562
563         if (rd(DIB3000MB_REG_AGC_LOCK))
564                 *stat |= FE_HAS_SIGNAL;
565         if (rd(DIB3000MB_REG_CARRIER_LOCK))
566                 *stat |= FE_HAS_CARRIER;
567         if (rd(DIB3000MB_REG_VIT_LCK))
568                 *stat |= FE_HAS_VITERBI;
569         if (rd(DIB3000MB_REG_TS_SYNC_LOCK))
570                 *stat |= (FE_HAS_SYNC | FE_HAS_LOCK);
571
572         deb_getf("actual status is %2x\n",*stat);
573
574         deb_getf("autoval: tps: %d, qam: %d, hrch: %d, alpha: %d, hp: %d, lp: %d, guard: %d, fft: %d cell: %d\n",
575                         rd(DIB3000MB_REG_TPS_LOCK),
576                         rd(DIB3000MB_REG_TPS_QAM),
577                         rd(DIB3000MB_REG_TPS_HRCH),
578                         rd(DIB3000MB_REG_TPS_VIT_ALPHA),
579                         rd(DIB3000MB_REG_TPS_CODE_RATE_HP),
580                         rd(DIB3000MB_REG_TPS_CODE_RATE_LP),
581                         rd(DIB3000MB_REG_TPS_GUARD_TIME),
582                         rd(DIB3000MB_REG_TPS_FFT),
583                         rd(DIB3000MB_REG_TPS_CELL_ID));
584
585         //*stat = FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
586         return 0;
587 }
588
589 static int dib3000mb_read_ber(struct dvb_frontend* fe, u32 *ber)
590 {
591         struct dib3000_state* state = fe->demodulator_priv;
592
593         *ber = ((rd(DIB3000MB_REG_BER_MSB) << 16) | rd(DIB3000MB_REG_BER_LSB));
594         return 0;
595 }
596
597 /* see dib3000-watch dvb-apps for exact calcuations of signal_strength and snr */
598 static int dib3000mb_read_signal_strength(struct dvb_frontend* fe, u16 *strength)
599 {
600         struct dib3000_state* state = fe->demodulator_priv;
601
602         *strength = rd(DIB3000MB_REG_SIGNAL_POWER) * 0xffff / 0x170;
603         return 0;
604 }
605
606 static int dib3000mb_read_snr(struct dvb_frontend* fe, u16 *snr)
607 {
608         struct dib3000_state* state = fe->demodulator_priv;
609         short sigpow = rd(DIB3000MB_REG_SIGNAL_POWER);
610         int icipow = ((rd(DIB3000MB_REG_NOISE_POWER_MSB) & 0xff) << 16) |
611                 rd(DIB3000MB_REG_NOISE_POWER_LSB);
612         *snr = (sigpow << 8) / ((icipow > 0) ? icipow : 1);
613         return 0;
614 }
615
616 static int dib3000mb_read_unc_blocks(struct dvb_frontend* fe, u32 *unc)
617 {
618         struct dib3000_state* state = fe->demodulator_priv;
619
620         *unc = rd(DIB3000MB_REG_PACKET_ERROR_RATE);
621         return 0;
622 }
623
624 static int dib3000mb_sleep(struct dvb_frontend* fe)
625 {
626         struct dib3000_state* state = fe->demodulator_priv;
627         deb_info("dib3000mb is going to bed.\n");
628         wr(DIB3000MB_REG_POWER_CONTROL, DIB3000MB_POWER_DOWN);
629         return 0;
630 }
631
632 static int dib3000mb_fe_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings *tune)
633 {
634         tune->min_delay_ms = 800;
635         return 0;
636 }
637
638 static int dib3000mb_fe_init_nonmobile(struct dvb_frontend* fe)
639 {
640         return dib3000mb_fe_init(fe, 0);
641 }
642
643 static int dib3000mb_set_frontend_and_tuner(struct dvb_frontend* fe, struct dvb_frontend_parameters *fep)
644 {
645         return dib3000mb_set_frontend(fe, fep, 1);
646 }
647
648 static void dib3000mb_release(struct dvb_frontend* fe)
649 {
650         struct dib3000_state *state = fe->demodulator_priv;
651         kfree(state);
652 }
653
654 /* pid filter and transfer stuff */
655 static int dib3000mb_pid_control(struct dvb_frontend *fe,int index, int pid,int onoff)
656 {
657         struct dib3000_state *state = fe->demodulator_priv;
658         pid = (onoff ? pid | DIB3000_ACTIVATE_PID_FILTERING : 0);
659         wr(index+DIB3000MB_REG_FIRST_PID,pid);
660         return 0;
661 }
662
663 static int dib3000mb_fifo_control(struct dvb_frontend *fe, int onoff)
664 {
665         struct dib3000_state *state = fe->demodulator_priv;
666
667         deb_xfer("%s fifo\n",onoff ? "enabling" : "disabling");
668         if (onoff) {
669                 wr(DIB3000MB_REG_FIFO, DIB3000MB_FIFO_ACTIVATE);
670         } else {
671                 wr(DIB3000MB_REG_FIFO, DIB3000MB_FIFO_INHIBIT);
672         }
673         return 0;
674 }
675
676 static int dib3000mb_pid_parse(struct dvb_frontend *fe, int onoff)
677 {
678         struct dib3000_state *state = fe->demodulator_priv;
679         deb_xfer("%s pid parsing\n",onoff ? "enabling" : "disabling");
680         wr(DIB3000MB_REG_PID_PARSE,onoff);
681         return 0;
682 }
683
684 static int dib3000mb_tuner_pass_ctrl(struct dvb_frontend *fe, int onoff, u8 pll_addr)
685 {
686         struct dib3000_state *state = fe->demodulator_priv;
687         if (onoff) {
688                 wr(DIB3000MB_REG_TUNER, DIB3000_TUNER_WRITE_ENABLE(pll_addr));
689         } else {
690                 wr(DIB3000MB_REG_TUNER, DIB3000_TUNER_WRITE_DISABLE(pll_addr));
691         }
692         return 0;
693 }
694
695 static struct dvb_frontend_ops dib3000mb_ops;
696
697 struct dvb_frontend* dib3000mb_attach(const struct dib3000_config* config,
698                                       struct i2c_adapter* i2c, struct dib_fe_xfer_ops *xfer_ops)
699 {
700         struct dib3000_state* state = NULL;
701
702         /* allocate memory for the internal state */
703         state = kmalloc(sizeof(struct dib3000_state), GFP_KERNEL);
704         if (state == NULL)
705                 goto error;
706         memset(state,0,sizeof(struct dib3000_state));
707
708         /* setup the state */
709         state->i2c = i2c;
710         memcpy(&state->config,config,sizeof(struct dib3000_config));
711         memcpy(&state->ops, &dib3000mb_ops, sizeof(struct dvb_frontend_ops));
712
713         /* check for the correct demod */
714         if (rd(DIB3000_REG_MANUFACTOR_ID) != DIB3000_I2C_ID_DIBCOM)
715                 goto error;
716
717         if (rd(DIB3000_REG_DEVICE_ID) != DIB3000MB_DEVICE_ID)
718                 goto error;
719
720         /* create dvb_frontend */
721         state->frontend.ops = &state->ops;
722         state->frontend.demodulator_priv = state;
723
724         /* set the xfer operations */
725         xfer_ops->pid_parse = dib3000mb_pid_parse;
726         xfer_ops->fifo_ctrl = dib3000mb_fifo_control;
727         xfer_ops->pid_ctrl = dib3000mb_pid_control;
728         xfer_ops->tuner_pass_ctrl = dib3000mb_tuner_pass_ctrl;
729
730         return &state->frontend;
731
732 error:
733         kfree(state);
734         return NULL;
735 }
736
737 static struct dvb_frontend_ops dib3000mb_ops = {
738
739         .info = {
740                 .name                   = "DiBcom 3000M-B DVB-T",
741                 .type                   = FE_OFDM,
742                 .frequency_min          = 44250000,
743                 .frequency_max          = 867250000,
744                 .frequency_stepsize     = 62500,
745                 .caps = FE_CAN_INVERSION_AUTO |
746                                 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
747                                 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
748                                 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
749                                 FE_CAN_TRANSMISSION_MODE_AUTO |
750                                 FE_CAN_GUARD_INTERVAL_AUTO |
751                                 FE_CAN_RECOVER |
752                                 FE_CAN_HIERARCHY_AUTO,
753         },
754
755         .release = dib3000mb_release,
756
757         .init = dib3000mb_fe_init_nonmobile,
758         .sleep = dib3000mb_sleep,
759
760         .set_frontend = dib3000mb_set_frontend_and_tuner,
761         .get_frontend = dib3000mb_get_frontend,
762         .get_tune_settings = dib3000mb_fe_get_tune_settings,
763
764         .read_status = dib3000mb_read_status,
765         .read_ber = dib3000mb_read_ber,
766         .read_signal_strength = dib3000mb_read_signal_strength,
767         .read_snr = dib3000mb_read_snr,
768         .read_ucblocks = dib3000mb_read_unc_blocks,
769 };
770
771 MODULE_AUTHOR(DRIVER_AUTHOR);
772 MODULE_DESCRIPTION(DRIVER_DESC);
773 MODULE_LICENSE("GPL");
774
775 EXPORT_SYMBOL(dib3000mb_attach);