git.oblomov.eu Git - linux-2.6/blob - drivers/media/video/cx18/cx18-irq.c

   1 /*
   2  *  cx18 interrupt handling
   3  *
   4  *  Copyright (C) 2007  Hans Verkuil <hverkuil@xs4all.nl>
   5  *
   6  *  This program is free software; you can redistribute it and/or modify
   7  *  it under the terms of the GNU General Public License as published by
   8  *  the Free Software Foundation; either version 2 of the License, or
   9  *  (at your option) any later version.
  10  *
  11  *  This program is distributed in the hope that it will be useful,
  12  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  *  GNU General Public License for more details.
  15  *
  16  *  You should have received a copy of the GNU General Public License
  17  *  along with this program; if not, write to the Free Software
  18  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
  19  *  02111-1307  USA
  20  */
  21
  22 #include "cx18-driver.h"
  23 #include "cx18-firmware.h"
  24 #include "cx18-fileops.h"
  25 #include "cx18-queue.h"
  26 #include "cx18-irq.h"
  27 #include "cx18-ioctl.h"
  28 #include "cx18-mailbox.h"
  29 #include "cx18-vbi.h"
  30 #include "cx18-scb.h"
  31
  32 #define DMA_MAGIC_COOKIE 0x000001fe
  33
  34 static void epu_dma_done(struct cx18 *cx, struct cx18_mailbox *mb)
  35 {
  36         u32 handle = mb->args[0];
  37         struct cx18_stream *s = NULL;
  38         struct cx18_buffer *buf;
  39         u32 off;
  40         int i;
  41         int id;
  42
  43         for (i = 0; i < CX18_MAX_STREAMS; i++) {
  44                 s = &cx->streams[i];
  45                 if ((handle == s->handle) && (s->dvb.enabled))
  46                         break;
  47                 if (s->v4l2dev && handle == s->handle)
  48                         break;
  49         }
  50         if (i == CX18_MAX_STREAMS) {
  51                 CX18_WARN("DMA done for unknown handle %d for stream %s\n",
  52                         handle, s->name);
  53                 mb->error = CXERR_NOT_OPEN;
  54                 mb->cmd = 0;
  55                 cx18_mb_ack(cx, mb);
  56                 return;
  57         }
  58
  59         off = mb->args[1];
  60         if (mb->args[2] != 1)
  61                 CX18_WARN("Ack struct = %d for %s\n",
  62                         mb->args[2], s->name);
  63         id = read_enc(off);
  64         buf = cx18_queue_get_buf_irq(s, id, read_enc(off + 4));
  65         CX18_DEBUG_HI_DMA("DMA DONE for %s (buffer %d)\n", s->name, id);
  66         if (buf) {
  67                 cx18_buf_sync_for_cpu(s, buf);
  68                 if (s->type == CX18_ENC_STREAM_TYPE_TS && s->dvb.enabled) {
  69                         /* process the buffer here */
  70                         CX18_DEBUG_HI_DMA("TS recv and sent bytesused=%d\n",
  71                                         buf->bytesused);
  72
  73                         dvb_dmx_swfilter(&s->dvb.demux, buf->buf,
  74                                         buf->bytesused);
  75
  76                         cx18_buf_sync_for_device(s, buf);
  77                         cx18_vapi(cx, CX18_CPU_DE_SET_MDL, 5, s->handle,
  78                             (void __iomem *)&cx->scb->cpu_mdl[buf->id] - cx->enc_mem,
  79                             1, buf->id, s->buf_size);
  80                 } else
  81                         set_bit(CX18_F_B_NEED_BUF_SWAP, &buf->b_flags);
  82         } else {
  83                 CX18_WARN("Could not find buf %d for stream %s\n",
  84                                 read_enc(off), s->name);
  85         }
  86         mb->error = 0;
  87         mb->cmd = 0;
  88         cx18_mb_ack(cx, mb);
  89         wake_up(&cx->dma_waitq);
  90         if (s->id != -1)
  91                 wake_up(&s->waitq);
  92 }
  93
  94 static void epu_debug(struct cx18 *cx, struct cx18_mailbox *mb)
  95 {
  96         char str[256] = { 0 };
  97         char *p;
  98
  99         if (mb->args[1]) {
 100                 setup_page(mb->args[1]);
 101                 memcpy_fromio(str, cx->enc_mem + mb->args[1], 252);
 102                 str[252] = 0;
 103         }
 104         cx18_mb_ack(cx, mb);
 105         CX18_DEBUG_INFO("%x %s\n", mb->args[0], str);
 106         p = strchr(str, '.');
 107         if (!test_bit(CX18_F_I_LOADED_FW, &cx->i_flags) && p && p > str)
 108                 CX18_INFO("FW version: %s\n", p - 1);
 109 }
 110
 111 static void hpu_cmd(struct cx18 *cx, u32 sw1)
 112 {
 113         struct cx18_mailbox mb;
 114
 115         if (sw1 & IRQ_CPU_TO_EPU) {
 116                 memcpy_fromio(&mb, &cx->scb->cpu2epu_mb, sizeof(mb));
 117                 mb.error = 0;
 118
 119                 switch (mb.cmd) {
 120                 case CX18_EPU_DMA_DONE:
 121                         epu_dma_done(cx, &mb);
 122                         break;
 123                 case CX18_EPU_DEBUG:
 124                         epu_debug(cx, &mb);
 125                         break;
 126                 default:
 127                         CX18_WARN("Unexpected mailbox command %08x\n", mb.cmd);
 128                         break;
 129                 }
 130         }
 131         if (sw1 & (IRQ_APU_TO_EPU | IRQ_HPU_TO_EPU))
 132                 CX18_WARN("Unexpected interrupt %08x\n", sw1);
 133 }
 134
 135 irqreturn_t cx18_irq_handler(int irq, void *dev_id)
 136 {
 137         struct cx18 *cx = (struct cx18 *)dev_id;
 138         u32 sw1, sw1_mask;
 139         u32 sw2, sw2_mask;
 140         u32 hw2, hw2_mask;
 141
 142         spin_lock(&cx->dma_reg_lock);
 143
 144         hw2_mask = read_reg(HW2_INT_MASK5_PCI);
 145         hw2 = read_reg(HW2_INT_CLR_STATUS) & hw2_mask;
 146         sw2_mask = read_reg(SW2_INT_ENABLE_PCI) | IRQ_EPU_TO_HPU_ACK;
 147         sw2 = read_reg(SW2_INT_STATUS) & sw2_mask;
 148         sw1_mask = read_reg(SW1_INT_ENABLE_PCI) | IRQ_EPU_TO_HPU;
 149         sw1 = read_reg(SW1_INT_STATUS) & sw1_mask;
 150
 151         write_reg(sw2&sw2_mask, SW2_INT_STATUS);
 152         write_reg(sw1&sw1_mask, SW1_INT_STATUS);
 153         write_reg(hw2&hw2_mask, HW2_INT_CLR_STATUS);
 154
 155         if (sw1 || sw2 || hw2)
 156                 CX18_DEBUG_HI_IRQ("SW1: %x  SW2: %x  HW2: %x\n", sw1, sw2, hw2);
 157
 158         /* To do: interrupt-based I2C handling
 159         if (hw2 & 0x00c00000) {
 160         }
 161         */
 162
 163         if (sw2) {
 164                 if (sw2 & (readl(&cx->scb->cpu2hpu_irq_ack) |
 165                            readl(&cx->scb->cpu2epu_irq_ack)))
 166                         wake_up(&cx->mb_cpu_waitq);
 167                 if (sw2 & (readl(&cx->scb->apu2hpu_irq_ack) |
 168                            readl(&cx->scb->apu2epu_irq_ack)))
 169                         wake_up(&cx->mb_apu_waitq);
 170                 if (sw2 & readl(&cx->scb->epu2hpu_irq_ack))
 171                         wake_up(&cx->mb_epu_waitq);
 172                 if (sw2 & readl(&cx->scb->hpu2epu_irq_ack))
 173                         wake_up(&cx->mb_hpu_waitq);
 174         }
 175
 176         if (sw1)
 177                 hpu_cmd(cx, sw1);
 178         spin_unlock(&cx->dma_reg_lock);
 179
 180         return (hw2 | sw1 | sw2) ? IRQ_HANDLED : IRQ_NONE;
 181 }