2 * linux/arch/arm/mach-realview/platsmp.c
4 * Copyright (C) 2002 ARM Ltd.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 #include <linux/init.h>
12 #include <linux/errno.h>
13 #include <linux/delay.h>
14 #include <linux/device.h>
15 #include <linux/smp.h>
17 #include <asm/cacheflush.h>
18 #include <asm/hardware.h>
20 #include <asm/mach-types.h>
22 #include <asm/arch/board-eb.h>
23 #include <asm/arch/board-pb11mp.h>
24 #include <asm/arch/scu.h>
26 extern void realview_secondary_startup(void);
29 * control for which core is the next to come out of the secondary
32 volatile int __cpuinitdata pen_release = -1;
34 static unsigned int __init get_core_count(void)
37 void __iomem *scu_base = 0;
39 if (machine_is_realview_eb() && core_tile_eb11mp())
40 scu_base = __io_address(REALVIEW_EB11MP_SCU_BASE);
41 else if (machine_is_realview_pb11mp())
42 scu_base = __io_address(REALVIEW_TC11MP_SCU_BASE);
45 ncores = __raw_readl(scu_base + SCU_CONFIG);
46 ncores = (ncores & 0x03) + 1;
56 static void scu_enable(void)
59 void __iomem *scu_base;
61 if (machine_is_realview_eb() && core_tile_eb11mp())
62 scu_base = __io_address(REALVIEW_EB11MP_SCU_BASE);
63 else if (machine_is_realview_pb11mp())
64 scu_base = __io_address(REALVIEW_TC11MP_SCU_BASE);
68 scu_ctrl = __raw_readl(scu_base + SCU_CTRL);
70 __raw_writel(scu_ctrl, scu_base + SCU_CTRL);
73 static DEFINE_SPINLOCK(boot_lock);
75 void __cpuinit platform_secondary_init(unsigned int cpu)
80 * the primary core may have used a "cross call" soft interrupt
81 * to get this processor out of WFI in the BootMonitor - make
82 * sure that we are no longer being sent this soft interrupt
84 smp_cross_call_done(cpumask_of_cpu(cpu));
87 * if any interrupts are already enabled for the primary
88 * core (e.g. timer irq), then they will not have been enabled
91 if (machine_is_realview_eb() && core_tile_eb11mp())
92 gic_cpu_init(0, __io_address(REALVIEW_EB11MP_GIC_CPU_BASE));
93 else if (machine_is_realview_pb11mp())
94 gic_cpu_init(0, __io_address(REALVIEW_TC11MP_GIC_CPU_BASE));
97 * let the primary processor know we're out of the
98 * pen, then head off into the C entry point
104 * Synchronise with the boot thread.
106 spin_lock(&boot_lock);
107 spin_unlock(&boot_lock);
110 int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
112 unsigned long timeout;
115 * set synchronisation state between this boot processor
116 * and the secondary one
118 spin_lock(&boot_lock);
121 * The secondary processor is waiting to be released from
122 * the holding pen - release it, then wait for it to flag
123 * that it has been released by resetting pen_release.
125 * Note that "pen_release" is the hardware CPU ID, whereas
126 * "cpu" is Linux's internal ID.
134 * This is a later addition to the booting protocol: the
135 * bootMonitor now puts secondary cores into WFI, so
136 * poke_milo() no longer gets the cores moving; we need
137 * to send a soft interrupt to wake the secondary core.
138 * Use smp_cross_call() for this, since there's little
139 * point duplicating the code here
141 smp_cross_call(cpumask_of_cpu(cpu));
143 timeout = jiffies + (1 * HZ);
144 while (time_before(jiffies, timeout)) {
146 if (pen_release == -1)
153 * now the secondary core is starting up let it run its
154 * calibrations, then wait for it to finish
156 spin_unlock(&boot_lock);
158 return pen_release != -1 ? -ENOSYS : 0;
161 static void __init poke_milo(void)
163 extern void secondary_startup(void);
165 /* nobody is to be released from the pen yet */
169 * write the address of secondary startup into the system-wide
170 * flags register, then clear the bottom two bits, which is what
171 * BootMonitor is waiting for
174 #define REALVIEW_SYS_FLAGSS_OFFSET 0x30
175 __raw_writel(virt_to_phys(realview_secondary_startup),
176 __io_address(REALVIEW_SYS_BASE) +
177 REALVIEW_SYS_FLAGSS_OFFSET);
178 #define REALVIEW_SYS_FLAGSC_OFFSET 0x34
180 __io_address(REALVIEW_SYS_BASE) +
181 REALVIEW_SYS_FLAGSC_OFFSET);
188 * Initialise the CPU possible map early - this describes the CPUs
189 * which may be present or become present in the system.
191 void __init smp_init_cpus(void)
193 unsigned int i, ncores = get_core_count();
195 for (i = 0; i < ncores; i++)
196 cpu_set(i, cpu_possible_map);
199 void __init smp_prepare_cpus(unsigned int max_cpus)
201 unsigned int ncores = get_core_count();
202 unsigned int cpu = smp_processor_id();
208 "Realview: strange CM count of 0? Default to 1\n");
213 if (ncores > NR_CPUS) {
215 "Realview: no. of cores (%d) greater than configured "
216 "maximum of %d - clipping\n",
221 smp_store_cpu_info(cpu);
224 * are we trying to boot more cores than exist?
226 if (max_cpus > ncores)
229 #ifdef CONFIG_LOCAL_TIMERS
231 * Enable the local timer for primary CPU. If the device is
232 * dummy (!CONFIG_LOCAL_TIMERS), it was already registers in
233 * realview_timer_init
235 if ((machine_is_realview_eb() && core_tile_eb11mp()) ||
236 machine_is_realview_pb11mp())
237 local_timer_setup(cpu);
241 * Initialise the present map, which describes the set of CPUs
242 * actually populated at the present time.
244 for (i = 0; i < max_cpus; i++)
245 cpu_set(i, cpu_present_map);
248 * Initialise the SCU if there are more than one CPU and let
249 * them know where to start. Note that, on modern versions of
250 * MILO, the "poke" doesn't actually do anything until each
251 * individual core is sent a soft interrupt to get it out of