git.oblomov.eu Git - linux-2.6/blob - drivers/media/dvb/frontends/tda1004x.c

   1   /*
   2      Driver for Philips tda1004xh OFDM Demodulator
   3
   4      (c) 2003, 2004 Andrew de Quincey & Robert Schlabbach
   5
   6      This program is free software; you can redistribute it and/or modify
   7      it under the terms of the GNU General Public License as published by
   8      the Free Software Foundation; either version 2 of the License, or
   9      (at your option) any later version.
  10
  11      This program is distributed in the hope that it will be useful,
  12      but WITHOUT ANY WARRANTY; without even the implied warranty of
  13      MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14
  15      GNU General Public License for more details.
  16
  17      You should have received a copy of the GNU General Public License
  18      along with this program; if not, write to the Free Software
  19      Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20
  21    */
  22 /*
  23  * This driver needs external firmware. Please use the commands
  24  * "<kerneldir>/Documentation/dvb/get_dvb_firmware tda10045",
  25  * "<kerneldir>/Documentation/dvb/get_dvb_firmware tda10046" to
  26  * download/extract them, and then copy them to /usr/lib/hotplug/firmware
  27  * or /lib/firmware (depending on configuration of firmware hotplug).
  28  */
  29 #define TDA10045_DEFAULT_FIRMWARE "dvb-fe-tda10045.fw"
  30 #define TDA10046_DEFAULT_FIRMWARE "dvb-fe-tda10046.fw"
  31
  32 #include <linux/init.h>
  33 #include <linux/module.h>
  34 #include <linux/moduleparam.h>
  35 #include <linux/device.h>
  36 #include <linux/jiffies.h>
  37 #include <linux/string.h>
  38 #include <linux/slab.h>
  39
  40 #include "dvb_frontend.h"
  41 #include "tda1004x.h"
  42
  43 enum tda1004x_demod {
  44         TDA1004X_DEMOD_TDA10045,
  45         TDA1004X_DEMOD_TDA10046,
  46 };
  47
  48 struct tda1004x_state {
  49         struct i2c_adapter* i2c;
  50         struct dvb_frontend_ops ops;
  51         const struct tda1004x_config* config;
  52         struct dvb_frontend frontend;
  53
  54         /* private demod data */
  55         enum tda1004x_demod demod_type;
  56 };
  57
  58 static int debug;
  59 #define dprintk(args...) \
  60         do { \
  61                 if (debug) printk(KERN_DEBUG "tda1004x: " args); \
  62         } while (0)
  63
  64 #define TDA1004X_CHIPID          0x00
  65 #define TDA1004X_AUTO            0x01
  66 #define TDA1004X_IN_CONF1        0x02
  67 #define TDA1004X_IN_CONF2        0x03
  68 #define TDA1004X_OUT_CONF1       0x04
  69 #define TDA1004X_OUT_CONF2       0x05
  70 #define TDA1004X_STATUS_CD       0x06
  71 #define TDA1004X_CONFC4          0x07
  72 #define TDA1004X_DSSPARE2        0x0C
  73 #define TDA10045H_CODE_IN        0x0D
  74 #define TDA10045H_FWPAGE         0x0E
  75 #define TDA1004X_SCAN_CPT        0x10
  76 #define TDA1004X_DSP_CMD         0x11
  77 #define TDA1004X_DSP_ARG         0x12
  78 #define TDA1004X_DSP_DATA1       0x13
  79 #define TDA1004X_DSP_DATA2       0x14
  80 #define TDA1004X_CONFADC1        0x15
  81 #define TDA1004X_CONFC1          0x16
  82 #define TDA10045H_S_AGC          0x1a
  83 #define TDA10046H_AGC_TUN_LEVEL  0x1a
  84 #define TDA1004X_SNR             0x1c
  85 #define TDA1004X_CONF_TS1        0x1e
  86 #define TDA1004X_CONF_TS2        0x1f
  87 #define TDA1004X_CBER_RESET      0x20
  88 #define TDA1004X_CBER_MSB        0x21
  89 #define TDA1004X_CBER_LSB        0x22
  90 #define TDA1004X_CVBER_LUT       0x23
  91 #define TDA1004X_VBER_MSB        0x24
  92 #define TDA1004X_VBER_MID        0x25
  93 #define TDA1004X_VBER_LSB        0x26
  94 #define TDA1004X_UNCOR           0x27
  95
  96 #define TDA10045H_CONFPLL_P      0x2D
  97 #define TDA10045H_CONFPLL_M_MSB  0x2E
  98 #define TDA10045H_CONFPLL_M_LSB  0x2F
  99 #define TDA10045H_CONFPLL_N      0x30
 100
 101 #define TDA10046H_CONFPLL1       0x2D
 102 #define TDA10046H_CONFPLL2       0x2F
 103 #define TDA10046H_CONFPLL3       0x30
 104 #define TDA10046H_TIME_WREF1     0x31
 105 #define TDA10046H_TIME_WREF2     0x32
 106 #define TDA10046H_TIME_WREF3     0x33
 107 #define TDA10046H_TIME_WREF4     0x34
 108 #define TDA10046H_TIME_WREF5     0x35
 109
 110 #define TDA10045H_UNSURW_MSB     0x31
 111 #define TDA10045H_UNSURW_LSB     0x32
 112 #define TDA10045H_WREF_MSB       0x33
 113 #define TDA10045H_WREF_MID       0x34
 114 #define TDA10045H_WREF_LSB       0x35
 115 #define TDA10045H_MUXOUT         0x36
 116 #define TDA1004X_CONFADC2        0x37
 117
 118 #define TDA10045H_IOFFSET        0x38
 119
 120 #define TDA10046H_CONF_TRISTATE1 0x3B
 121 #define TDA10046H_CONF_TRISTATE2 0x3C
 122 #define TDA10046H_CONF_POLARITY  0x3D
 123 #define TDA10046H_FREQ_OFFSET    0x3E
 124 #define TDA10046H_GPIO_OUT_SEL   0x41
 125 #define TDA10046H_GPIO_SELECT    0x42
 126 #define TDA10046H_AGC_CONF       0x43
 127 #define TDA10046H_AGC_THR        0x44
 128 #define TDA10046H_AGC_RENORM     0x45
 129 #define TDA10046H_AGC_GAINS      0x46
 130 #define TDA10046H_AGC_TUN_MIN    0x47
 131 #define TDA10046H_AGC_TUN_MAX    0x48
 132 #define TDA10046H_AGC_IF_MIN     0x49
 133 #define TDA10046H_AGC_IF_MAX     0x4A
 134
 135 #define TDA10046H_FREQ_PHY2_MSB  0x4D
 136 #define TDA10046H_FREQ_PHY2_LSB  0x4E
 137
 138 #define TDA10046H_CVBER_CTRL     0x4F
 139 #define TDA10046H_AGC_IF_LEVEL   0x52
 140 #define TDA10046H_CODE_CPT       0x57
 141 #define TDA10046H_CODE_IN        0x58
 142
 143
 144 static int tda1004x_write_byteI(struct tda1004x_state *state, int reg, int data)
 145 {
 146         int ret;
 147         u8 buf[] = { reg, data };
 148         struct i2c_msg msg = { .flags = 0, .buf = buf, .len = 2 };
 149
 150         dprintk("%s: reg=0x%x, data=0x%x\n", __FUNCTION__, reg, data);
 151
 152         msg.addr = state->config->demod_address;
 153         ret = i2c_transfer(state->i2c, &msg, 1);
 154
 155         if (ret != 1)
 156                 dprintk("%s: error reg=0x%x, data=0x%x, ret=%i\n",
 157                         __FUNCTION__, reg, data, ret);
 158
 159         dprintk("%s: success reg=0x%x, data=0x%x, ret=%i\n", __FUNCTION__,
 160                 reg, data, ret);
 161         return (ret != 1) ? -1 : 0;
 162 }
 163
 164 static int tda1004x_read_byte(struct tda1004x_state *state, int reg)
 165 {
 166         int ret;
 167         u8 b0[] = { reg };
 168         u8 b1[] = { 0 };
 169         struct i2c_msg msg[] = {{ .flags = 0, .buf = b0, .len = 1 },
 170                                 { .flags = I2C_M_RD, .buf = b1, .len = 1 }};
 171
 172         dprintk("%s: reg=0x%x\n", __FUNCTION__, reg);
 173
 174         msg[0].addr = state->config->demod_address;
 175         msg[1].addr = state->config->demod_address;
 176         ret = i2c_transfer(state->i2c, msg, 2);
 177
 178         if (ret != 2) {
 179                 dprintk("%s: error reg=0x%x, ret=%i\n", __FUNCTION__, reg,
 180                         ret);
 181                 return -1;
 182         }
 183
 184         dprintk("%s: success reg=0x%x, data=0x%x, ret=%i\n", __FUNCTION__,
 185                 reg, b1[0], ret);
 186         return b1[0];
 187 }
 188
 189 static int tda1004x_write_mask(struct tda1004x_state *state, int reg, int mask, int data)
 190 {
 191         int val;
 192         dprintk("%s: reg=0x%x, mask=0x%x, data=0x%x\n", __FUNCTION__, reg,
 193                 mask, data);
 194
 195         // read a byte and check
 196         val = tda1004x_read_byte(state, reg);
 197         if (val < 0)
 198                 return val;
 199
 200         // mask if off
 201         val = val & ~mask;
 202         val |= data & 0xff;
 203
 204         // write it out again
 205         return tda1004x_write_byteI(state, reg, val);
 206 }
 207
 208 static int tda1004x_write_buf(struct tda1004x_state *state, int reg, unsigned char *buf, int len)
 209 {
 210         int i;
 211         int result;
 212
 213         dprintk("%s: reg=0x%x, len=0x%x\n", __FUNCTION__, reg, len);
 214
 215         result = 0;
 216         for (i = 0; i < len; i++) {
 217                 result = tda1004x_write_byteI(state, reg + i, buf[i]);
 218                 if (result != 0)
 219                         break;
 220         }
 221
 222         return result;
 223 }
 224
 225 static int tda1004x_enable_tuner_i2c(struct tda1004x_state *state)
 226 {
 227         int result;
 228         dprintk("%s\n", __FUNCTION__);
 229
 230         result = tda1004x_write_mask(state, TDA1004X_CONFC4, 2, 2);
 231         msleep(20);
 232         return result;
 233 }
 234
 235 static int tda1004x_disable_tuner_i2c(struct tda1004x_state *state)
 236 {
 237         dprintk("%s\n", __FUNCTION__);
 238
 239         return tda1004x_write_mask(state, TDA1004X_CONFC4, 2, 0);
 240 }
 241
 242 static int tda10045h_set_bandwidth(struct tda1004x_state *state,
 243                                    fe_bandwidth_t bandwidth)
 244 {
 245         static u8 bandwidth_6mhz[] = { 0x02, 0x00, 0x3d, 0x00, 0x60, 0x1e, 0xa7, 0x45, 0x4f };
 246         static u8 bandwidth_7mhz[] = { 0x02, 0x00, 0x37, 0x00, 0x4a, 0x2f, 0x6d, 0x76, 0xdb };
 247         static u8 bandwidth_8mhz[] = { 0x02, 0x00, 0x3d, 0x00, 0x48, 0x17, 0x89, 0xc7, 0x14 };
 248
 249         switch (bandwidth) {
 250         case BANDWIDTH_6_MHZ:
 251                 tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_6mhz, sizeof(bandwidth_6mhz));
 252                 break;
 253
 254         case BANDWIDTH_7_MHZ:
 255                 tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_7mhz, sizeof(bandwidth_7mhz));
 256                 break;
 257
 258         case BANDWIDTH_8_MHZ:
 259                 tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_8mhz, sizeof(bandwidth_8mhz));
 260                 break;
 261
 262         default:
 263                 return -EINVAL;
 264         }
 265
 266         tda1004x_write_byteI(state, TDA10045H_IOFFSET, 0);
 267
 268         return 0;
 269 }
 270
 271 static int tda10046h_set_bandwidth(struct tda1004x_state *state,
 272                                    fe_bandwidth_t bandwidth)
 273 {
 274         static u8 bandwidth_6mhz_53M[] = { 0x7b, 0x2e, 0x11, 0xf0, 0xd2 };
 275         static u8 bandwidth_7mhz_53M[] = { 0x6a, 0x02, 0x6a, 0x43, 0x9f };
 276         static u8 bandwidth_8mhz_53M[] = { 0x5c, 0x32, 0xc2, 0x96, 0x6d };
 277
 278         static u8 bandwidth_6mhz_48M[] = { 0x70, 0x02, 0x49, 0x24, 0x92 };
 279         static u8 bandwidth_7mhz_48M[] = { 0x60, 0x02, 0xaa, 0xaa, 0xab };
 280         static u8 bandwidth_8mhz_48M[] = { 0x54, 0x03, 0x0c, 0x30, 0xc3 };
 281         int tda10046_clk53m;
 282
 283         if ((state->config->if_freq == TDA10046_FREQ_045) ||
 284             (state->config->if_freq == TDA10046_FREQ_052))
 285                 tda10046_clk53m = 0;
 286         else
 287                 tda10046_clk53m = 1;
 288         switch (bandwidth) {
 289         case BANDWIDTH_6_MHZ:
 290                 if (tda10046_clk53m)
 291                         tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_6mhz_53M,
 292                                                   sizeof(bandwidth_6mhz_53M));
 293                 else
 294                         tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_6mhz_48M,
 295                                                   sizeof(bandwidth_6mhz_48M));
 296                 if (state->config->if_freq == TDA10046_FREQ_045) {
 297                         tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0a);
 298                         tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0xab);
 299                 }
 300                 break;
 301
 302         case BANDWIDTH_7_MHZ:
 303                 if (tda10046_clk53m)
 304                         tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_7mhz_53M,
 305                                                   sizeof(bandwidth_7mhz_53M));
 306                 else
 307                         tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_7mhz_48M,
 308                                                   sizeof(bandwidth_7mhz_48M));
 309                 if (state->config->if_freq == TDA10046_FREQ_045) {
 310                         tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0c);
 311                         tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x00);
 312                 }
 313                 break;
 314
 315         case BANDWIDTH_8_MHZ:
 316                 if (tda10046_clk53m)
 317                         tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_8mhz_53M,
 318                                                   sizeof(bandwidth_8mhz_53M));
 319                 else
 320                         tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_8mhz_48M,
 321                                                   sizeof(bandwidth_8mhz_48M));
 322                 if (state->config->if_freq == TDA10046_FREQ_045) {
 323                         tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0d);
 324                         tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x55);
 325                 }
 326                 break;
 327
 328         default:
 329                 return -EINVAL;
 330         }
 331
 332         return 0;
 333 }
 334
 335 static int tda1004x_do_upload(struct tda1004x_state *state,
 336                               unsigned char *mem, unsigned int len,
 337                               u8 dspCodeCounterReg, u8 dspCodeInReg)
 338 {
 339         u8 buf[65];
 340         struct i2c_msg fw_msg = { .flags = 0, .buf = buf, .len = 0 };
 341         int tx_size;
 342         int pos = 0;
 343
 344         /* clear code counter */
 345         tda1004x_write_byteI(state, dspCodeCounterReg, 0);
 346         fw_msg.addr = state->config->demod_address;
 347
 348         buf[0] = dspCodeInReg;
 349         while (pos != len) {
 350                 // work out how much to send this time
 351                 tx_size = len - pos;
 352                 if (tx_size > 0x10)
 353                         tx_size = 0x10;
 354
 355                 // send the chunk
 356                 memcpy(buf + 1, mem + pos, tx_size);
 357                 fw_msg.len = tx_size + 1;
 358                 if (i2c_transfer(state->i2c, &fw_msg, 1) != 1) {
 359                         printk(KERN_ERR "tda1004x: Error during firmware upload\n");
 360                         return -EIO;
 361                 }
 362                 pos += tx_size;
 363
 364                 dprintk("%s: fw_pos=0x%x\n", __FUNCTION__, pos);
 365         }
 366         // give the DSP a chance to settle 03/10/05 Hac
 367         msleep(100);
 368
 369         return 0;
 370 }
 371
 372 static int tda1004x_check_upload_ok(struct tda1004x_state *state)
 373 {
 374         u8 data1, data2;
 375         unsigned long timeout;
 376
 377         if (state->demod_type == TDA1004X_DEMOD_TDA10046) {
 378                 timeout = jiffies + 2 * HZ;
 379                 while(!(tda1004x_read_byte(state, TDA1004X_STATUS_CD) & 0x20)) {
 380                         if (time_after(jiffies, timeout)) {
 381                                 printk(KERN_ERR "tda1004x: timeout waiting for DSP ready\n");
 382                                 break;
 383                         }
 384                         msleep(1);
 385                 }
 386         } else
 387                 msleep(100);
 388
 389         // check upload was OK
 390         tda1004x_write_mask(state, TDA1004X_CONFC4, 0x10, 0); // we want to read from the DSP
 391         tda1004x_write_byteI(state, TDA1004X_DSP_CMD, 0x67);
 392
 393         data1 = tda1004x_read_byte(state, TDA1004X_DSP_DATA1);
 394         data2 = tda1004x_read_byte(state, TDA1004X_DSP_DATA2);
 395         if (data1 != 0x67 || data2 < 0x20 || data2 > 0x2e) {
 396                 printk(KERN_INFO "tda1004x: found firmware revision %x -- invalid\n", data2);
 397                 return -EIO;
 398         }
 399         printk(KERN_INFO "tda1004x: found firmware revision %x -- ok\n", data2);
 400         return 0;
 401 }
 402
 403 static int tda10045_fwupload(struct dvb_frontend* fe)
 404 {
 405         struct tda1004x_state* state = fe->demodulator_priv;
 406         int ret;
 407         const struct firmware *fw;
 408
 409         /* don't re-upload unless necessary */
 410         if (tda1004x_check_upload_ok(state) == 0)
 411                 return 0;
 412
 413         /* request the firmware, this will block until someone uploads it */
 414         printk(KERN_INFO "tda1004x: waiting for firmware upload (%s)...\n", TDA10045_DEFAULT_FIRMWARE);
 415         ret = state->config->request_firmware(fe, &fw, TDA10045_DEFAULT_FIRMWARE);
 416         if (ret) {
 417                 printk(KERN_ERR "tda1004x: no firmware upload (timeout or file not found?)\n");
 418                 return ret;
 419         }
 420
 421         /* reset chip */
 422         tda1004x_write_mask(state, TDA1004X_CONFC4, 0x10, 0);
 423         tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8);
 424         tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 0);
 425         msleep(10);
 426
 427         /* set parameters */
 428         tda10045h_set_bandwidth(state, BANDWIDTH_8_MHZ);
 429
 430         ret = tda1004x_do_upload(state, fw->data, fw->size, TDA10045H_FWPAGE, TDA10045H_CODE_IN);
 431         release_firmware(fw);
 432         if (ret)
 433                 return ret;
 434         printk(KERN_INFO "tda1004x: firmware upload complete\n");
 435
 436         /* wait for DSP to initialise */
 437         /* DSPREADY doesn't seem to work on the TDA10045H */
 438         msleep(100);
 439
 440         return tda1004x_check_upload_ok(state);
 441 }
 442
 443 static void tda10046_init_plls(struct dvb_frontend* fe)
 444 {
 445         struct tda1004x_state* state = fe->demodulator_priv;
 446         int tda10046_clk53m;
 447
 448         if ((state->config->if_freq == TDA10046_FREQ_045) ||
 449             (state->config->if_freq == TDA10046_FREQ_052))
 450                 tda10046_clk53m = 0;
 451         else
 452                 tda10046_clk53m = 1;
 453
 454         tda1004x_write_byteI(state, TDA10046H_CONFPLL1, 0xf0);
 455         if(tda10046_clk53m) {
 456                 printk(KERN_INFO "tda1004x: setting up plls for 53MHz sampling clock\n");
 457                 tda1004x_write_byteI(state, TDA10046H_CONFPLL2, 0x08); // PLL M = 8
 458         } else {
 459                 printk(KERN_INFO "tda1004x: setting up plls for 48MHz sampling clock\n");
 460                 tda1004x_write_byteI(state, TDA10046H_CONFPLL2, 0x03); // PLL M = 3
 461         }
 462         if (state->config->xtal_freq == TDA10046_XTAL_4M ) {
 463                 dprintk("%s: setting up PLLs for a 4 MHz Xtal\n", __FUNCTION__);
 464                 tda1004x_write_byteI(state, TDA10046H_CONFPLL3, 0); // PLL P = N = 0
 465         } else {
 466                 dprintk("%s: setting up PLLs for a 16 MHz Xtal\n", __FUNCTION__);
 467                 tda1004x_write_byteI(state, TDA10046H_CONFPLL3, 3); // PLL P = 0, N = 3
 468         }
 469         if(tda10046_clk53m)
 470                 tda1004x_write_byteI(state, TDA10046H_FREQ_OFFSET, 0x67);
 471         else
 472                 tda1004x_write_byteI(state, TDA10046H_FREQ_OFFSET, 0x72);
 473         /* Note clock frequency is handled implicitly */
 474         switch (state->config->if_freq) {
 475         case TDA10046_FREQ_045:
 476                 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0c);
 477                 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x00);
 478                 break;
 479         case TDA10046_FREQ_052:
 480                 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0d);
 481                 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0xc7);
 482                 break;
 483         case TDA10046_FREQ_3617:
 484                 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0xd7);
 485                 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x59);
 486                 break;
 487         case TDA10046_FREQ_3613:
 488                 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0xd7);
 489                 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x3f);
 490                 break;
 491         }
 492         tda10046h_set_bandwidth(state, BANDWIDTH_8_MHZ); // default bandwidth 8 MHz
 493         /* let the PLLs settle */
 494         msleep(120);
 495 }
 496
 497 static int tda10046_fwupload(struct dvb_frontend* fe)
 498 {
 499         struct tda1004x_state* state = fe->demodulator_priv;
 500         int ret;
 501         const struct firmware *fw;
 502
 503         /* reset + wake up chip */
 504         if (state->config->xtal_freq == TDA10046_XTAL_4M) {
 505                 tda1004x_write_byteI(state, TDA1004X_CONFC4, 0);
 506         } else {
 507                 dprintk("%s: 16MHz Xtal, reducing I2C speed\n", __FUNCTION__);
 508                 tda1004x_write_byteI(state, TDA1004X_CONFC4, 0x80);
 509         }
 510         tda1004x_write_mask(state, TDA10046H_CONF_TRISTATE1, 1, 0);
 511         /* let the clocks recover from sleep */
 512         msleep(5);
 513
 514         /* The PLLs need to be reprogrammed after sleep */
 515         tda10046_init_plls(fe);
 516
 517         /* don't re-upload unless necessary */
 518         if (tda1004x_check_upload_ok(state) == 0)
 519                 return 0;
 520
 521         if (state->config->request_firmware != NULL) {
 522                 /* request the firmware, this will block until someone uploads it */
 523                 printk(KERN_INFO "tda1004x: waiting for firmware upload...\n");
 524                 ret = state->config->request_firmware(fe, &fw, TDA10046_DEFAULT_FIRMWARE);
 525                 if (ret) {
 526                         printk(KERN_ERR "tda1004x: no firmware upload (timeout or file not found?)\n");
 527                         return ret;
 528                 }
 529                 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8); // going to boot from HOST
 530                 ret = tda1004x_do_upload(state, fw->data, fw->size, TDA10046H_CODE_CPT, TDA10046H_CODE_IN);
 531                 release_firmware(fw);
 532                 if (ret)
 533                         return ret;
 534         } else {
 535                 /* boot from firmware eeprom */
 536                 printk(KERN_INFO "tda1004x: booting from eeprom\n");
 537                 tda1004x_write_mask(state, TDA1004X_CONFC4, 4, 4);
 538                 msleep(300);
 539         }
 540         return tda1004x_check_upload_ok(state);
 541 }
 542
 543 static int tda1004x_encode_fec(int fec)
 544 {
 545         // convert known FEC values
 546         switch (fec) {
 547         case FEC_1_2:
 548                 return 0;
 549         case FEC_2_3:
 550                 return 1;
 551         case FEC_3_4:
 552                 return 2;
 553         case FEC_5_6:
 554                 return 3;
 555         case FEC_7_8:
 556                 return 4;
 557         }
 558
 559         // unsupported
 560         return -EINVAL;
 561 }
 562
 563 static int tda1004x_decode_fec(int tdafec)
 564 {
 565         // convert known FEC values
 566         switch (tdafec) {
 567         case 0:
 568                 return FEC_1_2;
 569         case 1:
 570                 return FEC_2_3;
 571         case 2:
 572                 return FEC_3_4;
 573         case 3:
 574                 return FEC_5_6;
 575         case 4:
 576                 return FEC_7_8;
 577         }
 578
 579         // unsupported
 580         return -1;
 581 }
 582
 583 int tda1004x_write_byte(struct dvb_frontend* fe, int reg, int data)
 584 {
 585         struct tda1004x_state* state = fe->demodulator_priv;
 586
 587         return tda1004x_write_byteI(state, reg, data);
 588 }
 589
 590 static int tda10045_init(struct dvb_frontend* fe)
 591 {
 592         struct tda1004x_state* state = fe->demodulator_priv;
 593
 594         dprintk("%s\n", __FUNCTION__);
 595
 596         if (tda10045_fwupload(fe)) {
 597                 printk("tda1004x: firmware upload failed\n");
 598                 return -EIO;
 599         }
 600
 601         tda1004x_write_mask(state, TDA1004X_CONFADC1, 0x10, 0); // wake up the ADC
 602
 603         // tda setup
 604         tda1004x_write_mask(state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer
 605         tda1004x_write_mask(state, TDA1004X_AUTO, 8, 0); // select HP stream
 606         tda1004x_write_mask(state, TDA1004X_CONFC1, 0x40, 0); // set polarity of VAGC signal
 607         tda1004x_write_mask(state, TDA1004X_CONFC1, 0x80, 0x80); // enable pulse killer
 608         tda1004x_write_mask(state, TDA1004X_AUTO, 0x10, 0x10); // enable auto offset
 609         tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0xC0, 0x0); // no frequency offset
 610         tda1004x_write_byteI(state, TDA1004X_CONF_TS1, 0); // setup MPEG2 TS interface
 611         tda1004x_write_byteI(state, TDA1004X_CONF_TS2, 0); // setup MPEG2 TS interface
 612         tda1004x_write_mask(state, TDA1004X_VBER_MSB, 0xe0, 0xa0); // 10^6 VBER measurement bits
 613         tda1004x_write_mask(state, TDA1004X_CONFC1, 0x10, 0); // VAGC polarity
 614         tda1004x_write_byteI(state, TDA1004X_CONFADC1, 0x2e);
 615
 616         tda1004x_write_mask(state, 0x1f, 0x01, state->config->invert_oclk);
 617
 618         return 0;
 619 }
 620
 621 static int tda10046_init(struct dvb_frontend* fe)
 622 {
 623         struct tda1004x_state* state = fe->demodulator_priv;
 624         dprintk("%s\n", __FUNCTION__);
 625
 626         if (tda10046_fwupload(fe)) {
 627                 printk("tda1004x: firmware upload failed\n");
 628                         return -EIO;
 629         }
 630
 631         // tda setup
 632         tda1004x_write_mask(state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer
 633         tda1004x_write_byteI(state, TDA1004X_AUTO, 0x87);    // 100 ppm crystal, select HP stream
 634         tda1004x_write_byteI(state, TDA1004X_CONFC1, 0x88);      // enable pulse killer
 635
 636         switch (state->config->agc_config) {
 637         case TDA10046_AGC_DEFAULT:
 638                 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x00); // AGC setup
 639                 tda1004x_write_byteI(state, TDA10046H_CONF_POLARITY, 0x60); // set AGC polarities
 640                 break;
 641         case TDA10046_AGC_IFO_AUTO_NEG:
 642                 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x0a); // AGC setup
 643                 tda1004x_write_byteI(state, TDA10046H_CONF_POLARITY, 0x60); // set AGC polarities
 644                 break;
 645         case TDA10046_AGC_IFO_AUTO_POS:
 646                 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x0a); // AGC setup
 647                 tda1004x_write_byteI(state, TDA10046H_CONF_POLARITY, 0x00); // set AGC polarities
 648                 break;
 649         case TDA10046_AGC_TDA827X:
 650                 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x02);   // AGC setup
 651                 tda1004x_write_byteI(state, TDA10046H_AGC_THR, 0x70);    // AGC Threshold
 652                 tda1004x_write_byteI(state, TDA10046H_AGC_RENORM, 0x08); // Gain Renormalize
 653                 tda1004x_write_byteI(state, TDA10046H_CONF_POLARITY, 0x6a); // set AGC polarities
 654                 break;
 655         case TDA10046_AGC_TDA827X_GPL:
 656                 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x02);   // AGC setup
 657                 tda1004x_write_byteI(state, TDA10046H_AGC_THR, 0x70);    // AGC Threshold
 658                 tda1004x_write_byteI(state, TDA10046H_AGC_RENORM, 0x08); // Gain Renormalize
 659                 tda1004x_write_byteI(state, TDA10046H_CONF_POLARITY, 0x60); // set AGC polarities
 660                 break;
 661         }
 662         tda1004x_write_byteI(state, TDA1004X_CONFADC2, 0x38);
 663         tda1004x_write_byteI(state, TDA10046H_CONF_TRISTATE1, 0x61); // Turn both AGC outputs on
 664         tda1004x_write_byteI(state, TDA10046H_AGC_TUN_MIN, 0);    // }
 665         tda1004x_write_byteI(state, TDA10046H_AGC_TUN_MAX, 0xff); // } AGC min/max values
 666         tda1004x_write_byteI(state, TDA10046H_AGC_IF_MIN, 0);     // }
 667         tda1004x_write_byteI(state, TDA10046H_AGC_IF_MAX, 0xff);  // }
 668         tda1004x_write_byteI(state, TDA10046H_AGC_GAINS, 0x12); // IF gain 2, TUN gain 1
 669         tda1004x_write_byteI(state, TDA10046H_CVBER_CTRL, 0x1a); // 10^6 VBER measurement bits
 670         tda1004x_write_byteI(state, TDA1004X_CONF_TS1, 7); // MPEG2 interface config
 671         tda1004x_write_byteI(state, TDA1004X_CONF_TS2, 0xc0); // MPEG2 interface config
 672         // tda1004x_write_mask(state, 0x50, 0x80, 0x80);         // handle out of guard echoes
 673         tda1004x_write_mask(state, 0x3a, 0x80, state->config->invert_oclk << 7);
 674
 675         return 0;
 676 }
 677
 678 static int tda1004x_set_fe(struct dvb_frontend* fe,
 679                            struct dvb_frontend_parameters *fe_params)
 680 {
 681         struct tda1004x_state* state = fe->demodulator_priv;
 682         int tmp;
 683         int inversion;
 684
 685         dprintk("%s\n", __FUNCTION__);
 686
 687         if (state->demod_type == TDA1004X_DEMOD_TDA10046) {
 688                 // setup auto offset
 689                 tda1004x_write_mask(state, TDA1004X_AUTO, 0x10, 0x10);
 690                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x80, 0);
 691                 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0xC0, 0);
 692
 693                 // disable agc_conf[2]
 694                 tda1004x_write_mask(state, TDA10046H_AGC_CONF, 4, 0);
 695         }
 696
 697         // set frequency
 698         if (fe->ops->tuner_ops.set_params) {
 699                 fe->ops->tuner_ops.set_params(fe, fe_params);
 700                 if (fe->ops->i2c_gate_ctrl) fe->ops->i2c_gate_ctrl(fe, 0);
 701         }
 702
 703         // Hardcoded to use auto as much as possible on the TDA10045 as it
 704         // is very unreliable if AUTO mode is _not_ used.
 705         if (state->demod_type == TDA1004X_DEMOD_TDA10045) {
 706                 fe_params->u.ofdm.code_rate_HP = FEC_AUTO;
 707                 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_AUTO;
 708                 fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_AUTO;
 709         }
 710
 711         // Set standard params.. or put them to auto
 712         if ((fe_params->u.ofdm.code_rate_HP == FEC_AUTO) ||
 713                 (fe_params->u.ofdm.code_rate_LP == FEC_AUTO) ||
 714                 (fe_params->u.ofdm.constellation == QAM_AUTO) ||
 715                 (fe_params->u.ofdm.hierarchy_information == HIERARCHY_AUTO)) {
 716                 tda1004x_write_mask(state, TDA1004X_AUTO, 1, 1);        // enable auto
 717                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x03, 0); // turn off constellation bits
 718                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 0); // turn off hierarchy bits
 719                 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0x3f, 0); // turn off FEC bits
 720         } else {
 721                 tda1004x_write_mask(state, TDA1004X_AUTO, 1, 0);        // disable auto
 722
 723                 // set HP FEC
 724                 tmp = tda1004x_encode_fec(fe_params->u.ofdm.code_rate_HP);
 725                 if (tmp < 0)
 726                         return tmp;
 727                 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 7, tmp);
 728
 729                 // set LP FEC
 730                 tmp = tda1004x_encode_fec(fe_params->u.ofdm.code_rate_LP);
 731                 if (tmp < 0)
 732                         return tmp;
 733                 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0x38, tmp << 3);
 734
 735                 // set constellation
 736                 switch (fe_params->u.ofdm.constellation) {
 737                 case QPSK:
 738                         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 0);
 739                         break;
 740
 741                 case QAM_16:
 742                         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 1);
 743                         break;
 744
 745                 case QAM_64:
 746                         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 2);
 747                         break;
 748
 749                 default:
 750                         return -EINVAL;
 751                 }
 752
 753                 // set hierarchy
 754                 switch (fe_params->u.ofdm.hierarchy_information) {
 755                 case HIERARCHY_NONE:
 756                         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 0 << 5);
 757                         break;
 758
 759                 case HIERARCHY_1:
 760                         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 1 << 5);
 761                         break;
 762
 763                 case HIERARCHY_2:
 764                         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 2 << 5);
 765                         break;
 766
 767                 case HIERARCHY_4:
 768                         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 3 << 5);
 769                         break;
 770
 771                 default:
 772                         return -EINVAL;
 773                 }
 774         }
 775
 776         // set bandwidth
 777         switch (state->demod_type) {
 778         case TDA1004X_DEMOD_TDA10045:
 779                 tda10045h_set_bandwidth(state, fe_params->u.ofdm.bandwidth);
 780                 break;
 781
 782         case TDA1004X_DEMOD_TDA10046:
 783                 tda10046h_set_bandwidth(state, fe_params->u.ofdm.bandwidth);
 784                 break;
 785         }
 786
 787         // set inversion
 788         inversion = fe_params->inversion;
 789         if (state->config->invert)
 790                 inversion = inversion ? INVERSION_OFF : INVERSION_ON;
 791         switch (inversion) {
 792         case INVERSION_OFF:
 793                 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x20, 0);
 794                 break;
 795
 796         case INVERSION_ON:
 797                 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x20, 0x20);
 798                 break;
 799
 800         default:
 801                 return -EINVAL;
 802         }
 803
 804         // set guard interval
 805         switch (fe_params->u.ofdm.guard_interval) {
 806         case GUARD_INTERVAL_1_32:
 807                 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
 808                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 0 << 2);
 809                 break;
 810
 811         case GUARD_INTERVAL_1_16:
 812                 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
 813                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 1 << 2);
 814                 break;
 815
 816         case GUARD_INTERVAL_1_8:
 817                 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
 818                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 2 << 2);
 819                 break;
 820
 821         case GUARD_INTERVAL_1_4:
 822                 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
 823                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 3 << 2);
 824                 break;
 825
 826         case GUARD_INTERVAL_AUTO:
 827                 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 2);
 828                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 0 << 2);
 829                 break;
 830
 831         default:
 832                 return -EINVAL;
 833         }
 834
 835         // set transmission mode
 836         switch (fe_params->u.ofdm.transmission_mode) {
 837         case TRANSMISSION_MODE_2K:
 838                 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 0);
 839                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 0 << 4);
 840                 break;
 841
 842         case TRANSMISSION_MODE_8K:
 843                 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 0);
 844                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 1 << 4);
 845                 break;
 846
 847         case TRANSMISSION_MODE_AUTO:
 848                 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 4);
 849                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 0);
 850                 break;
 851
 852         default:
 853                 return -EINVAL;
 854         }
 855
 856         // start the lock
 857         switch (state->demod_type) {
 858         case TDA1004X_DEMOD_TDA10045:
 859                 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8);
 860                 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 0);
 861                 break;
 862
 863         case TDA1004X_DEMOD_TDA10046:
 864                 tda1004x_write_mask(state, TDA1004X_AUTO, 0x40, 0x40);
 865                 msleep(1);
 866                 tda1004x_write_mask(state, TDA10046H_AGC_CONF, 4, 1);
 867                 break;
 868         }
 869
 870         msleep(10);
 871
 872         return 0;
 873 }
 874
 875 static int tda1004x_get_fe(struct dvb_frontend* fe, struct dvb_frontend_parameters *fe_params)
 876 {
 877         struct tda1004x_state* state = fe->demodulator_priv;
 878
 879         dprintk("%s\n", __FUNCTION__);
 880
 881         // inversion status
 882         fe_params->inversion = INVERSION_OFF;
 883         if (tda1004x_read_byte(state, TDA1004X_CONFC1) & 0x20)
 884                 fe_params->inversion = INVERSION_ON;
 885         if (state->config->invert)
 886                 fe_params->inversion = fe_params->inversion ? INVERSION_OFF : INVERSION_ON;
 887
 888         // bandwidth
 889         switch (state->demod_type) {
 890         case TDA1004X_DEMOD_TDA10045:
 891                 switch (tda1004x_read_byte(state, TDA10045H_WREF_LSB)) {
 892                 case 0x14:
 893                         fe_params->u.ofdm.bandwidth = BANDWIDTH_8_MHZ;
 894                         break;
 895                 case 0xdb:
 896                         fe_params->u.ofdm.bandwidth = BANDWIDTH_7_MHZ;
 897                         break;
 898                 case 0x4f:
 899                         fe_params->u.ofdm.bandwidth = BANDWIDTH_6_MHZ;
 900                         break;
 901                 }
 902                 break;
 903         case TDA1004X_DEMOD_TDA10046:
 904                 switch (tda1004x_read_byte(state, TDA10046H_TIME_WREF1)) {
 905                 case 0x5c:
 906                 case 0x54:
 907                         fe_params->u.ofdm.bandwidth = BANDWIDTH_8_MHZ;
 908                         break;
 909                 case 0x6a:
 910                 case 0x60:
 911                         fe_params->u.ofdm.bandwidth = BANDWIDTH_7_MHZ;
 912                         break;
 913                 case 0x7b:
 914                 case 0x70:
 915                         fe_params->u.ofdm.bandwidth = BANDWIDTH_6_MHZ;
 916                         break;
 917                 }
 918                 break;
 919         }
 920
 921         // FEC
 922         fe_params->u.ofdm.code_rate_HP =
 923             tda1004x_decode_fec(tda1004x_read_byte(state, TDA1004X_OUT_CONF2) & 7);
 924         fe_params->u.ofdm.code_rate_LP =
 925             tda1004x_decode_fec((tda1004x_read_byte(state, TDA1004X_OUT_CONF2) >> 3) & 7);
 926
 927         // constellation
 928         switch (tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 3) {
 929         case 0:
 930                 fe_params->u.ofdm.constellation = QPSK;
 931                 break;
 932         case 1:
 933                 fe_params->u.ofdm.constellation = QAM_16;
 934                 break;
 935         case 2:
 936                 fe_params->u.ofdm.constellation = QAM_64;
 937                 break;
 938         }
 939
 940         // transmission mode
 941         fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_2K;
 942         if (tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x10)
 943                 fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_8K;
 944
 945         // guard interval
 946         switch ((tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x0c) >> 2) {
 947         case 0:
 948                 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_32;
 949                 break;
 950         case 1:
 951                 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_16;
 952                 break;
 953         case 2:
 954                 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_8;
 955                 break;
 956         case 3:
 957                 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_4;
 958                 break;
 959         }
 960
 961         // hierarchy
 962         switch ((tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x60) >> 5) {
 963         case 0:
 964                 fe_params->u.ofdm.hierarchy_information = HIERARCHY_NONE;
 965                 break;
 966         case 1:
 967                 fe_params->u.ofdm.hierarchy_information = HIERARCHY_1;
 968                 break;
 969         case 2:
 970                 fe_params->u.ofdm.hierarchy_information = HIERARCHY_2;
 971                 break;
 972         case 3:
 973                 fe_params->u.ofdm.hierarchy_information = HIERARCHY_4;
 974                 break;
 975         }
 976
 977         return 0;
 978 }
 979
 980 static int tda1004x_read_status(struct dvb_frontend* fe, fe_status_t * fe_status)
 981 {
 982         struct tda1004x_state* state = fe->demodulator_priv;
 983         int status;
 984         int cber;
 985         int vber;
 986
 987         dprintk("%s\n", __FUNCTION__);
 988
 989         // read status
 990         status = tda1004x_read_byte(state, TDA1004X_STATUS_CD);
 991         if (status == -1)
 992                 return -EIO;
 993
 994         // decode
 995         *fe_status = 0;
 996         if (status & 4)
 997                 *fe_status |= FE_HAS_SIGNAL;
 998         if (status & 2)
 999                 *fe_status |= FE_HAS_CARRIER;
1000         if (status & 8)
1001                 *fe_status |= FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
1002
1003         // if we don't already have VITERBI (i.e. not LOCKED), see if the viterbi
1004         // is getting anything valid
1005         if (!(*fe_status & FE_HAS_VITERBI)) {
1006                 // read the CBER
1007                 cber = tda1004x_read_byte(state, TDA1004X_CBER_LSB);
1008                 if (cber == -1)
1009                         return -EIO;
1010                 status = tda1004x_read_byte(state, TDA1004X_CBER_MSB);
1011                 if (status == -1)
1012                         return -EIO;
1013                 cber |= (status << 8);
1014                 // The address 0x20 should be read to cope with a TDA10046 bug
1015                 tda1004x_read_byte(state, TDA1004X_CBER_RESET);
1016
1017                 if (cber != 65535)
1018                         *fe_status |= FE_HAS_VITERBI;
1019         }
1020
1021         // if we DO have some valid VITERBI output, but don't already have SYNC
1022         // bytes (i.e. not LOCKED), see if the RS decoder is getting anything valid.
1023         if ((*fe_status & FE_HAS_VITERBI) && (!(*fe_status & FE_HAS_SYNC))) {
1024                 // read the VBER
1025                 vber = tda1004x_read_byte(state, TDA1004X_VBER_LSB);
1026                 if (vber == -1)
1027                         return -EIO;
1028                 status = tda1004x_read_byte(state, TDA1004X_VBER_MID);
1029                 if (status == -1)
1030                         return -EIO;
1031                 vber |= (status << 8);
1032                 status = tda1004x_read_byte(state, TDA1004X_VBER_MSB);
1033                 if (status == -1)
1034                         return -EIO;
1035                 vber |= (status & 0x0f) << 16;
1036                 // The CVBER_LUT should be read to cope with TDA10046 hardware bug
1037                 tda1004x_read_byte(state, TDA1004X_CVBER_LUT);
1038
1039                 // if RS has passed some valid TS packets, then we must be
1040                 // getting some SYNC bytes
1041                 if (vber < 16632)
1042                         *fe_status |= FE_HAS_SYNC;
1043         }
1044
1045         // success
1046         dprintk("%s: fe_status=0x%x\n", __FUNCTION__, *fe_status);
1047         return 0;
1048 }
1049
1050 static int tda1004x_read_signal_strength(struct dvb_frontend* fe, u16 * signal)
1051 {
1052         struct tda1004x_state* state = fe->demodulator_priv;
1053         int tmp;
1054         int reg = 0;
1055
1056         dprintk("%s\n", __FUNCTION__);
1057
1058         // determine the register to use
1059         switch (state->demod_type) {
1060         case TDA1004X_DEMOD_TDA10045:
1061                 reg = TDA10045H_S_AGC;
1062                 break;
1063
1064         case TDA1004X_DEMOD_TDA10046:
1065                 reg = TDA10046H_AGC_IF_LEVEL;
1066                 break;
1067         }
1068
1069         // read it
1070         tmp = tda1004x_read_byte(state, reg);
1071         if (tmp < 0)
1072                 return -EIO;
1073
1074         *signal = (tmp << 8) | tmp;
1075         dprintk("%s: signal=0x%x\n", __FUNCTION__, *signal);
1076         return 0;
1077 }
1078
1079 static int tda1004x_read_snr(struct dvb_frontend* fe, u16 * snr)
1080 {
1081         struct tda1004x_state* state = fe->demodulator_priv;
1082         int tmp;
1083
1084         dprintk("%s\n", __FUNCTION__);
1085
1086         // read it
1087         tmp = tda1004x_read_byte(state, TDA1004X_SNR);
1088         if (tmp < 0)
1089                 return -EIO;
1090         tmp = 255 - tmp;
1091
1092         *snr = ((tmp << 8) | tmp);
1093         dprintk("%s: snr=0x%x\n", __FUNCTION__, *snr);
1094         return 0;
1095 }
1096
1097 static int tda1004x_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
1098 {
1099         struct tda1004x_state* state = fe->demodulator_priv;
1100         int tmp;
1101         int tmp2;
1102         int counter;
1103
1104         dprintk("%s\n", __FUNCTION__);
1105
1106         // read the UCBLOCKS and reset
1107         counter = 0;
1108         tmp = tda1004x_read_byte(state, TDA1004X_UNCOR);
1109         if (tmp < 0)
1110                 return -EIO;
1111         tmp &= 0x7f;
1112         while (counter++ < 5) {
1113                 tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0);
1114                 tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0);
1115                 tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0);
1116
1117                 tmp2 = tda1004x_read_byte(state, TDA1004X_UNCOR);
1118                 if (tmp2 < 0)
1119                         return -EIO;
1120                 tmp2 &= 0x7f;
1121                 if ((tmp2 < tmp) || (tmp2 == 0))
1122                         break;
1123         }
1124
1125         if (tmp != 0x7f)
1126                 *ucblocks = tmp;
1127         else
1128                 *ucblocks = 0xffffffff;
1129
1130         dprintk("%s: ucblocks=0x%x\n", __FUNCTION__, *ucblocks);
1131         return 0;
1132 }
1133
1134 static int tda1004x_read_ber(struct dvb_frontend* fe, u32* ber)
1135 {
1136         struct tda1004x_state* state = fe->demodulator_priv;
1137         int tmp;
1138
1139         dprintk("%s\n", __FUNCTION__);
1140
1141         // read it in
1142         tmp = tda1004x_read_byte(state, TDA1004X_CBER_LSB);
1143         if (tmp < 0)
1144                 return -EIO;
1145         *ber = tmp << 1;
1146         tmp = tda1004x_read_byte(state, TDA1004X_CBER_MSB);
1147         if (tmp < 0)
1148                 return -EIO;
1149         *ber |= (tmp << 9);
1150         // The address 0x20 should be read to cope with a TDA10046 bug
1151         tda1004x_read_byte(state, TDA1004X_CBER_RESET);
1152
1153         dprintk("%s: ber=0x%x\n", __FUNCTION__, *ber);
1154         return 0;
1155 }
1156
1157 static int tda1004x_sleep(struct dvb_frontend* fe)
1158 {
1159         struct tda1004x_state* state = fe->demodulator_priv;
1160
1161         switch (state->demod_type) {
1162         case TDA1004X_DEMOD_TDA10045:
1163                 tda1004x_write_mask(state, TDA1004X_CONFADC1, 0x10, 0x10);
1164                 break;
1165
1166         case TDA1004X_DEMOD_TDA10046:
1167                 /* set outputs to tristate */
1168                 tda1004x_write_byteI(state, TDA10046H_CONF_TRISTATE1, 0xff);
1169                 tda1004x_write_mask(state, TDA1004X_CONFC4, 1, 1);
1170                 break;
1171         }
1172
1173         return 0;
1174 }
1175
1176 static int tda1004x_i2c_gate_ctrl(struct dvb_frontend* fe, int enable)
1177 {
1178         struct tda1004x_state* state = fe->demodulator_priv;
1179
1180         if (enable) {
1181                 return tda1004x_enable_tuner_i2c(state);
1182         } else {
1183                 return tda1004x_disable_tuner_i2c(state);
1184         }
1185 }
1186
1187 static int tda1004x_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fesettings)
1188 {
1189         fesettings->min_delay_ms = 800;
1190         /* Drift compensation makes no sense for DVB-T */
1191         fesettings->step_size = 0;
1192         fesettings->max_drift = 0;
1193         return 0;
1194 }
1195
1196 static void tda1004x_release(struct dvb_frontend* fe)
1197 {
1198         struct tda1004x_state *state = fe->demodulator_priv;
1199         kfree(state);
1200 }
1201
1202 static struct dvb_frontend_ops tda10045_ops = {
1203         .info = {
1204                 .name = "Philips TDA10045H DVB-T",
1205                 .type = FE_OFDM,
1206                 .frequency_min = 51000000,
1207                 .frequency_max = 858000000,
1208                 .frequency_stepsize = 166667,
1209                 .caps =
1210                     FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
1211                     FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
1212                     FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
1213                     FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO
1214         },
1215
1216         .release = tda1004x_release,
1217
1218         .init = tda10045_init,
1219         .sleep = tda1004x_sleep,
1220         .i2c_gate_ctrl = tda1004x_i2c_gate_ctrl,
1221
1222         .set_frontend = tda1004x_set_fe,
1223         .get_frontend = tda1004x_get_fe,
1224         .get_tune_settings = tda1004x_get_tune_settings,
1225
1226         .read_status = tda1004x_read_status,
1227         .read_ber = tda1004x_read_ber,
1228         .read_signal_strength = tda1004x_read_signal_strength,
1229         .read_snr = tda1004x_read_snr,
1230         .read_ucblocks = tda1004x_read_ucblocks,
1231 };
1232
1233 struct dvb_frontend* tda10045_attach(const struct tda1004x_config* config,
1234                                      struct i2c_adapter* i2c)
1235 {
1236         struct tda1004x_state *state;
1237
1238         /* allocate memory for the internal state */
1239         state = kmalloc(sizeof(struct tda1004x_state), GFP_KERNEL);
1240         if (!state)
1241                 return NULL;
1242
1243         /* setup the state */
1244         state->config = config;
1245         state->i2c = i2c;
1246         memcpy(&state->ops, &tda10045_ops, sizeof(struct dvb_frontend_ops));
1247         state->demod_type = TDA1004X_DEMOD_TDA10045;
1248
1249         /* check if the demod is there */
1250         if (tda1004x_read_byte(state, TDA1004X_CHIPID) != 0x25) {
1251                 kfree(state);
1252                 return NULL;
1253         }
1254
1255         /* create dvb_frontend */
1256         state->frontend.ops = &state->ops;
1257         state->frontend.demodulator_priv = state;
1258         return &state->frontend;
1259 }
1260
1261 static struct dvb_frontend_ops tda10046_ops = {
1262         .info = {
1263                 .name = "Philips TDA10046H DVB-T",
1264                 .type = FE_OFDM,
1265                 .frequency_min = 51000000,
1266                 .frequency_max = 858000000,
1267                 .frequency_stepsize = 166667,
1268                 .caps =
1269                     FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
1270                     FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
1271                     FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
1272                     FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO
1273         },
1274
1275         .release = tda1004x_release,
1276
1277         .init = tda10046_init,
1278         .sleep = tda1004x_sleep,
1279         .i2c_gate_ctrl = tda1004x_i2c_gate_ctrl,
1280
1281         .set_frontend = tda1004x_set_fe,
1282         .get_frontend = tda1004x_get_fe,
1283         .get_tune_settings = tda1004x_get_tune_settings,
1284
1285         .read_status = tda1004x_read_status,
1286         .read_ber = tda1004x_read_ber,
1287         .read_signal_strength = tda1004x_read_signal_strength,
1288         .read_snr = tda1004x_read_snr,
1289         .read_ucblocks = tda1004x_read_ucblocks,
1290 };
1291
1292 struct dvb_frontend* tda10046_attach(const struct tda1004x_config* config,
1293                                      struct i2c_adapter* i2c)
1294 {
1295         struct tda1004x_state *state;
1296
1297         /* allocate memory for the internal state */
1298         state = kmalloc(sizeof(struct tda1004x_state), GFP_KERNEL);
1299         if (!state)
1300                 return NULL;
1301
1302         /* setup the state */
1303         state->config = config;
1304         state->i2c = i2c;
1305         memcpy(&state->ops, &tda10046_ops, sizeof(struct dvb_frontend_ops));
1306         state->demod_type = TDA1004X_DEMOD_TDA10046;
1307
1308         /* check if the demod is there */
1309         if (tda1004x_read_byte(state, TDA1004X_CHIPID) != 0x46) {
1310                 kfree(state);
1311                 return NULL;
1312         }
1313
1314         /* create dvb_frontend */
1315         state->frontend.ops = &state->ops;
1316         state->frontend.demodulator_priv = state;
1317         return &state->frontend;
1318 }
1319
1320 module_param(debug, int, 0644);
1321 MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
1322
1323 MODULE_DESCRIPTION("Philips TDA10045H & TDA10046H DVB-T Demodulator");
1324 MODULE_AUTHOR("Andrew de Quincey & Robert Schlabbach");
1325 MODULE_LICENSE("GPL");
1326
1327 EXPORT_SYMBOL(tda10045_attach);
1328 EXPORT_SYMBOL(tda10046_attach);
1329 EXPORT_SYMBOL(tda1004x_write_byte);