Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-2.6
[linux-2.6] / arch / powerpc / platforms / cell / pmu.c
1 /*
2  * Cell Broadband Engine Performance Monitor
3  *
4  * (C) Copyright IBM Corporation 2001,2006
5  *
6  * Author:
7  *    David Erb (djerb@us.ibm.com)
8  *    Kevin Corry (kevcorry@us.ibm.com)
9  *
10  * This program is free software; you can redistribute it and/or modify
11  * it under the terms of the GNU General Public License as published by
12  * the Free Software Foundation; either version 2, or (at your option)
13  * any later version.
14  *
15  * This program is distributed in the hope that it will be useful,
16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18  * GNU General Public License for more details.
19  *
20  * You should have received a copy of the GNU General Public License
21  * along with this program; if not, write to the Free Software
22  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23  */
24
25 #include <linux/interrupt.h>
26 #include <linux/types.h>
27 #include <asm/io.h>
28 #include <asm/irq_regs.h>
29 #include <asm/machdep.h>
30 #include <asm/pmc.h>
31 #include <asm/reg.h>
32 #include <asm/spu.h>
33 #include <asm/cell-regs.h>
34
35 #include "interrupt.h"
36
37 /*
38  * When writing to write-only mmio addresses, save a shadow copy. All of the
39  * registers are 32-bit, but stored in the upper-half of a 64-bit field in
40  * pmd_regs.
41  */
42
43 #define WRITE_WO_MMIO(reg, x)                                   \
44         do {                                                    \
45                 u32 _x = (x);                                   \
46                 struct cbe_pmd_regs __iomem *pmd_regs;          \
47                 struct cbe_pmd_shadow_regs *shadow_regs;        \
48                 pmd_regs = cbe_get_cpu_pmd_regs(cpu);           \
49                 shadow_regs = cbe_get_cpu_pmd_shadow_regs(cpu); \
50                 out_be64(&(pmd_regs->reg), (((u64)_x) << 32));  \
51                 shadow_regs->reg = _x;                          \
52         } while (0)
53
54 #define READ_SHADOW_REG(val, reg)                               \
55         do {                                                    \
56                 struct cbe_pmd_shadow_regs *shadow_regs;        \
57                 shadow_regs = cbe_get_cpu_pmd_shadow_regs(cpu); \
58                 (val) = shadow_regs->reg;                       \
59         } while (0)
60
61 #define READ_MMIO_UPPER32(val, reg)                             \
62         do {                                                    \
63                 struct cbe_pmd_regs __iomem *pmd_regs;          \
64                 pmd_regs = cbe_get_cpu_pmd_regs(cpu);           \
65                 (val) = (u32)(in_be64(&pmd_regs->reg) >> 32);   \
66         } while (0)
67
68 /*
69  * Physical counter registers.
70  * Each physical counter can act as one 32-bit counter or two 16-bit counters.
71  */
72
73 u32 cbe_read_phys_ctr(u32 cpu, u32 phys_ctr)
74 {
75         u32 val_in_latch, val = 0;
76
77         if (phys_ctr < NR_PHYS_CTRS) {
78                 READ_SHADOW_REG(val_in_latch, counter_value_in_latch);
79
80                 /* Read the latch or the actual counter, whichever is newer. */
81                 if (val_in_latch & (1 << phys_ctr)) {
82                         READ_SHADOW_REG(val, pm_ctr[phys_ctr]);
83                 } else {
84                         READ_MMIO_UPPER32(val, pm_ctr[phys_ctr]);
85                 }
86         }
87
88         return val;
89 }
90 EXPORT_SYMBOL_GPL(cbe_read_phys_ctr);
91
92 void cbe_write_phys_ctr(u32 cpu, u32 phys_ctr, u32 val)
93 {
94         struct cbe_pmd_shadow_regs *shadow_regs;
95         u32 pm_ctrl;
96
97         if (phys_ctr < NR_PHYS_CTRS) {
98                 /* Writing to a counter only writes to a hardware latch.
99                  * The new value is not propagated to the actual counter
100                  * until the performance monitor is enabled.
101                  */
102                 WRITE_WO_MMIO(pm_ctr[phys_ctr], val);
103
104                 pm_ctrl = cbe_read_pm(cpu, pm_control);
105                 if (pm_ctrl & CBE_PM_ENABLE_PERF_MON) {
106                         /* The counters are already active, so we need to
107                          * rewrite the pm_control register to "re-enable"
108                          * the PMU.
109                          */
110                         cbe_write_pm(cpu, pm_control, pm_ctrl);
111                 } else {
112                         shadow_regs = cbe_get_cpu_pmd_shadow_regs(cpu);
113                         shadow_regs->counter_value_in_latch |= (1 << phys_ctr);
114                 }
115         }
116 }
117 EXPORT_SYMBOL_GPL(cbe_write_phys_ctr);
118
119 /*
120  * "Logical" counter registers.
121  * These will read/write 16-bits or 32-bits depending on the
122  * current size of the counter. Counters 4 - 7 are always 16-bit.
123  */
124
125 u32 cbe_read_ctr(u32 cpu, u32 ctr)
126 {
127         u32 val;
128         u32 phys_ctr = ctr & (NR_PHYS_CTRS - 1);
129
130         val = cbe_read_phys_ctr(cpu, phys_ctr);
131
132         if (cbe_get_ctr_size(cpu, phys_ctr) == 16)
133                 val = (ctr < NR_PHYS_CTRS) ? (val >> 16) : (val & 0xffff);
134
135         return val;
136 }
137 EXPORT_SYMBOL_GPL(cbe_read_ctr);
138
139 void cbe_write_ctr(u32 cpu, u32 ctr, u32 val)
140 {
141         u32 phys_ctr;
142         u32 phys_val;
143
144         phys_ctr = ctr & (NR_PHYS_CTRS - 1);
145
146         if (cbe_get_ctr_size(cpu, phys_ctr) == 16) {
147                 phys_val = cbe_read_phys_ctr(cpu, phys_ctr);
148
149                 if (ctr < NR_PHYS_CTRS)
150                         val = (val << 16) | (phys_val & 0xffff);
151                 else
152                         val = (val & 0xffff) | (phys_val & 0xffff0000);
153         }
154
155         cbe_write_phys_ctr(cpu, phys_ctr, val);
156 }
157 EXPORT_SYMBOL_GPL(cbe_write_ctr);
158
159 /*
160  * Counter-control registers.
161  * Each "logical" counter has a corresponding control register.
162  */
163
164 u32 cbe_read_pm07_control(u32 cpu, u32 ctr)
165 {
166         u32 pm07_control = 0;
167
168         if (ctr < NR_CTRS)
169                 READ_SHADOW_REG(pm07_control, pm07_control[ctr]);
170
171         return pm07_control;
172 }
173 EXPORT_SYMBOL_GPL(cbe_read_pm07_control);
174
175 void cbe_write_pm07_control(u32 cpu, u32 ctr, u32 val)
176 {
177         if (ctr < NR_CTRS)
178                 WRITE_WO_MMIO(pm07_control[ctr], val);
179 }
180 EXPORT_SYMBOL_GPL(cbe_write_pm07_control);
181
182 /*
183  * Other PMU control registers. Most of these are write-only.
184  */
185
186 u32 cbe_read_pm(u32 cpu, enum pm_reg_name reg)
187 {
188         u32 val = 0;
189
190         switch (reg) {
191         case group_control:
192                 READ_SHADOW_REG(val, group_control);
193                 break;
194
195         case debug_bus_control:
196                 READ_SHADOW_REG(val, debug_bus_control);
197                 break;
198
199         case trace_address:
200                 READ_MMIO_UPPER32(val, trace_address);
201                 break;
202
203         case ext_tr_timer:
204                 READ_SHADOW_REG(val, ext_tr_timer);
205                 break;
206
207         case pm_status:
208                 READ_MMIO_UPPER32(val, pm_status);
209                 break;
210
211         case pm_control:
212                 READ_SHADOW_REG(val, pm_control);
213                 break;
214
215         case pm_interval:
216                 READ_MMIO_UPPER32(val, pm_interval);
217                 break;
218
219         case pm_start_stop:
220                 READ_SHADOW_REG(val, pm_start_stop);
221                 break;
222         }
223
224         return val;
225 }
226 EXPORT_SYMBOL_GPL(cbe_read_pm);
227
228 void cbe_write_pm(u32 cpu, enum pm_reg_name reg, u32 val)
229 {
230         switch (reg) {
231         case group_control:
232                 WRITE_WO_MMIO(group_control, val);
233                 break;
234
235         case debug_bus_control:
236                 WRITE_WO_MMIO(debug_bus_control, val);
237                 break;
238
239         case trace_address:
240                 WRITE_WO_MMIO(trace_address, val);
241                 break;
242
243         case ext_tr_timer:
244                 WRITE_WO_MMIO(ext_tr_timer, val);
245                 break;
246
247         case pm_status:
248                 WRITE_WO_MMIO(pm_status, val);
249                 break;
250
251         case pm_control:
252                 WRITE_WO_MMIO(pm_control, val);
253                 break;
254
255         case pm_interval:
256                 WRITE_WO_MMIO(pm_interval, val);
257                 break;
258
259         case pm_start_stop:
260                 WRITE_WO_MMIO(pm_start_stop, val);
261                 break;
262         }
263 }
264 EXPORT_SYMBOL_GPL(cbe_write_pm);
265
266 /*
267  * Get/set the size of a physical counter to either 16 or 32 bits.
268  */
269
270 u32 cbe_get_ctr_size(u32 cpu, u32 phys_ctr)
271 {
272         u32 pm_ctrl, size = 0;
273
274         if (phys_ctr < NR_PHYS_CTRS) {
275                 pm_ctrl = cbe_read_pm(cpu, pm_control);
276                 size = (pm_ctrl & CBE_PM_16BIT_CTR(phys_ctr)) ? 16 : 32;
277         }
278
279         return size;
280 }
281 EXPORT_SYMBOL_GPL(cbe_get_ctr_size);
282
283 void cbe_set_ctr_size(u32 cpu, u32 phys_ctr, u32 ctr_size)
284 {
285         u32 pm_ctrl;
286
287         if (phys_ctr < NR_PHYS_CTRS) {
288                 pm_ctrl = cbe_read_pm(cpu, pm_control);
289                 switch (ctr_size) {
290                 case 16:
291                         pm_ctrl |= CBE_PM_16BIT_CTR(phys_ctr);
292                         break;
293
294                 case 32:
295                         pm_ctrl &= ~CBE_PM_16BIT_CTR(phys_ctr);
296                         break;
297                 }
298                 cbe_write_pm(cpu, pm_control, pm_ctrl);
299         }
300 }
301 EXPORT_SYMBOL_GPL(cbe_set_ctr_size);
302
303 /*
304  * Enable/disable the entire performance monitoring unit.
305  * When we enable the PMU, all pending writes to counters get committed.
306  */
307
308 void cbe_enable_pm(u32 cpu)
309 {
310         struct cbe_pmd_shadow_regs *shadow_regs;
311         u32 pm_ctrl;
312
313         shadow_regs = cbe_get_cpu_pmd_shadow_regs(cpu);
314         shadow_regs->counter_value_in_latch = 0;
315
316         pm_ctrl = cbe_read_pm(cpu, pm_control) | CBE_PM_ENABLE_PERF_MON;
317         cbe_write_pm(cpu, pm_control, pm_ctrl);
318 }
319 EXPORT_SYMBOL_GPL(cbe_enable_pm);
320
321 void cbe_disable_pm(u32 cpu)
322 {
323         u32 pm_ctrl;
324         pm_ctrl = cbe_read_pm(cpu, pm_control) & ~CBE_PM_ENABLE_PERF_MON;
325         cbe_write_pm(cpu, pm_control, pm_ctrl);
326 }
327 EXPORT_SYMBOL_GPL(cbe_disable_pm);
328
329 /*
330  * Reading from the trace_buffer.
331  * The trace buffer is two 64-bit registers. Reading from
332  * the second half automatically increments the trace_address.
333  */
334
335 void cbe_read_trace_buffer(u32 cpu, u64 *buf)
336 {
337         struct cbe_pmd_regs __iomem *pmd_regs = cbe_get_cpu_pmd_regs(cpu);
338
339         *buf++ = in_be64(&pmd_regs->trace_buffer_0_63);
340         *buf++ = in_be64(&pmd_regs->trace_buffer_64_127);
341 }
342 EXPORT_SYMBOL_GPL(cbe_read_trace_buffer);
343
344 /*
345  * Enabling/disabling interrupts for the entire performance monitoring unit.
346  */
347
348 u32 cbe_get_and_clear_pm_interrupts(u32 cpu)
349 {
350         /* Reading pm_status clears the interrupt bits. */
351         return cbe_read_pm(cpu, pm_status);
352 }
353 EXPORT_SYMBOL_GPL(cbe_get_and_clear_pm_interrupts);
354
355 void cbe_enable_pm_interrupts(u32 cpu, u32 thread, u32 mask)
356 {
357         /* Set which node and thread will handle the next interrupt. */
358         iic_set_interrupt_routing(cpu, thread, 0);
359
360         /* Enable the interrupt bits in the pm_status register. */
361         if (mask)
362                 cbe_write_pm(cpu, pm_status, mask);
363 }
364 EXPORT_SYMBOL_GPL(cbe_enable_pm_interrupts);
365
366 void cbe_disable_pm_interrupts(u32 cpu)
367 {
368         cbe_get_and_clear_pm_interrupts(cpu);
369         cbe_write_pm(cpu, pm_status, 0);
370 }
371 EXPORT_SYMBOL_GPL(cbe_disable_pm_interrupts);
372
373 static irqreturn_t cbe_pm_irq(int irq, void *dev_id)
374 {
375         perf_irq(get_irq_regs());
376         return IRQ_HANDLED;
377 }
378
379 static int __init cbe_init_pm_irq(void)
380 {
381         unsigned int irq;
382         int rc, node;
383
384         for_each_node(node) {
385                 irq = irq_create_mapping(NULL, IIC_IRQ_IOEX_PMI |
386                                                (node << IIC_IRQ_NODE_SHIFT));
387                 if (irq == NO_IRQ) {
388                         printk("ERROR: Unable to allocate irq for node %d\n",
389                                node);
390                         return -EINVAL;
391                 }
392
393                 rc = request_irq(irq, cbe_pm_irq,
394                                  IRQF_DISABLED, "cbe-pmu-0", NULL);
395                 if (rc) {
396                         printk("ERROR: Request for irq on node %d failed\n",
397                                node);
398                         return rc;
399                 }
400         }
401
402         return 0;
403 }
404 machine_arch_initcall(cell, cbe_init_pm_irq);
405
406 void cbe_sync_irq(int node)
407 {
408         unsigned int irq;
409
410         irq = irq_find_mapping(NULL,
411                                IIC_IRQ_IOEX_PMI
412                                | (node << IIC_IRQ_NODE_SHIFT));
413
414         if (irq == NO_IRQ) {
415                 printk(KERN_WARNING "ERROR, unable to get existing irq %d " \
416                 "for node %d\n", irq, node);
417                 return;
418         }
419
420         synchronize_irq(irq);
421 }
422 EXPORT_SYMBOL_GPL(cbe_sync_irq);
423