[PATCH] x86-64: Handle 32 bit PerfMon Counter writes cleanly in x86_64 nmi_watchdog
[linux-2.6] / arch / x86_64 / kernel / nmi.c
1 /*
2  *  linux/arch/x86_64/nmi.c
3  *
4  *  NMI watchdog support on APIC systems
5  *
6  *  Started by Ingo Molnar <mingo@redhat.com>
7  *
8  *  Fixes:
9  *  Mikael Pettersson   : AMD K7 support for local APIC NMI watchdog.
10  *  Mikael Pettersson   : Power Management for local APIC NMI watchdog.
11  *  Pavel Machek and
12  *  Mikael Pettersson   : PM converted to driver model. Disable/enable API.
13  */
14
15 #include <linux/nmi.h>
16 #include <linux/mm.h>
17 #include <linux/delay.h>
18 #include <linux/interrupt.h>
19 #include <linux/module.h>
20 #include <linux/sysdev.h>
21 #include <linux/sysctl.h>
22 #include <linux/kprobes.h>
23 #include <linux/cpumask.h>
24
25 #include <asm/smp.h>
26 #include <asm/nmi.h>
27 #include <asm/proto.h>
28 #include <asm/kdebug.h>
29 #include <asm/mce.h>
30 #include <asm/intel_arch_perfmon.h>
31
32 int unknown_nmi_panic;
33 int nmi_watchdog_enabled;
34 int panic_on_unrecovered_nmi;
35
36 /* perfctr_nmi_owner tracks the ownership of the perfctr registers:
37  * evtsel_nmi_owner tracks the ownership of the event selection
38  * - different performance counters/ event selection may be reserved for
39  *   different subsystems this reservation system just tries to coordinate
40  *   things a little
41  */
42 static DEFINE_PER_CPU(unsigned, perfctr_nmi_owner);
43 static DEFINE_PER_CPU(unsigned, evntsel_nmi_owner[2]);
44
45 static cpumask_t backtrace_mask = CPU_MASK_NONE;
46
47 /* this number is calculated from Intel's MSR_P4_CRU_ESCR5 register and it's
48  * offset from MSR_P4_BSU_ESCR0.  It will be the max for all platforms (for now)
49  */
50 #define NMI_MAX_COUNTER_BITS 66
51
52 /* nmi_active:
53  * >0: the lapic NMI watchdog is active, but can be disabled
54  * <0: the lapic NMI watchdog has not been set up, and cannot
55  *     be enabled
56  *  0: the lapic NMI watchdog is disabled, but can be enabled
57  */
58 atomic_t nmi_active = ATOMIC_INIT(0);           /* oprofile uses this */
59 int panic_on_timeout;
60
61 unsigned int nmi_watchdog = NMI_DEFAULT;
62 static unsigned int nmi_hz = HZ;
63
64 struct nmi_watchdog_ctlblk {
65         int enabled;
66         u64 check_bit;
67         unsigned int cccr_msr;
68         unsigned int perfctr_msr;  /* the MSR to reset in NMI handler */
69         unsigned int evntsel_msr;  /* the MSR to select the events to handle */
70 };
71 static DEFINE_PER_CPU(struct nmi_watchdog_ctlblk, nmi_watchdog_ctlblk);
72
73 /* local prototypes */
74 static int unknown_nmi_panic_callback(struct pt_regs *regs, int cpu);
75
76 /* converts an msr to an appropriate reservation bit */
77 static inline unsigned int nmi_perfctr_msr_to_bit(unsigned int msr)
78 {
79         /* returns the bit offset of the performance counter register */
80         switch (boot_cpu_data.x86_vendor) {
81         case X86_VENDOR_AMD:
82                 return (msr - MSR_K7_PERFCTR0);
83         case X86_VENDOR_INTEL:
84                 if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON))
85                         return (msr - MSR_ARCH_PERFMON_PERFCTR0);
86                 else
87                         return (msr - MSR_P4_BPU_PERFCTR0);
88         }
89         return 0;
90 }
91
92 /* converts an msr to an appropriate reservation bit */
93 static inline unsigned int nmi_evntsel_msr_to_bit(unsigned int msr)
94 {
95         /* returns the bit offset of the event selection register */
96         switch (boot_cpu_data.x86_vendor) {
97         case X86_VENDOR_AMD:
98                 return (msr - MSR_K7_EVNTSEL0);
99         case X86_VENDOR_INTEL:
100                 if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON))
101                         return (msr - MSR_ARCH_PERFMON_EVENTSEL0);
102                 else
103                         return (msr - MSR_P4_BSU_ESCR0);
104         }
105         return 0;
106 }
107
108 /* checks for a bit availability (hack for oprofile) */
109 int avail_to_resrv_perfctr_nmi_bit(unsigned int counter)
110 {
111         BUG_ON(counter > NMI_MAX_COUNTER_BITS);
112
113         return (!test_bit(counter, &__get_cpu_var(perfctr_nmi_owner)));
114 }
115
116 /* checks the an msr for availability */
117 int avail_to_resrv_perfctr_nmi(unsigned int msr)
118 {
119         unsigned int counter;
120
121         counter = nmi_perfctr_msr_to_bit(msr);
122         BUG_ON(counter > NMI_MAX_COUNTER_BITS);
123
124         return (!test_bit(counter, &__get_cpu_var(perfctr_nmi_owner)));
125 }
126
127 int reserve_perfctr_nmi(unsigned int msr)
128 {
129         unsigned int counter;
130
131         counter = nmi_perfctr_msr_to_bit(msr);
132         BUG_ON(counter > NMI_MAX_COUNTER_BITS);
133
134         if (!test_and_set_bit(counter, &__get_cpu_var(perfctr_nmi_owner)))
135                 return 1;
136         return 0;
137 }
138
139 void release_perfctr_nmi(unsigned int msr)
140 {
141         unsigned int counter;
142
143         counter = nmi_perfctr_msr_to_bit(msr);
144         BUG_ON(counter > NMI_MAX_COUNTER_BITS);
145
146         clear_bit(counter, &__get_cpu_var(perfctr_nmi_owner));
147 }
148
149 int reserve_evntsel_nmi(unsigned int msr)
150 {
151         unsigned int counter;
152
153         counter = nmi_evntsel_msr_to_bit(msr);
154         BUG_ON(counter > NMI_MAX_COUNTER_BITS);
155
156         if (!test_and_set_bit(counter, &__get_cpu_var(evntsel_nmi_owner)))
157                 return 1;
158         return 0;
159 }
160
161 void release_evntsel_nmi(unsigned int msr)
162 {
163         unsigned int counter;
164
165         counter = nmi_evntsel_msr_to_bit(msr);
166         BUG_ON(counter > NMI_MAX_COUNTER_BITS);
167
168         clear_bit(counter, &__get_cpu_var(evntsel_nmi_owner));
169 }
170
171 static __cpuinit inline int nmi_known_cpu(void)
172 {
173         switch (boot_cpu_data.x86_vendor) {
174         case X86_VENDOR_AMD:
175                 return boot_cpu_data.x86 == 15;
176         case X86_VENDOR_INTEL:
177                 if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON))
178                         return 1;
179                 else
180                         return (boot_cpu_data.x86 == 15);
181         }
182         return 0;
183 }
184
185 /* Run after command line and cpu_init init, but before all other checks */
186 void nmi_watchdog_default(void)
187 {
188         if (nmi_watchdog != NMI_DEFAULT)
189                 return;
190         if (nmi_known_cpu())
191                 nmi_watchdog = NMI_LOCAL_APIC;
192         else
193                 nmi_watchdog = NMI_IO_APIC;
194 }
195
196 static int endflag __initdata = 0;
197
198 #ifdef CONFIG_SMP
199 /* The performance counters used by NMI_LOCAL_APIC don't trigger when
200  * the CPU is idle. To make sure the NMI watchdog really ticks on all
201  * CPUs during the test make them busy.
202  */
203 static __init void nmi_cpu_busy(void *data)
204 {
205         local_irq_enable_in_hardirq();
206         /* Intentionally don't use cpu_relax here. This is
207            to make sure that the performance counter really ticks,
208            even if there is a simulator or similar that catches the
209            pause instruction. On a real HT machine this is fine because
210            all other CPUs are busy with "useless" delay loops and don't
211            care if they get somewhat less cycles. */
212         while (endflag == 0)
213                 mb();
214 }
215 #endif
216
217 static unsigned int adjust_for_32bit_ctr(unsigned int hz)
218 {
219         unsigned int retval = hz;
220
221         /*
222          * On Intel CPUs with ARCH_PERFMON only 32 bits in the counter
223          * are writable, with higher bits sign extending from bit 31.
224          * So, we can only program the counter with 31 bit values and
225          * 32nd bit should be 1, for 33.. to be 1.
226          * Find the appropriate nmi_hz
227          */
228         if ((((u64)cpu_khz * 1000) / retval) > 0x7fffffffULL) {
229                 retval = ((u64)cpu_khz * 1000) / 0x7fffffffUL + 1;
230         }
231         return retval;
232 }
233
234 int __init check_nmi_watchdog (void)
235 {
236         int *counts;
237         int cpu;
238
239         if ((nmi_watchdog == NMI_NONE) || (nmi_watchdog == NMI_DEFAULT))
240                 return 0;
241
242         if (!atomic_read(&nmi_active))
243                 return 0;
244
245         counts = kmalloc(NR_CPUS * sizeof(int), GFP_KERNEL);
246         if (!counts)
247                 return -1;
248
249         printk(KERN_INFO "testing NMI watchdog ... ");
250
251 #ifdef CONFIG_SMP
252         if (nmi_watchdog == NMI_LOCAL_APIC)
253                 smp_call_function(nmi_cpu_busy, (void *)&endflag, 0, 0);
254 #endif
255
256         for (cpu = 0; cpu < NR_CPUS; cpu++)
257                 counts[cpu] = cpu_pda(cpu)->__nmi_count;
258         local_irq_enable();
259         mdelay((10*1000)/nmi_hz); // wait 10 ticks
260
261         for_each_online_cpu(cpu) {
262                 if (!per_cpu(nmi_watchdog_ctlblk, cpu).enabled)
263                         continue;
264                 if (cpu_pda(cpu)->__nmi_count - counts[cpu] <= 5) {
265                         printk("CPU#%d: NMI appears to be stuck (%d->%d)!\n",
266                                cpu,
267                                counts[cpu],
268                                cpu_pda(cpu)->__nmi_count);
269                         per_cpu(nmi_watchdog_ctlblk, cpu).enabled = 0;
270                         atomic_dec(&nmi_active);
271                 }
272         }
273         if (!atomic_read(&nmi_active)) {
274                 kfree(counts);
275                 atomic_set(&nmi_active, -1);
276                 endflag = 1;
277                 return -1;
278         }
279         endflag = 1;
280         printk("OK.\n");
281
282         /* now that we know it works we can reduce NMI frequency to
283            something more reasonable; makes a difference in some configs */
284         if (nmi_watchdog == NMI_LOCAL_APIC) {
285                 struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
286
287                 nmi_hz = 1;
288                 if (wd->perfctr_msr == MSR_ARCH_PERFMON_PERFCTR0)
289                         nmi_hz = adjust_for_32bit_ctr(nmi_hz);
290         }
291
292         kfree(counts);
293         return 0;
294 }
295
296 int __init setup_nmi_watchdog(char *str)
297 {
298         int nmi;
299
300         if (!strncmp(str,"panic",5)) {
301                 panic_on_timeout = 1;
302                 str = strchr(str, ',');
303                 if (!str)
304                         return 1;
305                 ++str;
306         }
307
308         get_option(&str, &nmi);
309
310         if ((nmi >= NMI_INVALID) || (nmi < NMI_NONE))
311                 return 0;
312
313         nmi_watchdog = nmi;
314         return 1;
315 }
316
317 __setup("nmi_watchdog=", setup_nmi_watchdog);
318
319 static void disable_lapic_nmi_watchdog(void)
320 {
321         BUG_ON(nmi_watchdog != NMI_LOCAL_APIC);
322
323         if (atomic_read(&nmi_active) <= 0)
324                 return;
325
326         on_each_cpu(stop_apic_nmi_watchdog, NULL, 0, 1);
327
328         BUG_ON(atomic_read(&nmi_active) != 0);
329 }
330
331 static void enable_lapic_nmi_watchdog(void)
332 {
333         BUG_ON(nmi_watchdog != NMI_LOCAL_APIC);
334
335         /* are we already enabled */
336         if (atomic_read(&nmi_active) != 0)
337                 return;
338
339         /* are we lapic aware */
340         if (nmi_known_cpu() <= 0)
341                 return;
342
343         on_each_cpu(setup_apic_nmi_watchdog, NULL, 0, 1);
344         touch_nmi_watchdog();
345 }
346
347 void disable_timer_nmi_watchdog(void)
348 {
349         BUG_ON(nmi_watchdog != NMI_IO_APIC);
350
351         if (atomic_read(&nmi_active) <= 0)
352                 return;
353
354         disable_irq(0);
355         on_each_cpu(stop_apic_nmi_watchdog, NULL, 0, 1);
356
357         BUG_ON(atomic_read(&nmi_active) != 0);
358 }
359
360 void enable_timer_nmi_watchdog(void)
361 {
362         BUG_ON(nmi_watchdog != NMI_IO_APIC);
363
364         if (atomic_read(&nmi_active) == 0) {
365                 touch_nmi_watchdog();
366                 on_each_cpu(setup_apic_nmi_watchdog, NULL, 0, 1);
367                 enable_irq(0);
368         }
369 }
370
371 #ifdef CONFIG_PM
372
373 static int nmi_pm_active; /* nmi_active before suspend */
374
375 static int lapic_nmi_suspend(struct sys_device *dev, pm_message_t state)
376 {
377         /* only CPU0 goes here, other CPUs should be offline */
378         nmi_pm_active = atomic_read(&nmi_active);
379         stop_apic_nmi_watchdog(NULL);
380         BUG_ON(atomic_read(&nmi_active) != 0);
381         return 0;
382 }
383
384 static int lapic_nmi_resume(struct sys_device *dev)
385 {
386         /* only CPU0 goes here, other CPUs should be offline */
387         if (nmi_pm_active > 0) {
388                 setup_apic_nmi_watchdog(NULL);
389                 touch_nmi_watchdog();
390         }
391         return 0;
392 }
393
394 static struct sysdev_class nmi_sysclass = {
395         set_kset_name("lapic_nmi"),
396         .resume         = lapic_nmi_resume,
397         .suspend        = lapic_nmi_suspend,
398 };
399
400 static struct sys_device device_lapic_nmi = {
401         .id             = 0,
402         .cls    = &nmi_sysclass,
403 };
404
405 static int __init init_lapic_nmi_sysfs(void)
406 {
407         int error;
408
409         /* should really be a BUG_ON but b/c this is an
410          * init call, it just doesn't work.  -dcz
411          */
412         if (nmi_watchdog != NMI_LOCAL_APIC)
413                 return 0;
414
415         if ( atomic_read(&nmi_active) < 0 )
416                 return 0;
417
418         error = sysdev_class_register(&nmi_sysclass);
419         if (!error)
420                 error = sysdev_register(&device_lapic_nmi);
421         return error;
422 }
423 /* must come after the local APIC's device_initcall() */
424 late_initcall(init_lapic_nmi_sysfs);
425
426 #endif  /* CONFIG_PM */
427
428 /*
429  * Activate the NMI watchdog via the local APIC.
430  * Original code written by Keith Owens.
431  */
432
433 /* Note that these events don't tick when the CPU idles. This means
434    the frequency varies with CPU load. */
435
436 #define K7_EVNTSEL_ENABLE       (1 << 22)
437 #define K7_EVNTSEL_INT          (1 << 20)
438 #define K7_EVNTSEL_OS           (1 << 17)
439 #define K7_EVNTSEL_USR          (1 << 16)
440 #define K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING    0x76
441 #define K7_NMI_EVENT            K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING
442
443 static int setup_k7_watchdog(void)
444 {
445         unsigned int perfctr_msr, evntsel_msr;
446         unsigned int evntsel;
447         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
448
449         perfctr_msr = MSR_K7_PERFCTR0;
450         evntsel_msr = MSR_K7_EVNTSEL0;
451         if (!reserve_perfctr_nmi(perfctr_msr))
452                 goto fail;
453
454         if (!reserve_evntsel_nmi(evntsel_msr))
455                 goto fail1;
456
457         /* Simulator may not support it */
458         if (checking_wrmsrl(evntsel_msr, 0UL))
459                 goto fail2;
460         wrmsrl(perfctr_msr, 0UL);
461
462         evntsel = K7_EVNTSEL_INT
463                 | K7_EVNTSEL_OS
464                 | K7_EVNTSEL_USR
465                 | K7_NMI_EVENT;
466
467         /* setup the timer */
468         wrmsr(evntsel_msr, evntsel, 0);
469         wrmsrl(perfctr_msr, -((u64)cpu_khz * 1000 / nmi_hz));
470         apic_write(APIC_LVTPC, APIC_DM_NMI);
471         evntsel |= K7_EVNTSEL_ENABLE;
472         wrmsr(evntsel_msr, evntsel, 0);
473
474         wd->perfctr_msr = perfctr_msr;
475         wd->evntsel_msr = evntsel_msr;
476         wd->cccr_msr = 0;  //unused
477         wd->check_bit = 1ULL<<63;
478         return 1;
479 fail2:
480         release_evntsel_nmi(evntsel_msr);
481 fail1:
482         release_perfctr_nmi(perfctr_msr);
483 fail:
484         return 0;
485 }
486
487 static void stop_k7_watchdog(void)
488 {
489         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
490
491         wrmsr(wd->evntsel_msr, 0, 0);
492
493         release_evntsel_nmi(wd->evntsel_msr);
494         release_perfctr_nmi(wd->perfctr_msr);
495 }
496
497 /* Note that these events don't tick when the CPU idles. This means
498    the frequency varies with CPU load. */
499
500 #define MSR_P4_MISC_ENABLE_PERF_AVAIL   (1<<7)
501 #define P4_ESCR_EVENT_SELECT(N) ((N)<<25)
502 #define P4_ESCR_OS              (1<<3)
503 #define P4_ESCR_USR             (1<<2)
504 #define P4_CCCR_OVF_PMI0        (1<<26)
505 #define P4_CCCR_OVF_PMI1        (1<<27)
506 #define P4_CCCR_THRESHOLD(N)    ((N)<<20)
507 #define P4_CCCR_COMPLEMENT      (1<<19)
508 #define P4_CCCR_COMPARE         (1<<18)
509 #define P4_CCCR_REQUIRED        (3<<16)
510 #define P4_CCCR_ESCR_SELECT(N)  ((N)<<13)
511 #define P4_CCCR_ENABLE          (1<<12)
512 #define P4_CCCR_OVF             (1<<31)
513 /* Set up IQ_COUNTER0 to behave like a clock, by having IQ_CCCR0 filter
514    CRU_ESCR0 (with any non-null event selector) through a complemented
515    max threshold. [IA32-Vol3, Section 14.9.9] */
516
517 static int setup_p4_watchdog(void)
518 {
519         unsigned int perfctr_msr, evntsel_msr, cccr_msr;
520         unsigned int evntsel, cccr_val;
521         unsigned int misc_enable, dummy;
522         unsigned int ht_num;
523         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
524
525         rdmsr(MSR_IA32_MISC_ENABLE, misc_enable, dummy);
526         if (!(misc_enable & MSR_P4_MISC_ENABLE_PERF_AVAIL))
527                 return 0;
528
529 #ifdef CONFIG_SMP
530         /* detect which hyperthread we are on */
531         if (smp_num_siblings == 2) {
532                 unsigned int ebx, apicid;
533
534                 ebx = cpuid_ebx(1);
535                 apicid = (ebx >> 24) & 0xff;
536                 ht_num = apicid & 1;
537         } else
538 #endif
539                 ht_num = 0;
540
541         /* performance counters are shared resources
542          * assign each hyperthread its own set
543          * (re-use the ESCR0 register, seems safe
544          * and keeps the cccr_val the same)
545          */
546         if (!ht_num) {
547                 /* logical cpu 0 */
548                 perfctr_msr = MSR_P4_IQ_PERFCTR0;
549                 evntsel_msr = MSR_P4_CRU_ESCR0;
550                 cccr_msr = MSR_P4_IQ_CCCR0;
551                 cccr_val = P4_CCCR_OVF_PMI0 | P4_CCCR_ESCR_SELECT(4);
552         } else {
553                 /* logical cpu 1 */
554                 perfctr_msr = MSR_P4_IQ_PERFCTR1;
555                 evntsel_msr = MSR_P4_CRU_ESCR0;
556                 cccr_msr = MSR_P4_IQ_CCCR1;
557                 cccr_val = P4_CCCR_OVF_PMI1 | P4_CCCR_ESCR_SELECT(4);
558         }
559
560         if (!reserve_perfctr_nmi(perfctr_msr))
561                 goto fail;
562
563         if (!reserve_evntsel_nmi(evntsel_msr))
564                 goto fail1;
565
566         evntsel = P4_ESCR_EVENT_SELECT(0x3F)
567                 | P4_ESCR_OS
568                 | P4_ESCR_USR;
569
570         cccr_val |= P4_CCCR_THRESHOLD(15)
571                  | P4_CCCR_COMPLEMENT
572                  | P4_CCCR_COMPARE
573                  | P4_CCCR_REQUIRED;
574
575         wrmsr(evntsel_msr, evntsel, 0);
576         wrmsr(cccr_msr, cccr_val, 0);
577         wrmsrl(perfctr_msr, -((u64)cpu_khz * 1000 / nmi_hz));
578         apic_write(APIC_LVTPC, APIC_DM_NMI);
579         cccr_val |= P4_CCCR_ENABLE;
580         wrmsr(cccr_msr, cccr_val, 0);
581
582         wd->perfctr_msr = perfctr_msr;
583         wd->evntsel_msr = evntsel_msr;
584         wd->cccr_msr = cccr_msr;
585         wd->check_bit = 1ULL<<39;
586         return 1;
587 fail1:
588         release_perfctr_nmi(perfctr_msr);
589 fail:
590         return 0;
591 }
592
593 static void stop_p4_watchdog(void)
594 {
595         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
596
597         wrmsr(wd->cccr_msr, 0, 0);
598         wrmsr(wd->evntsel_msr, 0, 0);
599
600         release_evntsel_nmi(wd->evntsel_msr);
601         release_perfctr_nmi(wd->perfctr_msr);
602 }
603
604 #define ARCH_PERFMON_NMI_EVENT_SEL      ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL
605 #define ARCH_PERFMON_NMI_EVENT_UMASK    ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK
606
607 static int setup_intel_arch_watchdog(void)
608 {
609         unsigned int ebx;
610         union cpuid10_eax eax;
611         unsigned int unused;
612         unsigned int perfctr_msr, evntsel_msr;
613         unsigned int evntsel;
614         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
615
616         /*
617          * Check whether the Architectural PerfMon supports
618          * Unhalted Core Cycles Event or not.
619          * NOTE: Corresponding bit = 0 in ebx indicates event present.
620          */
621         cpuid(10, &(eax.full), &ebx, &unused, &unused);
622         if ((eax.split.mask_length < (ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX+1)) ||
623             (ebx & ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT))
624                 goto fail;
625
626         perfctr_msr = MSR_ARCH_PERFMON_PERFCTR0;
627         evntsel_msr = MSR_ARCH_PERFMON_EVENTSEL0;
628
629         if (!reserve_perfctr_nmi(perfctr_msr))
630                 goto fail;
631
632         if (!reserve_evntsel_nmi(evntsel_msr))
633                 goto fail1;
634
635         wrmsrl(perfctr_msr, 0UL);
636
637         evntsel = ARCH_PERFMON_EVENTSEL_INT
638                 | ARCH_PERFMON_EVENTSEL_OS
639                 | ARCH_PERFMON_EVENTSEL_USR
640                 | ARCH_PERFMON_NMI_EVENT_SEL
641                 | ARCH_PERFMON_NMI_EVENT_UMASK;
642
643         /* setup the timer */
644         wrmsr(evntsel_msr, evntsel, 0);
645
646         nmi_hz = adjust_for_32bit_ctr(nmi_hz);
647         wrmsr(perfctr_msr, (u32)(-((u64)cpu_khz * 1000 / nmi_hz)), 0);
648
649         apic_write(APIC_LVTPC, APIC_DM_NMI);
650         evntsel |= ARCH_PERFMON_EVENTSEL0_ENABLE;
651         wrmsr(evntsel_msr, evntsel, 0);
652
653         wd->perfctr_msr = perfctr_msr;
654         wd->evntsel_msr = evntsel_msr;
655         wd->cccr_msr = 0;  //unused
656         wd->check_bit = 1ULL << (eax.split.bit_width - 1);
657         return 1;
658 fail1:
659         release_perfctr_nmi(perfctr_msr);
660 fail:
661         return 0;
662 }
663
664 static void stop_intel_arch_watchdog(void)
665 {
666         unsigned int ebx;
667         union cpuid10_eax eax;
668         unsigned int unused;
669         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
670
671         /*
672          * Check whether the Architectural PerfMon supports
673          * Unhalted Core Cycles Event or not.
674          * NOTE: Corresponding bit = 0 in ebx indicates event present.
675          */
676         cpuid(10, &(eax.full), &ebx, &unused, &unused);
677         if ((eax.split.mask_length < (ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX+1)) ||
678             (ebx & ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT))
679                 return;
680
681         wrmsr(wd->evntsel_msr, 0, 0);
682
683         release_evntsel_nmi(wd->evntsel_msr);
684         release_perfctr_nmi(wd->perfctr_msr);
685 }
686
687 void setup_apic_nmi_watchdog(void *unused)
688 {
689         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
690
691         /* only support LOCAL and IO APICs for now */
692         if ((nmi_watchdog != NMI_LOCAL_APIC) &&
693             (nmi_watchdog != NMI_IO_APIC))
694                 return;
695
696         if (wd->enabled == 1)
697                 return;
698
699         /* cheap hack to support suspend/resume */
700         /* if cpu0 is not active neither should the other cpus */
701         if ((smp_processor_id() != 0) && (atomic_read(&nmi_active) <= 0))
702                 return;
703
704         if (nmi_watchdog == NMI_LOCAL_APIC) {
705                 switch (boot_cpu_data.x86_vendor) {
706                 case X86_VENDOR_AMD:
707                         if (strstr(boot_cpu_data.x86_model_id, "Screwdriver"))
708                                 return;
709                         if (!setup_k7_watchdog())
710                                 return;
711                         break;
712                 case X86_VENDOR_INTEL:
713                         if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
714                                 if (!setup_intel_arch_watchdog())
715                                         return;
716                                 break;
717                         }
718                         if (!setup_p4_watchdog())
719                                 return;
720                         break;
721                 default:
722                         return;
723                 }
724         }
725         wd->enabled = 1;
726         atomic_inc(&nmi_active);
727 }
728
729 void stop_apic_nmi_watchdog(void *unused)
730 {
731         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
732
733         /* only support LOCAL and IO APICs for now */
734         if ((nmi_watchdog != NMI_LOCAL_APIC) &&
735             (nmi_watchdog != NMI_IO_APIC))
736                 return;
737
738         if (wd->enabled == 0)
739                 return;
740
741         if (nmi_watchdog == NMI_LOCAL_APIC) {
742                 switch (boot_cpu_data.x86_vendor) {
743                 case X86_VENDOR_AMD:
744                         if (strstr(boot_cpu_data.x86_model_id, "Screwdriver"))
745                                 return;
746                         stop_k7_watchdog();
747                         break;
748                 case X86_VENDOR_INTEL:
749                         if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
750                                 stop_intel_arch_watchdog();
751                                 break;
752                         }
753                         stop_p4_watchdog();
754                         break;
755                 default:
756                         return;
757                 }
758         }
759         wd->enabled = 0;
760         atomic_dec(&nmi_active);
761 }
762
763 /*
764  * the best way to detect whether a CPU has a 'hard lockup' problem
765  * is to check it's local APIC timer IRQ counts. If they are not
766  * changing then that CPU has some problem.
767  *
768  * as these watchdog NMI IRQs are generated on every CPU, we only
769  * have to check the current processor.
770  */
771
772 static DEFINE_PER_CPU(unsigned, last_irq_sum);
773 static DEFINE_PER_CPU(local_t, alert_counter);
774 static DEFINE_PER_CPU(int, nmi_touch);
775
776 void touch_nmi_watchdog (void)
777 {
778         if (nmi_watchdog > 0) {
779                 unsigned cpu;
780
781                 /*
782                  * Tell other CPUs to reset their alert counters. We cannot
783                  * do it ourselves because the alert count increase is not
784                  * atomic.
785                  */
786                 for_each_present_cpu (cpu)
787                         per_cpu(nmi_touch, cpu) = 1;
788         }
789
790         touch_softlockup_watchdog();
791 }
792
793 int __kprobes nmi_watchdog_tick(struct pt_regs * regs, unsigned reason)
794 {
795         int sum;
796         int touched = 0;
797         int cpu = smp_processor_id();
798         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
799         u64 dummy;
800         int rc=0;
801
802         /* check for other users first */
803         if (notify_die(DIE_NMI, "nmi", regs, reason, 2, SIGINT)
804                         == NOTIFY_STOP) {
805                 rc = 1;
806                 touched = 1;
807         }
808
809         sum = read_pda(apic_timer_irqs);
810         if (__get_cpu_var(nmi_touch)) {
811                 __get_cpu_var(nmi_touch) = 0;
812                 touched = 1;
813         }
814
815         if (cpu_isset(cpu, backtrace_mask)) {
816                 static DEFINE_SPINLOCK(lock);   /* Serialise the printks */
817
818                 spin_lock(&lock);
819                 printk("NMI backtrace for cpu %d\n", cpu);
820                 dump_stack();
821                 spin_unlock(&lock);
822                 cpu_clear(cpu, backtrace_mask);
823         }
824
825 #ifdef CONFIG_X86_MCE
826         /* Could check oops_in_progress here too, but it's safer
827            not too */
828         if (atomic_read(&mce_entry) > 0)
829                 touched = 1;
830 #endif
831         /* if the apic timer isn't firing, this cpu isn't doing much */
832         if (!touched && __get_cpu_var(last_irq_sum) == sum) {
833                 /*
834                  * Ayiee, looks like this CPU is stuck ...
835                  * wait a few IRQs (5 seconds) before doing the oops ...
836                  */
837                 local_inc(&__get_cpu_var(alert_counter));
838                 if (local_read(&__get_cpu_var(alert_counter)) == 5*nmi_hz)
839                         die_nmi("NMI Watchdog detected LOCKUP on CPU %d\n", regs,
840                                 panic_on_timeout);
841         } else {
842                 __get_cpu_var(last_irq_sum) = sum;
843                 local_set(&__get_cpu_var(alert_counter), 0);
844         }
845
846         /* see if the nmi watchdog went off */
847         if (wd->enabled) {
848                 if (nmi_watchdog == NMI_LOCAL_APIC) {
849                         rdmsrl(wd->perfctr_msr, dummy);
850                         if (dummy & wd->check_bit){
851                                 /* this wasn't a watchdog timer interrupt */
852                                 goto done;
853                         }
854
855                         /* only Intel uses the cccr msr */
856                         if (wd->cccr_msr != 0) {
857                                 /*
858                                  * P4 quirks:
859                                  * - An overflown perfctr will assert its interrupt
860                                  *   until the OVF flag in its CCCR is cleared.
861                                  * - LVTPC is masked on interrupt and must be
862                                  *   unmasked by the LVTPC handler.
863                                  */
864                                 rdmsrl(wd->cccr_msr, dummy);
865                                 dummy &= ~P4_CCCR_OVF;
866                                 wrmsrl(wd->cccr_msr, dummy);
867                                 apic_write(APIC_LVTPC, APIC_DM_NMI);
868                                 /* start the cycle over again */
869                                 wrmsrl(wd->perfctr_msr,
870                                        -((u64)cpu_khz * 1000 / nmi_hz));
871                         } else if (wd->perfctr_msr == MSR_ARCH_PERFMON_PERFCTR0) {
872                                 /*
873                                  * ArchPerfom/Core Duo needs to re-unmask
874                                  * the apic vector
875                                  */
876                                 apic_write(APIC_LVTPC, APIC_DM_NMI);
877                                 /* ARCH_PERFMON has 32 bit counter writes */
878                                 wrmsr(wd->perfctr_msr,
879                                      (u32)(-((u64)cpu_khz * 1000 / nmi_hz)), 0);
880                         } else {
881                                 /* start the cycle over again */
882                                 wrmsrl(wd->perfctr_msr,
883                                        -((u64)cpu_khz * 1000 / nmi_hz));
884                         }
885                         rc = 1;
886                 } else  if (nmi_watchdog == NMI_IO_APIC) {
887                         /* don't know how to accurately check for this.
888                          * just assume it was a watchdog timer interrupt
889                          * This matches the old behaviour.
890                          */
891                         rc = 1;
892                 } else
893                         printk(KERN_WARNING "Unknown enabled NMI hardware?!\n");
894         }
895 done:
896         return rc;
897 }
898
899 asmlinkage __kprobes void do_nmi(struct pt_regs * regs, long error_code)
900 {
901         nmi_enter();
902         add_pda(__nmi_count,1);
903         default_do_nmi(regs);
904         nmi_exit();
905 }
906
907 int do_nmi_callback(struct pt_regs * regs, int cpu)
908 {
909 #ifdef CONFIG_SYSCTL
910         if (unknown_nmi_panic)
911                 return unknown_nmi_panic_callback(regs, cpu);
912 #endif
913         return 0;
914 }
915
916 #ifdef CONFIG_SYSCTL
917
918 static int unknown_nmi_panic_callback(struct pt_regs *regs, int cpu)
919 {
920         unsigned char reason = get_nmi_reason();
921         char buf[64];
922
923         sprintf(buf, "NMI received for unknown reason %02x\n", reason);
924         die_nmi(buf, regs, 1);  /* Always panic here */
925         return 0;
926 }
927
928 /*
929  * proc handler for /proc/sys/kernel/nmi
930  */
931 int proc_nmi_enabled(struct ctl_table *table, int write, struct file *file,
932                         void __user *buffer, size_t *length, loff_t *ppos)
933 {
934         int old_state;
935
936         nmi_watchdog_enabled = (atomic_read(&nmi_active) > 0) ? 1 : 0;
937         old_state = nmi_watchdog_enabled;
938         proc_dointvec(table, write, file, buffer, length, ppos);
939         if (!!old_state == !!nmi_watchdog_enabled)
940                 return 0;
941
942         if (atomic_read(&nmi_active) < 0) {
943                 printk( KERN_WARNING "NMI watchdog is permanently disabled\n");
944                 return -EIO;
945         }
946
947         /* if nmi_watchdog is not set yet, then set it */
948         nmi_watchdog_default();
949
950         if (nmi_watchdog == NMI_LOCAL_APIC) {
951                 if (nmi_watchdog_enabled)
952                         enable_lapic_nmi_watchdog();
953                 else
954                         disable_lapic_nmi_watchdog();
955         } else {
956                 printk( KERN_WARNING
957                         "NMI watchdog doesn't know what hardware to touch\n");
958                 return -EIO;
959         }
960         return 0;
961 }
962
963 #endif
964
965 void __trigger_all_cpu_backtrace(void)
966 {
967         int i;
968
969         backtrace_mask = cpu_online_map;
970         /* Wait for up to 10 seconds for all CPUs to do the backtrace */
971         for (i = 0; i < 10 * 1000; i++) {
972                 if (cpus_empty(backtrace_mask))
973                         break;
974                 mdelay(1);
975         }
976 }
977
978 EXPORT_SYMBOL(nmi_active);
979 EXPORT_SYMBOL(nmi_watchdog);
980 EXPORT_SYMBOL(avail_to_resrv_perfctr_nmi);
981 EXPORT_SYMBOL(avail_to_resrv_perfctr_nmi_bit);
982 EXPORT_SYMBOL(reserve_perfctr_nmi);
983 EXPORT_SYMBOL(release_perfctr_nmi);
984 EXPORT_SYMBOL(reserve_evntsel_nmi);
985 EXPORT_SYMBOL(release_evntsel_nmi);
986 EXPORT_SYMBOL(disable_timer_nmi_watchdog);
987 EXPORT_SYMBOL(enable_timer_nmi_watchdog);
988 EXPORT_SYMBOL(touch_nmi_watchdog);