2 * File: arch/blackfin/mach-bf548/head.S
3 * Based on: arch/blackfin/mach-bf537/head.S
4 * Author: Jeff Dionne <jeff@uclinux.org> COPYRIGHT 1998 D. Jeff Dionne
7 * Description: Startup code for Blackfin BF548
10 * Copyright 2004-2007 Analog Devices Inc.
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
30 #include <linux/linkage.h>
31 #include <asm/blackfin.h>
32 #include <asm/trace.h>
33 #if CONFIG_BFIN_KERNEL_CLOCK
34 #include <asm/mach-common/clocks.h>
35 #include <asm/mach/mem_init.h>
43 .extern _bf53x_relocate_l1_mem
45 #define INITIAL_STACK 0xFFB01000
51 /* R0: argument of command line string, passed from uboot, save it */
53 /* Enable Cycle Counter and Nesting Of Interrupts */
54 #ifdef CONFIG_BFIN_SCRATCH_REG_CYCLES
57 R0 = SYSCFG_SNEN | SYSCFG_CCEN;
62 /* Clear Out All the data and pointer Registers*/
84 /* Clear Out All the DAG Registers*/
100 trace_buffer_init(p0,r0);
104 /* Turn off the icache */
105 p0.l = LO(IMEM_CONTROL);
106 p0.h = HI(IMEM_CONTROL);
113 /* Turn off the dcache */
114 p0.l = LO(DMEM_CONTROL);
115 p0.h = HI(DMEM_CONTROL);
122 /* Initialize stack pointer */
123 SP.L = LO(INITIAL_STACK);
124 SP.H = HI(INITIAL_STACK);
128 /* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */
129 call _bf53x_relocate_l1_mem;
130 #if CONFIG_BFIN_KERNEL_CLOCK
131 call _start_dma_code;
133 /* Code for initializing Async memory banks */
135 p2.h = hi(EBIU_AMBCTL1);
136 p2.l = lo(EBIU_AMBCTL1);
137 r0.h = hi(AMBCTL1VAL);
138 r0.l = lo(AMBCTL1VAL);
142 p2.h = hi(EBIU_AMBCTL0);
143 p2.l = lo(EBIU_AMBCTL0);
144 r0.h = hi(AMBCTL0VAL);
145 r0.l = lo(AMBCTL0VAL);
149 p2.h = hi(EBIU_AMGCTL);
150 p2.l = lo(EBIU_AMGCTL);
155 /* This section keeps the processor in supervisor mode
156 * during kernel boot. Switches to user mode at end of boot.
157 * See page 3-9 of Hardware Reference manual for documentation.
160 /* EVT15 = _real_start */
195 w[p0] = r0; /* watchdog off for now */
198 /* Code update for BSS size == 0
199 * Zero out the bss region.
208 lsetup (.L_clear_bss, .L_clear_bss ) lc0 = p2;
212 /* In case there is a NULL pointer reference
213 * Zero out region before stext
223 lsetup (.L_clear_zero, .L_clear_zero ) lc0 = p2;
227 /* pass the uboot arguments to the global value command line */
247 * load the current thread pointer and stack
249 r1.l = _init_thread_union;
250 r1.h = _init_thread_union;
263 #if CONFIG_BFIN_KERNEL_CLOCK
264 ENTRY(_start_dma_code)
266 /* Enable PHY CLK buffer output */
283 * - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
284 * - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK
285 * - [7] = output delay (add 200ps of delay to mem signals)
286 * - [6] = input delay (add 200ps of input delay to mem signals)
287 * - [5] = PDWN : 1=All Clocks off
288 * - [3] = STOPCK : 1=Core Clock off
289 * - [1] = PLL_OFF : 1=Disable Power to PLL
290 * - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
291 * all other bits set to zero
294 p0.h = hi(PLL_LOCKCNT);
295 p0.l = lo(PLL_LOCKCNT);
300 P2.H = hi(EBIU_SDGCTL);
301 P2.L = lo(EBIU_SDGCTL);
307 r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
308 r0 = r0 << 9; /* Shift it over, */
309 r1 = CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/
311 r1 = PLL_BYPASS; /* Bypass the PLL? */
312 r1 = r1 << 8; /* Shift it over */
313 r0 = r1 | r0; /* add them all together */
316 p0.l = lo(PLL_CTL); /* Load the address */
317 cli r2; /* Disable interrupts */
319 w[p0] = r0.l; /* Set the value */
320 idle; /* Wait for the PLL to stablize */
321 sti r2; /* Enable interrupts */
328 if ! CC jump .Lcheck_again;
330 /* Configure SCLK & CCLK Dividers */
331 r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
337 p0.l = lo(EBIU_SDRRC);
338 p0.h = hi(EBIU_SDRRC);
343 p0.l = LO(EBIU_SDBCTL);
344 p0.h = HI(EBIU_SDBCTL); /* SDRAM Memory Bank Control Register */
349 P2.H = hi(EBIU_SDGCTL);
350 P2.L = lo(EBIU_SDGCTL);
353 p0.h = hi(EBIU_SDSTAT);
354 p0.l = lo(EBIU_SDSTAT);
364 R0.L = lo(mem_SDGCTL);
365 R0.H = hi(mem_SDGCTL);
373 r0.l = lo(IWR_ENABLE_ALL);
374 r0.h = hi(IWR_ENABLE_ALL);
379 #endif /* CONFIG_BFIN_KERNEL_CLOCK */
384 * Set up the usable of RAM stuff. Size of RAM is determined then
385 * an initial stack set up at the end.