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   1 /*
   2  * File:         arch/blackfin/mach-common/pm.c
   3  * Based on:     arm/mach-omap/pm.c
   4  * Author:       Cliff Brake <cbrake@accelent.com> Copyright (c) 2001
   5  *
   6  * Created:      2001
   7  * Description:  Blackfin power management
   8  *
   9  * Modified:     Nicolas Pitre - PXA250 support
  10  *                Copyright (c) 2002 Monta Vista Software, Inc.
  11  *               David Singleton - OMAP1510
  12  *                Copyright (c) 2002 Monta Vista Software, Inc.
  13  *               Dirk Behme <dirk.behme@de.bosch.com> - OMAP1510/1610
  14  *                Copyright 2004
  15  *               Copyright 2004-2008 Analog Devices Inc.
  16  *
  17  * Bugs:         Enter bugs at http://blackfin.uclinux.org/
  18  *
  19  * This program is free software; you can redistribute it and/or modify
  20  * it under the terms of the GNU General Public License as published by
  21  * the Free Software Foundation; either version 2 of the License, or
  22  * (at your option) any later version.
  23  *
  24  * This program is distributed in the hope that it will be useful,
  25  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  26  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  27  * GNU General Public License for more details.
  28  *
  29  * You should have received a copy of the GNU General Public License
  30  * along with this program; if not, see the file COPYING, or write
  31  * to the Free Software Foundation, Inc.,
  32  * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  33  */
  34
  35 #include <linux/suspend.h>
  36 #include <linux/sched.h>
  37 #include <linux/proc_fs.h>
  38 #include <linux/io.h>
  39 #include <linux/irq.h>
  40
  41 #include <asm/gpio.h>
  42 #include <asm/dma.h>
  43 #include <asm/dpmc.h>
  44
  45 #ifdef CONFIG_PM_WAKEUP_GPIO_POLAR_H
  46 #define WAKEUP_TYPE     PM_WAKE_HIGH
  47 #endif
  48
  49 #ifdef CONFIG_PM_WAKEUP_GPIO_POLAR_L
  50 #define WAKEUP_TYPE     PM_WAKE_LOW
  51 #endif
  52
  53 #ifdef CONFIG_PM_WAKEUP_GPIO_POLAR_EDGE_F
  54 #define WAKEUP_TYPE     PM_WAKE_FALLING
  55 #endif
  56
  57 #ifdef CONFIG_PM_WAKEUP_GPIO_POLAR_EDGE_R
  58 #define WAKEUP_TYPE     PM_WAKE_RISING
  59 #endif
  60
  61 #ifdef CONFIG_PM_WAKEUP_GPIO_POLAR_EDGE_B
  62 #define WAKEUP_TYPE     PM_WAKE_BOTH_EDGES
  63 #endif
  64
  65
  66 void bfin_pm_suspend_standby_enter(void)
  67 {
  68         unsigned long flags;
  69
  70 #ifdef CONFIG_PM_WAKEUP_BY_GPIO
  71         gpio_pm_wakeup_request(CONFIG_PM_WAKEUP_GPIO_NUMBER, WAKEUP_TYPE);
  72 #endif
  73
  74         local_irq_save(flags);
  75         bfin_pm_standby_setup();
  76
  77 #ifdef CONFIG_PM_BFIN_SLEEP_DEEPER
  78         sleep_deeper(bfin_sic_iwr[0], bfin_sic_iwr[1], bfin_sic_iwr[2]);
  79 #else
  80         sleep_mode(bfin_sic_iwr[0], bfin_sic_iwr[1], bfin_sic_iwr[2]);
  81 #endif
  82
  83         bfin_pm_standby_restore();
  84
  85 #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x)  || defined(CONFIG_BF561)
  86         bfin_write_SIC_IWR0(IWR_ENABLE_ALL);
  87         bfin_write_SIC_IWR1(IWR_ENABLE_ALL);
  88 # ifdef CONFIG_BF54x
  89         bfin_write_SIC_IWR2(IWR_ENABLE_ALL);
  90 # endif
  91 #else
  92         bfin_write_SIC_IWR(IWR_ENABLE_ALL);
  93 #endif
  94
  95         local_irq_restore(flags);
  96 }
  97
  98 int bf53x_suspend_l1_mem(unsigned char *memptr)
  99 {
 100         dma_memcpy(memptr, (const void *) L1_CODE_START, L1_CODE_LENGTH);
 101         dma_memcpy(memptr + L1_CODE_LENGTH, (const void *) L1_DATA_A_START,
 102                         L1_DATA_A_LENGTH);
 103         dma_memcpy(memptr + L1_CODE_LENGTH + L1_DATA_A_LENGTH,
 104                         (const void *) L1_DATA_B_START, L1_DATA_B_LENGTH);
 105         memcpy(memptr + L1_CODE_LENGTH + L1_DATA_A_LENGTH +
 106                         L1_DATA_B_LENGTH, (const void *) L1_SCRATCH_START,
 107                         L1_SCRATCH_LENGTH);
 108
 109         return 0;
 110 }
 111
 112 int bf53x_resume_l1_mem(unsigned char *memptr)
 113 {
 114         dma_memcpy((void *) L1_CODE_START, memptr, L1_CODE_LENGTH);
 115         dma_memcpy((void *) L1_DATA_A_START, memptr + L1_CODE_LENGTH,
 116                         L1_DATA_A_LENGTH);
 117         dma_memcpy((void *) L1_DATA_B_START, memptr + L1_CODE_LENGTH +
 118                         L1_DATA_A_LENGTH, L1_DATA_B_LENGTH);
 119         memcpy((void *) L1_SCRATCH_START, memptr + L1_CODE_LENGTH +
 120                         L1_DATA_A_LENGTH + L1_DATA_B_LENGTH, L1_SCRATCH_LENGTH);
 121
 122         return 0;
 123 }
 124
 125 #ifdef CONFIG_BFIN_WB
 126 static void flushinv_all_dcache(void)
 127 {
 128         u32 way, bank, subbank, set;
 129         u32 status, addr;
 130         u32 dmem_ctl = bfin_read_DMEM_CONTROL();
 131
 132         for (bank = 0; bank < 2; ++bank) {
 133                 if (!(dmem_ctl & (1 << (DMC1_P - bank))))
 134                         continue;
 135
 136                 for (way = 0; way < 2; ++way)
 137                         for (subbank = 0; subbank < 4; ++subbank)
 138                                 for (set = 0; set < 64; ++set) {
 139
 140                                         bfin_write_DTEST_COMMAND(
 141                                                 way << 26 |
 142                                                 bank << 23 |
 143                                                 subbank << 16 |
 144                                                 set << 5
 145                                         );
 146                                         CSYNC();
 147                                         status = bfin_read_DTEST_DATA0();
 148
 149                                         /* only worry about valid/dirty entries */
 150                                         if ((status & 0x3) != 0x3)
 151                                                 continue;
 152
 153                                         /* construct the address using the tag */
 154                                         addr = (status & 0xFFFFC800) | (subbank << 12) | (set << 5);
 155
 156                                         /* flush it */
 157                                         __asm__ __volatile__("FLUSHINV[%0];" : : "a"(addr));
 158                                 }
 159         }
 160 }
 161 #endif
 162
 163 static inline void dcache_disable(void)
 164 {
 165 #ifdef CONFIG_BFIN_DCACHE
 166         unsigned long ctrl;
 167
 168 #ifdef CONFIG_BFIN_WB
 169         flushinv_all_dcache();
 170 #endif
 171         SSYNC();
 172         ctrl = bfin_read_DMEM_CONTROL();
 173         ctrl &= ~ENDCPLB;
 174         bfin_write_DMEM_CONTROL(ctrl);
 175         SSYNC();
 176 #endif
 177 }
 178
 179 static inline void dcache_enable(void)
 180 {
 181 #ifdef CONFIG_BFIN_DCACHE
 182         unsigned long ctrl;
 183         SSYNC();
 184         ctrl = bfin_read_DMEM_CONTROL();
 185         ctrl |= ENDCPLB;
 186         bfin_write_DMEM_CONTROL(ctrl);
 187         SSYNC();
 188 #endif
 189 }
 190
 191 static inline void icache_disable(void)
 192 {
 193 #ifdef CONFIG_BFIN_ICACHE
 194         unsigned long ctrl;
 195         SSYNC();
 196         ctrl = bfin_read_IMEM_CONTROL();
 197         ctrl &= ~ENICPLB;
 198         bfin_write_IMEM_CONTROL(ctrl);
 199         SSYNC();
 200 #endif
 201 }
 202
 203 static inline void icache_enable(void)
 204 {
 205 #ifdef CONFIG_BFIN_ICACHE
 206         unsigned long ctrl;
 207         SSYNC();
 208         ctrl = bfin_read_IMEM_CONTROL();
 209         ctrl |= ENICPLB;
 210         bfin_write_IMEM_CONTROL(ctrl);
 211         SSYNC();
 212 #endif
 213 }
 214
 215 int bfin_pm_suspend_mem_enter(void)
 216 {
 217         unsigned long flags;
 218         int wakeup, ret;
 219
 220         unsigned char *memptr = kmalloc(L1_CODE_LENGTH + L1_DATA_A_LENGTH
 221                                          + L1_DATA_B_LENGTH + L1_SCRATCH_LENGTH,
 222                                           GFP_KERNEL);
 223
 224         if (memptr == NULL) {
 225                 panic("bf53x_suspend_l1_mem malloc failed");
 226                 return -ENOMEM;
 227         }
 228
 229         wakeup = bfin_read_VR_CTL() & ~FREQ;
 230         wakeup |= SCKELOW;
 231
 232         /* FIXME: merge this somehow with set_irq_wake */
 233 #ifdef CONFIG_PM_BFIN_WAKE_RTC
 234         wakeup |= WAKE;
 235 #endif
 236 #ifdef CONFIG_PM_BFIN_WAKE_PH6
 237         wakeup |= PHYWE;
 238 #endif
 239 #ifdef CONFIG_PM_BFIN_WAKE_CAN
 240         wakeup |= CANWE;
 241 #endif
 242 #ifdef CONFIG_PM_BFIN_WAKE_GP
 243         wakeup |= GPWE;
 244 #endif
 245 #ifdef CONFIG_PM_BFIN_WAKE_USB
 246         wakeup |= USBWE;
 247 #endif
 248 #ifdef CONFIG_PM_BFIN_WAKE_KEYPAD
 249         wakeup |= KPADWE;
 250 #endif
 251 #ifdef CONFIG_PM_BFIN_WAKE_ROTARY
 252         wakeup |= ROTWE;
 253 #endif
 254
 255         local_irq_save(flags);
 256
 257         ret = blackfin_dma_suspend();
 258
 259         if (ret) {
 260                 local_irq_restore(flags);
 261                 kfree(memptr);
 262                 return ret;
 263         }
 264
 265         bfin_gpio_pm_hibernate_suspend();
 266
 267         dcache_disable();
 268         icache_disable();
 269         bf53x_suspend_l1_mem(memptr);
 270
 271         do_hibernate(wakeup);   /* Goodbye */
 272
 273         bf53x_resume_l1_mem(memptr);
 274
 275         icache_enable();
 276         dcache_enable();
 277
 278         bfin_gpio_pm_hibernate_restore();
 279         blackfin_dma_resume();
 280
 281         local_irq_restore(flags);
 282         kfree(memptr);
 283
 284         return 0;
 285 }
 286
 287 /*
 288  *      bfin_pm_valid - Tell the PM core that we only support the standby sleep
 289  *                      state
 290  *      @state:         suspend state we're checking.
 291  *
 292  */
 293 static int bfin_pm_valid(suspend_state_t state)
 294 {
 295         return (state == PM_SUSPEND_STANDBY
 296 #ifndef BF533_FAMILY
 297         /*
 298          * On BF533/2/1:
 299          * If we enter Hibernate the SCKE Pin is driven Low,
 300          * so that the SDRAM enters Self Refresh Mode.
 301          * However when the reset sequence that follows hibernate
 302          * state is executed, SCKE is driven High, taking the
 303          * SDRAM out of Self Refresh.
 304          *
 305          * If you reconfigure and access the SDRAM "very quickly",
 306          * you are likely to avoid errors, otherwise the SDRAM
 307          * start losing its contents.
 308          * An external HW workaround is possible using logic gates.
 309          */
 310         || state == PM_SUSPEND_MEM
 311 #endif
 312         );
 313 }
 314
 315 /*
 316  *      bfin_pm_enter - Actually enter a sleep state.
 317  *      @state:         State we're entering.
 318  *
 319  */
 320 static int bfin_pm_enter(suspend_state_t state)
 321 {
 322         switch (state) {
 323         case PM_SUSPEND_STANDBY:
 324                 bfin_pm_suspend_standby_enter();
 325                 break;
 326         case PM_SUSPEND_MEM:
 327                 bfin_pm_suspend_mem_enter();
 328                 break;
 329         default:
 330                 return -EINVAL;
 331         }
 332
 333         return 0;
 334 }
 335
 336 struct platform_suspend_ops bfin_pm_ops = {
 337         .enter = bfin_pm_enter,
 338         .valid  = bfin_pm_valid,
 339 };
 340
 341 static int __init bfin_pm_init(void)
 342 {
 343         suspend_set_ops(&bfin_pm_ops);
 344         return 0;
 345 }
 346
 347 __initcall(bfin_pm_init);