2 * Copyright (c) 2008 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include <linux/etherdevice.h>
21 #include <linux/pci.h>
22 #include <net/mac80211.h>
23 #include <linux/leds.h>
24 #include <linux/rfkill.h>
31 /* Macro to expand scalars to 64-bit objects */
33 #define ito64(x) (sizeof(x) == 8) ? \
34 (((unsigned long long int)(x)) & (0xff)) : \
36 (((unsigned long long int)(x)) & 0xffff) : \
37 ((sizeof(x) == 32) ? \
38 (((unsigned long long int)(x)) & 0xffffffff) : \
39 (unsigned long long int)(x))
41 /* increment with wrap-around */
42 #define INCR(_l, _sz) do { \
44 (_l) &= ((_sz) - 1); \
47 /* decrement with wrap-around */
48 #define DECR(_l, _sz) do { \
50 (_l) &= ((_sz) - 1); \
53 #define A_MAX(a, b) ((a) > (b) ? (a) : (b))
55 #define ASSERT(exp) do { \
56 if (unlikely(!(exp))) { \
61 #define TSF_TO_TU(_h,_l) \
62 ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10))
64 #define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<<i))
66 static const u8 ath_bcast_mac[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
69 ATH_DBG_RESET = 0x00000001,
70 ATH_DBG_REG_IO = 0x00000002,
71 ATH_DBG_QUEUE = 0x00000004,
72 ATH_DBG_EEPROM = 0x00000008,
73 ATH_DBG_CALIBRATE = 0x00000010,
74 ATH_DBG_CHANNEL = 0x00000020,
75 ATH_DBG_INTERRUPT = 0x00000040,
76 ATH_DBG_REGULATORY = 0x00000080,
77 ATH_DBG_ANI = 0x00000100,
78 ATH_DBG_POWER_MGMT = 0x00000200,
79 ATH_DBG_XMIT = 0x00000400,
80 ATH_DBG_BEACON = 0x00001000,
81 ATH_DBG_CONFIG = 0x00002000,
82 ATH_DBG_KEYCACHE = 0x00004000,
83 ATH_DBG_FATAL = 0x00008000,
84 ATH_DBG_ANY = 0xffffffff
87 #define DBG_DEFAULT (ATH_DBG_FATAL)
89 #ifdef CONFIG_ATH9K_DEBUG
91 void DPRINTF(struct ath_softc *sc, int dbg_mask, const char *fmt, ...);
92 void ath9k_init_debug(struct ath_softc *sc);
96 static inline void DPRINTF(struct ath_softc *sc, int dbg_mask,
101 static inline ath9k_init_debug(struct ath_softc *sc)
110 u16 txpowlimit_override;
115 /*************************/
116 /* Descriptor Management */
117 /*************************/
119 #define ATH_TXBUF_RESET(_bf) do { \
120 (_bf)->bf_status = 0; \
121 (_bf)->bf_lastbf = NULL; \
122 (_bf)->bf_lastfrm = NULL; \
123 (_bf)->bf_next = NULL; \
124 memset(&((_bf)->bf_state), 0, \
125 sizeof(struct ath_buf_state)); \
135 BUF_SHORT_PREAMBLE = BIT(6),
138 BUF_AGGR_BURST = BIT(9),
139 BUF_CALC_AIRTIME = BIT(10),
142 struct ath_buf_state {
143 int bfs_nframes; /* # frames in aggregate */
144 u16 bfs_al; /* length of aggregate */
145 u16 bfs_frmlen; /* length of frame */
146 int bfs_seqno; /* sequence number */
147 int bfs_tidno; /* tid of this frame */
148 int bfs_retries; /* current retries */
149 u32 bf_type; /* BUF_* (enum buffer_type) */
151 enum ath9k_key_type bfs_keytype;
154 #define bf_nframes bf_state.bfs_nframes
155 #define bf_al bf_state.bfs_al
156 #define bf_frmlen bf_state.bfs_frmlen
157 #define bf_retries bf_state.bfs_retries
158 #define bf_seqno bf_state.bfs_seqno
159 #define bf_tidno bf_state.bfs_tidno
160 #define bf_rcs bf_state.bfs_rcs
161 #define bf_keyix bf_state.bfs_keyix
162 #define bf_keytype bf_state.bfs_keytype
163 #define bf_isdata(bf) (bf->bf_state.bf_type & BUF_DATA)
164 #define bf_isaggr(bf) (bf->bf_state.bf_type & BUF_AGGR)
165 #define bf_isampdu(bf) (bf->bf_state.bf_type & BUF_AMPDU)
166 #define bf_isht(bf) (bf->bf_state.bf_type & BUF_HT)
167 #define bf_isretried(bf) (bf->bf_state.bf_type & BUF_RETRY)
168 #define bf_isxretried(bf) (bf->bf_state.bf_type & BUF_XRETRY)
169 #define bf_isshpreamble(bf) (bf->bf_state.bf_type & BUF_SHORT_PREAMBLE)
170 #define bf_isbar(bf) (bf->bf_state.bf_type & BUF_BAR)
171 #define bf_ispspoll(bf) (bf->bf_state.bf_type & BUF_PSPOLL)
172 #define bf_isaggrburst(bf) (bf->bf_state.bf_type & BUF_AGGR_BURST)
175 * Abstraction of a contiguous buffer to transmit/receive. There is only
176 * a single hw descriptor encapsulated here.
179 struct list_head list;
180 struct list_head *last;
181 struct ath_buf *bf_lastbf; /* last buf of this unit (a frame or
183 struct ath_buf *bf_lastfrm; /* last buf of this frame */
184 struct ath_buf *bf_next; /* next subframe in the aggregate */
185 void *bf_mpdu; /* enclosing frame structure */
186 struct ath_desc *bf_desc; /* virtual addr of desc */
187 dma_addr_t bf_daddr; /* physical addr of desc */
188 dma_addr_t bf_buf_addr; /* physical addr of data buffer */
190 u16 bf_flags; /* tx descriptor flags */
191 struct ath_buf_state bf_state; /* buffer state */
192 dma_addr_t bf_dmacontext;
195 #define ATH_RXBUF_RESET(_bf) ((_bf)->bf_status = 0)
197 /* hw processing complete, desc processed by hal */
198 #define ATH_BUFSTATUS_DONE 0x00000001
199 /* hw processing complete, desc hold for hw */
200 #define ATH_BUFSTATUS_STALE 0x00000002
201 /* Rx-only: OS is done with this packet and it's ok to queued it to hw */
202 #define ATH_BUFSTATUS_FREE 0x00000004
204 /* DMA state for tx/rx descriptors */
208 struct ath_desc *dd_desc; /* descriptors */
209 dma_addr_t dd_desc_paddr; /* physical addr of dd_desc */
210 u32 dd_desc_len; /* size of dd_desc */
211 struct ath_buf *dd_bufptr; /* associated buffers */
212 dma_addr_t dd_dmacontext;
215 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
216 struct list_head *head, const char *name,
217 int nbuf, int ndesc);
218 void ath_descdma_cleanup(struct ath_softc *sc, struct ath_descdma *dd,
219 struct list_head *head);
225 #define ATH_MAX_ANTENNA 3
226 #define ATH_RXBUF 512
227 #define WME_NUM_TID 16
229 int ath_startrecv(struct ath_softc *sc);
230 bool ath_stoprecv(struct ath_softc *sc);
231 void ath_flushrecv(struct ath_softc *sc);
232 u32 ath_calcrxfilter(struct ath_softc *sc);
233 int ath_rx_init(struct ath_softc *sc, int nbufs);
234 void ath_rx_cleanup(struct ath_softc *sc);
235 int ath_rx_tasklet(struct ath_softc *sc, int flush);
237 #define ATH_TXBUF 512
238 #define ATH_TXMAXTRY 13
239 #define ATH_11N_TXMAXTRY 10
240 #define ATH_MGT_TXMAXTRY 4
241 #define WME_BA_BMP_SIZE 64
242 #define WME_MAX_BA WME_BA_BMP_SIZE
243 #define ATH_TID_MAX_BUFS (2 * WME_MAX_BA)
244 #define TID_TO_WME_AC(_tid) \
245 ((((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \
246 (((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK : \
247 (((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \
258 u32 axq_qnum; /* hardware q number */
259 u32 *axq_link; /* link ptr in last TX desc */
260 struct list_head axq_q; /* transmit queue */
262 unsigned long axq_lockflags; /* intr state when must cli */
263 u32 axq_depth; /* queue depth */
264 u8 axq_aggr_depth; /* aggregates queued */
265 u32 axq_totalqueued; /* total ever queued */
267 bool stopped; /* Is mac80211 queue stopped ? */
268 struct ath_buf *axq_linkbuf; /* virtual addr of last buffer*/
270 /* first desc of the last descriptor that contains CTS */
271 struct ath_desc *axq_lastdsWithCTS;
273 /* final desc of the gating desc that determines whether
274 lastdsWithCTS has been DMA'ed or not */
275 struct ath_desc *axq_gatingds;
277 struct list_head axq_acq;
280 #define AGGR_CLEANUP BIT(1)
281 #define AGGR_ADDBA_COMPLETE BIT(2)
282 #define AGGR_ADDBA_PROGRESS BIT(3)
284 /* per TID aggregate tx state for a destination */
286 struct list_head list; /* round-robin tid entry */
287 struct list_head buf_q; /* pending buffers */
289 struct ath_atx_ac *ac;
290 struct ath_buf *tx_buf[ATH_TID_MAX_BUFS]; /* active tx frames */
295 int baw_head; /* first un-acked tx buffer */
296 int baw_tail; /* next unused tx buffer slot */
300 int addba_exchangeattempts;
303 /* per access-category aggregate tx state for a destination */
305 int sched; /* dest-ac is scheduled */
306 int qnum; /* H/W queue number associated
308 struct list_head list; /* round-robin txq entry */
309 struct list_head tid_q; /* queue of TIDs with buffers */
312 /* per dest tx state */
314 struct ath_atx_tid tid[WME_NUM_TID];
315 struct ath_atx_ac ac[WME_NUM_AC];
318 /* per-frame tx control block */
319 struct ath_tx_control {
324 /* per frame tx status block */
325 struct ath_xmit_status {
326 int retries; /* number of retries to successufully
327 transmit this frame */
328 int flags; /* status of transmit */
329 #define ATH_TX_ERROR 0x01
330 #define ATH_TX_XRETRY 0x02
331 #define ATH_TX_BAR 0x04
334 /* All RSSI values are noise floor adjusted */
337 int rssictl[ATH_MAX_ANTENNA];
338 int rssiextn[ATH_MAX_ANTENNA];
343 /* if any of ctl,extn chain rssis are valid */
344 #define ATH_TX_CHAIN_RSSI_VALID 0x01
345 /* if extn chain rssis are valid */
346 #define ATH_TX_RSSI_EXTN_VALID 0x02
347 u32 airtime; /* time on air per final tx rate */
350 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype);
351 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq);
352 int ath_tx_setup(struct ath_softc *sc, int haltype);
353 void ath_draintxq(struct ath_softc *sc, bool retry_tx);
354 void ath_tx_draintxq(struct ath_softc *sc,
355 struct ath_txq *txq, bool retry_tx);
356 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an);
357 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an);
358 void ath_tx_node_free(struct ath_softc *sc, struct ath_node *an);
359 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq);
360 int ath_tx_init(struct ath_softc *sc, int nbufs);
361 int ath_tx_cleanup(struct ath_softc *sc);
362 int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype);
363 struct ath_txq *ath_test_get_txq(struct ath_softc *sc, struct sk_buff *skb);
364 int ath_txq_update(struct ath_softc *sc, int qnum,
365 struct ath9k_tx_queue_info *q);
366 int ath_tx_start(struct ath_softc *sc, struct sk_buff *skb,
367 struct ath_tx_control *txctl);
368 void ath_tx_tasklet(struct ath_softc *sc);
369 u32 ath_txq_depth(struct ath_softc *sc, int qnum);
370 u32 ath_txq_aggr_depth(struct ath_softc *sc, int qnum);
371 void ath_tx_cabq(struct ath_softc *sc, struct sk_buff *skb);
373 /**********************/
374 /* Node / Aggregation */
375 /**********************/
377 #define ADDBA_EXCHANGE_ATTEMPTS 10
378 #define ATH_AGGR_DELIM_SZ 4
379 #define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */
380 /* number of delimiters for encryption padding */
381 #define ATH_AGGR_ENCRYPTDELIM 10
382 /* minimum h/w qdepth to be sustained to maximize aggregation */
383 #define ATH_AGGR_MIN_QDEPTH 2
384 #define ATH_AMPDU_SUBFRAME_DEFAULT 32
385 #define IEEE80211_SEQ_SEQ_SHIFT 4
386 #define IEEE80211_SEQ_MAX 4096
387 #define IEEE80211_MIN_AMPDU_BUF 0x8
388 #define IEEE80211_HTCAP_MAXRXAMPDU_FACTOR 13
390 /* return whether a bit at index _n in bitmap _bm is set
391 * _sz is the size of the bitmap */
392 #define ATH_BA_ISSET(_bm, _n) (((_n) < (WME_BA_BMP_SIZE)) && \
393 ((_bm)[(_n) >> 5] & (1 << ((_n) & 31))))
395 /* return block-ack bitmap index given sequence and starting sequence */
396 #define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1))
398 /* returns delimiter padding required given the packet length */
399 #define ATH_AGGR_GET_NDELIM(_len) \
400 (((((_len) + ATH_AGGR_DELIM_SZ) < ATH_AGGR_MINPLEN) ? \
401 (ATH_AGGR_MINPLEN - (_len) - ATH_AGGR_DELIM_SZ) : 0) >> 2)
403 #define BAW_WITHIN(_start, _bawsz, _seqno) \
404 ((((_seqno) - (_start)) & 4095) < (_bawsz))
406 #define ATH_DS_BA_SEQ(_ds) ((_ds)->ds_us.tx.ts_seqnum)
407 #define ATH_DS_BA_BITMAP(_ds) (&(_ds)->ds_us.tx.ba_low)
408 #define ATH_DS_TX_BA(_ds) ((_ds)->ds_us.tx.ts_flags & ATH9K_TX_BA)
409 #define ATH_AN_2_TID(_an, _tidno) (&(_an)->an_aggr.tx.tid[(_tidno)])
411 enum ATH_AGGR_STATUS {
419 struct aggr_rifs_param {
420 int param_max_frames;
424 struct ath_rc_series *param_rcs;
427 /* Per-node aggregation state */
428 struct ath_node_aggr {
433 struct ath_softc *an_sc;
434 struct ath_node_aggr an_aggr;
439 void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid);
440 bool ath_tx_aggr_check(struct ath_softc *sc, struct ath_node *an, u8 tidno);
441 void ath_tx_aggr_teardown(struct ath_softc *sc, struct ath_node *an, u8 tidno);
442 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
444 int ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
445 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
452 * Define the scheme that we select MAC address for multiple
453 * BSS on the same radio. The very first VAP will just use the MAC
454 * address from the EEPROM. For the next 3 VAPs, we set the
455 * U/L bit (bit 1) in MAC address, and use the next two bits as the
459 #define ATH_SET_VAP_BSSID_MASK(bssid_mask) \
460 ((bssid_mask)[0] &= ~(((ATH_BCBUF-1)<<2)|0x02))
464 enum ath9k_opmode av_opmode;
465 struct ath_buf *av_bcbuf;
466 struct ath_tx_control av_btxctl;
469 /*******************/
470 /* Beacon Handling */
471 /*******************/
474 * Regardless of the number of beacons we stagger, (i.e. regardless of the
475 * number of BSSIDs) if a given beacon does not go out even after waiting this
476 * number of beacon intervals, the game's up.
478 #define BSTUCK_THRESH (9 * ATH_BCBUF)
480 #define ATH_DEFAULT_BINTVAL 100 /* TU */
481 #define ATH_DEFAULT_BMISS_LIMIT 10
482 #define IEEE80211_MS_TO_TU(x) (((x) * 1000) / 1024)
484 struct ath_beacon_config {
494 } u; /* last received beacon/probe response timestamp of this BSS. */
497 void ath9k_beacon_tasklet(unsigned long data);
498 void ath_beacon_config(struct ath_softc *sc, int if_id);
499 int ath_beaconq_setup(struct ath_hal *ah);
500 int ath_beacon_alloc(struct ath_softc *sc, int if_id);
501 void ath_beacon_return(struct ath_softc *sc, struct ath_vap *avp);
502 void ath_beacon_sync(struct ath_softc *sc, int if_id);
508 /* ANI values for STA only.
509 FIXME: Add appropriate values for AP later */
511 #define ATH_ANI_POLLINTERVAL 100 /* 100 milliseconds between ANI poll */
512 #define ATH_SHORT_CALINTERVAL 1000 /* 1 second between calibrations */
513 #define ATH_LONG_CALINTERVAL 30000 /* 30 seconds between calibrations */
514 #define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes between calibrations */
518 int16_t sc_noise_floor;
519 unsigned int sc_longcal_timer;
520 unsigned int sc_shortcal_timer;
521 unsigned int sc_resetcal_timer;
522 unsigned int sc_checkani_timer;
523 struct timer_list timer;
526 /********************/
528 /********************/
530 #define ATH_LED_PIN 1
540 struct ath_softc *sc;
541 struct led_classdev led_cdev;
542 enum ath_led_type led_type;
548 #define ATH_RFKILL_POLL_INTERVAL 2000 /* msecs */
551 struct rfkill *rfkill;
552 struct delayed_work rfkill_poll;
553 char rfkill_name[32];
556 /********************/
557 /* Main driver core */
558 /********************/
561 * Default cache line size, in bytes.
562 * Used when PCI device not fully initialized by bootrom/BIOS
564 #define DEFAULT_CACHELINE 32
565 #define ATH_DEFAULT_NOISE_FLOOR -95
566 #define ATH_REGCLASSIDS_MAX 10
567 #define ATH_CABQ_READY_TIME 80 /* % of beacon interval */
568 #define ATH_MAX_SW_RETRIES 10
569 #define ATH_CHAN_MAX 255
570 #define IEEE80211_WEP_NKID 4 /* number of key ids */
571 #define IEEE80211_RATE_VAL 0x7f
573 * The key cache is used for h/w cipher state and also for
574 * tracking station state such as the current tx antenna.
575 * We also setup a mapping table between key cache slot indices
576 * and station state to short-circuit node lookups on rx.
577 * Different parts have different size key caches. We handle
578 * up to ATH_KEYMAX entries (could dynamically allocate state).
580 #define ATH_KEYMAX 128 /* max key cache size we handle */
582 #define ATH_IF_ID_ANY 0xff
583 #define ATH_TXPOWER_MAX 100 /* .5 dBm units */
584 #define ATH_RSSI_DUMMY_MARKER 0x127
585 #define ATH_RATE_DUMMY_MARKER 0
593 #define SC_OP_INVALID BIT(0)
594 #define SC_OP_BEACONS BIT(1)
595 #define SC_OP_RXAGGR BIT(2)
596 #define SC_OP_TXAGGR BIT(3)
597 #define SC_OP_CHAINMASK_UPDATE BIT(4)
598 #define SC_OP_FULL_RESET BIT(5)
599 #define SC_OP_NO_RESET BIT(6)
600 #define SC_OP_PREAMBLE_SHORT BIT(7)
601 #define SC_OP_PROTECT_ENABLE BIT(8)
602 #define SC_OP_RXFLUSH BIT(9)
603 #define SC_OP_LED_ASSOCIATED BIT(10)
604 #define SC_OP_RFKILL_REGISTERED BIT(11)
605 #define SC_OP_RFKILL_SW_BLOCKED BIT(12)
606 #define SC_OP_RFKILL_HW_BLOCKED BIT(13)
609 struct ieee80211_hw *hw;
610 struct pci_dev *pdev;
611 struct tasklet_struct intr_tq;
612 struct tasklet_struct bcon_tasklet;
613 struct ath_config sc_config;
614 struct ath_hal *sc_ah;
617 u8 sc_curbssid[ETH_ALEN];
618 u8 sc_myaddr[ETH_ALEN];
619 u8 sc_bssidmask[ETH_ALEN];
621 #ifdef CONFIG_ATH9K_DEBUG
625 u32 sc_flags; /* SC_OP_* */
626 unsigned int rx_filter;
630 int sc_slotupdate; /* slot to next advance fsm */
632 int sc_bslot[ATH_BCBUF];
635 enum ath9k_int sc_imask;
636 enum wireless_mode sc_curmode;
637 enum PROT_MODE sc_protmode;
641 struct ieee80211_vif *sc_vaps[ATH_BCBUF];
647 struct ath9k_node_stats sc_halstats;
648 enum ath9k_ht_extprotspacing sc_ht_extprotspacing;
649 enum ath9k_ht_macmode tx_chan_width;
651 #ifdef CONFIG_SLOW_ANT_DIV
652 struct ath_antdiv sc_antdiv;
655 OK, /* no change needed */
656 UPDATE, /* update pending */
657 COMMIT /* beacon sent, commit change */
658 } sc_updateslot; /* slot time update fsm */
662 DECLARE_BITMAP(sc_keymap, ATH_KEYMAX);
663 u8 sc_splitmic; /* split TKIP MIC keys */
666 struct list_head sc_rxbuf;
667 struct ath_descdma sc_rxdma;
672 struct list_head sc_txbuf;
673 struct ath_txq sc_txq[ATH9K_NUM_TX_QUEUES];
674 struct ath_descdma sc_txdma;
676 int sc_haltype2q[ATH9K_WME_AC_VO+1];
677 u16 seq_no; /* TX sequence number */
680 struct ath9k_tx_queue_info sc_beacon_qi;
681 struct ath_descdma sc_bdma;
682 struct ath_txq *sc_cabq;
683 struct list_head sc_bbuf;
690 struct ieee80211_rate rates[IEEE80211_NUM_BANDS][ATH_RATE_MAX];
691 struct ath_rate_table *hw_rate_table[ATH9K_MODE_MAX];
695 struct ieee80211_channel channels[IEEE80211_NUM_BANDS][ATH_CHAN_MAX];
696 struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
699 spinlock_t sc_rxflushlock;
700 spinlock_t sc_rxbuflock;
701 spinlock_t sc_txbuflock;
702 spinlock_t sc_resetlock;
705 struct ath_led radio_led;
706 struct ath_led assoc_led;
707 struct ath_led tx_led;
708 struct ath_led rx_led;
711 struct ath_rfkill rf_kill;
714 struct ath_ani sc_ani;
717 int ath_reset(struct ath_softc *sc, bool retry_tx);
718 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc);
719 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc);
720 int ath_cabq_update(struct ath_softc *);