2 * linux/arch/i386/kernel/head.S -- the 32-bit startup code.
4 * Copyright (C) 1991, 1992 Linus Torvalds
6 * Enhanced CPU detection and feature setting code by Mike Jagdis
7 * and Martin Mares, November 1997.
11 #include <linux/threads.h>
12 #include <linux/linkage.h>
13 #include <asm/segment.h>
15 #include <asm/pgtable.h>
17 #include <asm/cache.h>
18 #include <asm/thread_info.h>
19 #include <asm/asm-offsets.h>
20 #include <asm/setup.h>
23 * References to members of the new_cpu_data structure.
26 #define X86 new_cpu_data+CPUINFO_x86
27 #define X86_VENDOR new_cpu_data+CPUINFO_x86_vendor
28 #define X86_MODEL new_cpu_data+CPUINFO_x86_model
29 #define X86_MASK new_cpu_data+CPUINFO_x86_mask
30 #define X86_HARD_MATH new_cpu_data+CPUINFO_hard_math
31 #define X86_CPUID new_cpu_data+CPUINFO_cpuid_level
32 #define X86_CAPABILITY new_cpu_data+CPUINFO_x86_capability
33 #define X86_VENDOR_ID new_cpu_data+CPUINFO_x86_vendor_id
36 * This is how much memory *in addition to the memory covered up to
37 * and including _end* we need mapped initially. We need one bit for
38 * each possible page, but only in low memory, which means
39 * 2^32/4096/8 = 128K worst case (4G/4G split.)
41 * Modulo rounding, each megabyte assigned here requires a kilobyte of
42 * memory, which is currently unreclaimed.
44 * This should be a multiple of a page.
46 #define INIT_MAP_BEYOND_END (128*1024)
50 * 32-bit kernel entrypoint; only used by the boot CPU. On entry,
51 * %esi points to the real-mode code as a 32-bit pointer.
52 * CS and DS must be 4 GB flat segments, but we don't depend on
53 * any particular GDT layout, because we load our own as soon as we
58 #ifdef CONFIG_PARAVIRT
65 * Set segments to known values.
68 lgdt boot_gdt_descr - __PAGE_OFFSET
69 movl $(__BOOT_DS),%eax
76 * Clear BSS first so that there are no surprises...
77 * No need to cld as DF is already clear from cld above...
80 movl $__bss_start - __PAGE_OFFSET,%edi
81 movl $__bss_stop - __PAGE_OFFSET,%ecx
86 * Copy bootup parameters out of the way.
87 * Note: %esi still has the pointer to the real-mode data.
88 * With the kexec as boot loader, parameter segment might be loaded beyond
89 * kernel image and might not even be addressable by early boot page tables.
90 * (kexec on panic case). Hence copy out the parameters before initializing
93 movl $(boot_params - __PAGE_OFFSET),%edi
94 movl $(PARAM_SIZE/4),%ecx
98 movl boot_params - __PAGE_OFFSET + NEW_CL_POINTER,%esi
100 jnz 2f # New command line protocol
101 cmpw $(OLD_CL_MAGIC),OLD_CL_MAGIC_ADDR
103 movzwl OLD_CL_OFFSET,%esi
104 addl $(OLD_CL_BASE_ADDR),%esi
106 movl $(saved_command_line - __PAGE_OFFSET),%edi
107 movl $(COMMAND_LINE_SIZE/4),%ecx
113 * Initialize page tables. This creates a PDE and a set of page
114 * tables, which are located immediately beyond _end. The variable
115 * init_pg_tables_end is set up to point to the first "safe" location.
116 * Mappings are created both at virtual address 0 (identity mapping)
117 * and PAGE_OFFSET for up to _end+sizeof(page tables)+INIT_MAP_BEYOND_END.
119 * Warning: don't use %esi or the stack in this code. However, %esp
120 * can be used as a GPR if you really need it...
122 page_pde_offset = (__PAGE_OFFSET >> 20);
124 movl $(pg0 - __PAGE_OFFSET), %edi
125 movl $(swapper_pg_dir - __PAGE_OFFSET), %edx
126 movl $0x007, %eax /* 0x007 = PRESENT+RW+USER */
128 leal 0x007(%edi),%ecx /* Create PDE entry */
129 movl %ecx,(%edx) /* Store identity PDE entry */
130 movl %ecx,page_pde_offset(%edx) /* Store kernel PDE entry */
137 /* End condition: we must map up to and including INIT_MAP_BEYOND_END */
138 /* bytes beyond the end of our own page tables; the +0x007 is the attribute bits */
139 leal (INIT_MAP_BEYOND_END+0x007)(%edi),%ebp
142 movl %edi,(init_pg_tables_end - __PAGE_OFFSET)
145 xorl %ebx,%ebx /* This is the boot CPU (BSP) */
149 * Non-boot CPU entry point; entered from trampoline.S
150 * We can't lgdt here, because lgdt itself uses a data segment, but
151 * we know the trampoline has already loaded the boot_gdt_table GDT
154 ENTRY(startup_32_smp)
156 movl $(__BOOT_DS),%eax
163 * New page tables may be in 4Mbyte page mode and may
164 * be using the global pages.
166 * NOTE! If we are on a 486 we may have no cr4 at all!
167 * So we do not try to touch it unless we really have
168 * some bits in it to set. This won't work if the BSP
169 * implements cr4 but this AP does not -- very unlikely
170 * but be warned! The same applies to the pse feature
171 * if not equally supported. --macro
173 * NOTE! We have to correct for the fact that we're
174 * not yet offset PAGE_OFFSET..
176 #define cr4_bits mmu_cr4_features-__PAGE_OFFSET
180 movl %cr4,%eax # Turn on paging options (PSE,PAE,..)
184 btl $5, %eax # check if PAE is enabled
187 /* Check if extended functions are implemented */
188 movl $0x80000000, %eax
190 cmpl $0x80000000, %eax
192 mov $0x80000001, %eax
194 /* Execute Disable bit supported? */
198 /* Setup EFER (Extended Feature Enable Register) */
199 movl $0xc0000080, %ecx
203 /* Make changes effective */
207 /* This is a secondary processor (AP) */
212 #endif /* CONFIG_SMP */
217 movl $swapper_pg_dir-__PAGE_OFFSET,%eax
218 movl %eax,%cr3 /* set the page table pointer.. */
221 movl %eax,%cr0 /* ..and set paging (PG) bit */
222 ljmp $__BOOT_CS,$1f /* Clear prefetch and normalize %eip */
224 /* Set up the stack pointer */
228 * Initialize eflags. Some BIOS's leave bits like NT set. This would
229 * confuse the debugger if this code is traced.
230 * XXX - best to initialize before switching to protected mode.
237 jz 1f /* Initial CPU cleans BSS */
240 #endif /* CONFIG_SMP */
243 * start system 32-bit setup. We need to re-do some of the things done
244 * in 16-bit mode for the "real" operations.
250 movl $-1,X86_CPUID # -1 for no CPUID initially
252 /* check if it is 486 or 386. */
254 * XXX - this does a lot of unnecessary setup. Alignment checks don't
255 * apply at our cpl of 0 and the stack ought to be aligned already, and
256 * we don't need to preserve eflags.
259 movb $3,X86 # at least 386
261 popl %eax # get EFLAGS
262 movl %eax,%ecx # save original EFLAGS
263 xorl $0x240000,%eax # flip AC and ID bits in EFLAGS
264 pushl %eax # copy to EFLAGS
266 pushfl # get new EFLAGS
267 popl %eax # put it in eax
268 xorl %ecx,%eax # change in flags
269 pushl %ecx # restore original EFLAGS
271 testl $0x40000,%eax # check if AC bit changed
274 movb $4,X86 # at least 486
275 testl $0x200000,%eax # check if ID bit changed
278 /* get vendor info */
279 xorl %eax,%eax # call CPUID with 0 -> return vendor ID
281 movl %eax,X86_CPUID # save CPUID level
282 movl %ebx,X86_VENDOR_ID # lo 4 chars
283 movl %edx,X86_VENDOR_ID+4 # next 4 chars
284 movl %ecx,X86_VENDOR_ID+8 # last 4 chars
286 orl %eax,%eax # do we have processor info as well?
289 movl $1,%eax # Use the CPUID instruction to get CPU type
291 movb %al,%cl # save reg for future use
292 andb $0x0f,%ah # mask processor family
294 andb $0xf0,%al # mask model
297 andb $0x0f,%cl # mask mask revision
299 movl %edx,X86_CAPABILITY
301 is486: movl $0x50022,%ecx # set AM, WP, NE and MP
304 is386: movl $2,%ecx # set MP
306 andl $0x80000011,%eax # Save PG,PE,ET
314 ljmp $(__KERNEL_CS),$1f
315 1: movl $(__KERNEL_DS),%eax # reload all the segment registers
316 movl %eax,%ss # after changing gdt.
318 movl $(__USER_DS),%eax # DS/ES contains default USER segment
322 xorl %eax,%eax # Clear FS and LDT
326 movl $(__KERNEL_PDA),%eax
329 cld # gcc2 wants the direction flag cleared at all times
330 pushl $0 # fake return address for unwinder
334 cmpb $0,%cl # the first CPU calls start_kernel
335 jne initialize_secondary # all other CPUs call initialize_secondary
336 #endif /* CONFIG_SMP */
340 * We depend on ET to be correct. This checks for 287/387.
343 movb $0,X86_HARD_MATH
349 movl %cr0,%eax /* no coprocessor: have to set bits */
350 xorl $4,%eax /* set EM */
354 1: movb $1,X86_HARD_MATH
355 .byte 0xDB,0xE4 /* fsetpm for 287, ignored by 387 */
359 * Point the GDT at this CPU's PDA. On boot this will be
360 * cpu_gdt_table and boot_pda; for secondary CPUs, these will be
361 * that CPU's GDT and PDA.
364 /* get the PDA pointer */
367 /* slot the PDA address into the GDT */
368 mov cpu_gdt_descr+2, %ecx
369 mov %ax, (__KERNEL_PDA+0+2)(%ecx) /* base & 0x0000ffff */
371 mov %al, (__KERNEL_PDA+4+0)(%ecx) /* base & 0x00ff0000 */
372 mov %ah, (__KERNEL_PDA+4+3)(%ecx) /* base & 0xff000000 */
378 * sets up a idt with 256 entries pointing to
379 * ignore_int, interrupt gates. It doesn't actually load
380 * idt - that can be done only after paging has been enabled
381 * and the kernel moved to PAGE_OFFSET. Interrupts
382 * are enabled elsewhere, when we can be relatively
383 * sure everything is ok.
385 * Warning: %esi is live across this function.
389 movl $(__KERNEL_CS << 16),%eax
390 movw %dx,%ax /* selector = 0x0010 = cs */
391 movw $0x8E00,%dx /* interrupt gate - dpl=0, present */
402 .macro set_early_handler handler,trapno
404 movl $(__KERNEL_CS << 16),%eax
406 movw $0x8E00,%dx /* interrupt gate - dpl=0, present */
408 movl %eax,8*\trapno(%edi)
409 movl %edx,8*\trapno+4(%edi)
412 set_early_handler handler=early_divide_err,trapno=0
413 set_early_handler handler=early_illegal_opcode,trapno=6
414 set_early_handler handler=early_protection_fault,trapno=13
415 set_early_handler handler=early_page_fault,trapno=14
421 pushl $0 /* fake errcode */
424 early_illegal_opcode:
426 pushl $0 /* fake errcode */
429 early_protection_fault:
440 movl $(__KERNEL_DS),%eax
443 cmpl $2,early_recursion_flag
445 incl early_recursion_flag
448 pushl %edx /* trapno */
450 #ifdef CONFIG_EARLY_PRINTK
460 /* This is the default interrupt "handler" :-) */
470 movl $(__KERNEL_DS),%eax
473 cmpl $2,early_recursion_flag
475 incl early_recursion_flag
481 #ifdef CONFIG_EARLY_PRINTK
495 #ifdef CONFIG_PARAVIRT
498 movl $(init_thread_union+THREAD_SIZE),%esp
500 /* We take pains to preserve all the regs. */
505 /* paravirt.o is last in link, and that probe fn never returns */
506 pushl $__start_paravirtprobe
523 * Real beginning of normal "text" segment
531 .section ".bss.page_aligned","w"
532 ENTRY(swapper_pg_dir)
534 ENTRY(empty_zero_page)
538 * This starts the data section.
545 .long init_thread_union+THREAD_SIZE
550 early_recursion_flag:
554 .asciz "Unknown interrupt or fault at EIP %p %p %p\n"
557 .ascii "Int %d: CR2 %p err %p EIP %p CS %p flags %p\n"
558 .asciz "Stack: %p %p %p %p %p %p %p %p\n"
561 * The IDT and GDT 'descriptors' are a strange 48-bit object
562 * only used by the lidt and lgdt instructions. They are not
563 * like usual segment descriptors - they consist of a 16-bit
564 * segment size, and 32-bit linear address value:
567 .globl boot_gdt_descr
571 # early boot GDT descriptor (must use 1:1 address mapping)
572 .word 0 # 32 bit align gdt_desc.address
575 .long boot_gdt_table - __PAGE_OFFSET
577 .word 0 # 32-bit align idt_desc.address
579 .word IDT_ENTRIES*8-1 # idt contains 256 entries
582 # boot GDT descriptor (later on used by CPU#0):
583 .word 0 # 32 bit align gdt_desc.address
585 .word GDT_ENTRIES*8-1
589 * The boot_gdt_table must mirror the equivalent in setup.S and is
590 * used only for booting.
592 .align L1_CACHE_BYTES
593 ENTRY(boot_gdt_table)
594 .fill GDT_ENTRY_BOOT_CS,8,0
595 .quad 0x00cf9a000000ffff /* kernel 4GB code at 0x00000000 */
596 .quad 0x00cf92000000ffff /* kernel 4GB data at 0x00000000 */
599 * The Global Descriptor Table contains 28 quadwords, per-CPU.
601 .align L1_CACHE_BYTES
603 .quad 0x0000000000000000 /* NULL descriptor */
604 .quad 0x0000000000000000 /* 0x0b reserved */
605 .quad 0x0000000000000000 /* 0x13 reserved */
606 .quad 0x0000000000000000 /* 0x1b reserved */
607 .quad 0x0000000000000000 /* 0x20 unused */
608 .quad 0x0000000000000000 /* 0x28 unused */
609 .quad 0x0000000000000000 /* 0x33 TLS entry 1 */
610 .quad 0x0000000000000000 /* 0x3b TLS entry 2 */
611 .quad 0x0000000000000000 /* 0x43 TLS entry 3 */
612 .quad 0x0000000000000000 /* 0x4b reserved */
613 .quad 0x0000000000000000 /* 0x53 reserved */
614 .quad 0x0000000000000000 /* 0x5b reserved */
616 .quad 0x00cf9a000000ffff /* 0x60 kernel 4GB code at 0x00000000 */
617 .quad 0x00cf92000000ffff /* 0x68 kernel 4GB data at 0x00000000 */
618 .quad 0x00cffa000000ffff /* 0x73 user 4GB code at 0x00000000 */
619 .quad 0x00cff2000000ffff /* 0x7b user 4GB data at 0x00000000 */
621 .quad 0x0000000000000000 /* 0x80 TSS descriptor */
622 .quad 0x0000000000000000 /* 0x88 LDT descriptor */
625 * Segments used for calling PnP BIOS have byte granularity.
626 * They code segments and data segments have fixed 64k limits,
627 * the transfer segment sizes are set at run time.
629 .quad 0x00409a000000ffff /* 0x90 32-bit code */
630 .quad 0x00009a000000ffff /* 0x98 16-bit code */
631 .quad 0x000092000000ffff /* 0xa0 16-bit data */
632 .quad 0x0000920000000000 /* 0xa8 16-bit data */
633 .quad 0x0000920000000000 /* 0xb0 16-bit data */
636 * The APM segments have byte granularity and their bases
637 * are set at run time. All have 64k limits.
639 .quad 0x00409a000000ffff /* 0xb8 APM CS code */
640 .quad 0x00009a000000ffff /* 0xc0 APM CS 16 code (16 bit) */
641 .quad 0x004092000000ffff /* 0xc8 APM DS data */
643 .quad 0x00c0920000000000 /* 0xd0 - ESPFIX SS */
644 .quad 0x00cf92000000ffff /* 0xd8 - PDA */
645 .quad 0x0000000000000000 /* 0xe0 - unused */
646 .quad 0x0000000000000000 /* 0xe8 - unused */
647 .quad 0x0000000000000000 /* 0xf0 - unused */
648 .quad 0x0000000000000000 /* 0xf8 - GDT entry 31: double-fault TSS */