git.oblomov.eu Git - linux-2.6/blob - arch/i386/kernel/nmi.c

   1 /*
   2  *  linux/arch/i386/nmi.c
   3  *
   4  *  NMI watchdog support on APIC systems
   5  *
   6  *  Started by Ingo Molnar <mingo@redhat.com>
   7  *
   8  *  Fixes:
   9  *  Mikael Pettersson   : AMD K7 support for local APIC NMI watchdog.
  10  *  Mikael Pettersson   : Power Management for local APIC NMI watchdog.
  11  *  Mikael Pettersson   : Pentium 4 support for local APIC NMI watchdog.
  12  *  Pavel Machek and
  13  *  Mikael Pettersson   : PM converted to driver model. Disable/enable API.
  14  */
  15
  16 #include <linux/delay.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/module.h>
  19 #include <linux/nmi.h>
  20 #include <linux/sysdev.h>
  21 #include <linux/sysctl.h>
  22 #include <linux/percpu.h>
  23 #include <linux/dmi.h>
  24 #include <linux/kprobes.h>
  25 #include <linux/cpumask.h>
  26 #include <linux/kernel_stat.h>
  27
  28 #include <asm/smp.h>
  29 #include <asm/nmi.h>
  30 #include <asm/kdebug.h>
  31 #include <asm/intel_arch_perfmon.h>
  32
  33 #include "mach_traps.h"
  34
  35 int unknown_nmi_panic;
  36 int nmi_watchdog_enabled;
  37
  38 /* perfctr_nmi_owner tracks the ownership of the perfctr registers:
  39  * evtsel_nmi_owner tracks the ownership of the event selection
  40  * - different performance counters/ event selection may be reserved for
  41  *   different subsystems this reservation system just tries to coordinate
  42  *   things a little
  43  */
  44
  45 /* this number is calculated from Intel's MSR_P4_CRU_ESCR5 register and it's
  46  * offset from MSR_P4_BSU_ESCR0.  It will be the max for all platforms (for now)
  47  */
  48 #define NMI_MAX_COUNTER_BITS 66
  49 #define NMI_MAX_COUNTER_LONGS BITS_TO_LONGS(NMI_MAX_COUNTER_BITS)
  50
  51 static DEFINE_PER_CPU(unsigned long, perfctr_nmi_owner[NMI_MAX_COUNTER_LONGS]);
  52 static DEFINE_PER_CPU(unsigned long, evntsel_nmi_owner[NMI_MAX_COUNTER_LONGS]);
  53
  54 static cpumask_t backtrace_mask = CPU_MASK_NONE;
  55 /* nmi_active:
  56  * >0: the lapic NMI watchdog is active, but can be disabled
  57  * <0: the lapic NMI watchdog has not been set up, and cannot
  58  *     be enabled
  59  *  0: the lapic NMI watchdog is disabled, but can be enabled
  60  */
  61 atomic_t nmi_active = ATOMIC_INIT(0);           /* oprofile uses this */
  62
  63 unsigned int nmi_watchdog = NMI_DEFAULT;
  64 static unsigned int nmi_hz = HZ;
  65
  66 struct nmi_watchdog_ctlblk {
  67         int enabled;
  68         u64 check_bit;
  69         unsigned int cccr_msr;
  70         unsigned int perfctr_msr;  /* the MSR to reset in NMI handler */
  71         unsigned int evntsel_msr;  /* the MSR to select the events to handle */
  72 };
  73 static DEFINE_PER_CPU(struct nmi_watchdog_ctlblk, nmi_watchdog_ctlblk);
  74
  75 /* local prototypes */
  76 static int unknown_nmi_panic_callback(struct pt_regs *regs, int cpu);
  77
  78 extern void show_registers(struct pt_regs *regs);
  79 extern int unknown_nmi_panic;
  80
  81 /* converts an msr to an appropriate reservation bit */
  82 static inline unsigned int nmi_perfctr_msr_to_bit(unsigned int msr)
  83 {
  84         /* returns the bit offset of the performance counter register */
  85         switch (boot_cpu_data.x86_vendor) {
  86         case X86_VENDOR_AMD:
  87                 return (msr - MSR_K7_PERFCTR0);
  88         case X86_VENDOR_INTEL:
  89                 if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON))
  90                         return (msr - MSR_ARCH_PERFMON_PERFCTR0);
  91
  92                 switch (boot_cpu_data.x86) {
  93                 case 6:
  94                         return (msr - MSR_P6_PERFCTR0);
  95                 case 15:
  96                         return (msr - MSR_P4_BPU_PERFCTR0);
  97                 }
  98         }
  99         return 0;
 100 }
 101
 102 /* converts an msr to an appropriate reservation bit */
 103 static inline unsigned int nmi_evntsel_msr_to_bit(unsigned int msr)
 104 {
 105         /* returns the bit offset of the event selection register */
 106         switch (boot_cpu_data.x86_vendor) {
 107         case X86_VENDOR_AMD:
 108                 return (msr - MSR_K7_EVNTSEL0);
 109         case X86_VENDOR_INTEL:
 110                 if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON))
 111                         return (msr - MSR_ARCH_PERFMON_EVENTSEL0);
 112
 113                 switch (boot_cpu_data.x86) {
 114                 case 6:
 115                         return (msr - MSR_P6_EVNTSEL0);
 116                 case 15:
 117                         return (msr - MSR_P4_BSU_ESCR0);
 118                 }
 119         }
 120         return 0;
 121 }
 122
 123 /* checks for a bit availability (hack for oprofile) */
 124 int avail_to_resrv_perfctr_nmi_bit(unsigned int counter)
 125 {
 126         int cpu;
 127         BUG_ON(counter > NMI_MAX_COUNTER_BITS);
 128         for_each_possible_cpu (cpu) {
 129                 if (test_bit(counter, &per_cpu(perfctr_nmi_owner, cpu)))
 130                         return 0;
 131         }
 132         return 1;
 133 }
 134
 135 /* checks the an msr for availability */
 136 int avail_to_resrv_perfctr_nmi(unsigned int msr)
 137 {
 138         unsigned int counter;
 139         int cpu;
 140
 141         counter = nmi_perfctr_msr_to_bit(msr);
 142         BUG_ON(counter > NMI_MAX_COUNTER_BITS);
 143
 144         for_each_possible_cpu (cpu) {
 145                 if (test_bit(counter, &per_cpu(perfctr_nmi_owner, cpu)))
 146                         return 0;
 147         }
 148         return 1;
 149 }
 150
 151 static int __reserve_perfctr_nmi(int cpu, unsigned int msr)
 152 {
 153         unsigned int counter;
 154         if (cpu < 0)
 155                 cpu = smp_processor_id();
 156
 157         counter = nmi_perfctr_msr_to_bit(msr);
 158         BUG_ON(counter > NMI_MAX_COUNTER_BITS);
 159
 160         if (!test_and_set_bit(counter, &per_cpu(perfctr_nmi_owner, cpu)))
 161                 return 1;
 162         return 0;
 163 }
 164
 165 static void __release_perfctr_nmi(int cpu, unsigned int msr)
 166 {
 167         unsigned int counter;
 168         if (cpu < 0)
 169                 cpu = smp_processor_id();
 170
 171         counter = nmi_perfctr_msr_to_bit(msr);
 172         BUG_ON(counter > NMI_MAX_COUNTER_BITS);
 173
 174         clear_bit(counter, &per_cpu(perfctr_nmi_owner, cpu));
 175 }
 176
 177 int reserve_perfctr_nmi(unsigned int msr)
 178 {
 179         int cpu, i;
 180         for_each_possible_cpu (cpu) {
 181                 if (!__reserve_perfctr_nmi(cpu, msr)) {
 182                         for_each_possible_cpu (i) {
 183                                 if (i >= cpu)
 184                                         break;
 185                                 __release_perfctr_nmi(i, msr);
 186                         }
 187                         return 0;
 188                 }
 189         }
 190         return 1;
 191 }
 192
 193 void release_perfctr_nmi(unsigned int msr)
 194 {
 195         int cpu;
 196         for_each_possible_cpu (cpu) {
 197                 __release_perfctr_nmi(cpu, msr);
 198         }
 199 }
 200
 201 int __reserve_evntsel_nmi(int cpu, unsigned int msr)
 202 {
 203         unsigned int counter;
 204         if (cpu < 0)
 205                 cpu = smp_processor_id();
 206
 207         counter = nmi_evntsel_msr_to_bit(msr);
 208         BUG_ON(counter > NMI_MAX_COUNTER_BITS);
 209
 210         if (!test_and_set_bit(counter, &per_cpu(evntsel_nmi_owner, cpu)[0]))
 211                 return 1;
 212         return 0;
 213 }
 214
 215 static void __release_evntsel_nmi(int cpu, unsigned int msr)
 216 {
 217         unsigned int counter;
 218         if (cpu < 0)
 219                 cpu = smp_processor_id();
 220
 221         counter = nmi_evntsel_msr_to_bit(msr);
 222         BUG_ON(counter > NMI_MAX_COUNTER_BITS);
 223
 224         clear_bit(counter, &per_cpu(evntsel_nmi_owner, cpu)[0]);
 225 }
 226
 227 int reserve_evntsel_nmi(unsigned int msr)
 228 {
 229         int cpu, i;
 230         for_each_possible_cpu (cpu) {
 231                 if (!__reserve_evntsel_nmi(cpu, msr)) {
 232                         for_each_possible_cpu (i) {
 233                                 if (i >= cpu)
 234                                         break;
 235                                 __release_evntsel_nmi(i, msr);
 236                         }
 237                         return 0;
 238                 }
 239         }
 240         return 1;
 241 }
 242
 243 void release_evntsel_nmi(unsigned int msr)
 244 {
 245         int cpu;
 246         for_each_possible_cpu (cpu) {
 247                 __release_evntsel_nmi(cpu, msr);
 248         }
 249 }
 250
 251 static __cpuinit inline int nmi_known_cpu(void)
 252 {
 253         switch (boot_cpu_data.x86_vendor) {
 254         case X86_VENDOR_AMD:
 255                 return ((boot_cpu_data.x86 == 15) || (boot_cpu_data.x86 == 6)
 256                         || (boot_cpu_data.x86 == 16));
 257         case X86_VENDOR_INTEL:
 258                 if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON))
 259                         return 1;
 260                 else
 261                         return ((boot_cpu_data.x86 == 15) || (boot_cpu_data.x86 == 6));
 262         }
 263         return 0;
 264 }
 265
 266 static int endflag __initdata = 0;
 267
 268 #ifdef CONFIG_SMP
 269 /* The performance counters used by NMI_LOCAL_APIC don't trigger when
 270  * the CPU is idle. To make sure the NMI watchdog really ticks on all
 271  * CPUs during the test make them busy.
 272  */
 273 static __init void nmi_cpu_busy(void *data)
 274 {
 275         local_irq_enable_in_hardirq();
 276         /* Intentionally don't use cpu_relax here. This is
 277            to make sure that the performance counter really ticks,
 278            even if there is a simulator or similar that catches the
 279            pause instruction. On a real HT machine this is fine because
 280            all other CPUs are busy with "useless" delay loops and don't
 281            care if they get somewhat less cycles. */
 282         while (endflag == 0)
 283                 mb();
 284 }
 285 #endif
 286
 287 static unsigned int adjust_for_32bit_ctr(unsigned int hz)
 288 {
 289         u64 counter_val;
 290         unsigned int retval = hz;
 291
 292         /*
 293          * On Intel CPUs with P6/ARCH_PERFMON only 32 bits in the counter
 294          * are writable, with higher bits sign extending from bit 31.
 295          * So, we can only program the counter with 31 bit values and
 296          * 32nd bit should be 1, for 33.. to be 1.
 297          * Find the appropriate nmi_hz
 298          */
 299         counter_val = (u64)cpu_khz * 1000;
 300         do_div(counter_val, retval);
 301         if (counter_val > 0x7fffffffULL) {
 302                 u64 count = (u64)cpu_khz * 1000;
 303                 do_div(count, 0x7fffffffUL);
 304                 retval = count + 1;
 305         }
 306         return retval;
 307 }
 308
 309 static int __init check_nmi_watchdog(void)
 310 {
 311         unsigned int *prev_nmi_count;
 312         int cpu;
 313
 314         if ((nmi_watchdog == NMI_NONE) || (nmi_watchdog == NMI_DEFAULT))
 315                 return 0;
 316
 317         if (!atomic_read(&nmi_active))
 318                 return 0;
 319
 320         prev_nmi_count = kmalloc(NR_CPUS * sizeof(int), GFP_KERNEL);
 321         if (!prev_nmi_count)
 322                 return -1;
 323
 324         printk(KERN_INFO "Testing NMI watchdog ... ");
 325
 326         if (nmi_watchdog == NMI_LOCAL_APIC)
 327                 smp_call_function(nmi_cpu_busy, (void *)&endflag, 0, 0);
 328
 329         for_each_possible_cpu(cpu)
 330                 prev_nmi_count[cpu] = per_cpu(irq_stat, cpu).__nmi_count;
 331         local_irq_enable();
 332         mdelay((20*1000)/nmi_hz); // wait 20 ticks
 333
 334         for_each_possible_cpu(cpu) {
 335 #ifdef CONFIG_SMP
 336                 /* Check cpu_callin_map here because that is set
 337                    after the timer is started. */
 338                 if (!cpu_isset(cpu, cpu_callin_map))
 339                         continue;
 340 #endif
 341                 if (!per_cpu(nmi_watchdog_ctlblk, cpu).enabled)
 342                         continue;
 343                 if (nmi_count(cpu) - prev_nmi_count[cpu] <= 5) {
 344                         printk("CPU#%d: NMI appears to be stuck (%d->%d)!\n",
 345                                 cpu,
 346                                 prev_nmi_count[cpu],
 347                                 nmi_count(cpu));
 348                         per_cpu(nmi_watchdog_ctlblk, cpu).enabled = 0;
 349                         atomic_dec(&nmi_active);
 350                 }
 351         }
 352         if (!atomic_read(&nmi_active)) {
 353                 kfree(prev_nmi_count);
 354                 atomic_set(&nmi_active, -1);
 355                 return -1;
 356         }
 357         endflag = 1;
 358         printk("OK.\n");
 359
 360         /* now that we know it works we can reduce NMI frequency to
 361            something more reasonable; makes a difference in some configs */
 362         if (nmi_watchdog == NMI_LOCAL_APIC) {
 363                 struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 364
 365                 nmi_hz = 1;
 366
 367                 if (wd->perfctr_msr == MSR_P6_PERFCTR0 ||
 368                     wd->perfctr_msr == MSR_ARCH_PERFMON_PERFCTR0) {
 369                         nmi_hz = adjust_for_32bit_ctr(nmi_hz);
 370                 }
 371         }
 372
 373         kfree(prev_nmi_count);
 374         return 0;
 375 }
 376 /* This needs to happen later in boot so counters are working */
 377 late_initcall(check_nmi_watchdog);
 378
 379 static int __init setup_nmi_watchdog(char *str)
 380 {
 381         int nmi;
 382
 383         get_option(&str, &nmi);
 384
 385         if ((nmi >= NMI_INVALID) || (nmi < NMI_NONE))
 386                 return 0;
 387
 388         nmi_watchdog = nmi;
 389         return 1;
 390 }
 391
 392 __setup("nmi_watchdog=", setup_nmi_watchdog);
 393
 394 static void disable_lapic_nmi_watchdog(void)
 395 {
 396         BUG_ON(nmi_watchdog != NMI_LOCAL_APIC);
 397
 398         if (atomic_read(&nmi_active) <= 0)
 399                 return;
 400
 401         on_each_cpu(stop_apic_nmi_watchdog, NULL, 0, 1);
 402
 403         BUG_ON(atomic_read(&nmi_active) != 0);
 404 }
 405
 406 static void enable_lapic_nmi_watchdog(void)
 407 {
 408         BUG_ON(nmi_watchdog != NMI_LOCAL_APIC);
 409
 410         /* are we already enabled */
 411         if (atomic_read(&nmi_active) != 0)
 412                 return;
 413
 414         /* are we lapic aware */
 415         if (nmi_known_cpu() <= 0)
 416                 return;
 417
 418         on_each_cpu(setup_apic_nmi_watchdog, NULL, 0, 1);
 419         touch_nmi_watchdog();
 420 }
 421
 422 void disable_timer_nmi_watchdog(void)
 423 {
 424         BUG_ON(nmi_watchdog != NMI_IO_APIC);
 425
 426         if (atomic_read(&nmi_active) <= 0)
 427                 return;
 428
 429         disable_irq(0);
 430         on_each_cpu(stop_apic_nmi_watchdog, NULL, 0, 1);
 431
 432         BUG_ON(atomic_read(&nmi_active) != 0);
 433 }
 434
 435 void enable_timer_nmi_watchdog(void)
 436 {
 437         BUG_ON(nmi_watchdog != NMI_IO_APIC);
 438
 439         if (atomic_read(&nmi_active) == 0) {
 440                 touch_nmi_watchdog();
 441                 on_each_cpu(setup_apic_nmi_watchdog, NULL, 0, 1);
 442                 enable_irq(0);
 443         }
 444 }
 445
 446 static void __acpi_nmi_disable(void *__unused)
 447 {
 448         apic_write_around(APIC_LVT0, APIC_DM_NMI | APIC_LVT_MASKED);
 449 }
 450
 451 /*
 452  * Disable timer based NMIs on all CPUs:
 453  */
 454 void acpi_nmi_disable(void)
 455 {
 456         if (atomic_read(&nmi_active) && nmi_watchdog == NMI_IO_APIC)
 457                 on_each_cpu(__acpi_nmi_disable, NULL, 0, 1);
 458 }
 459
 460 static void __acpi_nmi_enable(void *__unused)
 461 {
 462         apic_write_around(APIC_LVT0, APIC_DM_NMI);
 463 }
 464
 465 /*
 466  * Enable timer based NMIs on all CPUs:
 467  */
 468 void acpi_nmi_enable(void)
 469 {
 470         if (atomic_read(&nmi_active) && nmi_watchdog == NMI_IO_APIC)
 471                 on_each_cpu(__acpi_nmi_enable, NULL, 0, 1);
 472 }
 473
 474 #ifdef CONFIG_PM
 475
 476 static int nmi_pm_active; /* nmi_active before suspend */
 477
 478 static int lapic_nmi_suspend(struct sys_device *dev, pm_message_t state)
 479 {
 480         /* only CPU0 goes here, other CPUs should be offline */
 481         nmi_pm_active = atomic_read(&nmi_active);
 482         stop_apic_nmi_watchdog(NULL);
 483         BUG_ON(atomic_read(&nmi_active) != 0);
 484         return 0;
 485 }
 486
 487 static int lapic_nmi_resume(struct sys_device *dev)
 488 {
 489         /* only CPU0 goes here, other CPUs should be offline */
 490         if (nmi_pm_active > 0) {
 491                 setup_apic_nmi_watchdog(NULL);
 492                 touch_nmi_watchdog();
 493         }
 494         return 0;
 495 }
 496
 497
 498 static struct sysdev_class nmi_sysclass = {
 499         set_kset_name("lapic_nmi"),
 500         .resume         = lapic_nmi_resume,
 501         .suspend        = lapic_nmi_suspend,
 502 };
 503
 504 static struct sys_device device_lapic_nmi = {
 505         .id     = 0,
 506         .cls    = &nmi_sysclass,
 507 };
 508
 509 static int __init init_lapic_nmi_sysfs(void)
 510 {
 511         int error;
 512
 513         /* should really be a BUG_ON but b/c this is an
 514          * init call, it just doesn't work.  -dcz
 515          */
 516         if (nmi_watchdog != NMI_LOCAL_APIC)
 517                 return 0;
 518
 519         if ( atomic_read(&nmi_active) < 0 )
 520                 return 0;
 521
 522         error = sysdev_class_register(&nmi_sysclass);
 523         if (!error)
 524                 error = sysdev_register(&device_lapic_nmi);
 525         return error;
 526 }
 527 /* must come after the local APIC's device_initcall() */
 528 late_initcall(init_lapic_nmi_sysfs);
 529
 530 #endif  /* CONFIG_PM */
 531
 532 /*
 533  * Activate the NMI watchdog via the local APIC.
 534  * Original code written by Keith Owens.
 535  */
 536
 537 static void write_watchdog_counter(unsigned int perfctr_msr, const char *descr)
 538 {
 539         u64 count = (u64)cpu_khz * 1000;
 540
 541         do_div(count, nmi_hz);
 542         if(descr)
 543                 Dprintk("setting %s to -0x%08Lx\n", descr, count);
 544         wrmsrl(perfctr_msr, 0 - count);
 545 }
 546
 547 static void write_watchdog_counter32(unsigned int perfctr_msr,
 548                 const char *descr)
 549 {
 550         u64 count = (u64)cpu_khz * 1000;
 551
 552         do_div(count, nmi_hz);
 553         if(descr)
 554                 Dprintk("setting %s to -0x%08Lx\n", descr, count);
 555         wrmsr(perfctr_msr, (u32)(-count), 0);
 556 }
 557
 558 /* Note that these events don't tick when the CPU idles. This means
 559    the frequency varies with CPU load. */
 560
 561 #define K7_EVNTSEL_ENABLE       (1 << 22)
 562 #define K7_EVNTSEL_INT          (1 << 20)
 563 #define K7_EVNTSEL_OS           (1 << 17)
 564 #define K7_EVNTSEL_USR          (1 << 16)
 565 #define K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING    0x76
 566 #define K7_NMI_EVENT            K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING
 567
 568 static int setup_k7_watchdog(void)
 569 {
 570         unsigned int perfctr_msr, evntsel_msr;
 571         unsigned int evntsel;
 572         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 573
 574         perfctr_msr = MSR_K7_PERFCTR0;
 575         evntsel_msr = MSR_K7_EVNTSEL0;
 576         if (!__reserve_perfctr_nmi(-1, perfctr_msr))
 577                 goto fail;
 578
 579         if (!__reserve_evntsel_nmi(-1, evntsel_msr))
 580                 goto fail1;
 581
 582         wrmsrl(perfctr_msr, 0UL);
 583
 584         evntsel = K7_EVNTSEL_INT
 585                 | K7_EVNTSEL_OS
 586                 | K7_EVNTSEL_USR
 587                 | K7_NMI_EVENT;
 588
 589         /* setup the timer */
 590         wrmsr(evntsel_msr, evntsel, 0);
 591         write_watchdog_counter(perfctr_msr, "K7_PERFCTR0");
 592         apic_write(APIC_LVTPC, APIC_DM_NMI);
 593         evntsel |= K7_EVNTSEL_ENABLE;
 594         wrmsr(evntsel_msr, evntsel, 0);
 595
 596         wd->perfctr_msr = perfctr_msr;
 597         wd->evntsel_msr = evntsel_msr;
 598         wd->cccr_msr = 0;  //unused
 599         wd->check_bit = 1ULL<<63;
 600         return 1;
 601 fail1:
 602         __release_perfctr_nmi(-1, perfctr_msr);
 603 fail:
 604         return 0;
 605 }
 606
 607 static void stop_k7_watchdog(void)
 608 {
 609         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 610
 611         wrmsr(wd->evntsel_msr, 0, 0);
 612
 613         __release_evntsel_nmi(-1, wd->evntsel_msr);
 614         __release_perfctr_nmi(-1, wd->perfctr_msr);
 615 }
 616
 617 #define P6_EVNTSEL0_ENABLE      (1 << 22)
 618 #define P6_EVNTSEL_INT          (1 << 20)
 619 #define P6_EVNTSEL_OS           (1 << 17)
 620 #define P6_EVNTSEL_USR          (1 << 16)
 621 #define P6_EVENT_CPU_CLOCKS_NOT_HALTED  0x79
 622 #define P6_NMI_EVENT            P6_EVENT_CPU_CLOCKS_NOT_HALTED
 623
 624 static int setup_p6_watchdog(void)
 625 {
 626         unsigned int perfctr_msr, evntsel_msr;
 627         unsigned int evntsel;
 628         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 629
 630         perfctr_msr = MSR_P6_PERFCTR0;
 631         evntsel_msr = MSR_P6_EVNTSEL0;
 632         if (!__reserve_perfctr_nmi(-1, perfctr_msr))
 633                 goto fail;
 634
 635         if (!__reserve_evntsel_nmi(-1, evntsel_msr))
 636                 goto fail1;
 637
 638         wrmsrl(perfctr_msr, 0UL);
 639
 640         evntsel = P6_EVNTSEL_INT
 641                 | P6_EVNTSEL_OS
 642                 | P6_EVNTSEL_USR
 643                 | P6_NMI_EVENT;
 644
 645         /* setup the timer */
 646         wrmsr(evntsel_msr, evntsel, 0);
 647         nmi_hz = adjust_for_32bit_ctr(nmi_hz);
 648         write_watchdog_counter32(perfctr_msr, "P6_PERFCTR0");
 649         apic_write(APIC_LVTPC, APIC_DM_NMI);
 650         evntsel |= P6_EVNTSEL0_ENABLE;
 651         wrmsr(evntsel_msr, evntsel, 0);
 652
 653         wd->perfctr_msr = perfctr_msr;
 654         wd->evntsel_msr = evntsel_msr;
 655         wd->cccr_msr = 0;  //unused
 656         wd->check_bit = 1ULL<<39;
 657         return 1;
 658 fail1:
 659         __release_perfctr_nmi(-1, perfctr_msr);
 660 fail:
 661         return 0;
 662 }
 663
 664 static void stop_p6_watchdog(void)
 665 {
 666         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 667
 668         wrmsr(wd->evntsel_msr, 0, 0);
 669
 670         __release_evntsel_nmi(-1, wd->evntsel_msr);
 671         __release_perfctr_nmi(-1, wd->perfctr_msr);
 672 }
 673
 674 /* Note that these events don't tick when the CPU idles. This means
 675    the frequency varies with CPU load. */
 676
 677 #define MSR_P4_MISC_ENABLE_PERF_AVAIL   (1<<7)
 678 #define P4_ESCR_EVENT_SELECT(N) ((N)<<25)
 679 #define P4_ESCR_OS              (1<<3)
 680 #define P4_ESCR_USR             (1<<2)
 681 #define P4_CCCR_OVF_PMI0        (1<<26)
 682 #define P4_CCCR_OVF_PMI1        (1<<27)
 683 #define P4_CCCR_THRESHOLD(N)    ((N)<<20)
 684 #define P4_CCCR_COMPLEMENT      (1<<19)
 685 #define P4_CCCR_COMPARE         (1<<18)
 686 #define P4_CCCR_REQUIRED        (3<<16)
 687 #define P4_CCCR_ESCR_SELECT(N)  ((N)<<13)
 688 #define P4_CCCR_ENABLE          (1<<12)
 689 #define P4_CCCR_OVF             (1<<31)
 690 /* Set up IQ_COUNTER0 to behave like a clock, by having IQ_CCCR0 filter
 691    CRU_ESCR0 (with any non-null event selector) through a complemented
 692    max threshold. [IA32-Vol3, Section 14.9.9] */
 693
 694 static int setup_p4_watchdog(void)
 695 {
 696         unsigned int perfctr_msr, evntsel_msr, cccr_msr;
 697         unsigned int evntsel, cccr_val;
 698         unsigned int misc_enable, dummy;
 699         unsigned int ht_num;
 700         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 701
 702         rdmsr(MSR_IA32_MISC_ENABLE, misc_enable, dummy);
 703         if (!(misc_enable & MSR_P4_MISC_ENABLE_PERF_AVAIL))
 704                 return 0;
 705
 706 #ifdef CONFIG_SMP
 707         /* detect which hyperthread we are on */
 708         if (smp_num_siblings == 2) {
 709                 unsigned int ebx, apicid;
 710
 711                 ebx = cpuid_ebx(1);
 712                 apicid = (ebx >> 24) & 0xff;
 713                 ht_num = apicid & 1;
 714         } else
 715 #endif
 716                 ht_num = 0;
 717
 718         /* performance counters are shared resources
 719          * assign each hyperthread its own set
 720          * (re-use the ESCR0 register, seems safe
 721          * and keeps the cccr_val the same)
 722          */
 723         if (!ht_num) {
 724                 /* logical cpu 0 */
 725                 perfctr_msr = MSR_P4_IQ_PERFCTR0;
 726                 evntsel_msr = MSR_P4_CRU_ESCR0;
 727                 cccr_msr = MSR_P4_IQ_CCCR0;
 728                 cccr_val = P4_CCCR_OVF_PMI0 | P4_CCCR_ESCR_SELECT(4);
 729         } else {
 730                 /* logical cpu 1 */
 731                 perfctr_msr = MSR_P4_IQ_PERFCTR1;
 732                 evntsel_msr = MSR_P4_CRU_ESCR0;
 733                 cccr_msr = MSR_P4_IQ_CCCR1;
 734                 cccr_val = P4_CCCR_OVF_PMI1 | P4_CCCR_ESCR_SELECT(4);
 735         }
 736
 737         if (!__reserve_perfctr_nmi(-1, perfctr_msr))
 738                 goto fail;
 739
 740         if (!__reserve_evntsel_nmi(-1, evntsel_msr))
 741                 goto fail1;
 742
 743         evntsel = P4_ESCR_EVENT_SELECT(0x3F)
 744                 | P4_ESCR_OS
 745                 | P4_ESCR_USR;
 746
 747         cccr_val |= P4_CCCR_THRESHOLD(15)
 748                  | P4_CCCR_COMPLEMENT
 749                  | P4_CCCR_COMPARE
 750                  | P4_CCCR_REQUIRED;
 751
 752         wrmsr(evntsel_msr, evntsel, 0);
 753         wrmsr(cccr_msr, cccr_val, 0);
 754         write_watchdog_counter(perfctr_msr, "P4_IQ_COUNTER0");
 755         apic_write(APIC_LVTPC, APIC_DM_NMI);
 756         cccr_val |= P4_CCCR_ENABLE;
 757         wrmsr(cccr_msr, cccr_val, 0);
 758         wd->perfctr_msr = perfctr_msr;
 759         wd->evntsel_msr = evntsel_msr;
 760         wd->cccr_msr = cccr_msr;
 761         wd->check_bit = 1ULL<<39;
 762         return 1;
 763 fail1:
 764         __release_perfctr_nmi(-1, perfctr_msr);
 765 fail:
 766         return 0;
 767 }
 768
 769 static void stop_p4_watchdog(void)
 770 {
 771         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 772
 773         wrmsr(wd->cccr_msr, 0, 0);
 774         wrmsr(wd->evntsel_msr, 0, 0);
 775
 776         __release_evntsel_nmi(-1, wd->evntsel_msr);
 777         __release_perfctr_nmi(-1, wd->perfctr_msr);
 778 }
 779
 780 #define ARCH_PERFMON_NMI_EVENT_SEL      ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL
 781 #define ARCH_PERFMON_NMI_EVENT_UMASK    ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK
 782
 783 static int setup_intel_arch_watchdog(void)
 784 {
 785         unsigned int ebx;
 786         union cpuid10_eax eax;
 787         unsigned int unused;
 788         unsigned int perfctr_msr, evntsel_msr;
 789         unsigned int evntsel;
 790         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 791
 792         /*
 793          * Check whether the Architectural PerfMon supports
 794          * Unhalted Core Cycles Event or not.
 795          * NOTE: Corresponding bit = 0 in ebx indicates event present.
 796          */
 797         cpuid(10, &(eax.full), &ebx, &unused, &unused);
 798         if ((eax.split.mask_length < (ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX+1)) ||
 799             (ebx & ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT))
 800                 goto fail;
 801
 802         perfctr_msr = MSR_ARCH_PERFMON_PERFCTR0;
 803         evntsel_msr = MSR_ARCH_PERFMON_EVENTSEL0;
 804
 805         if (!__reserve_perfctr_nmi(-1, perfctr_msr))
 806                 goto fail;
 807
 808         if (!__reserve_evntsel_nmi(-1, evntsel_msr))
 809                 goto fail1;
 810
 811         wrmsrl(perfctr_msr, 0UL);
 812
 813         evntsel = ARCH_PERFMON_EVENTSEL_INT
 814                 | ARCH_PERFMON_EVENTSEL_OS
 815                 | ARCH_PERFMON_EVENTSEL_USR
 816                 | ARCH_PERFMON_NMI_EVENT_SEL
 817                 | ARCH_PERFMON_NMI_EVENT_UMASK;
 818
 819         /* setup the timer */
 820         wrmsr(evntsel_msr, evntsel, 0);
 821         nmi_hz = adjust_for_32bit_ctr(nmi_hz);
 822         write_watchdog_counter32(perfctr_msr, "INTEL_ARCH_PERFCTR0");
 823         apic_write(APIC_LVTPC, APIC_DM_NMI);
 824         evntsel |= ARCH_PERFMON_EVENTSEL0_ENABLE;
 825         wrmsr(evntsel_msr, evntsel, 0);
 826
 827         wd->perfctr_msr = perfctr_msr;
 828         wd->evntsel_msr = evntsel_msr;
 829         wd->cccr_msr = 0;  //unused
 830         wd->check_bit = 1ULL << (eax.split.bit_width - 1);
 831         return 1;
 832 fail1:
 833         __release_perfctr_nmi(-1, perfctr_msr);
 834 fail:
 835         return 0;
 836 }
 837
 838 static void stop_intel_arch_watchdog(void)
 839 {
 840         unsigned int ebx;
 841         union cpuid10_eax eax;
 842         unsigned int unused;
 843         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 844
 845         /*
 846          * Check whether the Architectural PerfMon supports
 847          * Unhalted Core Cycles Event or not.
 848          * NOTE: Corresponding bit = 0 in ebx indicates event present.
 849          */
 850         cpuid(10, &(eax.full), &ebx, &unused, &unused);
 851         if ((eax.split.mask_length < (ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX+1)) ||
 852             (ebx & ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT))
 853                 return;
 854
 855         wrmsr(wd->evntsel_msr, 0, 0);
 856         __release_evntsel_nmi(-1, wd->evntsel_msr);
 857         __release_perfctr_nmi(-1, wd->perfctr_msr);
 858 }
 859
 860 void setup_apic_nmi_watchdog (void *unused)
 861 {
 862         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 863
 864         /* only support LOCAL and IO APICs for now */
 865         if ((nmi_watchdog != NMI_LOCAL_APIC) &&
 866             (nmi_watchdog != NMI_IO_APIC))
 867                 return;
 868
 869         if (wd->enabled == 1)
 870                 return;
 871
 872         /* cheap hack to support suspend/resume */
 873         /* if cpu0 is not active neither should the other cpus */
 874         if ((smp_processor_id() != 0) && (atomic_read(&nmi_active) <= 0))
 875                 return;
 876
 877         if (nmi_watchdog == NMI_LOCAL_APIC) {
 878                 switch (boot_cpu_data.x86_vendor) {
 879                 case X86_VENDOR_AMD:
 880                         if (boot_cpu_data.x86 != 6 && boot_cpu_data.x86 != 15 &&
 881                                 boot_cpu_data.x86 != 16)
 882                                 return;
 883                         if (!setup_k7_watchdog())
 884                                 return;
 885                         break;
 886                 case X86_VENDOR_INTEL:
 887                         if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
 888                                 if (!setup_intel_arch_watchdog())
 889                                         return;
 890                                 break;
 891                         }
 892                         switch (boot_cpu_data.x86) {
 893                         case 6:
 894                                 if (boot_cpu_data.x86_model > 0xd)
 895                                         return;
 896
 897                                 if (!setup_p6_watchdog())
 898                                         return;
 899                                 break;
 900                         case 15:
 901                                 if (boot_cpu_data.x86_model > 0x4)
 902                                         return;
 903
 904                                 if (!setup_p4_watchdog())
 905                                         return;
 906                                 break;
 907                         default:
 908                                 return;
 909                         }
 910                         break;
 911                 default:
 912                         return;
 913                 }
 914         }
 915         wd->enabled = 1;
 916         atomic_inc(&nmi_active);
 917 }
 918
 919 void stop_apic_nmi_watchdog(void *unused)
 920 {
 921         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 922
 923         /* only support LOCAL and IO APICs for now */
 924         if ((nmi_watchdog != NMI_LOCAL_APIC) &&
 925             (nmi_watchdog != NMI_IO_APIC))
 926                 return;
 927
 928         if (wd->enabled == 0)
 929                 return;
 930
 931         if (nmi_watchdog == NMI_LOCAL_APIC) {
 932                 switch (boot_cpu_data.x86_vendor) {
 933                 case X86_VENDOR_AMD:
 934                         stop_k7_watchdog();
 935                         break;
 936                 case X86_VENDOR_INTEL:
 937                         if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
 938                                 stop_intel_arch_watchdog();
 939                                 break;
 940                         }
 941                         switch (boot_cpu_data.x86) {
 942                         case 6:
 943                                 if (boot_cpu_data.x86_model > 0xd)
 944                                         break;
 945                                 stop_p6_watchdog();
 946                                 break;
 947                         case 15:
 948                                 if (boot_cpu_data.x86_model > 0x4)
 949                                         break;
 950                                 stop_p4_watchdog();
 951                                 break;
 952                         }
 953                         break;
 954                 default:
 955                         return;
 956                 }
 957         }
 958         wd->enabled = 0;
 959         atomic_dec(&nmi_active);
 960 }
 961
 962 /*
 963  * the best way to detect whether a CPU has a 'hard lockup' problem
 964  * is to check it's local APIC timer IRQ counts. If they are not
 965  * changing then that CPU has some problem.
 966  *
 967  * as these watchdog NMI IRQs are generated on every CPU, we only
 968  * have to check the current processor.
 969  *
 970  * since NMIs don't listen to _any_ locks, we have to be extremely
 971  * careful not to rely on unsafe variables. The printk might lock
 972  * up though, so we have to break up any console locks first ...
 973  * [when there will be more tty-related locks, break them up
 974  *  here too!]
 975  */
 976
 977 static unsigned int
 978         last_irq_sums [NR_CPUS],
 979         alert_counter [NR_CPUS];
 980
 981 void touch_nmi_watchdog (void)
 982 {
 983         if (nmi_watchdog > 0) {
 984                 unsigned cpu;
 985
 986                 /*
 987                  * Just reset the alert counters, (other CPUs might be
 988                  * spinning on locks we hold):
 989                  */
 990                 for_each_present_cpu (cpu)
 991                         alert_counter[cpu] = 0;
 992         }
 993
 994         /*
 995          * Tickle the softlockup detector too:
 996          */
 997         touch_softlockup_watchdog();
 998 }
 999 EXPORT_SYMBOL(touch_nmi_watchdog);
1000
1001 extern void die_nmi(struct pt_regs *, const char *msg);
1002
1003 __kprobes int nmi_watchdog_tick(struct pt_regs * regs, unsigned reason)
1004 {
1005
1006         /*
1007          * Since current_thread_info()-> is always on the stack, and we
1008          * always switch the stack NMI-atomically, it's safe to use
1009          * smp_processor_id().
1010          */
1011         unsigned int sum;
1012         int touched = 0;
1013         int cpu = smp_processor_id();
1014         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
1015         u64 dummy;
1016         int rc=0;
1017
1018         /* check for other users first */
1019         if (notify_die(DIE_NMI, "nmi", regs, reason, 2, SIGINT)
1020                         == NOTIFY_STOP) {
1021                 rc = 1;
1022                 touched = 1;
1023         }
1024
1025         if (cpu_isset(cpu, backtrace_mask)) {
1026                 static DEFINE_SPINLOCK(lock);   /* Serialise the printks */
1027
1028                 spin_lock(&lock);
1029                 printk("NMI backtrace for cpu %d\n", cpu);
1030                 dump_stack();
1031                 spin_unlock(&lock);
1032                 cpu_clear(cpu, backtrace_mask);
1033         }
1034
1035         /*
1036          * Take the local apic timer and PIT/HPET into account. We don't
1037          * know which one is active, when we have highres/dyntick on
1038          */
1039         sum = per_cpu(irq_stat, cpu).apic_timer_irqs + kstat_irqs(0);
1040
1041         /* if the none of the timers isn't firing, this cpu isn't doing much */
1042         if (!touched && last_irq_sums[cpu] == sum) {
1043                 /*
1044                  * Ayiee, looks like this CPU is stuck ...
1045                  * wait a few IRQs (5 seconds) before doing the oops ...
1046                  */
1047                 alert_counter[cpu]++;
1048                 if (alert_counter[cpu] == 5*nmi_hz)
1049                         /*
1050                          * die_nmi will return ONLY if NOTIFY_STOP happens..
1051                          */
1052                         die_nmi(regs, "BUG: NMI Watchdog detected LOCKUP");
1053         } else {
1054                 last_irq_sums[cpu] = sum;
1055                 alert_counter[cpu] = 0;
1056         }
1057         /* see if the nmi watchdog went off */
1058         if (wd->enabled) {
1059                 if (nmi_watchdog == NMI_LOCAL_APIC) {
1060                         rdmsrl(wd->perfctr_msr, dummy);
1061                         if (dummy & wd->check_bit){
1062                                 /* this wasn't a watchdog timer interrupt */
1063                                 goto done;
1064                         }
1065
1066                         /* only Intel P4 uses the cccr msr */
1067                         if (wd->cccr_msr != 0) {
1068                                 /*
1069                                  * P4 quirks:
1070                                  * - An overflown perfctr will assert its interrupt
1071                                  *   until the OVF flag in its CCCR is cleared.
1072                                  * - LVTPC is masked on interrupt and must be
1073                                  *   unmasked by the LVTPC handler.
1074                                  */
1075                                 rdmsrl(wd->cccr_msr, dummy);
1076                                 dummy &= ~P4_CCCR_OVF;
1077                                 wrmsrl(wd->cccr_msr, dummy);
1078                                 apic_write(APIC_LVTPC, APIC_DM_NMI);
1079                                 /* start the cycle over again */
1080                                 write_watchdog_counter(wd->perfctr_msr, NULL);
1081                         }
1082                         else if (wd->perfctr_msr == MSR_P6_PERFCTR0 ||
1083                                  wd->perfctr_msr == MSR_ARCH_PERFMON_PERFCTR0) {
1084                                 /* P6 based Pentium M need to re-unmask
1085                                  * the apic vector but it doesn't hurt
1086                                  * other P6 variant.
1087                                  * ArchPerfom/Core Duo also needs this */
1088                                 apic_write(APIC_LVTPC, APIC_DM_NMI);
1089                                 /* P6/ARCH_PERFMON has 32 bit counter write */
1090                                 write_watchdog_counter32(wd->perfctr_msr, NULL);
1091                         } else {
1092                                 /* start the cycle over again */
1093                                 write_watchdog_counter(wd->perfctr_msr, NULL);
1094                         }
1095                         rc = 1;
1096                 } else if (nmi_watchdog == NMI_IO_APIC) {
1097                         /* don't know how to accurately check for this.
1098                          * just assume it was a watchdog timer interrupt
1099                          * This matches the old behaviour.
1100                          */
1101                         rc = 1;
1102                 }
1103         }
1104 done:
1105         return rc;
1106 }
1107
1108 int do_nmi_callback(struct pt_regs * regs, int cpu)
1109 {
1110 #ifdef CONFIG_SYSCTL
1111         if (unknown_nmi_panic)
1112                 return unknown_nmi_panic_callback(regs, cpu);
1113 #endif
1114         return 0;
1115 }
1116
1117 #ifdef CONFIG_SYSCTL
1118
1119 static int unknown_nmi_panic_callback(struct pt_regs *regs, int cpu)
1120 {
1121         unsigned char reason = get_nmi_reason();
1122         char buf[64];
1123
1124         sprintf(buf, "NMI received for unknown reason %02x\n", reason);
1125         die_nmi(regs, buf);
1126         return 0;
1127 }
1128
1129 /*
1130  * proc handler for /proc/sys/kernel/nmi
1131  */
1132 int proc_nmi_enabled(struct ctl_table *table, int write, struct file *file,
1133                         void __user *buffer, size_t *length, loff_t *ppos)
1134 {
1135         int old_state;
1136
1137         nmi_watchdog_enabled = (atomic_read(&nmi_active) > 0) ? 1 : 0;
1138         old_state = nmi_watchdog_enabled;
1139         proc_dointvec(table, write, file, buffer, length, ppos);
1140         if (!!old_state == !!nmi_watchdog_enabled)
1141                 return 0;
1142
1143         if (atomic_read(&nmi_active) < 0) {
1144                 printk( KERN_WARNING "NMI watchdog is permanently disabled\n");
1145                 return -EIO;
1146         }
1147
1148         if (nmi_watchdog == NMI_DEFAULT) {
1149                 if (nmi_known_cpu() > 0)
1150                         nmi_watchdog = NMI_LOCAL_APIC;
1151                 else
1152                         nmi_watchdog = NMI_IO_APIC;
1153         }
1154
1155         if (nmi_watchdog == NMI_LOCAL_APIC) {
1156                 if (nmi_watchdog_enabled)
1157                         enable_lapic_nmi_watchdog();
1158                 else
1159                         disable_lapic_nmi_watchdog();
1160         } else {
1161                 printk( KERN_WARNING
1162                         "NMI watchdog doesn't know what hardware to touch\n");
1163                 return -EIO;
1164         }
1165         return 0;
1166 }
1167
1168 #endif
1169
1170 void __trigger_all_cpu_backtrace(void)
1171 {
1172         int i;
1173
1174         backtrace_mask = cpu_online_map;
1175         /* Wait for up to 10 seconds for all CPUs to do the backtrace */
1176         for (i = 0; i < 10 * 1000; i++) {
1177                 if (cpus_empty(backtrace_mask))
1178                         break;
1179                 mdelay(1);
1180         }
1181 }
1182
1183 EXPORT_SYMBOL(nmi_active);
1184 EXPORT_SYMBOL(nmi_watchdog);
1185 EXPORT_SYMBOL(avail_to_resrv_perfctr_nmi);
1186 EXPORT_SYMBOL(avail_to_resrv_perfctr_nmi_bit);
1187 EXPORT_SYMBOL(reserve_perfctr_nmi);
1188 EXPORT_SYMBOL(release_perfctr_nmi);
1189 EXPORT_SYMBOL(reserve_evntsel_nmi);
1190 EXPORT_SYMBOL(release_evntsel_nmi);
1191 EXPORT_SYMBOL(disable_timer_nmi_watchdog);
1192 EXPORT_SYMBOL(enable_timer_nmi_watchdog);