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   1 /* b44.c: Broadcom 44xx/47xx Fast Ethernet device driver.
   2  *
   3  * Copyright (C) 2002 David S. Miller (davem@redhat.com)
   4  * Copyright (C) 2004 Pekka Pietikainen (pp@ee.oulu.fi)
   5  * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
   6  * Copyright (C) 2006 Felix Fietkau (nbd@openwrt.org)
   7  * Copyright (C) 2006 Broadcom Corporation.
   8  * Copyright (C) 2007 Michael Buesch <mb@bu3sch.de>
   9  *
  10  * Distribute under GPL.
  11  */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/module.h>
  15 #include <linux/moduleparam.h>
  16 #include <linux/types.h>
  17 #include <linux/netdevice.h>
  18 #include <linux/ethtool.h>
  19 #include <linux/mii.h>
  20 #include <linux/if_ether.h>
  21 #include <linux/if_vlan.h>
  22 #include <linux/etherdevice.h>
  23 #include <linux/pci.h>
  24 #include <linux/delay.h>
  25 #include <linux/init.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/ssb/ssb.h>
  28
  29 #include <asm/uaccess.h>
  30 #include <asm/io.h>
  31 #include <asm/irq.h>
  32
  33
  34 #include "b44.h"
  35
  36 #define DRV_MODULE_NAME         "b44"
  37 #define PFX DRV_MODULE_NAME     ": "
  38 #define DRV_MODULE_VERSION      "2.0"
  39
  40 #define B44_DEF_MSG_ENABLE        \
  41         (NETIF_MSG_DRV          | \
  42          NETIF_MSG_PROBE        | \
  43          NETIF_MSG_LINK         | \
  44          NETIF_MSG_TIMER        | \
  45          NETIF_MSG_IFDOWN       | \
  46          NETIF_MSG_IFUP         | \
  47          NETIF_MSG_RX_ERR       | \
  48          NETIF_MSG_TX_ERR)
  49
  50 /* length of time before we decide the hardware is borked,
  51  * and dev->tx_timeout() should be called to fix the problem
  52  */
  53 #define B44_TX_TIMEOUT                  (5 * HZ)
  54
  55 /* hardware minimum and maximum for a single frame's data payload */
  56 #define B44_MIN_MTU                     60
  57 #define B44_MAX_MTU                     1500
  58
  59 #define B44_RX_RING_SIZE                512
  60 #define B44_DEF_RX_RING_PENDING         200
  61 #define B44_RX_RING_BYTES       (sizeof(struct dma_desc) * \
  62                                  B44_RX_RING_SIZE)
  63 #define B44_TX_RING_SIZE                512
  64 #define B44_DEF_TX_RING_PENDING         (B44_TX_RING_SIZE - 1)
  65 #define B44_TX_RING_BYTES       (sizeof(struct dma_desc) * \
  66                                  B44_TX_RING_SIZE)
  67
  68 #define TX_RING_GAP(BP) \
  69         (B44_TX_RING_SIZE - (BP)->tx_pending)
  70 #define TX_BUFFS_AVAIL(BP)                                              \
  71         (((BP)->tx_cons <= (BP)->tx_prod) ?                             \
  72           (BP)->tx_cons + (BP)->tx_pending - (BP)->tx_prod :            \
  73           (BP)->tx_cons - (BP)->tx_prod - TX_RING_GAP(BP))
  74 #define NEXT_TX(N)              (((N) + 1) & (B44_TX_RING_SIZE - 1))
  75
  76 #define RX_PKT_OFFSET           30
  77 #define RX_PKT_BUF_SZ           (1536 + RX_PKT_OFFSET + 64)
  78
  79 /* minimum number of free TX descriptors required to wake up TX process */
  80 #define B44_TX_WAKEUP_THRESH            (B44_TX_RING_SIZE / 4)
  81
  82 /* b44 internal pattern match filter info */
  83 #define B44_PATTERN_BASE        0x400
  84 #define B44_PATTERN_SIZE        0x80
  85 #define B44_PMASK_BASE          0x600
  86 #define B44_PMASK_SIZE          0x10
  87 #define B44_MAX_PATTERNS        16
  88 #define B44_ETHIPV6UDP_HLEN     62
  89 #define B44_ETHIPV4UDP_HLEN     42
  90
  91 static char version[] __devinitdata =
  92         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION "\n";
  93
  94 MODULE_AUTHOR("Felix Fietkau, Florian Schirmer, Pekka Pietikainen, David S. Miller");
  95 MODULE_DESCRIPTION("Broadcom 44xx/47xx 10/100 PCI ethernet driver");
  96 MODULE_LICENSE("GPL");
  97 MODULE_VERSION(DRV_MODULE_VERSION);
  98
  99 static int b44_debug = -1;      /* -1 == use B44_DEF_MSG_ENABLE as value */
 100 module_param(b44_debug, int, 0);
 101 MODULE_PARM_DESC(b44_debug, "B44 bitmapped debugging message enable value");
 102
 103
 104 #ifdef CONFIG_B44_PCI
 105 static const struct pci_device_id b44_pci_tbl[] = {
 106         { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401) },
 107         { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401B0) },
 108         { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401B1) },
 109         { 0 } /* terminate list with empty entry */
 110 };
 111 MODULE_DEVICE_TABLE(pci, b44_pci_tbl);
 112
 113 static struct pci_driver b44_pci_driver = {
 114         .name           = DRV_MODULE_NAME,
 115         .id_table       = b44_pci_tbl,
 116 };
 117 #endif /* CONFIG_B44_PCI */
 118
 119 static const struct ssb_device_id b44_ssb_tbl[] = {
 120         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_ETHERNET, SSB_ANY_REV),
 121         SSB_DEVTABLE_END
 122 };
 123 MODULE_DEVICE_TABLE(ssb, b44_ssb_tbl);
 124
 125 static void b44_halt(struct b44 *);
 126 static void b44_init_rings(struct b44 *);
 127
 128 #define B44_FULL_RESET          1
 129 #define B44_FULL_RESET_SKIP_PHY 2
 130 #define B44_PARTIAL_RESET       3
 131 #define B44_CHIP_RESET_FULL     4
 132 #define B44_CHIP_RESET_PARTIAL  5
 133
 134 static void b44_init_hw(struct b44 *, int);
 135
 136 static int dma_desc_align_mask;
 137 static int dma_desc_sync_size;
 138 static int instance;
 139
 140 static const char b44_gstrings[][ETH_GSTRING_LEN] = {
 141 #define _B44(x...)      # x,
 142 B44_STAT_REG_DECLARE
 143 #undef _B44
 144 };
 145
 146 static inline void b44_sync_dma_desc_for_device(struct ssb_device *sdev,
 147                                                 dma_addr_t dma_base,
 148                                                 unsigned long offset,
 149                                                 enum dma_data_direction dir)
 150 {
 151         ssb_dma_sync_single_range_for_device(sdev, dma_base,
 152                                              offset & dma_desc_align_mask,
 153                                              dma_desc_sync_size, dir);
 154 }
 155
 156 static inline void b44_sync_dma_desc_for_cpu(struct ssb_device *sdev,
 157                                              dma_addr_t dma_base,
 158                                              unsigned long offset,
 159                                              enum dma_data_direction dir)
 160 {
 161         ssb_dma_sync_single_range_for_cpu(sdev, dma_base,
 162                                           offset & dma_desc_align_mask,
 163                                           dma_desc_sync_size, dir);
 164 }
 165
 166 static inline unsigned long br32(const struct b44 *bp, unsigned long reg)
 167 {
 168         return ssb_read32(bp->sdev, reg);
 169 }
 170
 171 static inline void bw32(const struct b44 *bp,
 172                         unsigned long reg, unsigned long val)
 173 {
 174         ssb_write32(bp->sdev, reg, val);
 175 }
 176
 177 static int b44_wait_bit(struct b44 *bp, unsigned long reg,
 178                         u32 bit, unsigned long timeout, const int clear)
 179 {
 180         unsigned long i;
 181
 182         for (i = 0; i < timeout; i++) {
 183                 u32 val = br32(bp, reg);
 184
 185                 if (clear && !(val & bit))
 186                         break;
 187                 if (!clear && (val & bit))
 188                         break;
 189                 udelay(10);
 190         }
 191         if (i == timeout) {
 192                 printk(KERN_ERR PFX "%s: BUG!  Timeout waiting for bit %08x of register "
 193                        "%lx to %s.\n",
 194                        bp->dev->name,
 195                        bit, reg,
 196                        (clear ? "clear" : "set"));
 197                 return -ENODEV;
 198         }
 199         return 0;
 200 }
 201
 202 static inline void __b44_cam_read(struct b44 *bp, unsigned char *data, int index)
 203 {
 204         u32 val;
 205
 206         bw32(bp, B44_CAM_CTRL, (CAM_CTRL_READ |
 207                             (index << CAM_CTRL_INDEX_SHIFT)));
 208
 209         b44_wait_bit(bp, B44_CAM_CTRL, CAM_CTRL_BUSY, 100, 1);
 210
 211         val = br32(bp, B44_CAM_DATA_LO);
 212
 213         data[2] = (val >> 24) & 0xFF;
 214         data[3] = (val >> 16) & 0xFF;
 215         data[4] = (val >> 8) & 0xFF;
 216         data[5] = (val >> 0) & 0xFF;
 217
 218         val = br32(bp, B44_CAM_DATA_HI);
 219
 220         data[0] = (val >> 8) & 0xFF;
 221         data[1] = (val >> 0) & 0xFF;
 222 }
 223
 224 static inline void __b44_cam_write(struct b44 *bp, unsigned char *data, int index)
 225 {
 226         u32 val;
 227
 228         val  = ((u32) data[2]) << 24;
 229         val |= ((u32) data[3]) << 16;
 230         val |= ((u32) data[4]) <<  8;
 231         val |= ((u32) data[5]) <<  0;
 232         bw32(bp, B44_CAM_DATA_LO, val);
 233         val = (CAM_DATA_HI_VALID |
 234                (((u32) data[0]) << 8) |
 235                (((u32) data[1]) << 0));
 236         bw32(bp, B44_CAM_DATA_HI, val);
 237         bw32(bp, B44_CAM_CTRL, (CAM_CTRL_WRITE |
 238                             (index << CAM_CTRL_INDEX_SHIFT)));
 239         b44_wait_bit(bp, B44_CAM_CTRL, CAM_CTRL_BUSY, 100, 1);
 240 }
 241
 242 static inline void __b44_disable_ints(struct b44 *bp)
 243 {
 244         bw32(bp, B44_IMASK, 0);
 245 }
 246
 247 static void b44_disable_ints(struct b44 *bp)
 248 {
 249         __b44_disable_ints(bp);
 250
 251         /* Flush posted writes. */
 252         br32(bp, B44_IMASK);
 253 }
 254
 255 static void b44_enable_ints(struct b44 *bp)
 256 {
 257         bw32(bp, B44_IMASK, bp->imask);
 258 }
 259
 260 static int __b44_readphy(struct b44 *bp, int phy_addr, int reg, u32 *val)
 261 {
 262         int err;
 263
 264         bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
 265         bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |
 266                              (MDIO_OP_READ << MDIO_DATA_OP_SHIFT) |
 267                              (phy_addr << MDIO_DATA_PMD_SHIFT) |
 268                              (reg << MDIO_DATA_RA_SHIFT) |
 269                              (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT)));
 270         err = b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
 271         *val = br32(bp, B44_MDIO_DATA) & MDIO_DATA_DATA;
 272
 273         return err;
 274 }
 275
 276 static int __b44_writephy(struct b44 *bp, int phy_addr, int reg, u32 val)
 277 {
 278         bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
 279         bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |
 280                              (MDIO_OP_WRITE << MDIO_DATA_OP_SHIFT) |
 281                              (phy_addr << MDIO_DATA_PMD_SHIFT) |
 282                              (reg << MDIO_DATA_RA_SHIFT) |
 283                              (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT) |
 284                              (val & MDIO_DATA_DATA)));
 285         return b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
 286 }
 287
 288 static inline int b44_readphy(struct b44 *bp, int reg, u32 *val)
 289 {
 290         if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
 291                 return 0;
 292
 293         return __b44_readphy(bp, bp->phy_addr, reg, val);
 294 }
 295
 296 static inline int b44_writephy(struct b44 *bp, int reg, u32 val)
 297 {
 298         if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
 299                 return 0;
 300
 301         return __b44_writephy(bp, bp->phy_addr, reg, val);
 302 }
 303
 304 /* miilib interface */
 305 static int b44_mii_read(struct net_device *dev, int phy_id, int location)
 306 {
 307         u32 val;
 308         struct b44 *bp = netdev_priv(dev);
 309         int rc = __b44_readphy(bp, phy_id, location, &val);
 310         if (rc)
 311                 return 0xffffffff;
 312         return val;
 313 }
 314
 315 static void b44_mii_write(struct net_device *dev, int phy_id, int location,
 316                          int val)
 317 {
 318         struct b44 *bp = netdev_priv(dev);
 319         __b44_writephy(bp, phy_id, location, val);
 320 }
 321
 322 static int b44_phy_reset(struct b44 *bp)
 323 {
 324         u32 val;
 325         int err;
 326
 327         if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
 328                 return 0;
 329         err = b44_writephy(bp, MII_BMCR, BMCR_RESET);
 330         if (err)
 331                 return err;
 332         udelay(100);
 333         err = b44_readphy(bp, MII_BMCR, &val);
 334         if (!err) {
 335                 if (val & BMCR_RESET) {
 336                         printk(KERN_ERR PFX "%s: PHY Reset would not complete.\n",
 337                                bp->dev->name);
 338                         err = -ENODEV;
 339                 }
 340         }
 341
 342         return 0;
 343 }
 344
 345 static void __b44_set_flow_ctrl(struct b44 *bp, u32 pause_flags)
 346 {
 347         u32 val;
 348
 349         bp->flags &= ~(B44_FLAG_TX_PAUSE | B44_FLAG_RX_PAUSE);
 350         bp->flags |= pause_flags;
 351
 352         val = br32(bp, B44_RXCONFIG);
 353         if (pause_flags & B44_FLAG_RX_PAUSE)
 354                 val |= RXCONFIG_FLOW;
 355         else
 356                 val &= ~RXCONFIG_FLOW;
 357         bw32(bp, B44_RXCONFIG, val);
 358
 359         val = br32(bp, B44_MAC_FLOW);
 360         if (pause_flags & B44_FLAG_TX_PAUSE)
 361                 val |= (MAC_FLOW_PAUSE_ENAB |
 362                         (0xc0 & MAC_FLOW_RX_HI_WATER));
 363         else
 364                 val &= ~MAC_FLOW_PAUSE_ENAB;
 365         bw32(bp, B44_MAC_FLOW, val);
 366 }
 367
 368 static void b44_set_flow_ctrl(struct b44 *bp, u32 local, u32 remote)
 369 {
 370         u32 pause_enab = 0;
 371
 372         /* The driver supports only rx pause by default because
 373            the b44 mac tx pause mechanism generates excessive
 374            pause frames.
 375            Use ethtool to turn on b44 tx pause if necessary.
 376          */
 377         if ((local & ADVERTISE_PAUSE_CAP) &&
 378             (local & ADVERTISE_PAUSE_ASYM)){
 379                 if ((remote & LPA_PAUSE_ASYM) &&
 380                     !(remote & LPA_PAUSE_CAP))
 381                         pause_enab |= B44_FLAG_RX_PAUSE;
 382         }
 383
 384         __b44_set_flow_ctrl(bp, pause_enab);
 385 }
 386
 387 #ifdef SSB_DRIVER_MIPS
 388 extern char *nvram_get(char *name);
 389 static void b44_wap54g10_workaround(struct b44 *bp)
 390 {
 391         const char *str;
 392         u32 val;
 393         int err;
 394
 395         /*
 396          * workaround for bad hardware design in Linksys WAP54G v1.0
 397          * see https://dev.openwrt.org/ticket/146
 398          * check and reset bit "isolate"
 399          */
 400         str = nvram_get("boardnum");
 401         if (!str)
 402                 return;
 403         if (simple_strtoul(str, NULL, 0) == 2) {
 404                 err = __b44_readphy(bp, 0, MII_BMCR, &val);
 405                 if (err)
 406                         goto error;
 407                 if (!(val & BMCR_ISOLATE))
 408                         return;
 409                 val &= ~BMCR_ISOLATE;
 410                 err = __b44_writephy(bp, 0, MII_BMCR, val);
 411                 if (err)
 412                         goto error;
 413         }
 414         return;
 415 error:
 416         printk(KERN_WARNING PFX "PHY: cannot reset MII transceiver isolate bit.\n");
 417 }
 418 #else
 419 static inline void b44_wap54g10_workaround(struct b44 *bp)
 420 {
 421 }
 422 #endif
 423
 424 static int b44_setup_phy(struct b44 *bp)
 425 {
 426         u32 val;
 427         int err;
 428
 429         b44_wap54g10_workaround(bp);
 430
 431         if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
 432                 return 0;
 433         if ((err = b44_readphy(bp, B44_MII_ALEDCTRL, &val)) != 0)
 434                 goto out;
 435         if ((err = b44_writephy(bp, B44_MII_ALEDCTRL,
 436                                 val & MII_ALEDCTRL_ALLMSK)) != 0)
 437                 goto out;
 438         if ((err = b44_readphy(bp, B44_MII_TLEDCTRL, &val)) != 0)
 439                 goto out;
 440         if ((err = b44_writephy(bp, B44_MII_TLEDCTRL,
 441                                 val | MII_TLEDCTRL_ENABLE)) != 0)
 442                 goto out;
 443
 444         if (!(bp->flags & B44_FLAG_FORCE_LINK)) {
 445                 u32 adv = ADVERTISE_CSMA;
 446
 447                 if (bp->flags & B44_FLAG_ADV_10HALF)
 448                         adv |= ADVERTISE_10HALF;
 449                 if (bp->flags & B44_FLAG_ADV_10FULL)
 450                         adv |= ADVERTISE_10FULL;
 451                 if (bp->flags & B44_FLAG_ADV_100HALF)
 452                         adv |= ADVERTISE_100HALF;
 453                 if (bp->flags & B44_FLAG_ADV_100FULL)
 454                         adv |= ADVERTISE_100FULL;
 455
 456                 if (bp->flags & B44_FLAG_PAUSE_AUTO)
 457                         adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
 458
 459                 if ((err = b44_writephy(bp, MII_ADVERTISE, adv)) != 0)
 460                         goto out;
 461                 if ((err = b44_writephy(bp, MII_BMCR, (BMCR_ANENABLE |
 462                                                        BMCR_ANRESTART))) != 0)
 463                         goto out;
 464         } else {
 465                 u32 bmcr;
 466
 467                 if ((err = b44_readphy(bp, MII_BMCR, &bmcr)) != 0)
 468                         goto out;
 469                 bmcr &= ~(BMCR_FULLDPLX | BMCR_ANENABLE | BMCR_SPEED100);
 470                 if (bp->flags & B44_FLAG_100_BASE_T)
 471                         bmcr |= BMCR_SPEED100;
 472                 if (bp->flags & B44_FLAG_FULL_DUPLEX)
 473                         bmcr |= BMCR_FULLDPLX;
 474                 if ((err = b44_writephy(bp, MII_BMCR, bmcr)) != 0)
 475                         goto out;
 476
 477                 /* Since we will not be negotiating there is no safe way
 478                  * to determine if the link partner supports flow control
 479                  * or not.  So just disable it completely in this case.
 480                  */
 481                 b44_set_flow_ctrl(bp, 0, 0);
 482         }
 483
 484 out:
 485         return err;
 486 }
 487
 488 static void b44_stats_update(struct b44 *bp)
 489 {
 490         unsigned long reg;
 491         u32 *val;
 492
 493         val = &bp->hw_stats.tx_good_octets;
 494         for (reg = B44_TX_GOOD_O; reg <= B44_TX_PAUSE; reg += 4UL) {
 495                 *val++ += br32(bp, reg);
 496         }
 497
 498         /* Pad */
 499         reg += 8*4UL;
 500
 501         for (reg = B44_RX_GOOD_O; reg <= B44_RX_NPAUSE; reg += 4UL) {
 502                 *val++ += br32(bp, reg);
 503         }
 504 }
 505
 506 static void b44_link_report(struct b44 *bp)
 507 {
 508         if (!netif_carrier_ok(bp->dev)) {
 509                 printk(KERN_INFO PFX "%s: Link is down.\n", bp->dev->name);
 510         } else {
 511                 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
 512                        bp->dev->name,
 513                        (bp->flags & B44_FLAG_100_BASE_T) ? 100 : 10,
 514                        (bp->flags & B44_FLAG_FULL_DUPLEX) ? "full" : "half");
 515
 516                 printk(KERN_INFO PFX "%s: Flow control is %s for TX and "
 517                        "%s for RX.\n",
 518                        bp->dev->name,
 519                        (bp->flags & B44_FLAG_TX_PAUSE) ? "on" : "off",
 520                        (bp->flags & B44_FLAG_RX_PAUSE) ? "on" : "off");
 521         }
 522 }
 523
 524 static void b44_check_phy(struct b44 *bp)
 525 {
 526         u32 bmsr, aux;
 527
 528         if (bp->phy_addr == B44_PHY_ADDR_NO_PHY) {
 529                 bp->flags |= B44_FLAG_100_BASE_T;
 530                 bp->flags |= B44_FLAG_FULL_DUPLEX;
 531                 if (!netif_carrier_ok(bp->dev)) {
 532                         u32 val = br32(bp, B44_TX_CTRL);
 533                         val |= TX_CTRL_DUPLEX;
 534                         bw32(bp, B44_TX_CTRL, val);
 535                         netif_carrier_on(bp->dev);
 536                         b44_link_report(bp);
 537                 }
 538                 return;
 539         }
 540
 541         if (!b44_readphy(bp, MII_BMSR, &bmsr) &&
 542             !b44_readphy(bp, B44_MII_AUXCTRL, &aux) &&
 543             (bmsr != 0xffff)) {
 544                 if (aux & MII_AUXCTRL_SPEED)
 545                         bp->flags |= B44_FLAG_100_BASE_T;
 546                 else
 547                         bp->flags &= ~B44_FLAG_100_BASE_T;
 548                 if (aux & MII_AUXCTRL_DUPLEX)
 549                         bp->flags |= B44_FLAG_FULL_DUPLEX;
 550                 else
 551                         bp->flags &= ~B44_FLAG_FULL_DUPLEX;
 552
 553                 if (!netif_carrier_ok(bp->dev) &&
 554                     (bmsr & BMSR_LSTATUS)) {
 555                         u32 val = br32(bp, B44_TX_CTRL);
 556                         u32 local_adv, remote_adv;
 557
 558                         if (bp->flags & B44_FLAG_FULL_DUPLEX)
 559                                 val |= TX_CTRL_DUPLEX;
 560                         else
 561                                 val &= ~TX_CTRL_DUPLEX;
 562                         bw32(bp, B44_TX_CTRL, val);
 563
 564                         if (!(bp->flags & B44_FLAG_FORCE_LINK) &&
 565                             !b44_readphy(bp, MII_ADVERTISE, &local_adv) &&
 566                             !b44_readphy(bp, MII_LPA, &remote_adv))
 567                                 b44_set_flow_ctrl(bp, local_adv, remote_adv);
 568
 569                         /* Link now up */
 570                         netif_carrier_on(bp->dev);
 571                         b44_link_report(bp);
 572                 } else if (netif_carrier_ok(bp->dev) && !(bmsr & BMSR_LSTATUS)) {
 573                         /* Link now down */
 574                         netif_carrier_off(bp->dev);
 575                         b44_link_report(bp);
 576                 }
 577
 578                 if (bmsr & BMSR_RFAULT)
 579                         printk(KERN_WARNING PFX "%s: Remote fault detected in PHY\n",
 580                                bp->dev->name);
 581                 if (bmsr & BMSR_JCD)
 582                         printk(KERN_WARNING PFX "%s: Jabber detected in PHY\n",
 583                                bp->dev->name);
 584         }
 585 }
 586
 587 static void b44_timer(unsigned long __opaque)
 588 {
 589         struct b44 *bp = (struct b44 *) __opaque;
 590
 591         spin_lock_irq(&bp->lock);
 592
 593         b44_check_phy(bp);
 594
 595         b44_stats_update(bp);
 596
 597         spin_unlock_irq(&bp->lock);
 598
 599         mod_timer(&bp->timer, round_jiffies(jiffies + HZ));
 600 }
 601
 602 static void b44_tx(struct b44 *bp)
 603 {
 604         u32 cur, cons;
 605
 606         cur  = br32(bp, B44_DMATX_STAT) & DMATX_STAT_CDMASK;
 607         cur /= sizeof(struct dma_desc);
 608
 609         /* XXX needs updating when NETIF_F_SG is supported */
 610         for (cons = bp->tx_cons; cons != cur; cons = NEXT_TX(cons)) {
 611                 struct ring_info *rp = &bp->tx_buffers[cons];
 612                 struct sk_buff *skb = rp->skb;
 613
 614                 BUG_ON(skb == NULL);
 615
 616                 ssb_dma_unmap_single(bp->sdev,
 617                                      rp->mapping,
 618                                      skb->len,
 619                                      DMA_TO_DEVICE);
 620                 rp->skb = NULL;
 621                 dev_kfree_skb_irq(skb);
 622         }
 623
 624         bp->tx_cons = cons;
 625         if (netif_queue_stopped(bp->dev) &&
 626             TX_BUFFS_AVAIL(bp) > B44_TX_WAKEUP_THRESH)
 627                 netif_wake_queue(bp->dev);
 628
 629         bw32(bp, B44_GPTIMER, 0);
 630 }
 631
 632 /* Works like this.  This chip writes a 'struct rx_header" 30 bytes
 633  * before the DMA address you give it.  So we allocate 30 more bytes
 634  * for the RX buffer, DMA map all of it, skb_reserve the 30 bytes, then
 635  * point the chip at 30 bytes past where the rx_header will go.
 636  */
 637 static int b44_alloc_rx_skb(struct b44 *bp, int src_idx, u32 dest_idx_unmasked)
 638 {
 639         struct dma_desc *dp;
 640         struct ring_info *src_map, *map;
 641         struct rx_header *rh;
 642         struct sk_buff *skb;
 643         dma_addr_t mapping;
 644         int dest_idx;
 645         u32 ctrl;
 646
 647         src_map = NULL;
 648         if (src_idx >= 0)
 649                 src_map = &bp->rx_buffers[src_idx];
 650         dest_idx = dest_idx_unmasked & (B44_RX_RING_SIZE - 1);
 651         map = &bp->rx_buffers[dest_idx];
 652         skb = netdev_alloc_skb(bp->dev, RX_PKT_BUF_SZ);
 653         if (skb == NULL)
 654                 return -ENOMEM;
 655
 656         mapping = ssb_dma_map_single(bp->sdev, skb->data,
 657                                      RX_PKT_BUF_SZ,
 658                                      DMA_FROM_DEVICE);
 659
 660         /* Hardware bug work-around, the chip is unable to do PCI DMA
 661            to/from anything above 1GB :-( */
 662         if (ssb_dma_mapping_error(bp->sdev, mapping) ||
 663                 mapping + RX_PKT_BUF_SZ > DMA_30BIT_MASK) {
 664                 /* Sigh... */
 665                 if (!ssb_dma_mapping_error(bp->sdev, mapping))
 666                         ssb_dma_unmap_single(bp->sdev, mapping,
 667                                              RX_PKT_BUF_SZ, DMA_FROM_DEVICE);
 668                 dev_kfree_skb_any(skb);
 669                 skb = __netdev_alloc_skb(bp->dev, RX_PKT_BUF_SZ, GFP_ATOMIC|GFP_DMA);
 670                 if (skb == NULL)
 671                         return -ENOMEM;
 672                 mapping = ssb_dma_map_single(bp->sdev, skb->data,
 673                                              RX_PKT_BUF_SZ,
 674                                              DMA_FROM_DEVICE);
 675                 if (ssb_dma_mapping_error(bp->sdev, mapping) ||
 676                         mapping + RX_PKT_BUF_SZ > DMA_30BIT_MASK) {
 677                         if (!ssb_dma_mapping_error(bp->sdev, mapping))
 678                                 ssb_dma_unmap_single(bp->sdev, mapping, RX_PKT_BUF_SZ,DMA_FROM_DEVICE);
 679                         dev_kfree_skb_any(skb);
 680                         return -ENOMEM;
 681                 }
 682         }
 683
 684         rh = (struct rx_header *) skb->data;
 685         skb_reserve(skb, RX_PKT_OFFSET);
 686
 687         rh->len = 0;
 688         rh->flags = 0;
 689
 690         map->skb = skb;
 691         map->mapping = mapping;
 692
 693         if (src_map != NULL)
 694                 src_map->skb = NULL;
 695
 696         ctrl  = (DESC_CTRL_LEN & (RX_PKT_BUF_SZ - RX_PKT_OFFSET));
 697         if (dest_idx == (B44_RX_RING_SIZE - 1))
 698                 ctrl |= DESC_CTRL_EOT;
 699
 700         dp = &bp->rx_ring[dest_idx];
 701         dp->ctrl = cpu_to_le32(ctrl);
 702         dp->addr = cpu_to_le32((u32) mapping + RX_PKT_OFFSET + bp->dma_offset);
 703
 704         if (bp->flags & B44_FLAG_RX_RING_HACK)
 705                 b44_sync_dma_desc_for_device(bp->sdev, bp->rx_ring_dma,
 706                                             dest_idx * sizeof(dp),
 707                                             DMA_BIDIRECTIONAL);
 708
 709         return RX_PKT_BUF_SZ;
 710 }
 711
 712 static void b44_recycle_rx(struct b44 *bp, int src_idx, u32 dest_idx_unmasked)
 713 {
 714         struct dma_desc *src_desc, *dest_desc;
 715         struct ring_info *src_map, *dest_map;
 716         struct rx_header *rh;
 717         int dest_idx;
 718         __le32 ctrl;
 719
 720         dest_idx = dest_idx_unmasked & (B44_RX_RING_SIZE - 1);
 721         dest_desc = &bp->rx_ring[dest_idx];
 722         dest_map = &bp->rx_buffers[dest_idx];
 723         src_desc = &bp->rx_ring[src_idx];
 724         src_map = &bp->rx_buffers[src_idx];
 725
 726         dest_map->skb = src_map->skb;
 727         rh = (struct rx_header *) src_map->skb->data;
 728         rh->len = 0;
 729         rh->flags = 0;
 730         dest_map->mapping = src_map->mapping;
 731
 732         if (bp->flags & B44_FLAG_RX_RING_HACK)
 733                 b44_sync_dma_desc_for_cpu(bp->sdev, bp->rx_ring_dma,
 734                                          src_idx * sizeof(src_desc),
 735                                          DMA_BIDIRECTIONAL);
 736
 737         ctrl = src_desc->ctrl;
 738         if (dest_idx == (B44_RX_RING_SIZE - 1))
 739                 ctrl |= cpu_to_le32(DESC_CTRL_EOT);
 740         else
 741                 ctrl &= cpu_to_le32(~DESC_CTRL_EOT);
 742
 743         dest_desc->ctrl = ctrl;
 744         dest_desc->addr = src_desc->addr;
 745
 746         src_map->skb = NULL;
 747
 748         if (bp->flags & B44_FLAG_RX_RING_HACK)
 749                 b44_sync_dma_desc_for_device(bp->sdev, bp->rx_ring_dma,
 750                                              dest_idx * sizeof(dest_desc),
 751                                              DMA_BIDIRECTIONAL);
 752
 753         ssb_dma_sync_single_for_device(bp->sdev, le32_to_cpu(src_desc->addr),
 754                                        RX_PKT_BUF_SZ,
 755                                        DMA_FROM_DEVICE);
 756 }
 757
 758 static int b44_rx(struct b44 *bp, int budget)
 759 {
 760         int received;
 761         u32 cons, prod;
 762
 763         received = 0;
 764         prod  = br32(bp, B44_DMARX_STAT) & DMARX_STAT_CDMASK;
 765         prod /= sizeof(struct dma_desc);
 766         cons = bp->rx_cons;
 767
 768         while (cons != prod && budget > 0) {
 769                 struct ring_info *rp = &bp->rx_buffers[cons];
 770                 struct sk_buff *skb = rp->skb;
 771                 dma_addr_t map = rp->mapping;
 772                 struct rx_header *rh;
 773                 u16 len;
 774
 775                 ssb_dma_sync_single_for_cpu(bp->sdev, map,
 776                                             RX_PKT_BUF_SZ,
 777                                             DMA_FROM_DEVICE);
 778                 rh = (struct rx_header *) skb->data;
 779                 len = le16_to_cpu(rh->len);
 780                 if ((len > (RX_PKT_BUF_SZ - RX_PKT_OFFSET)) ||
 781                     (rh->flags & cpu_to_le16(RX_FLAG_ERRORS))) {
 782                 drop_it:
 783                         b44_recycle_rx(bp, cons, bp->rx_prod);
 784                 drop_it_no_recycle:
 785                         bp->stats.rx_dropped++;
 786                         goto next_pkt;
 787                 }
 788
 789                 if (len == 0) {
 790                         int i = 0;
 791
 792                         do {
 793                                 udelay(2);
 794                                 barrier();
 795                                 len = le16_to_cpu(rh->len);
 796                         } while (len == 0 && i++ < 5);
 797                         if (len == 0)
 798                                 goto drop_it;
 799                 }
 800
 801                 /* Omit CRC. */
 802                 len -= 4;
 803
 804                 if (len > RX_COPY_THRESHOLD) {
 805                         int skb_size;
 806                         skb_size = b44_alloc_rx_skb(bp, cons, bp->rx_prod);
 807                         if (skb_size < 0)
 808                                 goto drop_it;
 809                         ssb_dma_unmap_single(bp->sdev, map,
 810                                              skb_size, DMA_FROM_DEVICE);
 811                         /* Leave out rx_header */
 812                         skb_put(skb, len + RX_PKT_OFFSET);
 813                         skb_pull(skb, RX_PKT_OFFSET);
 814                 } else {
 815                         struct sk_buff *copy_skb;
 816
 817                         b44_recycle_rx(bp, cons, bp->rx_prod);
 818                         copy_skb = dev_alloc_skb(len + 2);
 819                         if (copy_skb == NULL)
 820                                 goto drop_it_no_recycle;
 821
 822                         skb_reserve(copy_skb, 2);
 823                         skb_put(copy_skb, len);
 824                         /* DMA sync done above, copy just the actual packet */
 825                         skb_copy_from_linear_data_offset(skb, RX_PKT_OFFSET,
 826                                                          copy_skb->data, len);
 827                         skb = copy_skb;
 828                 }
 829                 skb->ip_summed = CHECKSUM_NONE;
 830                 skb->protocol = eth_type_trans(skb, bp->dev);
 831                 netif_receive_skb(skb);
 832                 received++;
 833                 budget--;
 834         next_pkt:
 835                 bp->rx_prod = (bp->rx_prod + 1) &
 836                         (B44_RX_RING_SIZE - 1);
 837                 cons = (cons + 1) & (B44_RX_RING_SIZE - 1);
 838         }
 839
 840         bp->rx_cons = cons;
 841         bw32(bp, B44_DMARX_PTR, cons * sizeof(struct dma_desc));
 842
 843         return received;
 844 }
 845
 846 static int b44_poll(struct napi_struct *napi, int budget)
 847 {
 848         struct b44 *bp = container_of(napi, struct b44, napi);
 849         struct net_device *netdev = bp->dev;
 850         int work_done;
 851
 852         spin_lock_irq(&bp->lock);
 853
 854         if (bp->istat & (ISTAT_TX | ISTAT_TO)) {
 855                 /* spin_lock(&bp->tx_lock); */
 856                 b44_tx(bp);
 857                 /* spin_unlock(&bp->tx_lock); */
 858         }
 859         spin_unlock_irq(&bp->lock);
 860
 861         work_done = 0;
 862         if (bp->istat & ISTAT_RX)
 863                 work_done += b44_rx(bp, budget);
 864
 865         if (bp->istat & ISTAT_ERRORS) {
 866                 unsigned long flags;
 867
 868                 spin_lock_irqsave(&bp->lock, flags);
 869                 b44_halt(bp);
 870                 b44_init_rings(bp);
 871                 b44_init_hw(bp, B44_FULL_RESET_SKIP_PHY);
 872                 netif_wake_queue(bp->dev);
 873                 spin_unlock_irqrestore(&bp->lock, flags);
 874                 work_done = 0;
 875         }
 876
 877         if (work_done < budget) {
 878                 netif_rx_complete(netdev, napi);
 879                 b44_enable_ints(bp);
 880         }
 881
 882         return work_done;
 883 }
 884
 885 static irqreturn_t b44_interrupt(int irq, void *dev_id)
 886 {
 887         struct net_device *dev = dev_id;
 888         struct b44 *bp = netdev_priv(dev);
 889         u32 istat, imask;
 890         int handled = 0;
 891
 892         spin_lock(&bp->lock);
 893
 894         istat = br32(bp, B44_ISTAT);
 895         imask = br32(bp, B44_IMASK);
 896
 897         /* The interrupt mask register controls which interrupt bits
 898          * will actually raise an interrupt to the CPU when set by hw/firmware,
 899          * but doesn't mask off the bits.
 900          */
 901         istat &= imask;
 902         if (istat) {
 903                 handled = 1;
 904
 905                 if (unlikely(!netif_running(dev))) {
 906                         printk(KERN_INFO "%s: late interrupt.\n", dev->name);
 907                         goto irq_ack;
 908                 }
 909
 910                 if (netif_rx_schedule_prep(dev, &bp->napi)) {
 911                         /* NOTE: These writes are posted by the readback of
 912                          *       the ISTAT register below.
 913                          */
 914                         bp->istat = istat;
 915                         __b44_disable_ints(bp);
 916                         __netif_rx_schedule(dev, &bp->napi);
 917                 } else {
 918                         printk(KERN_ERR PFX "%s: Error, poll already scheduled\n",
 919                                dev->name);
 920                 }
 921
 922 irq_ack:
 923                 bw32(bp, B44_ISTAT, istat);
 924                 br32(bp, B44_ISTAT);
 925         }
 926         spin_unlock(&bp->lock);
 927         return IRQ_RETVAL(handled);
 928 }
 929
 930 static void b44_tx_timeout(struct net_device *dev)
 931 {
 932         struct b44 *bp = netdev_priv(dev);
 933
 934         printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
 935                dev->name);
 936
 937         spin_lock_irq(&bp->lock);
 938
 939         b44_halt(bp);
 940         b44_init_rings(bp);
 941         b44_init_hw(bp, B44_FULL_RESET);
 942
 943         spin_unlock_irq(&bp->lock);
 944
 945         b44_enable_ints(bp);
 946
 947         netif_wake_queue(dev);
 948 }
 949
 950 static int b44_start_xmit(struct sk_buff *skb, struct net_device *dev)
 951 {
 952         struct b44 *bp = netdev_priv(dev);
 953         int rc = NETDEV_TX_OK;
 954         dma_addr_t mapping;
 955         u32 len, entry, ctrl;
 956
 957         len = skb->len;
 958         spin_lock_irq(&bp->lock);
 959
 960         /* This is a hard error, log it. */
 961         if (unlikely(TX_BUFFS_AVAIL(bp) < 1)) {
 962                 netif_stop_queue(dev);
 963                 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n",
 964                        dev->name);
 965                 goto err_out;
 966         }
 967
 968         mapping = ssb_dma_map_single(bp->sdev, skb->data, len, DMA_TO_DEVICE);
 969         if (ssb_dma_mapping_error(bp->sdev, mapping) || mapping + len > DMA_30BIT_MASK) {
 970                 struct sk_buff *bounce_skb;
 971
 972                 /* Chip can't handle DMA to/from >1GB, use bounce buffer */
 973                 if (!ssb_dma_mapping_error(bp->sdev, mapping))
 974                         ssb_dma_unmap_single(bp->sdev, mapping, len,
 975                                              DMA_TO_DEVICE);
 976
 977                 bounce_skb = __dev_alloc_skb(len, GFP_ATOMIC | GFP_DMA);
 978                 if (!bounce_skb)
 979                         goto err_out;
 980
 981                 mapping = ssb_dma_map_single(bp->sdev, bounce_skb->data,
 982                                              len, DMA_TO_DEVICE);
 983                 if (ssb_dma_mapping_error(bp->sdev, mapping) || mapping + len > DMA_30BIT_MASK) {
 984                         if (!ssb_dma_mapping_error(bp->sdev, mapping))
 985                                 ssb_dma_unmap_single(bp->sdev, mapping,
 986                                                      len, DMA_TO_DEVICE);
 987                         dev_kfree_skb_any(bounce_skb);
 988                         goto err_out;
 989                 }
 990
 991                 skb_copy_from_linear_data(skb, skb_put(bounce_skb, len), len);
 992                 dev_kfree_skb_any(skb);
 993                 skb = bounce_skb;
 994         }
 995
 996         entry = bp->tx_prod;
 997         bp->tx_buffers[entry].skb = skb;
 998         bp->tx_buffers[entry].mapping = mapping;
 999
1000         ctrl  = (len & DESC_CTRL_LEN);
1001         ctrl |= DESC_CTRL_IOC | DESC_CTRL_SOF | DESC_CTRL_EOF;
1002         if (entry == (B44_TX_RING_SIZE - 1))
1003                 ctrl |= DESC_CTRL_EOT;
1004
1005         bp->tx_ring[entry].ctrl = cpu_to_le32(ctrl);
1006         bp->tx_ring[entry].addr = cpu_to_le32((u32) mapping+bp->dma_offset);
1007
1008         if (bp->flags & B44_FLAG_TX_RING_HACK)
1009                 b44_sync_dma_desc_for_device(bp->sdev, bp->tx_ring_dma,
1010                                             entry * sizeof(bp->tx_ring[0]),
1011                                             DMA_TO_DEVICE);
1012
1013         entry = NEXT_TX(entry);
1014
1015         bp->tx_prod = entry;
1016
1017         wmb();
1018
1019         bw32(bp, B44_DMATX_PTR, entry * sizeof(struct dma_desc));
1020         if (bp->flags & B44_FLAG_BUGGY_TXPTR)
1021                 bw32(bp, B44_DMATX_PTR, entry * sizeof(struct dma_desc));
1022         if (bp->flags & B44_FLAG_REORDER_BUG)
1023                 br32(bp, B44_DMATX_PTR);
1024
1025         if (TX_BUFFS_AVAIL(bp) < 1)
1026                 netif_stop_queue(dev);
1027
1028         dev->trans_start = jiffies;
1029
1030 out_unlock:
1031         spin_unlock_irq(&bp->lock);
1032
1033         return rc;
1034
1035 err_out:
1036         rc = NETDEV_TX_BUSY;
1037         goto out_unlock;
1038 }
1039
1040 static int b44_change_mtu(struct net_device *dev, int new_mtu)
1041 {
1042         struct b44 *bp = netdev_priv(dev);
1043
1044         if (new_mtu < B44_MIN_MTU || new_mtu > B44_MAX_MTU)
1045                 return -EINVAL;
1046
1047         if (!netif_running(dev)) {
1048                 /* We'll just catch it later when the
1049                  * device is up'd.
1050                  */
1051                 dev->mtu = new_mtu;
1052                 return 0;
1053         }
1054
1055         spin_lock_irq(&bp->lock);
1056         b44_halt(bp);
1057         dev->mtu = new_mtu;
1058         b44_init_rings(bp);
1059         b44_init_hw(bp, B44_FULL_RESET);
1060         spin_unlock_irq(&bp->lock);
1061
1062         b44_enable_ints(bp);
1063
1064         return 0;
1065 }
1066
1067 /* Free up pending packets in all rx/tx rings.
1068  *
1069  * The chip has been shut down and the driver detached from
1070  * the networking, so no interrupts or new tx packets will
1071  * end up in the driver.  bp->lock is not held and we are not
1072  * in an interrupt context and thus may sleep.
1073  */
1074 static void b44_free_rings(struct b44 *bp)
1075 {
1076         struct ring_info *rp;
1077         int i;
1078
1079         for (i = 0; i < B44_RX_RING_SIZE; i++) {
1080                 rp = &bp->rx_buffers[i];
1081
1082                 if (rp->skb == NULL)
1083                         continue;
1084                 ssb_dma_unmap_single(bp->sdev, rp->mapping, RX_PKT_BUF_SZ,
1085                                      DMA_FROM_DEVICE);
1086                 dev_kfree_skb_any(rp->skb);
1087                 rp->skb = NULL;
1088         }
1089
1090         /* XXX needs changes once NETIF_F_SG is set... */
1091         for (i = 0; i < B44_TX_RING_SIZE; i++) {
1092                 rp = &bp->tx_buffers[i];
1093
1094                 if (rp->skb == NULL)
1095                         continue;
1096                 ssb_dma_unmap_single(bp->sdev, rp->mapping, rp->skb->len,
1097                                      DMA_TO_DEVICE);
1098                 dev_kfree_skb_any(rp->skb);
1099                 rp->skb = NULL;
1100         }
1101 }
1102
1103 /* Initialize tx/rx rings for packet processing.
1104  *
1105  * The chip has been shut down and the driver detached from
1106  * the networking, so no interrupts or new tx packets will
1107  * end up in the driver.
1108  */
1109 static void b44_init_rings(struct b44 *bp)
1110 {
1111         int i;
1112
1113         b44_free_rings(bp);
1114
1115         memset(bp->rx_ring, 0, B44_RX_RING_BYTES);
1116         memset(bp->tx_ring, 0, B44_TX_RING_BYTES);
1117
1118         if (bp->flags & B44_FLAG_RX_RING_HACK)
1119                 ssb_dma_sync_single_for_device(bp->sdev, bp->rx_ring_dma,
1120                                                DMA_TABLE_BYTES,
1121                                                DMA_BIDIRECTIONAL);
1122
1123         if (bp->flags & B44_FLAG_TX_RING_HACK)
1124                 ssb_dma_sync_single_for_device(bp->sdev, bp->tx_ring_dma,
1125                                                DMA_TABLE_BYTES,
1126                                                DMA_TO_DEVICE);
1127
1128         for (i = 0; i < bp->rx_pending; i++) {
1129                 if (b44_alloc_rx_skb(bp, -1, i) < 0)
1130                         break;
1131         }
1132 }
1133
1134 /*
1135  * Must not be invoked with interrupt sources disabled and
1136  * the hardware shutdown down.
1137  */
1138 static void b44_free_consistent(struct b44 *bp)
1139 {
1140         kfree(bp->rx_buffers);
1141         bp->rx_buffers = NULL;
1142         kfree(bp->tx_buffers);
1143         bp->tx_buffers = NULL;
1144         if (bp->rx_ring) {
1145                 if (bp->flags & B44_FLAG_RX_RING_HACK) {
1146                         ssb_dma_unmap_single(bp->sdev, bp->rx_ring_dma,
1147                                              DMA_TABLE_BYTES,
1148                                              DMA_BIDIRECTIONAL);
1149                         kfree(bp->rx_ring);
1150                 } else
1151                         ssb_dma_free_consistent(bp->sdev, DMA_TABLE_BYTES,
1152                                                 bp->rx_ring, bp->rx_ring_dma,
1153                                                 GFP_KERNEL);
1154                 bp->rx_ring = NULL;
1155                 bp->flags &= ~B44_FLAG_RX_RING_HACK;
1156         }
1157         if (bp->tx_ring) {
1158                 if (bp->flags & B44_FLAG_TX_RING_HACK) {
1159                         ssb_dma_unmap_single(bp->sdev, bp->tx_ring_dma,
1160                                              DMA_TABLE_BYTES,
1161                                              DMA_TO_DEVICE);
1162                         kfree(bp->tx_ring);
1163                 } else
1164                         ssb_dma_free_consistent(bp->sdev, DMA_TABLE_BYTES,
1165                                                 bp->tx_ring, bp->tx_ring_dma,
1166                                                 GFP_KERNEL);
1167                 bp->tx_ring = NULL;
1168                 bp->flags &= ~B44_FLAG_TX_RING_HACK;
1169         }
1170 }
1171
1172 /*
1173  * Must not be invoked with interrupt sources disabled and
1174  * the hardware shutdown down.  Can sleep.
1175  */
1176 static int b44_alloc_consistent(struct b44 *bp, gfp_t gfp)
1177 {
1178         int size;
1179
1180         size  = B44_RX_RING_SIZE * sizeof(struct ring_info);
1181         bp->rx_buffers = kzalloc(size, gfp);
1182         if (!bp->rx_buffers)
1183                 goto out_err;
1184
1185         size = B44_TX_RING_SIZE * sizeof(struct ring_info);
1186         bp->tx_buffers = kzalloc(size, gfp);
1187         if (!bp->tx_buffers)
1188                 goto out_err;
1189
1190         size = DMA_TABLE_BYTES;
1191         bp->rx_ring = ssb_dma_alloc_consistent(bp->sdev, size, &bp->rx_ring_dma, gfp);
1192         if (!bp->rx_ring) {
1193                 /* Allocation may have failed due to pci_alloc_consistent
1194                    insisting on use of GFP_DMA, which is more restrictive
1195                    than necessary...  */
1196                 struct dma_desc *rx_ring;
1197                 dma_addr_t rx_ring_dma;
1198
1199                 rx_ring = kzalloc(size, gfp);
1200                 if (!rx_ring)
1201                         goto out_err;
1202
1203                 rx_ring_dma = ssb_dma_map_single(bp->sdev, rx_ring,
1204                                                  DMA_TABLE_BYTES,
1205                                                  DMA_BIDIRECTIONAL);
1206
1207                 if (ssb_dma_mapping_error(bp->sdev, rx_ring_dma) ||
1208                         rx_ring_dma + size > DMA_30BIT_MASK) {
1209                         kfree(rx_ring);
1210                         goto out_err;
1211                 }
1212
1213                 bp->rx_ring = rx_ring;
1214                 bp->rx_ring_dma = rx_ring_dma;
1215                 bp->flags |= B44_FLAG_RX_RING_HACK;
1216         }
1217
1218         bp->tx_ring = ssb_dma_alloc_consistent(bp->sdev, size, &bp->tx_ring_dma, gfp);
1219         if (!bp->tx_ring) {
1220                 /* Allocation may have failed due to ssb_dma_alloc_consistent
1221                    insisting on use of GFP_DMA, which is more restrictive
1222                    than necessary...  */
1223                 struct dma_desc *tx_ring;
1224                 dma_addr_t tx_ring_dma;
1225
1226                 tx_ring = kzalloc(size, gfp);
1227                 if (!tx_ring)
1228                         goto out_err;
1229
1230                 tx_ring_dma = ssb_dma_map_single(bp->sdev, tx_ring,
1231                                             DMA_TABLE_BYTES,
1232                                             DMA_TO_DEVICE);
1233
1234                 if (ssb_dma_mapping_error(bp->sdev, tx_ring_dma) ||
1235                         tx_ring_dma + size > DMA_30BIT_MASK) {
1236                         kfree(tx_ring);
1237                         goto out_err;
1238                 }
1239
1240                 bp->tx_ring = tx_ring;
1241                 bp->tx_ring_dma = tx_ring_dma;
1242                 bp->flags |= B44_FLAG_TX_RING_HACK;
1243         }
1244
1245         return 0;
1246
1247 out_err:
1248         b44_free_consistent(bp);
1249         return -ENOMEM;
1250 }
1251
1252 /* bp->lock is held. */
1253 static void b44_clear_stats(struct b44 *bp)
1254 {
1255         unsigned long reg;
1256
1257         bw32(bp, B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ);
1258         for (reg = B44_TX_GOOD_O; reg <= B44_TX_PAUSE; reg += 4UL)
1259                 br32(bp, reg);
1260         for (reg = B44_RX_GOOD_O; reg <= B44_RX_NPAUSE; reg += 4UL)
1261                 br32(bp, reg);
1262 }
1263
1264 /* bp->lock is held. */
1265 static void b44_chip_reset(struct b44 *bp, int reset_kind)
1266 {
1267         struct ssb_device *sdev = bp->sdev;
1268
1269         if (ssb_device_is_enabled(bp->sdev)) {
1270                 bw32(bp, B44_RCV_LAZY, 0);
1271                 bw32(bp, B44_ENET_CTRL, ENET_CTRL_DISABLE);
1272                 b44_wait_bit(bp, B44_ENET_CTRL, ENET_CTRL_DISABLE, 200, 1);
1273                 bw32(bp, B44_DMATX_CTRL, 0);
1274                 bp->tx_prod = bp->tx_cons = 0;
1275                 if (br32(bp, B44_DMARX_STAT) & DMARX_STAT_EMASK) {
1276                         b44_wait_bit(bp, B44_DMARX_STAT, DMARX_STAT_SIDLE,
1277                                      100, 0);
1278                 }
1279                 bw32(bp, B44_DMARX_CTRL, 0);
1280                 bp->rx_prod = bp->rx_cons = 0;
1281         } else
1282                 ssb_pcicore_dev_irqvecs_enable(&sdev->bus->pcicore, sdev);
1283
1284         ssb_device_enable(bp->sdev, 0);
1285         b44_clear_stats(bp);
1286
1287         /*
1288          * Don't enable PHY if we are doing a partial reset
1289          * we are probably going to power down
1290          */
1291         if (reset_kind == B44_CHIP_RESET_PARTIAL)
1292                 return;
1293
1294         switch (sdev->bus->bustype) {
1295         case SSB_BUSTYPE_SSB:
1296                 bw32(bp, B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
1297                      (((ssb_clockspeed(sdev->bus) + (B44_MDC_RATIO / 2)) / B44_MDC_RATIO)
1298                      & MDIO_CTRL_MAXF_MASK)));
1299                 break;
1300         case SSB_BUSTYPE_PCI:
1301         case SSB_BUSTYPE_PCMCIA:
1302                 bw32(bp, B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
1303                      (0x0d & MDIO_CTRL_MAXF_MASK)));
1304                 break;
1305         }
1306
1307         br32(bp, B44_MDIO_CTRL);
1308
1309         if (!(br32(bp, B44_DEVCTRL) & DEVCTRL_IPP)) {
1310                 bw32(bp, B44_ENET_CTRL, ENET_CTRL_EPSEL);
1311                 br32(bp, B44_ENET_CTRL);
1312                 bp->flags &= ~B44_FLAG_INTERNAL_PHY;
1313         } else {
1314                 u32 val = br32(bp, B44_DEVCTRL);
1315
1316                 if (val & DEVCTRL_EPR) {
1317                         bw32(bp, B44_DEVCTRL, (val & ~DEVCTRL_EPR));
1318                         br32(bp, B44_DEVCTRL);
1319                         udelay(100);
1320                 }
1321                 bp->flags |= B44_FLAG_INTERNAL_PHY;
1322         }
1323 }
1324
1325 /* bp->lock is held. */
1326 static void b44_halt(struct b44 *bp)
1327 {
1328         b44_disable_ints(bp);
1329         /* reset PHY */
1330         b44_phy_reset(bp);
1331         /* power down PHY */
1332         printk(KERN_INFO PFX "%s: powering down PHY\n", bp->dev->name);
1333         bw32(bp, B44_MAC_CTRL, MAC_CTRL_PHY_PDOWN);
1334         /* now reset the chip, but without enabling the MAC&PHY
1335          * part of it. This has to be done _after_ we shut down the PHY */
1336         b44_chip_reset(bp, B44_CHIP_RESET_PARTIAL);
1337 }
1338
1339 /* bp->lock is held. */
1340 static void __b44_set_mac_addr(struct b44 *bp)
1341 {
1342         bw32(bp, B44_CAM_CTRL, 0);
1343         if (!(bp->dev->flags & IFF_PROMISC)) {
1344                 u32 val;
1345
1346                 __b44_cam_write(bp, bp->dev->dev_addr, 0);
1347                 val = br32(bp, B44_CAM_CTRL);
1348                 bw32(bp, B44_CAM_CTRL, val | CAM_CTRL_ENABLE);
1349         }
1350 }
1351
1352 static int b44_set_mac_addr(struct net_device *dev, void *p)
1353 {
1354         struct b44 *bp = netdev_priv(dev);
1355         struct sockaddr *addr = p;
1356         u32 val;
1357
1358         if (netif_running(dev))
1359                 return -EBUSY;
1360
1361         if (!is_valid_ether_addr(addr->sa_data))
1362                 return -EINVAL;
1363
1364         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1365
1366         spin_lock_irq(&bp->lock);
1367
1368         val = br32(bp, B44_RXCONFIG);
1369         if (!(val & RXCONFIG_CAM_ABSENT))
1370                 __b44_set_mac_addr(bp);
1371
1372         spin_unlock_irq(&bp->lock);
1373
1374         return 0;
1375 }
1376
1377 /* Called at device open time to get the chip ready for
1378  * packet processing.  Invoked with bp->lock held.
1379  */
1380 static void __b44_set_rx_mode(struct net_device *);
1381 static void b44_init_hw(struct b44 *bp, int reset_kind)
1382 {
1383         u32 val;
1384
1385         b44_chip_reset(bp, B44_CHIP_RESET_FULL);
1386         if (reset_kind == B44_FULL_RESET) {
1387                 b44_phy_reset(bp);
1388                 b44_setup_phy(bp);
1389         }
1390
1391         /* Enable CRC32, set proper LED modes and power on PHY */
1392         bw32(bp, B44_MAC_CTRL, MAC_CTRL_CRC32_ENAB | MAC_CTRL_PHY_LEDCTRL);
1393         bw32(bp, B44_RCV_LAZY, (1 << RCV_LAZY_FC_SHIFT));
1394
1395         /* This sets the MAC address too.  */
1396         __b44_set_rx_mode(bp->dev);
1397
1398         /* MTU + eth header + possible VLAN tag + struct rx_header */
1399         bw32(bp, B44_RXMAXLEN, bp->dev->mtu + ETH_HLEN + 8 + RX_HEADER_LEN);
1400         bw32(bp, B44_TXMAXLEN, bp->dev->mtu + ETH_HLEN + 8 + RX_HEADER_LEN);
1401
1402         bw32(bp, B44_TX_WMARK, 56); /* XXX magic */
1403         if (reset_kind == B44_PARTIAL_RESET) {
1404                 bw32(bp, B44_DMARX_CTRL, (DMARX_CTRL_ENABLE |
1405                                       (RX_PKT_OFFSET << DMARX_CTRL_ROSHIFT)));
1406         } else {
1407                 bw32(bp, B44_DMATX_CTRL, DMATX_CTRL_ENABLE);
1408                 bw32(bp, B44_DMATX_ADDR, bp->tx_ring_dma + bp->dma_offset);
1409                 bw32(bp, B44_DMARX_CTRL, (DMARX_CTRL_ENABLE |
1410                                       (RX_PKT_OFFSET << DMARX_CTRL_ROSHIFT)));
1411                 bw32(bp, B44_DMARX_ADDR, bp->rx_ring_dma + bp->dma_offset);
1412
1413                 bw32(bp, B44_DMARX_PTR, bp->rx_pending);
1414                 bp->rx_prod = bp->rx_pending;
1415
1416                 bw32(bp, B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ);
1417         }
1418
1419         val = br32(bp, B44_ENET_CTRL);
1420         bw32(bp, B44_ENET_CTRL, (val | ENET_CTRL_ENABLE));
1421 }
1422
1423 static int b44_open(struct net_device *dev)
1424 {
1425         struct b44 *bp = netdev_priv(dev);
1426         int err;
1427
1428         err = b44_alloc_consistent(bp, GFP_KERNEL);
1429         if (err)
1430                 goto out;
1431
1432         napi_enable(&bp->napi);
1433
1434         b44_init_rings(bp);
1435         b44_init_hw(bp, B44_FULL_RESET);
1436
1437         b44_check_phy(bp);
1438
1439         err = request_irq(dev->irq, b44_interrupt, IRQF_SHARED, dev->name, dev);
1440         if (unlikely(err < 0)) {
1441                 napi_disable(&bp->napi);
1442                 b44_chip_reset(bp, B44_CHIP_RESET_PARTIAL);
1443                 b44_free_rings(bp);
1444                 b44_free_consistent(bp);
1445                 goto out;
1446         }
1447
1448         init_timer(&bp->timer);
1449         bp->timer.expires = jiffies + HZ;
1450         bp->timer.data = (unsigned long) bp;
1451         bp->timer.function = b44_timer;
1452         add_timer(&bp->timer);
1453
1454         b44_enable_ints(bp);
1455         netif_start_queue(dev);
1456 out:
1457         return err;
1458 }
1459
1460 #ifdef CONFIG_NET_POLL_CONTROLLER
1461 /*
1462  * Polling receive - used by netconsole and other diagnostic tools
1463  * to allow network i/o with interrupts disabled.
1464  */
1465 static void b44_poll_controller(struct net_device *dev)
1466 {
1467         disable_irq(dev->irq);
1468         b44_interrupt(dev->irq, dev);
1469         enable_irq(dev->irq);
1470 }
1471 #endif
1472
1473 static void bwfilter_table(struct b44 *bp, u8 *pp, u32 bytes, u32 table_offset)
1474 {
1475         u32 i;
1476         u32 *pattern = (u32 *) pp;
1477
1478         for (i = 0; i < bytes; i += sizeof(u32)) {
1479                 bw32(bp, B44_FILT_ADDR, table_offset + i);
1480                 bw32(bp, B44_FILT_DATA, pattern[i / sizeof(u32)]);
1481         }
1482 }
1483
1484 static int b44_magic_pattern(u8 *macaddr, u8 *ppattern, u8 *pmask, int offset)
1485 {
1486         int magicsync = 6;
1487         int k, j, len = offset;
1488         int ethaddr_bytes = ETH_ALEN;
1489
1490         memset(ppattern + offset, 0xff, magicsync);
1491         for (j = 0; j < magicsync; j++)
1492                 set_bit(len++, (unsigned long *) pmask);
1493
1494         for (j = 0; j < B44_MAX_PATTERNS; j++) {
1495                 if ((B44_PATTERN_SIZE - len) >= ETH_ALEN)
1496                         ethaddr_bytes = ETH_ALEN;
1497                 else
1498                         ethaddr_bytes = B44_PATTERN_SIZE - len;
1499                 if (ethaddr_bytes <=0)
1500                         break;
1501                 for (k = 0; k< ethaddr_bytes; k++) {
1502                         ppattern[offset + magicsync +
1503                                 (j * ETH_ALEN) + k] = macaddr[k];
1504                         len++;
1505                         set_bit(len, (unsigned long *) pmask);
1506                 }
1507         }
1508         return len - 1;
1509 }
1510
1511 /* Setup magic packet patterns in the b44 WOL
1512  * pattern matching filter.
1513  */
1514 static void b44_setup_pseudo_magicp(struct b44 *bp)
1515 {
1516
1517         u32 val;
1518         int plen0, plen1, plen2;
1519         u8 *pwol_pattern;
1520         u8 pwol_mask[B44_PMASK_SIZE];
1521
1522         pwol_pattern = kzalloc(B44_PATTERN_SIZE, GFP_KERNEL);
1523         if (!pwol_pattern) {
1524                 printk(KERN_ERR PFX "Memory not available for WOL\n");
1525                 return;
1526         }
1527
1528         /* Ipv4 magic packet pattern - pattern 0.*/
1529         memset(pwol_mask, 0, B44_PMASK_SIZE);
1530         plen0 = b44_magic_pattern(bp->dev->dev_addr, pwol_pattern, pwol_mask,
1531                                   B44_ETHIPV4UDP_HLEN);
1532
1533         bwfilter_table(bp, pwol_pattern, B44_PATTERN_SIZE, B44_PATTERN_BASE);
1534         bwfilter_table(bp, pwol_mask, B44_PMASK_SIZE, B44_PMASK_BASE);
1535
1536         /* Raw ethernet II magic packet pattern - pattern 1 */
1537         memset(pwol_pattern, 0, B44_PATTERN_SIZE);
1538         memset(pwol_mask, 0, B44_PMASK_SIZE);
1539         plen1 = b44_magic_pattern(bp->dev->dev_addr, pwol_pattern, pwol_mask,
1540                                   ETH_HLEN);
1541
1542         bwfilter_table(bp, pwol_pattern, B44_PATTERN_SIZE,
1543                        B44_PATTERN_BASE + B44_PATTERN_SIZE);
1544         bwfilter_table(bp, pwol_mask, B44_PMASK_SIZE,
1545                        B44_PMASK_BASE + B44_PMASK_SIZE);
1546
1547         /* Ipv6 magic packet pattern - pattern 2 */
1548         memset(pwol_pattern, 0, B44_PATTERN_SIZE);
1549         memset(pwol_mask, 0, B44_PMASK_SIZE);
1550         plen2 = b44_magic_pattern(bp->dev->dev_addr, pwol_pattern, pwol_mask,
1551                                   B44_ETHIPV6UDP_HLEN);
1552
1553         bwfilter_table(bp, pwol_pattern, B44_PATTERN_SIZE,
1554                        B44_PATTERN_BASE + B44_PATTERN_SIZE + B44_PATTERN_SIZE);
1555         bwfilter_table(bp, pwol_mask, B44_PMASK_SIZE,
1556                        B44_PMASK_BASE + B44_PMASK_SIZE + B44_PMASK_SIZE);
1557
1558         kfree(pwol_pattern);
1559
1560         /* set these pattern's lengths: one less than each real length */
1561         val = plen0 | (plen1 << 8) | (plen2 << 16) | WKUP_LEN_ENABLE_THREE;
1562         bw32(bp, B44_WKUP_LEN, val);
1563
1564         /* enable wakeup pattern matching */
1565         val = br32(bp, B44_DEVCTRL);
1566         bw32(bp, B44_DEVCTRL, val | DEVCTRL_PFE);
1567
1568 }
1569
1570 #ifdef CONFIG_B44_PCI
1571 static void b44_setup_wol_pci(struct b44 *bp)
1572 {
1573         u16 val;
1574
1575         if (bp->sdev->bus->bustype != SSB_BUSTYPE_SSB) {
1576                 bw32(bp, SSB_TMSLOW, br32(bp, SSB_TMSLOW) | SSB_TMSLOW_PE);
1577                 pci_read_config_word(bp->sdev->bus->host_pci, SSB_PMCSR, &val);
1578                 pci_write_config_word(bp->sdev->bus->host_pci, SSB_PMCSR, val | SSB_PE);
1579         }
1580 }
1581 #else
1582 static inline void b44_setup_wol_pci(struct b44 *bp) { }
1583 #endif /* CONFIG_B44_PCI */
1584
1585 static void b44_setup_wol(struct b44 *bp)
1586 {
1587         u32 val;
1588
1589         bw32(bp, B44_RXCONFIG, RXCONFIG_ALLMULTI);
1590
1591         if (bp->flags & B44_FLAG_B0_ANDLATER) {
1592
1593                 bw32(bp, B44_WKUP_LEN, WKUP_LEN_DISABLE);
1594
1595                 val = bp->dev->dev_addr[2] << 24 |
1596                         bp->dev->dev_addr[3] << 16 |
1597                         bp->dev->dev_addr[4] << 8 |
1598                         bp->dev->dev_addr[5];
1599                 bw32(bp, B44_ADDR_LO, val);
1600
1601                 val = bp->dev->dev_addr[0] << 8 |
1602                         bp->dev->dev_addr[1];
1603                 bw32(bp, B44_ADDR_HI, val);
1604
1605                 val = br32(bp, B44_DEVCTRL);
1606                 bw32(bp, B44_DEVCTRL, val | DEVCTRL_MPM | DEVCTRL_PFE);
1607
1608         } else {
1609                 b44_setup_pseudo_magicp(bp);
1610         }
1611         b44_setup_wol_pci(bp);
1612 }
1613
1614 static int b44_close(struct net_device *dev)
1615 {
1616         struct b44 *bp = netdev_priv(dev);
1617
1618         netif_stop_queue(dev);
1619
1620         napi_disable(&bp->napi);
1621
1622         del_timer_sync(&bp->timer);
1623
1624         spin_lock_irq(&bp->lock);
1625
1626         b44_halt(bp);
1627         b44_free_rings(bp);
1628         netif_carrier_off(dev);
1629
1630         spin_unlock_irq(&bp->lock);
1631
1632         free_irq(dev->irq, dev);
1633
1634         if (bp->flags & B44_FLAG_WOL_ENABLE) {
1635                 b44_init_hw(bp, B44_PARTIAL_RESET);
1636                 b44_setup_wol(bp);
1637         }
1638
1639         b44_free_consistent(bp);
1640
1641         return 0;
1642 }
1643
1644 static struct net_device_stats *b44_get_stats(struct net_device *dev)
1645 {
1646         struct b44 *bp = netdev_priv(dev);
1647         struct net_device_stats *nstat = &bp->stats;
1648         struct b44_hw_stats *hwstat = &bp->hw_stats;
1649
1650         /* Convert HW stats into netdevice stats. */
1651         nstat->rx_packets = hwstat->rx_pkts;
1652         nstat->tx_packets = hwstat->tx_pkts;
1653         nstat->rx_bytes   = hwstat->rx_octets;
1654         nstat->tx_bytes   = hwstat->tx_octets;
1655         nstat->tx_errors  = (hwstat->tx_jabber_pkts +
1656                              hwstat->tx_oversize_pkts +
1657                              hwstat->tx_underruns +
1658                              hwstat->tx_excessive_cols +
1659                              hwstat->tx_late_cols);
1660         nstat->multicast  = hwstat->tx_multicast_pkts;
1661         nstat->collisions = hwstat->tx_total_cols;
1662
1663         nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
1664                                    hwstat->rx_undersize);
1665         nstat->rx_over_errors   = hwstat->rx_missed_pkts;
1666         nstat->rx_frame_errors  = hwstat->rx_align_errs;
1667         nstat->rx_crc_errors    = hwstat->rx_crc_errs;
1668         nstat->rx_errors        = (hwstat->rx_jabber_pkts +
1669                                    hwstat->rx_oversize_pkts +
1670                                    hwstat->rx_missed_pkts +
1671                                    hwstat->rx_crc_align_errs +
1672                                    hwstat->rx_undersize +
1673                                    hwstat->rx_crc_errs +
1674                                    hwstat->rx_align_errs +
1675                                    hwstat->rx_symbol_errs);
1676
1677         nstat->tx_aborted_errors = hwstat->tx_underruns;
1678 #if 0
1679         /* Carrier lost counter seems to be broken for some devices */
1680         nstat->tx_carrier_errors = hwstat->tx_carrier_lost;
1681 #endif
1682
1683         return nstat;
1684 }
1685
1686 static int __b44_load_mcast(struct b44 *bp, struct net_device *dev)
1687 {
1688         struct dev_mc_list *mclist;
1689         int i, num_ents;
1690
1691         num_ents = min_t(int, dev->mc_count, B44_MCAST_TABLE_SIZE);
1692         mclist = dev->mc_list;
1693         for (i = 0; mclist && i < num_ents; i++, mclist = mclist->next) {
1694                 __b44_cam_write(bp, mclist->dmi_addr, i + 1);
1695         }
1696         return i+1;
1697 }
1698
1699 static void __b44_set_rx_mode(struct net_device *dev)
1700 {
1701         struct b44 *bp = netdev_priv(dev);
1702         u32 val;
1703
1704         val = br32(bp, B44_RXCONFIG);
1705         val &= ~(RXCONFIG_PROMISC | RXCONFIG_ALLMULTI);
1706         if ((dev->flags & IFF_PROMISC) || (val & RXCONFIG_CAM_ABSENT)) {
1707                 val |= RXCONFIG_PROMISC;
1708                 bw32(bp, B44_RXCONFIG, val);
1709         } else {
1710                 unsigned char zero[6] = {0, 0, 0, 0, 0, 0};
1711                 int i = 1;
1712
1713                 __b44_set_mac_addr(bp);
1714
1715                 if ((dev->flags & IFF_ALLMULTI) ||
1716                     (dev->mc_count > B44_MCAST_TABLE_SIZE))
1717                         val |= RXCONFIG_ALLMULTI;
1718                 else
1719                         i = __b44_load_mcast(bp, dev);
1720
1721                 for (; i < 64; i++)
1722                         __b44_cam_write(bp, zero, i);
1723
1724                 bw32(bp, B44_RXCONFIG, val);
1725                 val = br32(bp, B44_CAM_CTRL);
1726                 bw32(bp, B44_CAM_CTRL, val | CAM_CTRL_ENABLE);
1727         }
1728 }
1729
1730 static void b44_set_rx_mode(struct net_device *dev)
1731 {
1732         struct b44 *bp = netdev_priv(dev);
1733
1734         spin_lock_irq(&bp->lock);
1735         __b44_set_rx_mode(dev);
1736         spin_unlock_irq(&bp->lock);
1737 }
1738
1739 static u32 b44_get_msglevel(struct net_device *dev)
1740 {
1741         struct b44 *bp = netdev_priv(dev);
1742         return bp->msg_enable;
1743 }
1744
1745 static void b44_set_msglevel(struct net_device *dev, u32 value)
1746 {
1747         struct b44 *bp = netdev_priv(dev);
1748         bp->msg_enable = value;
1749 }
1750
1751 static void b44_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
1752 {
1753         struct b44 *bp = netdev_priv(dev);
1754         struct ssb_bus *bus = bp->sdev->bus;
1755
1756         strncpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
1757         strncpy(info->version, DRV_MODULE_VERSION, sizeof(info->driver));
1758         switch (bus->bustype) {
1759         case SSB_BUSTYPE_PCI:
1760                 strncpy(info->bus_info, pci_name(bus->host_pci), sizeof(info->bus_info));
1761                 break;
1762         case SSB_BUSTYPE_PCMCIA:
1763         case SSB_BUSTYPE_SSB:
1764                 strncpy(info->bus_info, "SSB", sizeof(info->bus_info));
1765                 break;
1766         }
1767 }
1768
1769 static int b44_nway_reset(struct net_device *dev)
1770 {
1771         struct b44 *bp = netdev_priv(dev);
1772         u32 bmcr;
1773         int r;
1774
1775         spin_lock_irq(&bp->lock);
1776         b44_readphy(bp, MII_BMCR, &bmcr);
1777         b44_readphy(bp, MII_BMCR, &bmcr);
1778         r = -EINVAL;
1779         if (bmcr & BMCR_ANENABLE) {
1780                 b44_writephy(bp, MII_BMCR,
1781                              bmcr | BMCR_ANRESTART);
1782                 r = 0;
1783         }
1784         spin_unlock_irq(&bp->lock);
1785
1786         return r;
1787 }
1788
1789 static int b44_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1790 {
1791         struct b44 *bp = netdev_priv(dev);
1792
1793         cmd->supported = (SUPPORTED_Autoneg);
1794         cmd->supported |= (SUPPORTED_100baseT_Half |
1795                           SUPPORTED_100baseT_Full |
1796                           SUPPORTED_10baseT_Half |
1797                           SUPPORTED_10baseT_Full |
1798                           SUPPORTED_MII);
1799
1800         cmd->advertising = 0;
1801         if (bp->flags & B44_FLAG_ADV_10HALF)
1802                 cmd->advertising |= ADVERTISED_10baseT_Half;
1803         if (bp->flags & B44_FLAG_ADV_10FULL)
1804                 cmd->advertising |= ADVERTISED_10baseT_Full;
1805         if (bp->flags & B44_FLAG_ADV_100HALF)
1806                 cmd->advertising |= ADVERTISED_100baseT_Half;
1807         if (bp->flags & B44_FLAG_ADV_100FULL)
1808                 cmd->advertising |= ADVERTISED_100baseT_Full;
1809         cmd->advertising |= ADVERTISED_Pause | ADVERTISED_Asym_Pause;
1810         cmd->speed = (bp->flags & B44_FLAG_100_BASE_T) ?
1811                 SPEED_100 : SPEED_10;
1812         cmd->duplex = (bp->flags & B44_FLAG_FULL_DUPLEX) ?
1813                 DUPLEX_FULL : DUPLEX_HALF;
1814         cmd->port = 0;
1815         cmd->phy_address = bp->phy_addr;
1816         cmd->transceiver = (bp->flags & B44_FLAG_INTERNAL_PHY) ?
1817                 XCVR_INTERNAL : XCVR_EXTERNAL;
1818         cmd->autoneg = (bp->flags & B44_FLAG_FORCE_LINK) ?
1819                 AUTONEG_DISABLE : AUTONEG_ENABLE;
1820         if (cmd->autoneg == AUTONEG_ENABLE)
1821                 cmd->advertising |= ADVERTISED_Autoneg;
1822         if (!netif_running(dev)){
1823                 cmd->speed = 0;
1824                 cmd->duplex = 0xff;
1825         }
1826         cmd->maxtxpkt = 0;
1827         cmd->maxrxpkt = 0;
1828         return 0;
1829 }
1830
1831 static int b44_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1832 {
1833         struct b44 *bp = netdev_priv(dev);
1834
1835         /* We do not support gigabit. */
1836         if (cmd->autoneg == AUTONEG_ENABLE) {
1837                 if (cmd->advertising &
1838                     (ADVERTISED_1000baseT_Half |
1839                      ADVERTISED_1000baseT_Full))
1840                         return -EINVAL;
1841         } else if ((cmd->speed != SPEED_100 &&
1842                     cmd->speed != SPEED_10) ||
1843                    (cmd->duplex != DUPLEX_HALF &&
1844                     cmd->duplex != DUPLEX_FULL)) {
1845                         return -EINVAL;
1846         }
1847
1848         spin_lock_irq(&bp->lock);
1849
1850         if (cmd->autoneg == AUTONEG_ENABLE) {
1851                 bp->flags &= ~(B44_FLAG_FORCE_LINK |
1852                                B44_FLAG_100_BASE_T |
1853                                B44_FLAG_FULL_DUPLEX |
1854                                B44_FLAG_ADV_10HALF |
1855                                B44_FLAG_ADV_10FULL |
1856                                B44_FLAG_ADV_100HALF |
1857                                B44_FLAG_ADV_100FULL);
1858                 if (cmd->advertising == 0) {
1859                         bp->flags |= (B44_FLAG_ADV_10HALF |
1860                                       B44_FLAG_ADV_10FULL |
1861                                       B44_FLAG_ADV_100HALF |
1862                                       B44_FLAG_ADV_100FULL);
1863                 } else {
1864                         if (cmd->advertising & ADVERTISED_10baseT_Half)
1865                                 bp->flags |= B44_FLAG_ADV_10HALF;
1866                         if (cmd->advertising & ADVERTISED_10baseT_Full)
1867                                 bp->flags |= B44_FLAG_ADV_10FULL;
1868                         if (cmd->advertising & ADVERTISED_100baseT_Half)
1869                                 bp->flags |= B44_FLAG_ADV_100HALF;
1870                         if (cmd->advertising & ADVERTISED_100baseT_Full)
1871                                 bp->flags |= B44_FLAG_ADV_100FULL;
1872                 }
1873         } else {
1874                 bp->flags |= B44_FLAG_FORCE_LINK;
1875                 bp->flags &= ~(B44_FLAG_100_BASE_T | B44_FLAG_FULL_DUPLEX);
1876                 if (cmd->speed == SPEED_100)
1877                         bp->flags |= B44_FLAG_100_BASE_T;
1878                 if (cmd->duplex == DUPLEX_FULL)
1879                         bp->flags |= B44_FLAG_FULL_DUPLEX;
1880         }
1881
1882         if (netif_running(dev))
1883                 b44_setup_phy(bp);
1884
1885         spin_unlock_irq(&bp->lock);
1886
1887         return 0;
1888 }
1889
1890 static void b44_get_ringparam(struct net_device *dev,
1891                               struct ethtool_ringparam *ering)
1892 {
1893         struct b44 *bp = netdev_priv(dev);
1894
1895         ering->rx_max_pending = B44_RX_RING_SIZE - 1;
1896         ering->rx_pending = bp->rx_pending;
1897
1898         /* XXX ethtool lacks a tx_max_pending, oops... */
1899 }
1900
1901 static int b44_set_ringparam(struct net_device *dev,
1902                              struct ethtool_ringparam *ering)
1903 {
1904         struct b44 *bp = netdev_priv(dev);
1905
1906         if ((ering->rx_pending > B44_RX_RING_SIZE - 1) ||
1907             (ering->rx_mini_pending != 0) ||
1908             (ering->rx_jumbo_pending != 0) ||
1909             (ering->tx_pending > B44_TX_RING_SIZE - 1))
1910                 return -EINVAL;
1911
1912         spin_lock_irq(&bp->lock);
1913
1914         bp->rx_pending = ering->rx_pending;
1915         bp->tx_pending = ering->tx_pending;
1916
1917         b44_halt(bp);
1918         b44_init_rings(bp);
1919         b44_init_hw(bp, B44_FULL_RESET);
1920         netif_wake_queue(bp->dev);
1921         spin_unlock_irq(&bp->lock);
1922
1923         b44_enable_ints(bp);
1924
1925         return 0;
1926 }
1927
1928 static void b44_get_pauseparam(struct net_device *dev,
1929                                 struct ethtool_pauseparam *epause)
1930 {
1931         struct b44 *bp = netdev_priv(dev);
1932
1933         epause->autoneg =
1934                 (bp->flags & B44_FLAG_PAUSE_AUTO) != 0;
1935         epause->rx_pause =
1936                 (bp->flags & B44_FLAG_RX_PAUSE) != 0;
1937         epause->tx_pause =
1938                 (bp->flags & B44_FLAG_TX_PAUSE) != 0;
1939 }
1940
1941 static int b44_set_pauseparam(struct net_device *dev,
1942                                 struct ethtool_pauseparam *epause)
1943 {
1944         struct b44 *bp = netdev_priv(dev);
1945
1946         spin_lock_irq(&bp->lock);
1947         if (epause->autoneg)
1948                 bp->flags |= B44_FLAG_PAUSE_AUTO;
1949         else
1950                 bp->flags &= ~B44_FLAG_PAUSE_AUTO;
1951         if (epause->rx_pause)
1952                 bp->flags |= B44_FLAG_RX_PAUSE;
1953         else
1954                 bp->flags &= ~B44_FLAG_RX_PAUSE;
1955         if (epause->tx_pause)
1956                 bp->flags |= B44_FLAG_TX_PAUSE;
1957         else
1958                 bp->flags &= ~B44_FLAG_TX_PAUSE;
1959         if (bp->flags & B44_FLAG_PAUSE_AUTO) {
1960                 b44_halt(bp);
1961                 b44_init_rings(bp);
1962                 b44_init_hw(bp, B44_FULL_RESET);
1963         } else {
1964                 __b44_set_flow_ctrl(bp, bp->flags);
1965         }
1966         spin_unlock_irq(&bp->lock);
1967
1968         b44_enable_ints(bp);
1969
1970         return 0;
1971 }
1972
1973 static void b44_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1974 {
1975         switch(stringset) {
1976         case ETH_SS_STATS:
1977                 memcpy(data, *b44_gstrings, sizeof(b44_gstrings));
1978                 break;
1979         }
1980 }
1981
1982 static int b44_get_sset_count(struct net_device *dev, int sset)
1983 {
1984         switch (sset) {
1985         case ETH_SS_STATS:
1986                 return ARRAY_SIZE(b44_gstrings);
1987         default:
1988                 return -EOPNOTSUPP;
1989         }
1990 }
1991
1992 static void b44_get_ethtool_stats(struct net_device *dev,
1993                                   struct ethtool_stats *stats, u64 *data)
1994 {
1995         struct b44 *bp = netdev_priv(dev);
1996         u32 *val = &bp->hw_stats.tx_good_octets;
1997         u32 i;
1998
1999         spin_lock_irq(&bp->lock);
2000
2001         b44_stats_update(bp);
2002
2003         for (i = 0; i < ARRAY_SIZE(b44_gstrings); i++)
2004                 *data++ = *val++;
2005
2006         spin_unlock_irq(&bp->lock);
2007 }
2008
2009 static void b44_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2010 {
2011         struct b44 *bp = netdev_priv(dev);
2012
2013         wol->supported = WAKE_MAGIC;
2014         if (bp->flags & B44_FLAG_WOL_ENABLE)
2015                 wol->wolopts = WAKE_MAGIC;
2016         else
2017                 wol->wolopts = 0;
2018         memset(&wol->sopass, 0, sizeof(wol->sopass));
2019 }
2020
2021 static int b44_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2022 {
2023         struct b44 *bp = netdev_priv(dev);
2024
2025         spin_lock_irq(&bp->lock);
2026         if (wol->wolopts & WAKE_MAGIC)
2027                 bp->flags |= B44_FLAG_WOL_ENABLE;
2028         else
2029                 bp->flags &= ~B44_FLAG_WOL_ENABLE;
2030         spin_unlock_irq(&bp->lock);
2031
2032         return 0;
2033 }
2034
2035 static const struct ethtool_ops b44_ethtool_ops = {
2036         .get_drvinfo            = b44_get_drvinfo,
2037         .get_settings           = b44_get_settings,
2038         .set_settings           = b44_set_settings,
2039         .nway_reset             = b44_nway_reset,
2040         .get_link               = ethtool_op_get_link,
2041         .get_wol                = b44_get_wol,
2042         .set_wol                = b44_set_wol,
2043         .get_ringparam          = b44_get_ringparam,
2044         .set_ringparam          = b44_set_ringparam,
2045         .get_pauseparam         = b44_get_pauseparam,
2046         .set_pauseparam         = b44_set_pauseparam,
2047         .get_msglevel           = b44_get_msglevel,
2048         .set_msglevel           = b44_set_msglevel,
2049         .get_strings            = b44_get_strings,
2050         .get_sset_count         = b44_get_sset_count,
2051         .get_ethtool_stats      = b44_get_ethtool_stats,
2052 };
2053
2054 static int b44_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2055 {
2056         struct mii_ioctl_data *data = if_mii(ifr);
2057         struct b44 *bp = netdev_priv(dev);
2058         int err = -EINVAL;
2059
2060         if (!netif_running(dev))
2061                 goto out;
2062
2063         spin_lock_irq(&bp->lock);
2064         err = generic_mii_ioctl(&bp->mii_if, data, cmd, NULL);
2065         spin_unlock_irq(&bp->lock);
2066 out:
2067         return err;
2068 }
2069
2070 static int __devinit b44_get_invariants(struct b44 *bp)
2071 {
2072         struct ssb_device *sdev = bp->sdev;
2073         int err = 0;
2074         u8 *addr;
2075
2076         bp->dma_offset = ssb_dma_translation(sdev);
2077
2078         if (sdev->bus->bustype == SSB_BUSTYPE_SSB &&
2079             instance > 1) {
2080                 addr = sdev->bus->sprom.et1mac;
2081                 bp->phy_addr = sdev->bus->sprom.et1phyaddr;
2082         } else {
2083                 addr = sdev->bus->sprom.et0mac;
2084                 bp->phy_addr = sdev->bus->sprom.et0phyaddr;
2085         }
2086         /* Some ROMs have buggy PHY addresses with the high
2087          * bits set (sign extension?). Truncate them to a
2088          * valid PHY address. */
2089         bp->phy_addr &= 0x1F;
2090
2091         memcpy(bp->dev->dev_addr, addr, 6);
2092
2093         if (!is_valid_ether_addr(&bp->dev->dev_addr[0])){
2094                 printk(KERN_ERR PFX "Invalid MAC address found in EEPROM\n");
2095                 return -EINVAL;
2096         }
2097
2098         memcpy(bp->dev->perm_addr, bp->dev->dev_addr, bp->dev->addr_len);
2099
2100         bp->imask = IMASK_DEF;
2101
2102         /* XXX - really required?
2103            bp->flags |= B44_FLAG_BUGGY_TXPTR;
2104         */
2105
2106         if (bp->sdev->id.revision >= 7)
2107                 bp->flags |= B44_FLAG_B0_ANDLATER;
2108
2109         return err;
2110 }
2111
2112 static int __devinit b44_init_one(struct ssb_device *sdev,
2113                                   const struct ssb_device_id *ent)
2114 {
2115         static int b44_version_printed = 0;
2116         struct net_device *dev;
2117         struct b44 *bp;
2118         int err;
2119
2120         instance++;
2121
2122         if (b44_version_printed++ == 0)
2123                 printk(KERN_INFO "%s", version);
2124
2125
2126         dev = alloc_etherdev(sizeof(*bp));
2127         if (!dev) {
2128                 dev_err(sdev->dev, "Etherdev alloc failed, aborting.\n");
2129                 err = -ENOMEM;
2130                 goto out;
2131         }
2132
2133         SET_NETDEV_DEV(dev, sdev->dev);
2134
2135         /* No interesting netdevice features in this card... */
2136         dev->features |= 0;
2137
2138         bp = netdev_priv(dev);
2139         bp->sdev = sdev;
2140         bp->dev = dev;
2141
2142         bp->msg_enable = netif_msg_init(b44_debug, B44_DEF_MSG_ENABLE);
2143
2144         spin_lock_init(&bp->lock);
2145
2146         bp->rx_pending = B44_DEF_RX_RING_PENDING;
2147         bp->tx_pending = B44_DEF_TX_RING_PENDING;
2148
2149         dev->open = b44_open;
2150         dev->stop = b44_close;
2151         dev->hard_start_xmit = b44_start_xmit;
2152         dev->get_stats = b44_get_stats;
2153         dev->set_multicast_list = b44_set_rx_mode;
2154         dev->set_mac_address = b44_set_mac_addr;
2155         dev->do_ioctl = b44_ioctl;
2156         dev->tx_timeout = b44_tx_timeout;
2157         netif_napi_add(dev, &bp->napi, b44_poll, 64);
2158         dev->watchdog_timeo = B44_TX_TIMEOUT;
2159 #ifdef CONFIG_NET_POLL_CONTROLLER
2160         dev->poll_controller = b44_poll_controller;
2161 #endif
2162         dev->change_mtu = b44_change_mtu;
2163         dev->irq = sdev->irq;
2164         SET_ETHTOOL_OPS(dev, &b44_ethtool_ops);
2165
2166         netif_carrier_off(dev);
2167
2168         err = ssb_bus_powerup(sdev->bus, 0);
2169         if (err) {
2170                 dev_err(sdev->dev,
2171                         "Failed to powerup the bus\n");
2172                 goto err_out_free_dev;
2173         }
2174         err = ssb_dma_set_mask(sdev, DMA_30BIT_MASK);
2175         if (err) {
2176                 dev_err(sdev->dev,
2177                         "Required 30BIT DMA mask unsupported by the system.\n");
2178                 goto err_out_powerdown;
2179         }
2180         err = b44_get_invariants(bp);
2181         if (err) {
2182                 dev_err(sdev->dev,
2183                         "Problem fetching invariants of chip, aborting.\n");
2184                 goto err_out_powerdown;
2185         }
2186
2187         bp->mii_if.dev = dev;
2188         bp->mii_if.mdio_read = b44_mii_read;
2189         bp->mii_if.mdio_write = b44_mii_write;
2190         bp->mii_if.phy_id = bp->phy_addr;
2191         bp->mii_if.phy_id_mask = 0x1f;
2192         bp->mii_if.reg_num_mask = 0x1f;
2193
2194         /* By default, advertise all speed/duplex settings. */
2195         bp->flags |= (B44_FLAG_ADV_10HALF | B44_FLAG_ADV_10FULL |
2196                       B44_FLAG_ADV_100HALF | B44_FLAG_ADV_100FULL);
2197
2198         /* By default, auto-negotiate PAUSE. */
2199         bp->flags |= B44_FLAG_PAUSE_AUTO;
2200
2201         err = register_netdev(dev);
2202         if (err) {
2203                 dev_err(sdev->dev, "Cannot register net device, aborting.\n");
2204                 goto err_out_powerdown;
2205         }
2206
2207         ssb_set_drvdata(sdev, dev);
2208
2209         /* Chip reset provides power to the b44 MAC & PCI cores, which
2210          * is necessary for MAC register access.
2211          */
2212         b44_chip_reset(bp, B44_CHIP_RESET_FULL);
2213
2214         printk(KERN_INFO "%s: Broadcom 44xx/47xx 10/100BaseT Ethernet %pM\n",
2215                dev->name, dev->dev_addr);
2216
2217         return 0;
2218
2219 err_out_powerdown:
2220         ssb_bus_may_powerdown(sdev->bus);
2221
2222 err_out_free_dev:
2223         free_netdev(dev);
2224
2225 out:
2226         return err;
2227 }
2228
2229 static void __devexit b44_remove_one(struct ssb_device *sdev)
2230 {
2231         struct net_device *dev = ssb_get_drvdata(sdev);
2232
2233         unregister_netdev(dev);
2234         ssb_bus_may_powerdown(sdev->bus);
2235         free_netdev(dev);
2236         ssb_pcihost_set_power_state(sdev, PCI_D3hot);
2237         ssb_set_drvdata(sdev, NULL);
2238 }
2239
2240 static int b44_suspend(struct ssb_device *sdev, pm_message_t state)
2241 {
2242         struct net_device *dev = ssb_get_drvdata(sdev);
2243         struct b44 *bp = netdev_priv(dev);
2244
2245         if (!netif_running(dev))
2246                 return 0;
2247
2248         del_timer_sync(&bp->timer);
2249
2250         spin_lock_irq(&bp->lock);
2251
2252         b44_halt(bp);
2253         netif_carrier_off(bp->dev);
2254         netif_device_detach(bp->dev);
2255         b44_free_rings(bp);
2256
2257         spin_unlock_irq(&bp->lock);
2258
2259         free_irq(dev->irq, dev);
2260         if (bp->flags & B44_FLAG_WOL_ENABLE) {
2261                 b44_init_hw(bp, B44_PARTIAL_RESET);
2262                 b44_setup_wol(bp);
2263         }
2264
2265         ssb_pcihost_set_power_state(sdev, PCI_D3hot);
2266         return 0;
2267 }
2268
2269 static int b44_resume(struct ssb_device *sdev)
2270 {
2271         struct net_device *dev = ssb_get_drvdata(sdev);
2272         struct b44 *bp = netdev_priv(dev);
2273         int rc = 0;
2274
2275         rc = ssb_bus_powerup(sdev->bus, 0);
2276         if (rc) {
2277                 dev_err(sdev->dev,
2278                         "Failed to powerup the bus\n");
2279                 return rc;
2280         }
2281
2282         if (!netif_running(dev))
2283                 return 0;
2284
2285         rc = request_irq(dev->irq, b44_interrupt, IRQF_SHARED, dev->name, dev);
2286         if (rc) {
2287                 printk(KERN_ERR PFX "%s: request_irq failed\n", dev->name);
2288                 return rc;
2289         }
2290
2291         spin_lock_irq(&bp->lock);
2292
2293         b44_init_rings(bp);
2294         b44_init_hw(bp, B44_FULL_RESET);
2295         netif_device_attach(bp->dev);
2296         spin_unlock_irq(&bp->lock);
2297
2298         b44_enable_ints(bp);
2299         netif_wake_queue(dev);
2300
2301         mod_timer(&bp->timer, jiffies + 1);
2302
2303         return 0;
2304 }
2305
2306 static struct ssb_driver b44_ssb_driver = {
2307         .name           = DRV_MODULE_NAME,
2308         .id_table       = b44_ssb_tbl,
2309         .probe          = b44_init_one,
2310         .remove         = __devexit_p(b44_remove_one),
2311         .suspend        = b44_suspend,
2312         .resume         = b44_resume,
2313 };
2314
2315 static inline int b44_pci_init(void)
2316 {
2317         int err = 0;
2318 #ifdef CONFIG_B44_PCI
2319         err = ssb_pcihost_register(&b44_pci_driver);
2320 #endif
2321         return err;
2322 }
2323
2324 static inline void b44_pci_exit(void)
2325 {
2326 #ifdef CONFIG_B44_PCI
2327         ssb_pcihost_unregister(&b44_pci_driver);
2328 #endif
2329 }
2330
2331 static int __init b44_init(void)
2332 {
2333         unsigned int dma_desc_align_size = dma_get_cache_alignment();
2334         int err;
2335
2336         /* Setup paramaters for syncing RX/TX DMA descriptors */
2337         dma_desc_align_mask = ~(dma_desc_align_size - 1);
2338         dma_desc_sync_size = max_t(unsigned int, dma_desc_align_size, sizeof(struct dma_desc));
2339
2340         err = b44_pci_init();
2341         if (err)
2342                 return err;
2343         err = ssb_driver_register(&b44_ssb_driver);
2344         if (err)
2345                 b44_pci_exit();
2346         return err;
2347 }
2348
2349 static void __exit b44_cleanup(void)
2350 {
2351         ssb_driver_unregister(&b44_ssb_driver);
2352         b44_pci_exit();
2353 }
2354
2355 module_init(b44_init);
2356 module_exit(b44_cleanup);
2357