2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * $Id: mthca_eq.c 1382 2004-12-24 02:21:02Z roland $
35 #include <linux/init.h>
36 #include <linux/errno.h>
37 #include <linux/interrupt.h>
38 #include <linux/pci.h>
40 #include "mthca_dev.h"
41 #include "mthca_cmd.h"
42 #include "mthca_config_reg.h"
45 MTHCA_NUM_ASYNC_EQE = 0x80,
46 MTHCA_NUM_CMD_EQE = 0x80,
47 MTHCA_EQ_ENTRY_SIZE = 0x20
51 * Must be packed because start is 64 bits but only aligned to 32 bits.
53 struct mthca_eq_context {
57 u32 tavor_pd; /* reserved for Arbel */
60 u32 arbel_pd; /* lost_count for Tavor */
66 } __attribute__((packed));
68 #define MTHCA_EQ_STATUS_OK ( 0 << 28)
69 #define MTHCA_EQ_STATUS_OVERFLOW ( 9 << 28)
70 #define MTHCA_EQ_STATUS_WRITE_FAIL (10 << 28)
71 #define MTHCA_EQ_OWNER_SW ( 0 << 24)
72 #define MTHCA_EQ_OWNER_HW ( 1 << 24)
73 #define MTHCA_EQ_FLAG_TR ( 1 << 18)
74 #define MTHCA_EQ_FLAG_OI ( 1 << 17)
75 #define MTHCA_EQ_STATE_ARMED ( 1 << 8)
76 #define MTHCA_EQ_STATE_FIRED ( 2 << 8)
77 #define MTHCA_EQ_STATE_ALWAYS_ARMED ( 3 << 8)
78 #define MTHCA_EQ_STATE_ARBEL ( 8 << 8)
81 MTHCA_EVENT_TYPE_COMP = 0x00,
82 MTHCA_EVENT_TYPE_PATH_MIG = 0x01,
83 MTHCA_EVENT_TYPE_COMM_EST = 0x02,
84 MTHCA_EVENT_TYPE_SQ_DRAINED = 0x03,
85 MTHCA_EVENT_TYPE_SRQ_LAST_WQE = 0x13,
86 MTHCA_EVENT_TYPE_CQ_ERROR = 0x04,
87 MTHCA_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
88 MTHCA_EVENT_TYPE_EEC_CATAS_ERROR = 0x06,
89 MTHCA_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
90 MTHCA_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
91 MTHCA_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
92 MTHCA_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
93 MTHCA_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08,
94 MTHCA_EVENT_TYPE_PORT_CHANGE = 0x09,
95 MTHCA_EVENT_TYPE_EQ_OVERFLOW = 0x0f,
96 MTHCA_EVENT_TYPE_ECC_DETECT = 0x0e,
97 MTHCA_EVENT_TYPE_CMD = 0x0a
100 #define MTHCA_ASYNC_EVENT_MASK ((1ULL << MTHCA_EVENT_TYPE_PATH_MIG) | \
101 (1ULL << MTHCA_EVENT_TYPE_COMM_EST) | \
102 (1ULL << MTHCA_EVENT_TYPE_SQ_DRAINED) | \
103 (1ULL << MTHCA_EVENT_TYPE_CQ_ERROR) | \
104 (1ULL << MTHCA_EVENT_TYPE_WQ_CATAS_ERROR) | \
105 (1ULL << MTHCA_EVENT_TYPE_EEC_CATAS_ERROR) | \
106 (1ULL << MTHCA_EVENT_TYPE_PATH_MIG_FAILED) | \
107 (1ULL << MTHCA_EVENT_TYPE_WQ_INVAL_REQ_ERROR) | \
108 (1ULL << MTHCA_EVENT_TYPE_WQ_ACCESS_ERROR) | \
109 (1ULL << MTHCA_EVENT_TYPE_LOCAL_CATAS_ERROR) | \
110 (1ULL << MTHCA_EVENT_TYPE_PORT_CHANGE) | \
111 (1ULL << MTHCA_EVENT_TYPE_ECC_DETECT))
112 #define MTHCA_SRQ_EVENT_MASK (1ULL << MTHCA_EVENT_TYPE_SRQ_CATAS_ERROR) | \
113 (1ULL << MTHCA_EVENT_TYPE_SRQ_LAST_WQE)
114 #define MTHCA_CMD_EVENT_MASK (1ULL << MTHCA_EVENT_TYPE_CMD)
116 #define MTHCA_EQ_DB_INC_CI (1 << 24)
117 #define MTHCA_EQ_DB_REQ_NOT (2 << 24)
118 #define MTHCA_EQ_DB_DISARM_CQ (3 << 24)
119 #define MTHCA_EQ_DB_SET_CI (4 << 24)
120 #define MTHCA_EQ_DB_ALWAYS_ARM (5 << 24)
131 } __attribute__((packed)) comp;
139 } __attribute__((packed)) cmd;
142 } __attribute__((packed)) qp;
148 } __attribute__((packed)) cq_err;
152 } __attribute__((packed)) port_change;
156 } __attribute__((packed));
158 #define MTHCA_EQ_ENTRY_OWNER_SW (0 << 7)
159 #define MTHCA_EQ_ENTRY_OWNER_HW (1 << 7)
161 static inline u64 async_mask(struct mthca_dev *dev)
163 return dev->mthca_flags & MTHCA_FLAG_SRQ ?
164 MTHCA_ASYNC_EVENT_MASK | MTHCA_SRQ_EVENT_MASK :
165 MTHCA_ASYNC_EVENT_MASK;
168 static inline void tavor_set_eq_ci(struct mthca_dev *dev, struct mthca_eq *eq, u32 ci)
172 doorbell[0] = cpu_to_be32(MTHCA_EQ_DB_SET_CI | eq->eqn);
173 doorbell[1] = cpu_to_be32(ci & (eq->nent - 1));
176 * This barrier makes sure that all updates to ownership bits
177 * done by set_eqe_hw() hit memory before the consumer index
178 * is updated. set_eq_ci() allows the HCA to possibly write
179 * more EQ entries, and we want to avoid the exceedingly
180 * unlikely possibility of the HCA writing an entry and then
181 * having set_eqe_hw() overwrite the owner field.
184 mthca_write64(doorbell,
185 dev->kar + MTHCA_EQ_DOORBELL,
186 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
189 static inline void arbel_set_eq_ci(struct mthca_dev *dev, struct mthca_eq *eq, u32 ci)
191 /* See comment in tavor_set_eq_ci() above. */
193 __raw_writel(cpu_to_be32(ci), dev->eq_regs.arbel.eq_set_ci_base +
195 /* We still want ordering, just not swabbing, so add a barrier */
199 static inline void set_eq_ci(struct mthca_dev *dev, struct mthca_eq *eq, u32 ci)
201 if (mthca_is_memfree(dev))
202 arbel_set_eq_ci(dev, eq, ci);
204 tavor_set_eq_ci(dev, eq, ci);
207 static inline void tavor_eq_req_not(struct mthca_dev *dev, int eqn)
211 doorbell[0] = cpu_to_be32(MTHCA_EQ_DB_REQ_NOT | eqn);
214 mthca_write64(doorbell,
215 dev->kar + MTHCA_EQ_DOORBELL,
216 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
219 static inline void arbel_eq_req_not(struct mthca_dev *dev, u32 eqn_mask)
221 writel(eqn_mask, dev->eq_regs.arbel.eq_arm);
224 static inline void disarm_cq(struct mthca_dev *dev, int eqn, int cqn)
226 if (!mthca_is_memfree(dev)) {
229 doorbell[0] = cpu_to_be32(MTHCA_EQ_DB_DISARM_CQ | eqn);
230 doorbell[1] = cpu_to_be32(cqn);
232 mthca_write64(doorbell,
233 dev->kar + MTHCA_EQ_DOORBELL,
234 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
238 static inline struct mthca_eqe *get_eqe(struct mthca_eq *eq, u32 entry)
240 unsigned long off = (entry & (eq->nent - 1)) * MTHCA_EQ_ENTRY_SIZE;
241 return eq->page_list[off / PAGE_SIZE].buf + off % PAGE_SIZE;
244 static inline struct mthca_eqe* next_eqe_sw(struct mthca_eq *eq)
246 struct mthca_eqe* eqe;
247 eqe = get_eqe(eq, eq->cons_index);
248 return (MTHCA_EQ_ENTRY_OWNER_HW & eqe->owner) ? NULL : eqe;
251 static inline void set_eqe_hw(struct mthca_eqe *eqe)
253 eqe->owner = MTHCA_EQ_ENTRY_OWNER_HW;
256 static void port_change(struct mthca_dev *dev, int port, int active)
258 struct ib_event record;
260 mthca_dbg(dev, "Port change to %s for port %d\n",
261 active ? "active" : "down", port);
263 record.device = &dev->ib_dev;
264 record.event = active ? IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
265 record.element.port_num = port;
267 ib_dispatch_event(&record);
270 static int mthca_eq_int(struct mthca_dev *dev, struct mthca_eq *eq)
272 struct mthca_eqe *eqe;
276 while ((eqe = next_eqe_sw(eq))) {
280 * Make sure we read EQ entry contents after we've
281 * checked the ownership bit.
286 case MTHCA_EVENT_TYPE_COMP:
287 disarm_cqn = be32_to_cpu(eqe->event.comp.cqn) & 0xffffff;
288 disarm_cq(dev, eq->eqn, disarm_cqn);
289 mthca_cq_event(dev, disarm_cqn);
292 case MTHCA_EVENT_TYPE_PATH_MIG:
293 mthca_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff,
297 case MTHCA_EVENT_TYPE_COMM_EST:
298 mthca_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff,
302 case MTHCA_EVENT_TYPE_SQ_DRAINED:
303 mthca_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff,
304 IB_EVENT_SQ_DRAINED);
307 case MTHCA_EVENT_TYPE_WQ_CATAS_ERROR:
308 mthca_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff,
312 case MTHCA_EVENT_TYPE_PATH_MIG_FAILED:
313 mthca_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff,
314 IB_EVENT_PATH_MIG_ERR);
317 case MTHCA_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
318 mthca_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff,
319 IB_EVENT_QP_REQ_ERR);
322 case MTHCA_EVENT_TYPE_WQ_ACCESS_ERROR:
323 mthca_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff,
324 IB_EVENT_QP_ACCESS_ERR);
327 case MTHCA_EVENT_TYPE_CMD:
329 be16_to_cpu(eqe->event.cmd.token),
330 eqe->event.cmd.status,
331 be64_to_cpu(eqe->event.cmd.out_param));
333 * cmd_event() may add more commands.
334 * The card will think the queue has overflowed if
335 * we don't tell it we've been processing events.
340 case MTHCA_EVENT_TYPE_PORT_CHANGE:
342 (be32_to_cpu(eqe->event.port_change.port) >> 28) & 3,
343 eqe->subtype == 0x4);
346 case MTHCA_EVENT_TYPE_CQ_ERROR:
347 mthca_warn(dev, "CQ %s on CQN %06x\n",
348 eqe->event.cq_err.syndrome == 1 ?
349 "overrun" : "access violation",
350 be32_to_cpu(eqe->event.cq_err.cqn) & 0xffffff);
353 case MTHCA_EVENT_TYPE_EQ_OVERFLOW:
354 mthca_warn(dev, "EQ overrun on EQN %d\n", eq->eqn);
357 case MTHCA_EVENT_TYPE_EEC_CATAS_ERROR:
358 case MTHCA_EVENT_TYPE_SRQ_CATAS_ERROR:
359 case MTHCA_EVENT_TYPE_LOCAL_CATAS_ERROR:
360 case MTHCA_EVENT_TYPE_ECC_DETECT:
362 mthca_warn(dev, "Unhandled event %02x(%02x) on EQ %d\n",
363 eqe->type, eqe->subtype, eq->eqn);
371 if (unlikely(set_ci)) {
373 * Conditional on hca_type is OK here because
374 * this is a rare case, not the fast path.
376 set_eq_ci(dev, eq, eq->cons_index);
382 * Rely on caller to set consumer index so that we don't have
383 * to test hca_type in our interrupt handling fast path.
388 static irqreturn_t mthca_tavor_interrupt(int irq, void *dev_ptr, struct pt_regs *regs)
390 struct mthca_dev *dev = dev_ptr;
394 if (dev->eq_table.clr_mask)
395 writel(dev->eq_table.clr_mask, dev->eq_table.clr_int);
397 ecr = readl(dev->eq_regs.tavor.ecr_base + 4);
399 writel(ecr, dev->eq_regs.tavor.ecr_base +
400 MTHCA_ECR_CLR_BASE - MTHCA_ECR_BASE + 4);
402 for (i = 0; i < MTHCA_NUM_EQ; ++i)
403 if (ecr & dev->eq_table.eq[i].eqn_mask &&
404 mthca_eq_int(dev, &dev->eq_table.eq[i])) {
405 tavor_set_eq_ci(dev, &dev->eq_table.eq[i],
406 dev->eq_table.eq[i].cons_index);
407 tavor_eq_req_not(dev, dev->eq_table.eq[i].eqn);
411 return IRQ_RETVAL(ecr);
414 static irqreturn_t mthca_tavor_msi_x_interrupt(int irq, void *eq_ptr,
415 struct pt_regs *regs)
417 struct mthca_eq *eq = eq_ptr;
418 struct mthca_dev *dev = eq->dev;
420 mthca_eq_int(dev, eq);
421 tavor_set_eq_ci(dev, eq, eq->cons_index);
422 tavor_eq_req_not(dev, eq->eqn);
424 /* MSI-X vectors always belong to us */
428 static irqreturn_t mthca_arbel_interrupt(int irq, void *dev_ptr, struct pt_regs *regs)
430 struct mthca_dev *dev = dev_ptr;
434 if (dev->eq_table.clr_mask)
435 writel(dev->eq_table.clr_mask, dev->eq_table.clr_int);
437 for (i = 0; i < MTHCA_NUM_EQ; ++i)
438 if (mthca_eq_int(dev, &dev->eq_table.eq[i])) {
440 arbel_set_eq_ci(dev, &dev->eq_table.eq[i],
441 dev->eq_table.eq[i].cons_index);
444 arbel_eq_req_not(dev, dev->eq_table.arm_mask);
446 return IRQ_RETVAL(work);
449 static irqreturn_t mthca_arbel_msi_x_interrupt(int irq, void *eq_ptr,
450 struct pt_regs *regs)
452 struct mthca_eq *eq = eq_ptr;
453 struct mthca_dev *dev = eq->dev;
455 mthca_eq_int(dev, eq);
456 arbel_set_eq_ci(dev, eq, eq->cons_index);
457 arbel_eq_req_not(dev, eq->eqn_mask);
459 /* MSI-X vectors always belong to us */
463 static int __devinit mthca_create_eq(struct mthca_dev *dev,
468 int npages = (nent * MTHCA_EQ_ENTRY_SIZE + PAGE_SIZE - 1) /
470 u64 *dma_list = NULL;
472 void *mailbox = NULL;
473 struct mthca_eq_context *eq_context;
478 /* Make sure EQ size is aligned to a power of 2 size. */
479 for (i = 1; i < nent; i <<= 1)
485 eq->page_list = kmalloc(npages * sizeof *eq->page_list,
490 for (i = 0; i < npages; ++i)
491 eq->page_list[i].buf = NULL;
493 dma_list = kmalloc(npages * sizeof *dma_list, GFP_KERNEL);
497 mailbox = kmalloc(sizeof *eq_context + MTHCA_CMD_MAILBOX_EXTRA,
501 eq_context = MAILBOX_ALIGN(mailbox);
503 for (i = 0; i < npages; ++i) {
504 eq->page_list[i].buf = pci_alloc_consistent(dev->pdev,
506 if (!eq->page_list[i].buf)
510 pci_unmap_addr_set(&eq->page_list[i], mapping, t);
512 memset(eq->page_list[i].buf, 0, PAGE_SIZE);
515 for (i = 0; i < nent; ++i)
516 set_eqe_hw(get_eqe(eq, i));
518 eq->eqn = mthca_alloc(&dev->eq_table.alloc);
522 err = mthca_mr_alloc_phys(dev, dev->driver_pd.pd_num,
523 dma_list, PAGE_SHIFT, npages,
524 0, npages * PAGE_SIZE,
525 MTHCA_MPT_FLAG_LOCAL_WRITE |
526 MTHCA_MPT_FLAG_LOCAL_READ,
529 goto err_out_free_eq;
533 memset(eq_context, 0, sizeof *eq_context);
534 eq_context->flags = cpu_to_be32(MTHCA_EQ_STATUS_OK |
536 MTHCA_EQ_STATE_ARMED |
538 if (mthca_is_memfree(dev))
539 eq_context->flags |= cpu_to_be32(MTHCA_EQ_STATE_ARBEL);
541 eq_context->logsize_usrpage = cpu_to_be32((ffs(nent) - 1) << 24);
542 if (mthca_is_memfree(dev)) {
543 eq_context->arbel_pd = cpu_to_be32(dev->driver_pd.pd_num);
545 eq_context->logsize_usrpage |= cpu_to_be32(dev->driver_uar.index);
546 eq_context->tavor_pd = cpu_to_be32(dev->driver_pd.pd_num);
548 eq_context->intr = intr;
549 eq_context->lkey = cpu_to_be32(eq->mr.ibmr.lkey);
551 err = mthca_SW2HW_EQ(dev, eq_context, eq->eqn, &status);
553 mthca_warn(dev, "SW2HW_EQ failed (%d)\n", err);
554 goto err_out_free_mr;
557 mthca_warn(dev, "SW2HW_EQ returned status 0x%02x\n",
560 goto err_out_free_mr;
566 eq->eqn_mask = swab32(1 << eq->eqn);
569 dev->eq_table.arm_mask |= eq->eqn_mask;
571 mthca_dbg(dev, "Allocated EQ %d with %d entries\n",
577 mthca_free_mr(dev, &eq->mr);
580 mthca_free(&dev->eq_table.alloc, eq->eqn);
583 for (i = 0; i < npages; ++i)
584 if (eq->page_list[i].buf)
585 pci_free_consistent(dev->pdev, PAGE_SIZE,
586 eq->page_list[i].buf,
587 pci_unmap_addr(&eq->page_list[i],
590 kfree(eq->page_list);
598 static void mthca_free_eq(struct mthca_dev *dev,
601 void *mailbox = NULL;
604 int npages = (eq->nent * MTHCA_EQ_ENTRY_SIZE + PAGE_SIZE - 1) /
608 mailbox = kmalloc(sizeof (struct mthca_eq_context) + MTHCA_CMD_MAILBOX_EXTRA,
613 err = mthca_HW2SW_EQ(dev, MAILBOX_ALIGN(mailbox),
616 mthca_warn(dev, "HW2SW_EQ failed (%d)\n", err);
618 mthca_warn(dev, "HW2SW_EQ returned status 0x%02x\n", status);
620 dev->eq_table.arm_mask &= ~eq->eqn_mask;
623 mthca_dbg(dev, "Dumping EQ context %02x:\n", eq->eqn);
624 for (i = 0; i < sizeof (struct mthca_eq_context) / 4; ++i) {
626 printk("[%02x] ", i * 4);
627 printk(" %08x", be32_to_cpup(MAILBOX_ALIGN(mailbox) + i * 4));
628 if ((i + 1) % 4 == 0)
633 mthca_free_mr(dev, &eq->mr);
634 for (i = 0; i < npages; ++i)
635 pci_free_consistent(dev->pdev, PAGE_SIZE,
636 eq->page_list[i].buf,
637 pci_unmap_addr(&eq->page_list[i], mapping));
639 kfree(eq->page_list);
643 static void mthca_free_irqs(struct mthca_dev *dev)
647 if (dev->eq_table.have_irq)
648 free_irq(dev->pdev->irq, dev);
649 for (i = 0; i < MTHCA_NUM_EQ; ++i)
650 if (dev->eq_table.eq[i].have_irq)
651 free_irq(dev->eq_table.eq[i].msi_x_vector,
652 dev->eq_table.eq + i);
655 static int __devinit mthca_map_reg(struct mthca_dev *dev,
656 unsigned long offset, unsigned long size,
659 unsigned long base = pci_resource_start(dev->pdev, 0);
661 if (!request_mem_region(base + offset, size, DRV_NAME))
664 *map = ioremap(base + offset, size);
666 release_mem_region(base + offset, size);
673 static void mthca_unmap_reg(struct mthca_dev *dev, unsigned long offset,
674 unsigned long size, void __iomem *map)
676 unsigned long base = pci_resource_start(dev->pdev, 0);
678 release_mem_region(base + offset, size);
682 static int __devinit mthca_map_eq_regs(struct mthca_dev *dev)
684 unsigned long mthca_base;
686 mthca_base = pci_resource_start(dev->pdev, 0);
688 if (mthca_is_memfree(dev)) {
690 * We assume that the EQ arm and EQ set CI registers
691 * fall within the first BAR. We can't trust the
692 * values firmware gives us, since those addresses are
693 * valid on the HCA's side of the PCI bus but not
694 * necessarily the host side.
696 if (mthca_map_reg(dev, (pci_resource_len(dev->pdev, 0) - 1) &
697 dev->fw.arbel.clr_int_base, MTHCA_CLR_INT_SIZE,
699 mthca_err(dev, "Couldn't map interrupt clear register, "
705 * Add 4 because we limit ourselves to EQs 0 ... 31,
706 * so we only need the low word of the register.
708 if (mthca_map_reg(dev, ((pci_resource_len(dev->pdev, 0) - 1) &
709 dev->fw.arbel.eq_arm_base) + 4, 4,
710 &dev->eq_regs.arbel.eq_arm)) {
711 mthca_err(dev, "Couldn't map EQ arm register, aborting.\n");
712 mthca_unmap_reg(dev, (pci_resource_len(dev->pdev, 0) - 1) &
713 dev->fw.arbel.clr_int_base, MTHCA_CLR_INT_SIZE,
718 if (mthca_map_reg(dev, (pci_resource_len(dev->pdev, 0) - 1) &
719 dev->fw.arbel.eq_set_ci_base,
720 MTHCA_EQ_SET_CI_SIZE,
721 &dev->eq_regs.arbel.eq_set_ci_base)) {
722 mthca_err(dev, "Couldn't map EQ CI register, aborting.\n");
723 mthca_unmap_reg(dev, ((pci_resource_len(dev->pdev, 0) - 1) &
724 dev->fw.arbel.eq_arm_base) + 4, 4,
725 dev->eq_regs.arbel.eq_arm);
726 mthca_unmap_reg(dev, (pci_resource_len(dev->pdev, 0) - 1) &
727 dev->fw.arbel.clr_int_base, MTHCA_CLR_INT_SIZE,
732 if (mthca_map_reg(dev, MTHCA_CLR_INT_BASE, MTHCA_CLR_INT_SIZE,
734 mthca_err(dev, "Couldn't map interrupt clear register, "
739 if (mthca_map_reg(dev, MTHCA_ECR_BASE,
740 MTHCA_ECR_SIZE + MTHCA_ECR_CLR_SIZE,
741 &dev->eq_regs.tavor.ecr_base)) {
742 mthca_err(dev, "Couldn't map ecr register, "
744 mthca_unmap_reg(dev, MTHCA_CLR_INT_BASE, MTHCA_CLR_INT_SIZE,
754 static void __devexit mthca_unmap_eq_regs(struct mthca_dev *dev)
756 if (mthca_is_memfree(dev)) {
757 mthca_unmap_reg(dev, (pci_resource_len(dev->pdev, 0) - 1) &
758 dev->fw.arbel.eq_set_ci_base,
759 MTHCA_EQ_SET_CI_SIZE,
760 dev->eq_regs.arbel.eq_set_ci_base);
761 mthca_unmap_reg(dev, ((pci_resource_len(dev->pdev, 0) - 1) &
762 dev->fw.arbel.eq_arm_base) + 4, 4,
763 dev->eq_regs.arbel.eq_arm);
764 mthca_unmap_reg(dev, (pci_resource_len(dev->pdev, 0) - 1) &
765 dev->fw.arbel.clr_int_base, MTHCA_CLR_INT_SIZE,
768 mthca_unmap_reg(dev, MTHCA_ECR_BASE,
769 MTHCA_ECR_SIZE + MTHCA_ECR_CLR_SIZE,
770 dev->eq_regs.tavor.ecr_base);
771 mthca_unmap_reg(dev, MTHCA_CLR_INT_BASE, MTHCA_CLR_INT_SIZE,
776 int __devinit mthca_map_eq_icm(struct mthca_dev *dev, u64 icm_virt)
782 * We assume that mapping one page is enough for the whole EQ
783 * context table. This is fine with all current HCAs, because
784 * we only use 32 EQs and each EQ uses 32 bytes of context
785 * memory, or 1 KB total.
787 dev->eq_table.icm_virt = icm_virt;
788 dev->eq_table.icm_page = alloc_page(GFP_HIGHUSER);
789 if (!dev->eq_table.icm_page)
791 dev->eq_table.icm_dma = pci_map_page(dev->pdev, dev->eq_table.icm_page, 0,
792 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
793 if (pci_dma_mapping_error(dev->eq_table.icm_dma)) {
794 __free_page(dev->eq_table.icm_page);
798 ret = mthca_MAP_ICM_page(dev, dev->eq_table.icm_dma, icm_virt, &status);
802 pci_unmap_page(dev->pdev, dev->eq_table.icm_dma, PAGE_SIZE,
803 PCI_DMA_BIDIRECTIONAL);
804 __free_page(dev->eq_table.icm_page);
810 void __devexit mthca_unmap_eq_icm(struct mthca_dev *dev)
814 mthca_UNMAP_ICM(dev, dev->eq_table.icm_virt, PAGE_SIZE / 4096, &status);
815 pci_unmap_page(dev->pdev, dev->eq_table.icm_dma, PAGE_SIZE,
816 PCI_DMA_BIDIRECTIONAL);
817 __free_page(dev->eq_table.icm_page);
820 int __devinit mthca_init_eq_table(struct mthca_dev *dev)
827 err = mthca_alloc_init(&dev->eq_table.alloc,
829 dev->limits.num_eqs - 1,
830 dev->limits.reserved_eqs);
834 err = mthca_map_eq_regs(dev);
838 if (dev->mthca_flags & MTHCA_FLAG_MSI ||
839 dev->mthca_flags & MTHCA_FLAG_MSI_X) {
840 dev->eq_table.clr_mask = 0;
842 dev->eq_table.clr_mask =
843 swab32(1 << (dev->eq_table.inta_pin & 31));
844 dev->eq_table.clr_int = dev->clr_base +
845 (dev->eq_table.inta_pin < 31 ? 4 : 0);
848 dev->eq_table.arm_mask = 0;
850 intr = (dev->mthca_flags & MTHCA_FLAG_MSI) ?
851 128 : dev->eq_table.inta_pin;
853 err = mthca_create_eq(dev, dev->limits.num_cqs,
854 (dev->mthca_flags & MTHCA_FLAG_MSI_X) ? 128 : intr,
855 &dev->eq_table.eq[MTHCA_EQ_COMP]);
859 err = mthca_create_eq(dev, MTHCA_NUM_ASYNC_EQE,
860 (dev->mthca_flags & MTHCA_FLAG_MSI_X) ? 129 : intr,
861 &dev->eq_table.eq[MTHCA_EQ_ASYNC]);
865 err = mthca_create_eq(dev, MTHCA_NUM_CMD_EQE,
866 (dev->mthca_flags & MTHCA_FLAG_MSI_X) ? 130 : intr,
867 &dev->eq_table.eq[MTHCA_EQ_CMD]);
871 if (dev->mthca_flags & MTHCA_FLAG_MSI_X) {
872 static const char *eq_name[] = {
873 [MTHCA_EQ_COMP] = DRV_NAME " (comp)",
874 [MTHCA_EQ_ASYNC] = DRV_NAME " (async)",
875 [MTHCA_EQ_CMD] = DRV_NAME " (cmd)"
878 for (i = 0; i < MTHCA_NUM_EQ; ++i) {
879 err = request_irq(dev->eq_table.eq[i].msi_x_vector,
880 mthca_is_memfree(dev) ?
881 mthca_arbel_msi_x_interrupt :
882 mthca_tavor_msi_x_interrupt,
883 0, eq_name[i], dev->eq_table.eq + i);
886 dev->eq_table.eq[i].have_irq = 1;
889 err = request_irq(dev->pdev->irq,
890 mthca_is_memfree(dev) ?
891 mthca_arbel_interrupt :
892 mthca_tavor_interrupt,
893 SA_SHIRQ, DRV_NAME, dev);
896 dev->eq_table.have_irq = 1;
899 err = mthca_MAP_EQ(dev, async_mask(dev),
900 0, dev->eq_table.eq[MTHCA_EQ_ASYNC].eqn, &status);
902 mthca_warn(dev, "MAP_EQ for async EQ %d failed (%d)\n",
903 dev->eq_table.eq[MTHCA_EQ_ASYNC].eqn, err);
905 mthca_warn(dev, "MAP_EQ for async EQ %d returned status 0x%02x\n",
906 dev->eq_table.eq[MTHCA_EQ_ASYNC].eqn, status);
908 err = mthca_MAP_EQ(dev, MTHCA_CMD_EVENT_MASK,
909 0, dev->eq_table.eq[MTHCA_EQ_CMD].eqn, &status);
911 mthca_warn(dev, "MAP_EQ for cmd EQ %d failed (%d)\n",
912 dev->eq_table.eq[MTHCA_EQ_CMD].eqn, err);
914 mthca_warn(dev, "MAP_EQ for cmd EQ %d returned status 0x%02x\n",
915 dev->eq_table.eq[MTHCA_EQ_CMD].eqn, status);
917 for (i = 0; i < MTHCA_EQ_CMD; ++i)
918 if (mthca_is_memfree(dev))
919 arbel_eq_req_not(dev, dev->eq_table.eq[i].eqn_mask);
921 tavor_eq_req_not(dev, dev->eq_table.eq[i].eqn);
926 mthca_free_irqs(dev);
927 mthca_free_eq(dev, &dev->eq_table.eq[MTHCA_EQ_CMD]);
930 mthca_free_eq(dev, &dev->eq_table.eq[MTHCA_EQ_ASYNC]);
933 mthca_free_eq(dev, &dev->eq_table.eq[MTHCA_EQ_COMP]);
936 mthca_unmap_eq_regs(dev);
939 mthca_alloc_cleanup(&dev->eq_table.alloc);
943 void __devexit mthca_cleanup_eq_table(struct mthca_dev *dev)
948 mthca_free_irqs(dev);
950 mthca_MAP_EQ(dev, async_mask(dev),
951 1, dev->eq_table.eq[MTHCA_EQ_ASYNC].eqn, &status);
952 mthca_MAP_EQ(dev, MTHCA_CMD_EVENT_MASK,
953 1, dev->eq_table.eq[MTHCA_EQ_CMD].eqn, &status);
955 for (i = 0; i < MTHCA_NUM_EQ; ++i)
956 mthca_free_eq(dev, &dev->eq_table.eq[i]);
958 mthca_unmap_eq_regs(dev);
960 mthca_alloc_cleanup(&dev->eq_table.alloc);