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   1 /*
   2  * linux/arch/arm/mach-omap1/pm.c
   3  *
   4  * OMAP Power Management Routines
   5  *
   6  * Original code for the SA11x0:
   7  * Copyright (c) 2001 Cliff Brake <cbrake@accelent.com>
   8  *
   9  * Modified for the PXA250 by Nicolas Pitre:
  10  * Copyright (c) 2002 Monta Vista Software, Inc.
  11  *
  12  * Modified for the OMAP1510 by David Singleton:
  13  * Copyright (c) 2002 Monta Vista Software, Inc.
  14  *
  15  * Cleanup 2004 for OMAP1510/1610 by Dirk Behme <dirk.behme@de.bosch.com>
  16  *
  17  * This program is free software; you can redistribute it and/or modify it
  18  * under the terms of the GNU General Public License as published by the
  19  * Free Software Foundation; either version 2 of the License, or (at your
  20  * option) any later version.
  21  *
  22  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  23  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  24  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  25  * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  26  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  27  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  28  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  29  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  31  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  *
  33  * You should have received a copy of the GNU General Public License along
  34  * with this program; if not, write to the Free Software Foundation, Inc.,
  35  * 675 Mass Ave, Cambridge, MA 02139, USA.
  36  */
  37
  38 #include <linux/pm.h>
  39 #include <linux/sched.h>
  40 #include <linux/proc_fs.h>
  41 #include <linux/pm.h>
  42 #include <linux/interrupt.h>
  43 #include <linux/sysfs.h>
  44 #include <linux/module.h>
  45
  46 #include <asm/io.h>
  47 #include <asm/irq.h>
  48 #include <asm/atomic.h>
  49 #include <asm/mach/time.h>
  50 #include <asm/mach/irq.h>
  51 #include <asm/mach-types.h>
  52
  53 #include <asm/arch/irqs.h>
  54 #include <asm/arch/clock.h>
  55 #include <asm/arch/sram.h>
  56 #include <asm/arch/tc.h>
  57 #include <asm/arch/pm.h>
  58 #include <asm/arch/mux.h>
  59 #include <asm/arch/tps65010.h>
  60 #include <asm/arch/dma.h>
  61 #include <asm/arch/dsp_common.h>
  62 #include <asm/arch/dmtimer.h>
  63
  64 static unsigned int arm_sleep_save[ARM_SLEEP_SAVE_SIZE];
  65 static unsigned short dsp_sleep_save[DSP_SLEEP_SAVE_SIZE];
  66 static unsigned short ulpd_sleep_save[ULPD_SLEEP_SAVE_SIZE];
  67 static unsigned int mpui730_sleep_save[MPUI730_SLEEP_SAVE_SIZE];
  68 static unsigned int mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_SIZE];
  69 static unsigned int mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_SIZE];
  70
  71 static unsigned short enable_dyn_sleep = 1;
  72
  73 static ssize_t omap_pm_sleep_while_idle_show(struct subsystem * subsys, char *buf)
  74 {
  75         return sprintf(buf, "%hu\n", enable_dyn_sleep);
  76 }
  77
  78 static ssize_t omap_pm_sleep_while_idle_store(struct subsystem * subsys,
  79                                               const char * buf,
  80                                               size_t n)
  81 {
  82         unsigned short value;
  83         if (sscanf(buf, "%hu", &value) != 1 ||
  84             (value != 0 && value != 1)) {
  85                 printk(KERN_ERR "idle_sleep_store: Invalid value\n");
  86                 return -EINVAL;
  87         }
  88         enable_dyn_sleep = value;
  89         return n;
  90 }
  91
  92 static struct subsys_attribute sleep_while_idle_attr = {
  93         .attr   = {
  94                 .name = __stringify(sleep_while_idle),
  95                 .mode = 0644,
  96         },
  97         .show   = omap_pm_sleep_while_idle_show,
  98         .store  = omap_pm_sleep_while_idle_store,
  99 };
 100
 101 extern struct subsystem power_subsys;
 102 static void (*omap_sram_idle)(void) = NULL;
 103 static void (*omap_sram_suspend)(unsigned long r0, unsigned long r1) = NULL;
 104
 105 /*
 106  * Let's power down on idle, but only if we are really
 107  * idle, because once we start down the path of
 108  * going idle we continue to do idle even if we get
 109  * a clock tick interrupt . .
 110  */
 111 void omap_pm_idle(void)
 112 {
 113         extern __u32 arm_idlect1_mask;
 114         __u32 use_idlect1 = arm_idlect1_mask;
 115 #ifndef CONFIG_OMAP_MPU_TIMER
 116         int do_sleep;
 117 #endif
 118
 119         local_irq_disable();
 120         local_fiq_disable();
 121         if (need_resched()) {
 122                 local_fiq_enable();
 123                 local_irq_enable();
 124                 return;
 125         }
 126
 127         /*
 128          * Since an interrupt may set up a timer, we don't want to
 129          * reprogram the hardware timer with interrupts enabled.
 130          * Re-enable interrupts only after returning from idle.
 131          */
 132         timer_dyn_reprogram();
 133
 134 #ifdef CONFIG_OMAP_MPU_TIMER
 135 #warning Enable 32kHz OS timer in order to allow sleep states in idle
 136         use_idlect1 = use_idlect1 & ~(1 << 9);
 137 #else
 138
 139         do_sleep = 0;
 140         while (enable_dyn_sleep) {
 141
 142 #ifdef CONFIG_CBUS_TAHVO_USB
 143                 extern int vbus_active;
 144                 /* Clock requirements? */
 145                 if (vbus_active)
 146                         break;
 147 #endif
 148                 do_sleep = 1;
 149                 break;
 150         }
 151
 152 #ifdef CONFIG_OMAP_DM_TIMER
 153         use_idlect1 = omap_dm_timer_modify_idlect_mask(use_idlect1);
 154 #endif
 155
 156         if (omap_dma_running()) {
 157                 use_idlect1 &= ~(1 << 6);
 158                 if (omap_lcd_dma_ext_running())
 159                         use_idlect1 &= ~(1 << 12);
 160         }
 161
 162         /* We should be able to remove the do_sleep variable and multiple
 163          * tests above as soon as drivers, timer and DMA code have been fixed.
 164          * Even the sleep block count should become obsolete. */
 165         if ((use_idlect1 != ~0) || !do_sleep) {
 166
 167                 __u32 saved_idlect1 = omap_readl(ARM_IDLECT1);
 168                 if (cpu_is_omap15xx())
 169                         use_idlect1 &= OMAP1510_BIG_SLEEP_REQUEST;
 170                 else
 171                         use_idlect1 &= OMAP1610_IDLECT1_SLEEP_VAL;
 172                 omap_writel(use_idlect1, ARM_IDLECT1);
 173                 __asm__ volatile ("mcr  p15, 0, r0, c7, c0, 4");
 174                 omap_writel(saved_idlect1, ARM_IDLECT1);
 175
 176                 local_fiq_enable();
 177                 local_irq_enable();
 178                 return;
 179         }
 180         omap_sram_suspend(omap_readl(ARM_IDLECT1),
 181                           omap_readl(ARM_IDLECT2));
 182 #endif
 183
 184         local_fiq_enable();
 185         local_irq_enable();
 186 }
 187
 188 /*
 189  * Configuration of the wakeup event is board specific. For the
 190  * moment we put it into this helper function. Later it may move
 191  * to board specific files.
 192  */
 193 static void omap_pm_wakeup_setup(void)
 194 {
 195         u32 level1_wake = 0;
 196         u32 level2_wake = OMAP_IRQ_BIT(INT_UART2);
 197
 198         /*
 199          * Turn off all interrupts except GPIO bank 1, L1-2nd level cascade,
 200          * and the L2 wakeup interrupts: keypad and UART2. Note that the
 201          * drivers must still separately call omap_set_gpio_wakeup() to
 202          * wake up to a GPIO interrupt.
 203          */
 204         if (cpu_is_omap730())
 205                 level1_wake = OMAP_IRQ_BIT(INT_730_GPIO_BANK1) |
 206                         OMAP_IRQ_BIT(INT_730_IH2_IRQ);
 207         else if (cpu_is_omap15xx())
 208                 level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) |
 209                         OMAP_IRQ_BIT(INT_1510_IH2_IRQ);
 210         else if (cpu_is_omap16xx())
 211                 level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) |
 212                         OMAP_IRQ_BIT(INT_1610_IH2_IRQ);
 213
 214         omap_writel(~level1_wake, OMAP_IH1_MIR);
 215
 216         if (cpu_is_omap730()) {
 217                 omap_writel(~level2_wake, OMAP_IH2_0_MIR);
 218                 omap_writel(~(OMAP_IRQ_BIT(INT_730_WAKE_UP_REQ) |
 219                                 OMAP_IRQ_BIT(INT_730_MPUIO_KEYPAD)),
 220                                 OMAP_IH2_1_MIR);
 221         } else if (cpu_is_omap15xx()) {
 222                 level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD);
 223                 omap_writel(~level2_wake,  OMAP_IH2_MIR);
 224         } else if (cpu_is_omap16xx()) {
 225                 level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD);
 226                 omap_writel(~level2_wake, OMAP_IH2_0_MIR);
 227
 228                 /* INT_1610_WAKE_UP_REQ is needed for GPIO wakeup... */
 229                 omap_writel(~OMAP_IRQ_BIT(INT_1610_WAKE_UP_REQ),
 230                             OMAP_IH2_1_MIR);
 231                 omap_writel(~0x0, OMAP_IH2_2_MIR);
 232                 omap_writel(~0x0, OMAP_IH2_3_MIR);
 233         }
 234
 235         /*  New IRQ agreement, recalculate in cascade order */
 236         omap_writel(1, OMAP_IH2_CONTROL);
 237         omap_writel(1, OMAP_IH1_CONTROL);
 238 }
 239
 240 #define EN_DSPCK        13      /* ARM_CKCTL */
 241 #define EN_APICK        6       /* ARM_IDLECT2 */
 242 #define DSP_EN          1       /* ARM_RSTCT1 */
 243
 244 void omap_pm_suspend(void)
 245 {
 246         unsigned long arg0 = 0, arg1 = 0;
 247
 248         printk("PM: OMAP%x is trying to enter deep sleep...\n", system_rev);
 249
 250         omap_serial_wake_trigger(1);
 251
 252         if (machine_is_omap_osk()) {
 253                 /* Stop LED1 (D9) blink */
 254                 tps65010_set_led(LED1, OFF);
 255         }
 256
 257         omap_writew(0xffff, ULPD_SOFT_DISABLE_REQ_REG);
 258
 259         /*
 260          * Step 1: turn off interrupts (FIXME: NOTE: already disabled)
 261          */
 262
 263         local_irq_disable();
 264         local_fiq_disable();
 265
 266         /*
 267          * Step 2: save registers
 268          *
 269          * The omap is a strange/beautiful device. The caches, memory
 270          * and register state are preserved across power saves.
 271          * We have to save and restore very little register state to
 272          * idle the omap.
 273          *
 274          * Save interrupt, MPUI, ARM and UPLD control registers.
 275          */
 276
 277         if (cpu_is_omap730()) {
 278                 MPUI730_SAVE(OMAP_IH1_MIR);
 279                 MPUI730_SAVE(OMAP_IH2_0_MIR);
 280                 MPUI730_SAVE(OMAP_IH2_1_MIR);
 281                 MPUI730_SAVE(MPUI_CTRL);
 282                 MPUI730_SAVE(MPUI_DSP_BOOT_CONFIG);
 283                 MPUI730_SAVE(MPUI_DSP_API_CONFIG);
 284                 MPUI730_SAVE(EMIFS_CONFIG);
 285                 MPUI730_SAVE(EMIFF_SDRAM_CONFIG);
 286
 287         } else if (cpu_is_omap15xx()) {
 288                 MPUI1510_SAVE(OMAP_IH1_MIR);
 289                 MPUI1510_SAVE(OMAP_IH2_MIR);
 290                 MPUI1510_SAVE(MPUI_CTRL);
 291                 MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG);
 292                 MPUI1510_SAVE(MPUI_DSP_API_CONFIG);
 293                 MPUI1510_SAVE(EMIFS_CONFIG);
 294                 MPUI1510_SAVE(EMIFF_SDRAM_CONFIG);
 295         } else if (cpu_is_omap16xx()) {
 296                 MPUI1610_SAVE(OMAP_IH1_MIR);
 297                 MPUI1610_SAVE(OMAP_IH2_0_MIR);
 298                 MPUI1610_SAVE(OMAP_IH2_1_MIR);
 299                 MPUI1610_SAVE(OMAP_IH2_2_MIR);
 300                 MPUI1610_SAVE(OMAP_IH2_3_MIR);
 301                 MPUI1610_SAVE(MPUI_CTRL);
 302                 MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG);
 303                 MPUI1610_SAVE(MPUI_DSP_API_CONFIG);
 304                 MPUI1610_SAVE(EMIFS_CONFIG);
 305                 MPUI1610_SAVE(EMIFF_SDRAM_CONFIG);
 306         }
 307
 308         ARM_SAVE(ARM_CKCTL);
 309         ARM_SAVE(ARM_IDLECT1);
 310         ARM_SAVE(ARM_IDLECT2);
 311         if (!(cpu_is_omap15xx()))
 312                 ARM_SAVE(ARM_IDLECT3);
 313         ARM_SAVE(ARM_EWUPCT);
 314         ARM_SAVE(ARM_RSTCT1);
 315         ARM_SAVE(ARM_RSTCT2);
 316         ARM_SAVE(ARM_SYSST);
 317         ULPD_SAVE(ULPD_CLOCK_CTRL);
 318         ULPD_SAVE(ULPD_STATUS_REQ);
 319
 320         /* (Step 3 removed - we now allow deep sleep by default) */
 321
 322         /*
 323          * Step 4: OMAP DSP Shutdown
 324          */
 325
 326         /* stop DSP */
 327         omap_writew(omap_readw(ARM_RSTCT1) & ~(1 << DSP_EN), ARM_RSTCT1);
 328
 329         /* shut down dsp_ck */
 330         omap_writew(omap_readw(ARM_CKCTL) & ~(1 << EN_DSPCK), ARM_CKCTL);
 331
 332         /* temporarily enabling api_ck to access DSP registers */
 333         omap_writew(omap_readw(ARM_IDLECT2) | 1 << EN_APICK, ARM_IDLECT2);
 334
 335         /* save DSP registers */
 336         DSP_SAVE(DSP_IDLECT2);
 337
 338         /* Stop all DSP domain clocks */
 339         __raw_writew(0, DSP_IDLECT2);
 340
 341         /*
 342          * Step 5: Wakeup Event Setup
 343          */
 344
 345         omap_pm_wakeup_setup();
 346
 347         /*
 348          * Step 6: ARM and Traffic controller shutdown
 349          */
 350
 351         /* disable ARM watchdog */
 352         omap_writel(0x00F5, OMAP_WDT_TIMER_MODE);
 353         omap_writel(0x00A0, OMAP_WDT_TIMER_MODE);
 354
 355         /*
 356          * Step 6b: ARM and Traffic controller shutdown
 357          *
 358          * Step 6 continues here. Prepare jump to power management
 359          * assembly code in internal SRAM.
 360          *
 361          * Since the omap_cpu_suspend routine has been copied to
 362          * SRAM, we'll do an indirect procedure call to it and pass the
 363          * contents of arm_idlect1 and arm_idlect2 so it can restore
 364          * them when it wakes up and it will return.
 365          */
 366
 367         arg0 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT1];
 368         arg1 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT2];
 369
 370         /*
 371          * Step 6c: ARM and Traffic controller shutdown
 372          *
 373          * Jump to assembly code. The processor will stay there
 374          * until wake up.
 375          */
 376         omap_sram_suspend(arg0, arg1);
 377
 378         /*
 379          * If we are here, processor is woken up!
 380          */
 381
 382         /*
 383          * Restore DSP clocks
 384          */
 385
 386         /* again temporarily enabling api_ck to access DSP registers */
 387         omap_writew(omap_readw(ARM_IDLECT2) | 1 << EN_APICK, ARM_IDLECT2);
 388
 389         /* Restore DSP domain clocks */
 390         DSP_RESTORE(DSP_IDLECT2);
 391
 392         /*
 393          * Restore ARM state, except ARM_IDLECT1/2 which omap_cpu_suspend did
 394          */
 395
 396         if (!(cpu_is_omap15xx()))
 397                 ARM_RESTORE(ARM_IDLECT3);
 398         ARM_RESTORE(ARM_CKCTL);
 399         ARM_RESTORE(ARM_EWUPCT);
 400         ARM_RESTORE(ARM_RSTCT1);
 401         ARM_RESTORE(ARM_RSTCT2);
 402         ARM_RESTORE(ARM_SYSST);
 403         ULPD_RESTORE(ULPD_CLOCK_CTRL);
 404         ULPD_RESTORE(ULPD_STATUS_REQ);
 405
 406         if (cpu_is_omap730()) {
 407                 MPUI730_RESTORE(EMIFS_CONFIG);
 408                 MPUI730_RESTORE(EMIFF_SDRAM_CONFIG);
 409                 MPUI730_RESTORE(OMAP_IH1_MIR);
 410                 MPUI730_RESTORE(OMAP_IH2_0_MIR);
 411                 MPUI730_RESTORE(OMAP_IH2_1_MIR);
 412         } else if (cpu_is_omap15xx()) {
 413                 MPUI1510_RESTORE(MPUI_CTRL);
 414                 MPUI1510_RESTORE(MPUI_DSP_BOOT_CONFIG);
 415                 MPUI1510_RESTORE(MPUI_DSP_API_CONFIG);
 416                 MPUI1510_RESTORE(EMIFS_CONFIG);
 417                 MPUI1510_RESTORE(EMIFF_SDRAM_CONFIG);
 418                 MPUI1510_RESTORE(OMAP_IH1_MIR);
 419                 MPUI1510_RESTORE(OMAP_IH2_MIR);
 420         } else if (cpu_is_omap16xx()) {
 421                 MPUI1610_RESTORE(MPUI_CTRL);
 422                 MPUI1610_RESTORE(MPUI_DSP_BOOT_CONFIG);
 423                 MPUI1610_RESTORE(MPUI_DSP_API_CONFIG);
 424                 MPUI1610_RESTORE(EMIFS_CONFIG);
 425                 MPUI1610_RESTORE(EMIFF_SDRAM_CONFIG);
 426
 427                 MPUI1610_RESTORE(OMAP_IH1_MIR);
 428                 MPUI1610_RESTORE(OMAP_IH2_0_MIR);
 429                 MPUI1610_RESTORE(OMAP_IH2_1_MIR);
 430                 MPUI1610_RESTORE(OMAP_IH2_2_MIR);
 431                 MPUI1610_RESTORE(OMAP_IH2_3_MIR);
 432         }
 433
 434         omap_writew(0, ULPD_SOFT_DISABLE_REQ_REG);
 435
 436         /*
 437          * Reenable interrupts
 438          */
 439
 440         local_irq_enable();
 441         local_fiq_enable();
 442
 443         omap_serial_wake_trigger(0);
 444
 445         printk("PM: OMAP%x is re-starting from deep sleep...\n", system_rev);
 446
 447         if (machine_is_omap_osk()) {
 448                 /* Let LED1 (D9) blink again */
 449                 tps65010_set_led(LED1, BLINK);
 450         }
 451 }
 452
 453 #if defined(DEBUG) && defined(CONFIG_PROC_FS)
 454 static int g_read_completed;
 455
 456 /*
 457  * Read system PM registers for debugging
 458  */
 459 static int omap_pm_read_proc(
 460         char *page_buffer,
 461         char **my_first_byte,
 462         off_t virtual_start,
 463         int length,
 464         int *eof,
 465         void *data)
 466 {
 467         int my_buffer_offset = 0;
 468         char * const my_base = page_buffer;
 469
 470         ARM_SAVE(ARM_CKCTL);
 471         ARM_SAVE(ARM_IDLECT1);
 472         ARM_SAVE(ARM_IDLECT2);
 473         if (!(cpu_is_omap15xx()))
 474                 ARM_SAVE(ARM_IDLECT3);
 475         ARM_SAVE(ARM_EWUPCT);
 476         ARM_SAVE(ARM_RSTCT1);
 477         ARM_SAVE(ARM_RSTCT2);
 478         ARM_SAVE(ARM_SYSST);
 479
 480         ULPD_SAVE(ULPD_IT_STATUS);
 481         ULPD_SAVE(ULPD_CLOCK_CTRL);
 482         ULPD_SAVE(ULPD_SOFT_REQ);
 483         ULPD_SAVE(ULPD_STATUS_REQ);
 484         ULPD_SAVE(ULPD_DPLL_CTRL);
 485         ULPD_SAVE(ULPD_POWER_CTRL);
 486
 487         if (cpu_is_omap730()) {
 488                 MPUI730_SAVE(MPUI_CTRL);
 489                 MPUI730_SAVE(MPUI_DSP_STATUS);
 490                 MPUI730_SAVE(MPUI_DSP_BOOT_CONFIG);
 491                 MPUI730_SAVE(MPUI_DSP_API_CONFIG);
 492                 MPUI730_SAVE(EMIFF_SDRAM_CONFIG);
 493                 MPUI730_SAVE(EMIFS_CONFIG);
 494         } else if (cpu_is_omap15xx()) {
 495                 MPUI1510_SAVE(MPUI_CTRL);
 496                 MPUI1510_SAVE(MPUI_DSP_STATUS);
 497                 MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG);
 498                 MPUI1510_SAVE(MPUI_DSP_API_CONFIG);
 499                 MPUI1510_SAVE(EMIFF_SDRAM_CONFIG);
 500                 MPUI1510_SAVE(EMIFS_CONFIG);
 501         } else if (cpu_is_omap16xx()) {
 502                 MPUI1610_SAVE(MPUI_CTRL);
 503                 MPUI1610_SAVE(MPUI_DSP_STATUS);
 504                 MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG);
 505                 MPUI1610_SAVE(MPUI_DSP_API_CONFIG);
 506                 MPUI1610_SAVE(EMIFF_SDRAM_CONFIG);
 507                 MPUI1610_SAVE(EMIFS_CONFIG);
 508         }
 509
 510         if (virtual_start == 0) {
 511                 g_read_completed = 0;
 512
 513                 my_buffer_offset += sprintf(my_base + my_buffer_offset,
 514                    "ARM_CKCTL_REG:            0x%-8x     \n"
 515                    "ARM_IDLECT1_REG:          0x%-8x     \n"
 516                    "ARM_IDLECT2_REG:          0x%-8x     \n"
 517                    "ARM_IDLECT3_REG:          0x%-8x     \n"
 518                    "ARM_EWUPCT_REG:           0x%-8x     \n"
 519                    "ARM_RSTCT1_REG:           0x%-8x     \n"
 520                    "ARM_RSTCT2_REG:           0x%-8x     \n"
 521                    "ARM_SYSST_REG:            0x%-8x     \n"
 522                    "ULPD_IT_STATUS_REG:       0x%-4x     \n"
 523                    "ULPD_CLOCK_CTRL_REG:      0x%-4x     \n"
 524                    "ULPD_SOFT_REQ_REG:        0x%-4x     \n"
 525                    "ULPD_DPLL_CTRL_REG:       0x%-4x     \n"
 526                    "ULPD_STATUS_REQ_REG:      0x%-4x     \n"
 527                    "ULPD_POWER_CTRL_REG:      0x%-4x     \n",
 528                    ARM_SHOW(ARM_CKCTL),
 529                    ARM_SHOW(ARM_IDLECT1),
 530                    ARM_SHOW(ARM_IDLECT2),
 531                    ARM_SHOW(ARM_IDLECT3),
 532                    ARM_SHOW(ARM_EWUPCT),
 533                    ARM_SHOW(ARM_RSTCT1),
 534                    ARM_SHOW(ARM_RSTCT2),
 535                    ARM_SHOW(ARM_SYSST),
 536                    ULPD_SHOW(ULPD_IT_STATUS),
 537                    ULPD_SHOW(ULPD_CLOCK_CTRL),
 538                    ULPD_SHOW(ULPD_SOFT_REQ),
 539                    ULPD_SHOW(ULPD_DPLL_CTRL),
 540                    ULPD_SHOW(ULPD_STATUS_REQ),
 541                    ULPD_SHOW(ULPD_POWER_CTRL));
 542
 543                 if (cpu_is_omap730()) {
 544                         my_buffer_offset += sprintf(my_base + my_buffer_offset,
 545                            "MPUI730_CTRL_REG         0x%-8x \n"
 546                            "MPUI730_DSP_STATUS_REG:      0x%-8x \n"
 547                            "MPUI730_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
 548                            "MPUI730_DSP_API_CONFIG_REG:  0x%-8x \n"
 549                            "MPUI730_SDRAM_CONFIG_REG:    0x%-8x \n"
 550                            "MPUI730_EMIFS_CONFIG_REG:    0x%-8x \n",
 551                            MPUI730_SHOW(MPUI_CTRL),
 552                            MPUI730_SHOW(MPUI_DSP_STATUS),
 553                            MPUI730_SHOW(MPUI_DSP_BOOT_CONFIG),
 554                            MPUI730_SHOW(MPUI_DSP_API_CONFIG),
 555                            MPUI730_SHOW(EMIFF_SDRAM_CONFIG),
 556                            MPUI730_SHOW(EMIFS_CONFIG));
 557                 } else if (cpu_is_omap15xx()) {
 558                         my_buffer_offset += sprintf(my_base + my_buffer_offset,
 559                            "MPUI1510_CTRL_REG             0x%-8x \n"
 560                            "MPUI1510_DSP_STATUS_REG:      0x%-8x \n"
 561                            "MPUI1510_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
 562                            "MPUI1510_DSP_API_CONFIG_REG:  0x%-8x \n"
 563                            "MPUI1510_SDRAM_CONFIG_REG:    0x%-8x \n"
 564                            "MPUI1510_EMIFS_CONFIG_REG:    0x%-8x \n",
 565                            MPUI1510_SHOW(MPUI_CTRL),
 566                            MPUI1510_SHOW(MPUI_DSP_STATUS),
 567                            MPUI1510_SHOW(MPUI_DSP_BOOT_CONFIG),
 568                            MPUI1510_SHOW(MPUI_DSP_API_CONFIG),
 569                            MPUI1510_SHOW(EMIFF_SDRAM_CONFIG),
 570                            MPUI1510_SHOW(EMIFS_CONFIG));
 571                 } else if (cpu_is_omap16xx()) {
 572                         my_buffer_offset += sprintf(my_base + my_buffer_offset,
 573                            "MPUI1610_CTRL_REG             0x%-8x \n"
 574                            "MPUI1610_DSP_STATUS_REG:      0x%-8x \n"
 575                            "MPUI1610_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
 576                            "MPUI1610_DSP_API_CONFIG_REG:  0x%-8x \n"
 577                            "MPUI1610_SDRAM_CONFIG_REG:    0x%-8x \n"
 578                            "MPUI1610_EMIFS_CONFIG_REG:    0x%-8x \n",
 579                            MPUI1610_SHOW(MPUI_CTRL),
 580                            MPUI1610_SHOW(MPUI_DSP_STATUS),
 581                            MPUI1610_SHOW(MPUI_DSP_BOOT_CONFIG),
 582                            MPUI1610_SHOW(MPUI_DSP_API_CONFIG),
 583                            MPUI1610_SHOW(EMIFF_SDRAM_CONFIG),
 584                            MPUI1610_SHOW(EMIFS_CONFIG));
 585                 }
 586
 587                 g_read_completed++;
 588         } else if (g_read_completed >= 1) {
 589                  *eof = 1;
 590                  return 0;
 591         }
 592         g_read_completed++;
 593
 594         *my_first_byte = page_buffer;
 595         return  my_buffer_offset;
 596 }
 597
 598 static void omap_pm_init_proc(void)
 599 {
 600         struct proc_dir_entry *entry;
 601
 602         entry = create_proc_read_entry("driver/omap_pm",
 603                                        S_IWUSR | S_IRUGO, NULL,
 604                                        omap_pm_read_proc, NULL);
 605 }
 606
 607 #endif /* DEBUG && CONFIG_PROC_FS */
 608
 609 static void (*saved_idle)(void) = NULL;
 610
 611 /*
 612  *      omap_pm_prepare - Do preliminary suspend work.
 613  *      @state:         suspend state we're entering.
 614  *
 615  */
 616 static int omap_pm_prepare(suspend_state_t state)
 617 {
 618         int error = 0;
 619
 620         /* We cannot sleep in idle until we have resumed */
 621         saved_idle = pm_idle;
 622         pm_idle = NULL;
 623
 624         switch (state)
 625         {
 626         case PM_SUSPEND_STANDBY:
 627         case PM_SUSPEND_MEM:
 628                 break;
 629
 630         case PM_SUSPEND_DISK:
 631                 return -ENOTSUPP;
 632
 633         default:
 634                 return -EINVAL;
 635         }
 636
 637         return error;
 638 }
 639
 640
 641 /*
 642  *      omap_pm_enter - Actually enter a sleep state.
 643  *      @state:         State we're entering.
 644  *
 645  */
 646
 647 static int omap_pm_enter(suspend_state_t state)
 648 {
 649         switch (state)
 650         {
 651         case PM_SUSPEND_STANDBY:
 652         case PM_SUSPEND_MEM:
 653                 omap_pm_suspend();
 654                 break;
 655
 656         case PM_SUSPEND_DISK:
 657                 return -ENOTSUPP;
 658
 659         default:
 660                 return -EINVAL;
 661         }
 662
 663         return 0;
 664 }
 665
 666
 667 /**
 668  *      omap_pm_finish - Finish up suspend sequence.
 669  *      @state:         State we're coming out of.
 670  *
 671  *      This is called after we wake back up (or if entering the sleep state
 672  *      failed).
 673  */
 674
 675 static int omap_pm_finish(suspend_state_t state)
 676 {
 677         pm_idle = saved_idle;
 678         return 0;
 679 }
 680
 681
 682 static irqreturn_t  omap_wakeup_interrupt(int  irq, void *  dev,
 683                                      struct pt_regs *  regs)
 684 {
 685         return IRQ_HANDLED;
 686 }
 687
 688 static struct irqaction omap_wakeup_irq = {
 689         .name           = "peripheral wakeup",
 690         .flags          = SA_INTERRUPT,
 691         .handler        = omap_wakeup_interrupt
 692 };
 693
 694
 695
 696 static struct pm_ops omap_pm_ops ={
 697         .pm_disk_mode   = 0,
 698         .prepare        = omap_pm_prepare,
 699         .enter          = omap_pm_enter,
 700         .finish         = omap_pm_finish,
 701 };
 702
 703 static int __init omap_pm_init(void)
 704 {
 705         printk("Power Management for TI OMAP.\n");
 706
 707         /*
 708          * We copy the assembler sleep/wakeup routines to SRAM.
 709          * These routines need to be in SRAM as that's the only
 710          * memory the MPU can see when it wakes up.
 711          */
 712         if (cpu_is_omap730()) {
 713                 omap_sram_idle = omap_sram_push(omap730_idle_loop_suspend,
 714                                                 omap730_idle_loop_suspend_sz);
 715                 omap_sram_suspend = omap_sram_push(omap730_cpu_suspend,
 716                                                    omap730_cpu_suspend_sz);
 717         } else if (cpu_is_omap15xx()) {
 718                 omap_sram_idle = omap_sram_push(omap1510_idle_loop_suspend,
 719                                                 omap1510_idle_loop_suspend_sz);
 720                 omap_sram_suspend = omap_sram_push(omap1510_cpu_suspend,
 721                                                    omap1510_cpu_suspend_sz);
 722         } else if (cpu_is_omap16xx()) {
 723                 omap_sram_idle = omap_sram_push(omap1610_idle_loop_suspend,
 724                                                 omap1610_idle_loop_suspend_sz);
 725                 omap_sram_suspend = omap_sram_push(omap1610_cpu_suspend,
 726                                                    omap1610_cpu_suspend_sz);
 727         }
 728
 729         if (omap_sram_idle == NULL || omap_sram_suspend == NULL) {
 730                 printk(KERN_ERR "PM not initialized: Missing SRAM support\n");
 731                 return -ENODEV;
 732         }
 733
 734         pm_idle = omap_pm_idle;
 735
 736         if (cpu_is_omap730())
 737                 setup_irq(INT_730_WAKE_UP_REQ, &omap_wakeup_irq);
 738         else if (cpu_is_omap16xx())
 739                 setup_irq(INT_1610_WAKE_UP_REQ, &omap_wakeup_irq);
 740
 741         /* Program new power ramp-up time
 742          * (0 for most boards since we don't lower voltage when in deep sleep)
 743          */
 744         omap_writew(ULPD_SETUP_ANALOG_CELL_3_VAL, ULPD_SETUP_ANALOG_CELL_3);
 745
 746         /* Setup ULPD POWER_CTRL_REG - enter deep sleep whenever possible */
 747         omap_writew(ULPD_POWER_CTRL_REG_VAL, ULPD_POWER_CTRL);
 748
 749         /* Configure IDLECT3 */
 750         if (cpu_is_omap730())
 751                 omap_writel(OMAP730_IDLECT3_VAL, OMAP730_IDLECT3);
 752         else if (cpu_is_omap16xx())
 753                 omap_writel(OMAP1610_IDLECT3_VAL, OMAP1610_IDLECT3);
 754
 755         pm_set_ops(&omap_pm_ops);
 756
 757 #if defined(DEBUG) && defined(CONFIG_PROC_FS)
 758         omap_pm_init_proc();
 759 #endif
 760
 761         subsys_create_file(&power_subsys, &sleep_while_idle_attr);
 762
 763         if (cpu_is_omap16xx()) {
 764                 /* configure LOW_PWR pin */
 765                 omap_cfg_reg(T20_1610_LOW_PWR);
 766         }
 767
 768         return 0;
 769 }
 770 __initcall(omap_pm_init);