1 # drivers/mtd/chips/Kconfig
2 # $Id: Kconfig,v 1.18 2005/11/07 11:14:22 gleixner Exp $
4 menu "RAM/ROM/Flash chip drivers"
8 tristate "Detect flash chips by Common Flash Interface (CFI) probe"
12 The Common Flash Interface specification was developed by Intel,
13 AMD and other flash manufactures that provides a universal method
14 for probing the capabilities of flash devices. If you wish to
15 support any device that is CFI-compliant, you need to enable this
16 option. Visit <http://www.amd.com/products/nvd/overview/cfi.html>
17 for more information on CFI.
20 tristate "Detect non-CFI AMD/JEDEC-compatible flash chips"
24 This option enables JEDEC-style probing of flash chips which are not
25 compatible with the Common Flash Interface, but will use the common
26 CFI-targetted flash drivers for any chips which are identified which
27 are in fact compatible in all but the probe method. This actually
28 covers most AMD/Fujitsu-compatible chips and also non-CFI
33 select OBSOLETE_INTERMODULE
35 config MTD_CFI_ADV_OPTIONS
36 bool "Flash chip driver advanced configuration options"
37 depends on MTD_GEN_PROBE
39 If you need to specify a specific endianness for access to flash
40 chips, or if you wish to reduce the size of the kernel by including
41 support for only specific arrangements of flash chips, say 'Y'. This
42 option does not directly affect the code, but will enable other
43 configuration options which allow you to do so.
48 prompt "Flash cmd/query data swapping"
49 depends on MTD_CFI_ADV_OPTIONS
50 default MTD_CFI_NOSWAP
55 This option defines the way in which the CPU attempts to arrange
56 data bits when writing the 'magic' commands to the chips. Saying
57 'NO', which is the default when CONFIG_MTD_CFI_ADV_OPTIONS isn't
58 enabled, means that the CPU will not do any swapping; the chips
59 are expected to be wired to the CPU in 'host-endian' form.
60 Specific arrangements are possible with the BIG_ENDIAN_BYTE and
61 LITTLE_ENDIAN_BYTE, if the bytes are reversed.
63 If you have a LART, on which the data (and address) lines were
64 connected in a fashion which ensured that the nets were as short
65 as possible, resulting in a bit-shuffling which seems utterly
66 random to the untrained eye, you need the LART_ENDIAN_BYTE option.
68 Yes, there really exists something sicker than PDP-endian :)
70 config MTD_CFI_BE_BYTE_SWAP
71 bool "BIG_ENDIAN_BYTE"
73 config MTD_CFI_LE_BYTE_SWAP
74 bool "LITTLE_ENDIAN_BYTE"
78 config MTD_CFI_GEOMETRY
79 bool "Specific CFI Flash geometry selection"
80 depends on MTD_CFI_ADV_OPTIONS
82 This option does not affect the code directly, but will enable
83 some other configuration options which would allow you to reduce
84 the size of the kernel by including support for only certain
85 arrangements of CFI chips. If unsure, say 'N' and all options
86 which are supported by the current code will be enabled.
88 config MTD_MAP_BANK_WIDTH_1
89 bool "Support 8-bit buswidth" if MTD_CFI_GEOMETRY
92 If you wish to support CFI devices on a physical bus which is
95 config MTD_MAP_BANK_WIDTH_2
96 bool "Support 16-bit buswidth" if MTD_CFI_GEOMETRY
99 If you wish to support CFI devices on a physical bus which is
100 16 bits wide, say 'Y'.
102 config MTD_MAP_BANK_WIDTH_4
103 bool "Support 32-bit buswidth" if MTD_CFI_GEOMETRY
106 If you wish to support CFI devices on a physical bus which is
107 32 bits wide, say 'Y'.
109 config MTD_MAP_BANK_WIDTH_8
110 bool "Support 64-bit buswidth" if MTD_CFI_GEOMETRY
113 If you wish to support CFI devices on a physical bus which is
114 64 bits wide, say 'Y'.
116 config MTD_MAP_BANK_WIDTH_16
117 bool "Support 128-bit buswidth" if MTD_CFI_GEOMETRY
120 If you wish to support CFI devices on a physical bus which is
121 128 bits wide, say 'Y'.
123 config MTD_MAP_BANK_WIDTH_32
124 bool "Support 256-bit buswidth" if MTD_CFI_GEOMETRY
127 If you wish to support CFI devices on a physical bus which is
128 256 bits wide, say 'Y'.
131 bool "Support 1-chip flash interleave" if MTD_CFI_GEOMETRY
134 If your flash chips are not interleaved - i.e. you only have one
135 flash chip addressed by each bus cycle, then say 'Y'.
138 bool "Support 2-chip flash interleave" if MTD_CFI_GEOMETRY
141 If your flash chips are interleaved in pairs - i.e. you have two
142 flash chips addressed by each bus cycle, then say 'Y'.
145 bool "Support 4-chip flash interleave" if MTD_CFI_GEOMETRY
148 If your flash chips are interleaved in fours - i.e. you have four
149 flash chips addressed by each bus cycle, then say 'Y'.
152 bool "Support 8-chip flash interleave" if MTD_CFI_GEOMETRY
155 If your flash chips are interleaved in eights - i.e. you have eight
156 flash chips addressed by each bus cycle, then say 'Y'.
159 bool "Protection Registers aka one-time programmable (OTP) bits"
160 depends on MTD_CFI_ADV_OPTIONS
163 This enables support for reading, writing and locking so called
164 "Protection Registers" present on some flash chips.
165 A subset of them are pre-programmed at the factory with a
166 unique set of values. The rest is user-programmable.
168 The user-programmable Protection Registers contain one-time
169 programmable (OTP) bits; when programmed, register bits cannot be
170 erased. Each Protection Register can be accessed multiple times to
171 program individual bits, as long as the register remains unlocked.
173 Each Protection Register has an associated Lock Register bit. When a
174 Lock Register bit is programmed, the associated Protection Register
175 can only be read; it can no longer be programmed. Additionally,
176 because the Lock Register bits themselves are OTP, when programmed,
177 Lock Register bits cannot be erased. Therefore, when a Protection
178 Register is locked, it cannot be unlocked.
180 This feature should therefore be used with extreme care. Any mistake
181 in the programming of OTP bits will waste them.
183 config MTD_CFI_INTELEXT
184 tristate "Support for Intel/Sharp flash chips"
185 depends on MTD_GEN_PROBE
188 The Common Flash Interface defines a number of different command
189 sets which a CFI-compliant chip may claim to implement. This code
190 provides support for one of those command sets, used on Intel
191 StrataFlash and other parts.
193 config MTD_CFI_AMDSTD
194 tristate "Support for AMD/Fujitsu flash chips"
195 depends on MTD_GEN_PROBE
198 The Common Flash Interface defines a number of different command
199 sets which a CFI-compliant chip may claim to implement. This code
200 provides support for one of those command sets, used on chips
201 including the AMD Am29LV320.
204 tristate "Support for ST (Advanced Architecture) flash chips"
205 depends on MTD_GEN_PROBE
208 The Common Flash Interface defines a number of different command
209 sets which a CFI-compliant chip may claim to implement. This code
210 provides support for one of those command sets.
216 tristate "Support for RAM chips in bus mapping"
219 This option enables basic support for RAM chips accessed through
220 a bus mapping driver.
223 tristate "Support for ROM chips in bus mapping"
226 This option enables basic support for ROM chips accessed through
227 a bus mapping driver.
230 tristate "Support for absent chips in bus mapping"
233 This option enables support for a dummy probing driver used to
234 allocated placeholder MTD devices on systems that have socketed
235 or removable media. Use of this driver as a fallback chip probe
236 preserves the expected registration order of MTD device nodes on
237 the system regardless of media presence. Device nodes created
238 with this driver will return -ENODEV upon access.
240 config MTD_OBSOLETE_CHIPS
242 bool "Older (theoretically obsoleted now) drivers for non-CFI chips"
244 This option does not enable any code directly, but will allow you to
245 select some other chip drivers which are now considered obsolete,
246 because the generic CONFIG_JEDECPROBE code above should now detect
247 the chips which are supported by these drivers, and allow the generic
248 CFI-compatible drivers to drive the chips. Say 'N' here unless you have
249 already tried the CONFIG_JEDECPROBE method and reported its failure
250 to the MTD mailing list at <linux-mtd@lists.infradead.org>
253 tristate "AMD compatible flash chip support (non-CFI)"
254 depends on MTD && MTD_OBSOLETE_CHIPS && BROKEN
256 This option enables support for flash chips using AMD-compatible
257 commands, including some which are not CFI-compatible and hence
258 cannot be used with the CONFIG_MTD_CFI_AMDSTD option.
260 It also works on AMD compatible chips that do conform to CFI.
263 tristate "pre-CFI Sharp chip support"
264 depends on MTD && MTD_OBSOLETE_CHIPS
266 This option enables support for flash chips using Sharp-compatible
267 commands, including some which are not CFI-compatible and hence
268 cannot be used with the CONFIG_MTD_CFI_INTELxxx options.
271 tristate "JEDEC device support"
272 depends on MTD && MTD_OBSOLETE_CHIPS && BROKEN
274 Enable older older JEDEC flash interface devices for self
275 programming flash. It is commonly used in older AMD chips. It is
276 only called JEDEC because the JEDEC association
277 <http://www.jedec.org/> distributes the identification codes for the
281 bool "XIP aware MTD support"
282 depends on !SMP && (MTD_CFI_INTELEXT || MTD_CFI_AMDSTD) && EXPERIMENTAL && ARCH_MTD_XIP
283 default y if XIP_KERNEL
285 This allows MTD support to work with flash memory which is also
286 used for XIP purposes. If you're not sure what this is all about