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   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2009 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/types.h>
  29 #include <linux/module.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/string.h>
  34 #include <linux/in.h>
  35 #include <linux/ip.h>
  36 #include <linux/tcp.h>
  37 #include <linux/ipv6.h>
  38 #include <net/checksum.h>
  39 #include <net/ip6_checksum.h>
  40 #include <linux/ethtool.h>
  41 #include <linux/if_vlan.h>
  42
  43 #include "ixgbe.h"
  44 #include "ixgbe_common.h"
  45
  46 char ixgbe_driver_name[] = "ixgbe";
  47 static const char ixgbe_driver_string[] =
  48                               "Intel(R) 10 Gigabit PCI Express Network Driver";
  49
  50 #define DRV_VERSION "2.0.16-k2"
  51 const char ixgbe_driver_version[] = DRV_VERSION;
  52 static char ixgbe_copyright[] = "Copyright (c) 1999-2009 Intel Corporation.";
  53
  54 static const struct ixgbe_info *ixgbe_info_tbl[] = {
  55         [board_82598] = &ixgbe_82598_info,
  56         [board_82599] = &ixgbe_82599_info,
  57 };
  58
  59 /* ixgbe_pci_tbl - PCI Device ID Table
  60  *
  61  * Wildcard entries (PCI_ANY_ID) should come last
  62  * Last entry must be all 0s
  63  *
  64  * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
  65  *   Class, Class Mask, private data (not used) }
  66  */
  67 static struct pci_device_id ixgbe_pci_tbl[] = {
  68         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
  69          board_82598 },
  70         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
  71          board_82598 },
  72         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
  73          board_82598 },
  74         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
  75          board_82598 },
  76         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
  77          board_82598 },
  78         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
  79          board_82598 },
  80         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
  81          board_82598 },
  82         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
  83          board_82598 },
  84         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
  85          board_82598 },
  86         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
  87          board_82598 },
  88         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
  89          board_82598 },
  90         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
  91          board_82599 },
  92         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
  93          board_82599 },
  94
  95         /* required last entry */
  96         {0, }
  97 };
  98 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
  99
 100 #ifdef CONFIG_IXGBE_DCA
 101 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
 102                             void *p);
 103 static struct notifier_block dca_notifier = {
 104         .notifier_call = ixgbe_notify_dca,
 105         .next          = NULL,
 106         .priority      = 0
 107 };
 108 #endif
 109
 110 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
 111 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
 112 MODULE_LICENSE("GPL");
 113 MODULE_VERSION(DRV_VERSION);
 114
 115 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
 116
 117 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
 118 {
 119         u32 ctrl_ext;
 120
 121         /* Let firmware take over control of h/w */
 122         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 123         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 124                         ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
 125 }
 126
 127 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
 128 {
 129         u32 ctrl_ext;
 130
 131         /* Let firmware know the driver has taken over */
 132         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 133         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 134                         ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
 135 }
 136
 137 /*
 138  * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
 139  * @adapter: pointer to adapter struct
 140  * @direction: 0 for Rx, 1 for Tx, -1 for other causes
 141  * @queue: queue to map the corresponding interrupt to
 142  * @msix_vector: the vector to map to the corresponding queue
 143  *
 144  */
 145 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
 146                            u8 queue, u8 msix_vector)
 147 {
 148         u32 ivar, index;
 149         struct ixgbe_hw *hw = &adapter->hw;
 150         switch (hw->mac.type) {
 151         case ixgbe_mac_82598EB:
 152                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 153                 if (direction == -1)
 154                         direction = 0;
 155                 index = (((direction * 64) + queue) >> 2) & 0x1F;
 156                 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
 157                 ivar &= ~(0xFF << (8 * (queue & 0x3)));
 158                 ivar |= (msix_vector << (8 * (queue & 0x3)));
 159                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
 160                 break;
 161         case ixgbe_mac_82599EB:
 162                 if (direction == -1) {
 163                         /* other causes */
 164                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 165                         index = ((queue & 1) * 8);
 166                         ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
 167                         ivar &= ~(0xFF << index);
 168                         ivar |= (msix_vector << index);
 169                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
 170                         break;
 171                 } else {
 172                         /* tx or rx causes */
 173                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 174                         index = ((16 * (queue & 1)) + (8 * direction));
 175                         ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
 176                         ivar &= ~(0xFF << index);
 177                         ivar |= (msix_vector << index);
 178                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
 179                         break;
 180                 }
 181         default:
 182                 break;
 183         }
 184 }
 185
 186 static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
 187                                              struct ixgbe_tx_buffer
 188                                              *tx_buffer_info)
 189 {
 190         tx_buffer_info->dma = 0;
 191         if (tx_buffer_info->skb) {
 192                 skb_dma_unmap(&adapter->pdev->dev, tx_buffer_info->skb,
 193                               DMA_TO_DEVICE);
 194                 dev_kfree_skb_any(tx_buffer_info->skb);
 195                 tx_buffer_info->skb = NULL;
 196         }
 197         tx_buffer_info->time_stamp = 0;
 198         /* tx_buffer_info must be completely set up in the transmit path */
 199 }
 200
 201 static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
 202                                        struct ixgbe_ring *tx_ring,
 203                                        unsigned int eop)
 204 {
 205         struct ixgbe_hw *hw = &adapter->hw;
 206
 207         /* Detect a transmit hang in hardware, this serializes the
 208          * check with the clearing of time_stamp and movement of eop */
 209         adapter->detect_tx_hung = false;
 210         if (tx_ring->tx_buffer_info[eop].time_stamp &&
 211             time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
 212             !(IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & IXGBE_TFCS_TXOFF)) {
 213                 /* detected Tx unit hang */
 214                 union ixgbe_adv_tx_desc *tx_desc;
 215                 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 216                 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
 217                         "  Tx Queue             <%d>\n"
 218                         "  TDH, TDT             <%x>, <%x>\n"
 219                         "  next_to_use          <%x>\n"
 220                         "  next_to_clean        <%x>\n"
 221                         "tx_buffer_info[next_to_clean]\n"
 222                         "  time_stamp           <%lx>\n"
 223                         "  jiffies              <%lx>\n",
 224                         tx_ring->queue_index,
 225                         IXGBE_READ_REG(hw, tx_ring->head),
 226                         IXGBE_READ_REG(hw, tx_ring->tail),
 227                         tx_ring->next_to_use, eop,
 228                         tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
 229                 return true;
 230         }
 231
 232         return false;
 233 }
 234
 235 #define IXGBE_MAX_TXD_PWR       14
 236 #define IXGBE_MAX_DATA_PER_TXD  (1 << IXGBE_MAX_TXD_PWR)
 237
 238 /* Tx Descriptors needed, worst case */
 239 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
 240                          (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
 241 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
 242         MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
 243
 244 static void ixgbe_tx_timeout(struct net_device *netdev);
 245
 246 /**
 247  * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
 248  * @adapter: board private structure
 249  * @tx_ring: tx ring to clean
 250  *
 251  * returns true if transmit work is done
 252  **/
 253 static bool ixgbe_clean_tx_irq(struct ixgbe_adapter *adapter,
 254                                struct ixgbe_ring *tx_ring)
 255 {
 256         struct net_device *netdev = adapter->netdev;
 257         union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
 258         struct ixgbe_tx_buffer *tx_buffer_info;
 259         unsigned int i, eop, count = 0;
 260         unsigned int total_bytes = 0, total_packets = 0;
 261
 262         i = tx_ring->next_to_clean;
 263         eop = tx_ring->tx_buffer_info[i].next_to_watch;
 264         eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 265
 266         while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
 267                (count < tx_ring->work_limit)) {
 268                 bool cleaned = false;
 269                 for ( ; !cleaned; count++) {
 270                         struct sk_buff *skb;
 271                         tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
 272                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 273                         cleaned = (i == eop);
 274                         skb = tx_buffer_info->skb;
 275
 276                         if (cleaned && skb) {
 277                                 unsigned int segs, bytecount;
 278
 279                                 /* gso_segs is currently only valid for tcp */
 280                                 segs = skb_shinfo(skb)->gso_segs ?: 1;
 281                                 /* multiply data chunks by size of headers */
 282                                 bytecount = ((segs - 1) * skb_headlen(skb)) +
 283                                             skb->len;
 284                                 total_packets += segs;
 285                                 total_bytes += bytecount;
 286                         }
 287
 288                         ixgbe_unmap_and_free_tx_resource(adapter,
 289                                                          tx_buffer_info);
 290
 291                         tx_desc->wb.status = 0;
 292
 293                         i++;
 294                         if (i == tx_ring->count)
 295                                 i = 0;
 296                 }
 297
 298                 eop = tx_ring->tx_buffer_info[i].next_to_watch;
 299                 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 300         }
 301
 302         tx_ring->next_to_clean = i;
 303
 304 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
 305         if (unlikely(count && netif_carrier_ok(netdev) &&
 306                      (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
 307                 /* Make sure that anybody stopping the queue after this
 308                  * sees the new next_to_clean.
 309                  */
 310                 smp_mb();
 311                 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
 312                     !test_bit(__IXGBE_DOWN, &adapter->state)) {
 313                         netif_wake_subqueue(netdev, tx_ring->queue_index);
 314                         ++adapter->restart_queue;
 315                 }
 316         }
 317
 318         if (adapter->detect_tx_hung) {
 319                 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
 320                         /* schedule immediate reset if we believe we hung */
 321                         DPRINTK(PROBE, INFO,
 322                                 "tx hang %d detected, resetting adapter\n",
 323                                 adapter->tx_timeout_count + 1);
 324                         ixgbe_tx_timeout(adapter->netdev);
 325                 }
 326         }
 327
 328         /* re-arm the interrupt */
 329         if (count >= tx_ring->work_limit)
 330                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, tx_ring->v_idx);
 331
 332         tx_ring->total_bytes += total_bytes;
 333         tx_ring->total_packets += total_packets;
 334         tx_ring->stats.packets += total_packets;
 335         tx_ring->stats.bytes += total_bytes;
 336         adapter->net_stats.tx_bytes += total_bytes;
 337         adapter->net_stats.tx_packets += total_packets;
 338         return (count < tx_ring->work_limit);
 339 }
 340
 341 #ifdef CONFIG_IXGBE_DCA
 342 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
 343                                 struct ixgbe_ring *rx_ring)
 344 {
 345         u32 rxctrl;
 346         int cpu = get_cpu();
 347         int q = rx_ring - adapter->rx_ring;
 348
 349         if (rx_ring->cpu != cpu) {
 350                 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
 351                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 352                         rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
 353                         rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 354                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 355                         rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
 356                         rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 357                                    IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
 358                 }
 359                 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
 360                 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
 361                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
 362                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
 363                             IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
 364                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
 365                 rx_ring->cpu = cpu;
 366         }
 367         put_cpu();
 368 }
 369
 370 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
 371                                 struct ixgbe_ring *tx_ring)
 372 {
 373         u32 txctrl;
 374         int cpu = get_cpu();
 375         int q = tx_ring - adapter->tx_ring;
 376
 377         if (tx_ring->cpu != cpu) {
 378                 txctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q));
 379                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 380                         txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
 381                         txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 382                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 383                         txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
 384                         txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 385                                    IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
 386                 }
 387                 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 388                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q), txctrl);
 389                 tx_ring->cpu = cpu;
 390         }
 391         put_cpu();
 392 }
 393
 394 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
 395 {
 396         int i;
 397
 398         if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
 399                 return;
 400
 401         for (i = 0; i < adapter->num_tx_queues; i++) {
 402                 adapter->tx_ring[i].cpu = -1;
 403                 ixgbe_update_tx_dca(adapter, &adapter->tx_ring[i]);
 404         }
 405         for (i = 0; i < adapter->num_rx_queues; i++) {
 406                 adapter->rx_ring[i].cpu = -1;
 407                 ixgbe_update_rx_dca(adapter, &adapter->rx_ring[i]);
 408         }
 409 }
 410
 411 static int __ixgbe_notify_dca(struct device *dev, void *data)
 412 {
 413         struct net_device *netdev = dev_get_drvdata(dev);
 414         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 415         unsigned long event = *(unsigned long *)data;
 416
 417         switch (event) {
 418         case DCA_PROVIDER_ADD:
 419                 /* if we're already enabled, don't do it again */
 420                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
 421                         break;
 422                 /* Always use CB2 mode, difference is masked
 423                  * in the CB driver. */
 424                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
 425                 if (dca_add_requester(dev) == 0) {
 426                         adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
 427                         ixgbe_setup_dca(adapter);
 428                         break;
 429                 }
 430                 /* Fall Through since DCA is disabled. */
 431         case DCA_PROVIDER_REMOVE:
 432                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
 433                         dca_remove_requester(dev);
 434                         adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
 435                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
 436                 }
 437                 break;
 438         }
 439
 440         return 0;
 441 }
 442
 443 #endif /* CONFIG_IXGBE_DCA */
 444 /**
 445  * ixgbe_receive_skb - Send a completed packet up the stack
 446  * @adapter: board private structure
 447  * @skb: packet to send up
 448  * @status: hardware indication of status of receive
 449  * @rx_ring: rx descriptor ring (for a specific queue) to setup
 450  * @rx_desc: rx descriptor
 451  **/
 452 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
 453                               struct sk_buff *skb, u8 status,
 454                               union ixgbe_adv_rx_desc *rx_desc)
 455 {
 456         struct ixgbe_adapter *adapter = q_vector->adapter;
 457         struct napi_struct *napi = &q_vector->napi;
 458         bool is_vlan = (status & IXGBE_RXD_STAT_VP);
 459         u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
 460
 461         skb_record_rx_queue(skb, q_vector - &adapter->q_vector[0]);
 462         if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
 463                 if (adapter->vlgrp && is_vlan && (tag != 0))
 464                         vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
 465                 else
 466                         napi_gro_receive(napi, skb);
 467         } else {
 468                 if (adapter->vlgrp && is_vlan && (tag != 0))
 469                         vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
 470                 else
 471                         netif_rx(skb);
 472         }
 473 }
 474
 475 /**
 476  * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
 477  * @adapter: address of board private structure
 478  * @status_err: hardware indication of status of receive
 479  * @skb: skb currently being received and modified
 480  **/
 481 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
 482                                      u32 status_err, struct sk_buff *skb)
 483 {
 484         skb->ip_summed = CHECKSUM_NONE;
 485
 486         /* Rx csum disabled */
 487         if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
 488                 return;
 489
 490         /* if IP and error */
 491         if ((status_err & IXGBE_RXD_STAT_IPCS) &&
 492             (status_err & IXGBE_RXDADV_ERR_IPE)) {
 493                 adapter->hw_csum_rx_error++;
 494                 return;
 495         }
 496
 497         if (!(status_err & IXGBE_RXD_STAT_L4CS))
 498                 return;
 499
 500         if (status_err & IXGBE_RXDADV_ERR_TCPE) {
 501                 adapter->hw_csum_rx_error++;
 502                 return;
 503         }
 504
 505         /* It must be a TCP or UDP packet with a valid checksum */
 506         skb->ip_summed = CHECKSUM_UNNECESSARY;
 507         adapter->hw_csum_rx_good++;
 508 }
 509
 510 static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
 511                                          struct ixgbe_ring *rx_ring, u32 val)
 512 {
 513         /*
 514          * Force memory writes to complete before letting h/w
 515          * know there are new descriptors to fetch.  (Only
 516          * applicable for weak-ordered memory model archs,
 517          * such as IA-64).
 518          */
 519         wmb();
 520         IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
 521 }
 522
 523 /**
 524  * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
 525  * @adapter: address of board private structure
 526  **/
 527 static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
 528                                    struct ixgbe_ring *rx_ring,
 529                                    int cleaned_count)
 530 {
 531         struct pci_dev *pdev = adapter->pdev;
 532         union ixgbe_adv_rx_desc *rx_desc;
 533         struct ixgbe_rx_buffer *bi;
 534         unsigned int i;
 535         unsigned int bufsz = rx_ring->rx_buf_len + NET_IP_ALIGN;
 536
 537         i = rx_ring->next_to_use;
 538         bi = &rx_ring->rx_buffer_info[i];
 539
 540         while (cleaned_count--) {
 541                 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
 542
 543                 if (!bi->page_dma &&
 544                     (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)) {
 545                         if (!bi->page) {
 546                                 bi->page = alloc_page(GFP_ATOMIC);
 547                                 if (!bi->page) {
 548                                         adapter->alloc_rx_page_failed++;
 549                                         goto no_buffers;
 550                                 }
 551                                 bi->page_offset = 0;
 552                         } else {
 553                                 /* use a half page if we're re-using */
 554                                 bi->page_offset ^= (PAGE_SIZE / 2);
 555                         }
 556
 557                         bi->page_dma = pci_map_page(pdev, bi->page,
 558                                                     bi->page_offset,
 559                                                     (PAGE_SIZE / 2),
 560                                                     PCI_DMA_FROMDEVICE);
 561                 }
 562
 563                 if (!bi->skb) {
 564                         struct sk_buff *skb;
 565                         skb = netdev_alloc_skb(adapter->netdev, bufsz);
 566
 567                         if (!skb) {
 568                                 adapter->alloc_rx_buff_failed++;
 569                                 goto no_buffers;
 570                         }
 571
 572                         /*
 573                          * Make buffer alignment 2 beyond a 16 byte boundary
 574                          * this will result in a 16 byte aligned IP header after
 575                          * the 14 byte MAC header is removed
 576                          */
 577                         skb_reserve(skb, NET_IP_ALIGN);
 578
 579                         bi->skb = skb;
 580                         bi->dma = pci_map_single(pdev, skb->data, bufsz,
 581                                                  PCI_DMA_FROMDEVICE);
 582                 }
 583                 /* Refresh the desc even if buffer_addrs didn't change because
 584                  * each write-back erases this info. */
 585                 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
 586                         rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
 587                         rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
 588                 } else {
 589                         rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
 590                 }
 591
 592                 i++;
 593                 if (i == rx_ring->count)
 594                         i = 0;
 595                 bi = &rx_ring->rx_buffer_info[i];
 596         }
 597
 598 no_buffers:
 599         if (rx_ring->next_to_use != i) {
 600                 rx_ring->next_to_use = i;
 601                 if (i-- == 0)
 602                         i = (rx_ring->count - 1);
 603
 604                 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
 605         }
 606 }
 607
 608 static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
 609 {
 610         return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
 611 }
 612
 613 static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
 614 {
 615         return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
 616 }
 617
 618 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
 619                                struct ixgbe_ring *rx_ring,
 620                                int *work_done, int work_to_do)
 621 {
 622         struct ixgbe_adapter *adapter = q_vector->adapter;
 623         struct pci_dev *pdev = adapter->pdev;
 624         union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
 625         struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
 626         struct sk_buff *skb;
 627         unsigned int i;
 628         u32 len, staterr;
 629         u16 hdr_info;
 630         bool cleaned = false;
 631         int cleaned_count = 0;
 632         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
 633
 634         i = rx_ring->next_to_clean;
 635         rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
 636         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 637         rx_buffer_info = &rx_ring->rx_buffer_info[i];
 638
 639         while (staterr & IXGBE_RXD_STAT_DD) {
 640                 u32 upper_len = 0;
 641                 if (*work_done >= work_to_do)
 642                         break;
 643                 (*work_done)++;
 644
 645                 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
 646                         hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
 647                         len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
 648                                IXGBE_RXDADV_HDRBUFLEN_SHIFT;
 649                         if (hdr_info & IXGBE_RXDADV_SPH)
 650                                 adapter->rx_hdr_split++;
 651                         if (len > IXGBE_RX_HDR_SIZE)
 652                                 len = IXGBE_RX_HDR_SIZE;
 653                         upper_len = le16_to_cpu(rx_desc->wb.upper.length);
 654                 } else {
 655                         len = le16_to_cpu(rx_desc->wb.upper.length);
 656                 }
 657
 658                 cleaned = true;
 659                 skb = rx_buffer_info->skb;
 660                 prefetch(skb->data - NET_IP_ALIGN);
 661                 rx_buffer_info->skb = NULL;
 662
 663                 if (len && !skb_shinfo(skb)->nr_frags) {
 664                         pci_unmap_single(pdev, rx_buffer_info->dma,
 665                                          rx_ring->rx_buf_len,
 666                                          PCI_DMA_FROMDEVICE);
 667                         skb_put(skb, len);
 668                 }
 669
 670                 if (upper_len) {
 671                         pci_unmap_page(pdev, rx_buffer_info->page_dma,
 672                                        PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
 673                         rx_buffer_info->page_dma = 0;
 674                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
 675                                            rx_buffer_info->page,
 676                                            rx_buffer_info->page_offset,
 677                                            upper_len);
 678
 679                         if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
 680                             (page_count(rx_buffer_info->page) != 1))
 681                                 rx_buffer_info->page = NULL;
 682                         else
 683                                 get_page(rx_buffer_info->page);
 684
 685                         skb->len += upper_len;
 686                         skb->data_len += upper_len;
 687                         skb->truesize += upper_len;
 688                 }
 689
 690                 i++;
 691                 if (i == rx_ring->count)
 692                         i = 0;
 693                 next_buffer = &rx_ring->rx_buffer_info[i];
 694
 695                 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
 696                 prefetch(next_rxd);
 697
 698                 cleaned_count++;
 699                 if (staterr & IXGBE_RXD_STAT_EOP) {
 700                         rx_ring->stats.packets++;
 701                         rx_ring->stats.bytes += skb->len;
 702                 } else {
 703                         rx_buffer_info->skb = next_buffer->skb;
 704                         rx_buffer_info->dma = next_buffer->dma;
 705                         next_buffer->skb = skb;
 706                         next_buffer->dma = 0;
 707                         adapter->non_eop_descs++;
 708                         goto next_desc;
 709                 }
 710
 711                 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
 712                         dev_kfree_skb_irq(skb);
 713                         goto next_desc;
 714                 }
 715
 716                 ixgbe_rx_checksum(adapter, staterr, skb);
 717
 718                 /* probably a little skewed due to removing CRC */
 719                 total_rx_bytes += skb->len;
 720                 total_rx_packets++;
 721
 722                 skb->protocol = eth_type_trans(skb, adapter->netdev);
 723                 ixgbe_receive_skb(q_vector, skb, staterr, rx_desc);
 724
 725 next_desc:
 726                 rx_desc->wb.upper.status_error = 0;
 727
 728                 /* return some buffers to hardware, one at a time is too slow */
 729                 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
 730                         ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
 731                         cleaned_count = 0;
 732                 }
 733
 734                 /* use prefetched values */
 735                 rx_desc = next_rxd;
 736                 rx_buffer_info = next_buffer;
 737
 738                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 739         }
 740
 741         rx_ring->next_to_clean = i;
 742         cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
 743
 744         if (cleaned_count)
 745                 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
 746
 747         rx_ring->total_packets += total_rx_packets;
 748         rx_ring->total_bytes += total_rx_bytes;
 749         adapter->net_stats.rx_bytes += total_rx_bytes;
 750         adapter->net_stats.rx_packets += total_rx_packets;
 751
 752         return cleaned;
 753 }
 754
 755 static int ixgbe_clean_rxonly(struct napi_struct *, int);
 756 /**
 757  * ixgbe_configure_msix - Configure MSI-X hardware
 758  * @adapter: board private structure
 759  *
 760  * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
 761  * interrupts.
 762  **/
 763 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
 764 {
 765         struct ixgbe_q_vector *q_vector;
 766         int i, j, q_vectors, v_idx, r_idx;
 767         u32 mask;
 768
 769         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
 770
 771         /*
 772          * Populate the IVAR table and set the ITR values to the
 773          * corresponding register.
 774          */
 775         for (v_idx = 0; v_idx < q_vectors; v_idx++) {
 776                 q_vector = &adapter->q_vector[v_idx];
 777                 /* XXX for_each_bit(...) */
 778                 r_idx = find_first_bit(q_vector->rxr_idx,
 779                                        adapter->num_rx_queues);
 780
 781                 for (i = 0; i < q_vector->rxr_count; i++) {
 782                         j = adapter->rx_ring[r_idx].reg_idx;
 783                         ixgbe_set_ivar(adapter, 0, j, v_idx);
 784                         r_idx = find_next_bit(q_vector->rxr_idx,
 785                                               adapter->num_rx_queues,
 786                                               r_idx + 1);
 787                 }
 788                 r_idx = find_first_bit(q_vector->txr_idx,
 789                                        adapter->num_tx_queues);
 790
 791                 for (i = 0; i < q_vector->txr_count; i++) {
 792                         j = adapter->tx_ring[r_idx].reg_idx;
 793                         ixgbe_set_ivar(adapter, 1, j, v_idx);
 794                         r_idx = find_next_bit(q_vector->txr_idx,
 795                                               adapter->num_tx_queues,
 796                                               r_idx + 1);
 797                 }
 798
 799                 /* if this is a tx only vector halve the interrupt rate */
 800                 if (q_vector->txr_count && !q_vector->rxr_count)
 801                         q_vector->eitr = (adapter->eitr_param >> 1);
 802                 else if (q_vector->rxr_count)
 803                         /* rx only */
 804                         q_vector->eitr = adapter->eitr_param;
 805
 806                 /*
 807                  * since this is initial set up don't need to call
 808                  * ixgbe_write_eitr helper
 809                  */
 810                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx),
 811                                 EITR_INTS_PER_SEC_TO_REG(q_vector->eitr));
 812         }
 813
 814         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
 815                 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
 816                                v_idx);
 817         else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
 818                 ixgbe_set_ivar(adapter, -1, 1, v_idx);
 819         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
 820
 821         /* set up to autoclear timer, and the vectors */
 822         mask = IXGBE_EIMS_ENABLE_MASK;
 823         mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
 824         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
 825 }
 826
 827 enum latency_range {
 828         lowest_latency = 0,
 829         low_latency = 1,
 830         bulk_latency = 2,
 831         latency_invalid = 255
 832 };
 833
 834 /**
 835  * ixgbe_update_itr - update the dynamic ITR value based on statistics
 836  * @adapter: pointer to adapter
 837  * @eitr: eitr setting (ints per sec) to give last timeslice
 838  * @itr_setting: current throttle rate in ints/second
 839  * @packets: the number of packets during this measurement interval
 840  * @bytes: the number of bytes during this measurement interval
 841  *
 842  *      Stores a new ITR value based on packets and byte
 843  *      counts during the last interrupt.  The advantage of per interrupt
 844  *      computation is faster updates and more accurate ITR for the current
 845  *      traffic pattern.  Constants in this function were computed
 846  *      based on theoretical maximum wire speed and thresholds were set based
 847  *      on testing data as well as attempting to minimize response time
 848  *      while increasing bulk throughput.
 849  *      this functionality is controlled by the InterruptThrottleRate module
 850  *      parameter (see ixgbe_param.c)
 851  **/
 852 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
 853                            u32 eitr, u8 itr_setting,
 854                            int packets, int bytes)
 855 {
 856         unsigned int retval = itr_setting;
 857         u32 timepassed_us;
 858         u64 bytes_perint;
 859
 860         if (packets == 0)
 861                 goto update_itr_done;
 862
 863
 864         /* simple throttlerate management
 865          *    0-20MB/s lowest (100000 ints/s)
 866          *   20-100MB/s low   (20000 ints/s)
 867          *  100-1249MB/s bulk (8000 ints/s)
 868          */
 869         /* what was last interrupt timeslice? */
 870         timepassed_us = 1000000/eitr;
 871         bytes_perint = bytes / timepassed_us; /* bytes/usec */
 872
 873         switch (itr_setting) {
 874         case lowest_latency:
 875                 if (bytes_perint > adapter->eitr_low)
 876                         retval = low_latency;
 877                 break;
 878         case low_latency:
 879                 if (bytes_perint > adapter->eitr_high)
 880                         retval = bulk_latency;
 881                 else if (bytes_perint <= adapter->eitr_low)
 882                         retval = lowest_latency;
 883                 break;
 884         case bulk_latency:
 885                 if (bytes_perint <= adapter->eitr_high)
 886                         retval = low_latency;
 887                 break;
 888         }
 889
 890 update_itr_done:
 891         return retval;
 892 }
 893
 894 /**
 895  * ixgbe_write_eitr - write EITR register in hardware specific way
 896  * @adapter: pointer to adapter struct
 897  * @v_idx: vector index into q_vector array
 898  * @itr_reg: new value to be written in *register* format, not ints/s
 899  *
 900  * This function is made to be called by ethtool and by the driver
 901  * when it needs to update EITR registers at runtime.  Hardware
 902  * specific quirks/differences are taken care of here.
 903  */
 904 void ixgbe_write_eitr(struct ixgbe_adapter *adapter, int v_idx, u32 itr_reg)
 905 {
 906         struct ixgbe_hw *hw = &adapter->hw;
 907         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 908                 /* must write high and low 16 bits to reset counter */
 909                 itr_reg |= (itr_reg << 16);
 910         } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 911                 /*
 912                  * set the WDIS bit to not clear the timer bits and cause an
 913                  * immediate assertion of the interrupt
 914                  */
 915                 itr_reg |= IXGBE_EITR_CNT_WDIS;
 916         }
 917         IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
 918 }
 919
 920 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
 921 {
 922         struct ixgbe_adapter *adapter = q_vector->adapter;
 923         u32 new_itr;
 924         u8 current_itr, ret_itr;
 925         int i, r_idx, v_idx = ((void *)q_vector - (void *)(adapter->q_vector)) /
 926                                sizeof(struct ixgbe_q_vector);
 927         struct ixgbe_ring *rx_ring, *tx_ring;
 928
 929         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
 930         for (i = 0; i < q_vector->txr_count; i++) {
 931                 tx_ring = &(adapter->tx_ring[r_idx]);
 932                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
 933                                            q_vector->tx_itr,
 934                                            tx_ring->total_packets,
 935                                            tx_ring->total_bytes);
 936                 /* if the result for this queue would decrease interrupt
 937                  * rate for this vector then use that result */
 938                 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
 939                                     q_vector->tx_itr - 1 : ret_itr);
 940                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
 941                                       r_idx + 1);
 942         }
 943
 944         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
 945         for (i = 0; i < q_vector->rxr_count; i++) {
 946                 rx_ring = &(adapter->rx_ring[r_idx]);
 947                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
 948                                            q_vector->rx_itr,
 949                                            rx_ring->total_packets,
 950                                            rx_ring->total_bytes);
 951                 /* if the result for this queue would decrease interrupt
 952                  * rate for this vector then use that result */
 953                 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
 954                                     q_vector->rx_itr - 1 : ret_itr);
 955                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
 956                                       r_idx + 1);
 957         }
 958
 959         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
 960
 961         switch (current_itr) {
 962         /* counts and packets in update_itr are dependent on these numbers */
 963         case lowest_latency:
 964                 new_itr = 100000;
 965                 break;
 966         case low_latency:
 967                 new_itr = 20000; /* aka hwitr = ~200 */
 968                 break;
 969         case bulk_latency:
 970         default:
 971                 new_itr = 8000;
 972                 break;
 973         }
 974
 975         if (new_itr != q_vector->eitr) {
 976                 u32 itr_reg;
 977
 978                 /* save the algorithm value here, not the smoothed one */
 979                 q_vector->eitr = new_itr;
 980                 /* do an exponential smoothing */
 981                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
 982                 itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr);
 983                 ixgbe_write_eitr(adapter, v_idx, itr_reg);
 984         }
 985
 986         return;
 987 }
 988
 989 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
 990 {
 991         struct ixgbe_hw *hw = &adapter->hw;
 992
 993         if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
 994             (eicr & IXGBE_EICR_GPI_SDP1)) {
 995                 DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n");
 996                 /* write to clear the interrupt */
 997                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
 998         }
 999 }
1000
1001 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1002 {
1003         struct ixgbe_hw *hw = &adapter->hw;
1004
1005         if (eicr & IXGBE_EICR_GPI_SDP1) {
1006                 /* Clear the interrupt */
1007                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1008                 schedule_work(&adapter->multispeed_fiber_task);
1009         } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1010                 /* Clear the interrupt */
1011                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1012                 schedule_work(&adapter->sfp_config_module_task);
1013         } else {
1014                 /* Interrupt isn't for us... */
1015                 return;
1016         }
1017 }
1018
1019 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1020 {
1021         struct ixgbe_hw *hw = &adapter->hw;
1022
1023         adapter->lsc_int++;
1024         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1025         adapter->link_check_timeout = jiffies;
1026         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1027                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1028                 schedule_work(&adapter->watchdog_task);
1029         }
1030 }
1031
1032 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1033 {
1034         struct net_device *netdev = data;
1035         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1036         struct ixgbe_hw *hw = &adapter->hw;
1037         u32 eicr;
1038
1039         /*
1040          * Workaround for Silicon errata.  Use clear-by-write instead
1041          * of clear-by-read.  Reading with EICS will return the
1042          * interrupt causes without clearing, which later be done
1043          * with the write to EICR.
1044          */
1045         eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1046         IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1047
1048         if (eicr & IXGBE_EICR_LSC)
1049                 ixgbe_check_lsc(adapter);
1050
1051         if (hw->mac.type == ixgbe_mac_82598EB)
1052                 ixgbe_check_fan_failure(adapter, eicr);
1053
1054         if (hw->mac.type == ixgbe_mac_82599EB)
1055                 ixgbe_check_sfp_event(adapter, eicr);
1056         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1057                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
1058
1059         return IRQ_HANDLED;
1060 }
1061
1062 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1063 {
1064         struct ixgbe_q_vector *q_vector = data;
1065         struct ixgbe_adapter  *adapter = q_vector->adapter;
1066         struct ixgbe_ring     *tx_ring;
1067         int i, r_idx;
1068
1069         if (!q_vector->txr_count)
1070                 return IRQ_HANDLED;
1071
1072         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1073         for (i = 0; i < q_vector->txr_count; i++) {
1074                 tx_ring = &(adapter->tx_ring[r_idx]);
1075 #ifdef CONFIG_IXGBE_DCA
1076                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1077                         ixgbe_update_tx_dca(adapter, tx_ring);
1078 #endif
1079                 tx_ring->total_bytes = 0;
1080                 tx_ring->total_packets = 0;
1081                 ixgbe_clean_tx_irq(adapter, tx_ring);
1082                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1083                                       r_idx + 1);
1084         }
1085
1086         return IRQ_HANDLED;
1087 }
1088
1089 /**
1090  * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1091  * @irq: unused
1092  * @data: pointer to our q_vector struct for this interrupt vector
1093  **/
1094 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1095 {
1096         struct ixgbe_q_vector *q_vector = data;
1097         struct ixgbe_adapter  *adapter = q_vector->adapter;
1098         struct ixgbe_ring  *rx_ring;
1099         int r_idx;
1100         int i;
1101
1102         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1103         for (i = 0;  i < q_vector->rxr_count; i++) {
1104                 rx_ring = &(adapter->rx_ring[r_idx]);
1105                 rx_ring->total_bytes = 0;
1106                 rx_ring->total_packets = 0;
1107                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1108                                       r_idx + 1);
1109         }
1110
1111         if (!q_vector->rxr_count)
1112                 return IRQ_HANDLED;
1113
1114         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1115         rx_ring = &(adapter->rx_ring[r_idx]);
1116         /* disable interrupts on this vector only */
1117         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, rx_ring->v_idx);
1118         napi_schedule(&q_vector->napi);
1119
1120         return IRQ_HANDLED;
1121 }
1122
1123 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1124 {
1125         ixgbe_msix_clean_rx(irq, data);
1126         ixgbe_msix_clean_tx(irq, data);
1127
1128         return IRQ_HANDLED;
1129 }
1130
1131 /**
1132  * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1133  * @napi: napi struct with our devices info in it
1134  * @budget: amount of work driver is allowed to do this pass, in packets
1135  *
1136  * This function is optimized for cleaning one queue only on a single
1137  * q_vector!!!
1138  **/
1139 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1140 {
1141         struct ixgbe_q_vector *q_vector =
1142                                container_of(napi, struct ixgbe_q_vector, napi);
1143         struct ixgbe_adapter *adapter = q_vector->adapter;
1144         struct ixgbe_ring *rx_ring = NULL;
1145         int work_done = 0;
1146         long r_idx;
1147
1148         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1149         rx_ring = &(adapter->rx_ring[r_idx]);
1150 #ifdef CONFIG_IXGBE_DCA
1151         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1152                 ixgbe_update_rx_dca(adapter, rx_ring);
1153 #endif
1154
1155         ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
1156
1157         /* If all Rx work done, exit the polling mode */
1158         if (work_done < budget) {
1159                 napi_complete(napi);
1160                 if (adapter->itr_setting & 1)
1161                         ixgbe_set_itr_msix(q_vector);
1162                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1163                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, rx_ring->v_idx);
1164         }
1165
1166         return work_done;
1167 }
1168
1169 /**
1170  * ixgbe_clean_rxonly_many - msix (aka one shot) rx clean routine
1171  * @napi: napi struct with our devices info in it
1172  * @budget: amount of work driver is allowed to do this pass, in packets
1173  *
1174  * This function will clean more than one rx queue associated with a
1175  * q_vector.
1176  **/
1177 static int ixgbe_clean_rxonly_many(struct napi_struct *napi, int budget)
1178 {
1179         struct ixgbe_q_vector *q_vector =
1180                                container_of(napi, struct ixgbe_q_vector, napi);
1181         struct ixgbe_adapter *adapter = q_vector->adapter;
1182         struct ixgbe_ring *rx_ring = NULL;
1183         int work_done = 0, i;
1184         long r_idx;
1185         u16 enable_mask = 0;
1186
1187         /* attempt to distribute budget to each queue fairly, but don't allow
1188          * the budget to go below 1 because we'll exit polling */
1189         budget /= (q_vector->rxr_count ?: 1);
1190         budget = max(budget, 1);
1191         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1192         for (i = 0; i < q_vector->rxr_count; i++) {
1193                 rx_ring = &(adapter->rx_ring[r_idx]);
1194 #ifdef CONFIG_IXGBE_DCA
1195                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1196                         ixgbe_update_rx_dca(adapter, rx_ring);
1197 #endif
1198                 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
1199                 enable_mask |= rx_ring->v_idx;
1200                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1201                                       r_idx + 1);
1202         }
1203
1204         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1205         rx_ring = &(adapter->rx_ring[r_idx]);
1206         /* If all Rx work done, exit the polling mode */
1207         if (work_done < budget) {
1208                 napi_complete(napi);
1209                 if (adapter->itr_setting & 1)
1210                         ixgbe_set_itr_msix(q_vector);
1211                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1212                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, enable_mask);
1213                 return 0;
1214         }
1215
1216         return work_done;
1217 }
1218 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
1219                                      int r_idx)
1220 {
1221         a->q_vector[v_idx].adapter = a;
1222         set_bit(r_idx, a->q_vector[v_idx].rxr_idx);
1223         a->q_vector[v_idx].rxr_count++;
1224         a->rx_ring[r_idx].v_idx = 1 << v_idx;
1225 }
1226
1227 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
1228                                      int r_idx)
1229 {
1230         a->q_vector[v_idx].adapter = a;
1231         set_bit(r_idx, a->q_vector[v_idx].txr_idx);
1232         a->q_vector[v_idx].txr_count++;
1233         a->tx_ring[r_idx].v_idx = 1 << v_idx;
1234 }
1235
1236 /**
1237  * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1238  * @adapter: board private structure to initialize
1239  * @vectors: allotted vector count for descriptor rings
1240  *
1241  * This function maps descriptor rings to the queue-specific vectors
1242  * we were allotted through the MSI-X enabling code.  Ideally, we'd have
1243  * one vector per ring/queue, but on a constrained vector budget, we
1244  * group the rings as "efficiently" as possible.  You would add new
1245  * mapping configurations in here.
1246  **/
1247 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
1248                                       int vectors)
1249 {
1250         int v_start = 0;
1251         int rxr_idx = 0, txr_idx = 0;
1252         int rxr_remaining = adapter->num_rx_queues;
1253         int txr_remaining = adapter->num_tx_queues;
1254         int i, j;
1255         int rqpv, tqpv;
1256         int err = 0;
1257
1258         /* No mapping required if MSI-X is disabled. */
1259         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1260                 goto out;
1261
1262         /*
1263          * The ideal configuration...
1264          * We have enough vectors to map one per queue.
1265          */
1266         if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
1267                 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
1268                         map_vector_to_rxq(adapter, v_start, rxr_idx);
1269
1270                 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
1271                         map_vector_to_txq(adapter, v_start, txr_idx);
1272
1273                 goto out;
1274         }
1275
1276         /*
1277          * If we don't have enough vectors for a 1-to-1
1278          * mapping, we'll have to group them so there are
1279          * multiple queues per vector.
1280          */
1281         /* Re-adjusting *qpv takes care of the remainder. */
1282         for (i = v_start; i < vectors; i++) {
1283                 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
1284                 for (j = 0; j < rqpv; j++) {
1285                         map_vector_to_rxq(adapter, i, rxr_idx);
1286                         rxr_idx++;
1287                         rxr_remaining--;
1288                 }
1289         }
1290         for (i = v_start; i < vectors; i++) {
1291                 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
1292                 for (j = 0; j < tqpv; j++) {
1293                         map_vector_to_txq(adapter, i, txr_idx);
1294                         txr_idx++;
1295                         txr_remaining--;
1296                 }
1297         }
1298
1299 out:
1300         return err;
1301 }
1302
1303 /**
1304  * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1305  * @adapter: board private structure
1306  *
1307  * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1308  * interrupts from the kernel.
1309  **/
1310 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
1311 {
1312         struct net_device *netdev = adapter->netdev;
1313         irqreturn_t (*handler)(int, void *);
1314         int i, vector, q_vectors, err;
1315         int ri=0, ti=0;
1316
1317         /* Decrement for Other and TCP Timer vectors */
1318         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1319
1320         /* Map the Tx/Rx rings to the vectors we were allotted. */
1321         err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
1322         if (err)
1323                 goto out;
1324
1325 #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
1326                          (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1327                          &ixgbe_msix_clean_many)
1328         for (vector = 0; vector < q_vectors; vector++) {
1329                 handler = SET_HANDLER(&adapter->q_vector[vector]);
1330
1331                 if(handler == &ixgbe_msix_clean_rx) {
1332                         sprintf(adapter->name[vector], "%s-%s-%d",
1333                                 netdev->name, "rx", ri++);
1334                 }
1335                 else if(handler == &ixgbe_msix_clean_tx) {
1336                         sprintf(adapter->name[vector], "%s-%s-%d",
1337                                 netdev->name, "tx", ti++);
1338                 }
1339                 else
1340                         sprintf(adapter->name[vector], "%s-%s-%d",
1341                                 netdev->name, "TxRx", vector);
1342
1343                 err = request_irq(adapter->msix_entries[vector].vector,
1344                                   handler, 0, adapter->name[vector],
1345                                   &(adapter->q_vector[vector]));
1346                 if (err) {
1347                         DPRINTK(PROBE, ERR,
1348                                 "request_irq failed for MSIX interrupt "
1349                                 "Error: %d\n", err);
1350                         goto free_queue_irqs;
1351                 }
1352         }
1353
1354         sprintf(adapter->name[vector], "%s:lsc", netdev->name);
1355         err = request_irq(adapter->msix_entries[vector].vector,
1356                           &ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
1357         if (err) {
1358                 DPRINTK(PROBE, ERR,
1359                         "request_irq for msix_lsc failed: %d\n", err);
1360                 goto free_queue_irqs;
1361         }
1362
1363         return 0;
1364
1365 free_queue_irqs:
1366         for (i = vector - 1; i >= 0; i--)
1367                 free_irq(adapter->msix_entries[--vector].vector,
1368                          &(adapter->q_vector[i]));
1369         adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1370         pci_disable_msix(adapter->pdev);
1371         kfree(adapter->msix_entries);
1372         adapter->msix_entries = NULL;
1373 out:
1374         return err;
1375 }
1376
1377 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
1378 {
1379         struct ixgbe_q_vector *q_vector = adapter->q_vector;
1380         u8 current_itr;
1381         u32 new_itr = q_vector->eitr;
1382         struct ixgbe_ring *rx_ring = &adapter->rx_ring[0];
1383         struct ixgbe_ring *tx_ring = &adapter->tx_ring[0];
1384
1385         q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
1386                                             q_vector->tx_itr,
1387                                             tx_ring->total_packets,
1388                                             tx_ring->total_bytes);
1389         q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
1390                                             q_vector->rx_itr,
1391                                             rx_ring->total_packets,
1392                                             rx_ring->total_bytes);
1393
1394         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1395
1396         switch (current_itr) {
1397         /* counts and packets in update_itr are dependent on these numbers */
1398         case lowest_latency:
1399                 new_itr = 100000;
1400                 break;
1401         case low_latency:
1402                 new_itr = 20000; /* aka hwitr = ~200 */
1403                 break;
1404         case bulk_latency:
1405                 new_itr = 8000;
1406                 break;
1407         default:
1408                 break;
1409         }
1410
1411         if (new_itr != q_vector->eitr) {
1412                 u32 itr_reg;
1413
1414                 /* save the algorithm value here, not the smoothed one */
1415                 q_vector->eitr = new_itr;
1416                 /* do an exponential smoothing */
1417                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1418                 itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr);
1419                 ixgbe_write_eitr(adapter, 0, itr_reg);
1420         }
1421
1422         return;
1423 }
1424
1425 /**
1426  * ixgbe_irq_enable - Enable default interrupt generation settings
1427  * @adapter: board private structure
1428  **/
1429 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1430 {
1431         u32 mask;
1432         mask = IXGBE_EIMS_ENABLE_MASK;
1433         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1434                 mask |= IXGBE_EIMS_GPI_SDP1;
1435         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1436                 mask |= IXGBE_EIMS_ECC;
1437                 mask |= IXGBE_EIMS_GPI_SDP1;
1438                 mask |= IXGBE_EIMS_GPI_SDP2;
1439         }
1440
1441         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1442         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1443                 /* enable the rest of the queue vectors */
1444                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1),
1445                                 (IXGBE_EIMS_RTX_QUEUE << 16));
1446                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(2),
1447                                 ((IXGBE_EIMS_RTX_QUEUE << 16) |
1448                                   IXGBE_EIMS_RTX_QUEUE));
1449         }
1450         IXGBE_WRITE_FLUSH(&adapter->hw);
1451 }
1452
1453 /**
1454  * ixgbe_intr - legacy mode Interrupt Handler
1455  * @irq: interrupt number
1456  * @data: pointer to a network interface device structure
1457  **/
1458 static irqreturn_t ixgbe_intr(int irq, void *data)
1459 {
1460         struct net_device *netdev = data;
1461         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1462         struct ixgbe_hw *hw = &adapter->hw;
1463         u32 eicr;
1464
1465         /*
1466          * Workaround for silicon errata.  Mask the interrupts
1467          * before the read of EICR.
1468          */
1469         IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1470
1471         /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1472          * therefore no explict interrupt disable is necessary */
1473         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
1474         if (!eicr) {
1475                 /* shared interrupt alert!
1476                  * make sure interrupts are enabled because the read will
1477                  * have disabled interrupts due to EIAM */
1478                 ixgbe_irq_enable(adapter);
1479                 return IRQ_NONE;        /* Not our interrupt */
1480         }
1481
1482         if (eicr & IXGBE_EICR_LSC)
1483                 ixgbe_check_lsc(adapter);
1484
1485         if (hw->mac.type == ixgbe_mac_82599EB)
1486                 ixgbe_check_sfp_event(adapter, eicr);
1487
1488         ixgbe_check_fan_failure(adapter, eicr);
1489
1490         if (napi_schedule_prep(&adapter->q_vector[0].napi)) {
1491                 adapter->tx_ring[0].total_packets = 0;
1492                 adapter->tx_ring[0].total_bytes = 0;
1493                 adapter->rx_ring[0].total_packets = 0;
1494                 adapter->rx_ring[0].total_bytes = 0;
1495                 /* would disable interrupts here but EIAM disabled it */
1496                 __napi_schedule(&adapter->q_vector[0].napi);
1497         }
1498
1499         return IRQ_HANDLED;
1500 }
1501
1502 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
1503 {
1504         int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1505
1506         for (i = 0; i < q_vectors; i++) {
1507                 struct ixgbe_q_vector *q_vector = &adapter->q_vector[i];
1508                 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1509                 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1510                 q_vector->rxr_count = 0;
1511                 q_vector->txr_count = 0;
1512         }
1513 }
1514
1515 /**
1516  * ixgbe_request_irq - initialize interrupts
1517  * @adapter: board private structure
1518  *
1519  * Attempts to configure interrupts using the best available
1520  * capabilities of the hardware and kernel.
1521  **/
1522 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
1523 {
1524         struct net_device *netdev = adapter->netdev;
1525         int err;
1526
1527         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1528                 err = ixgbe_request_msix_irqs(adapter);
1529         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1530                 err = request_irq(adapter->pdev->irq, &ixgbe_intr, 0,
1531                                   netdev->name, netdev);
1532         } else {
1533                 err = request_irq(adapter->pdev->irq, &ixgbe_intr, IRQF_SHARED,
1534                                   netdev->name, netdev);
1535         }
1536
1537         if (err)
1538                 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
1539
1540         return err;
1541 }
1542
1543 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
1544 {
1545         struct net_device *netdev = adapter->netdev;
1546
1547         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1548                 int i, q_vectors;
1549
1550                 q_vectors = adapter->num_msix_vectors;
1551
1552                 i = q_vectors - 1;
1553                 free_irq(adapter->msix_entries[i].vector, netdev);
1554
1555                 i--;
1556                 for (; i >= 0; i--) {
1557                         free_irq(adapter->msix_entries[i].vector,
1558                                  &(adapter->q_vector[i]));
1559                 }
1560
1561                 ixgbe_reset_q_vectors(adapter);
1562         } else {
1563                 free_irq(adapter->pdev->irq, netdev);
1564         }
1565 }
1566
1567 /**
1568  * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1569  * @adapter: board private structure
1570  **/
1571 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
1572 {
1573         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
1574         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1575                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
1576                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(2), ~0);
1577         }
1578         IXGBE_WRITE_FLUSH(&adapter->hw);
1579         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1580                 int i;
1581                 for (i = 0; i < adapter->num_msix_vectors; i++)
1582                         synchronize_irq(adapter->msix_entries[i].vector);
1583         } else {
1584                 synchronize_irq(adapter->pdev->irq);
1585         }
1586 }
1587
1588 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter)
1589 {
1590         u32 mask = IXGBE_EIMS_RTX_QUEUE;
1591         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1592         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1593                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask << 16);
1594                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(2),
1595                                 (mask << 16 | mask));
1596         }
1597         /* skip the flush */
1598 }
1599
1600 /**
1601  * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
1602  *
1603  **/
1604 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
1605 {
1606         struct ixgbe_hw *hw = &adapter->hw;
1607
1608         IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
1609                         EITR_INTS_PER_SEC_TO_REG(adapter->eitr_param));
1610
1611         ixgbe_set_ivar(adapter, 0, 0, 0);
1612         ixgbe_set_ivar(adapter, 1, 0, 0);
1613
1614         map_vector_to_rxq(adapter, 0, 0);
1615         map_vector_to_txq(adapter, 0, 0);
1616
1617         DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
1618 }
1619
1620 /**
1621  * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
1622  * @adapter: board private structure
1623  *
1624  * Configure the Tx unit of the MAC after a reset.
1625  **/
1626 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
1627 {
1628         u64 tdba;
1629         struct ixgbe_hw *hw = &adapter->hw;
1630         u32 i, j, tdlen, txctrl;
1631
1632         /* Setup the HW Tx Head and Tail descriptor pointers */
1633         for (i = 0; i < adapter->num_tx_queues; i++) {
1634                 struct ixgbe_ring *ring = &adapter->tx_ring[i];
1635                 j = ring->reg_idx;
1636                 tdba = ring->dma;
1637                 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
1638                 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
1639                                 (tdba & DMA_BIT_MASK(32)));
1640                 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
1641                 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
1642                 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
1643                 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
1644                 adapter->tx_ring[i].head = IXGBE_TDH(j);
1645                 adapter->tx_ring[i].tail = IXGBE_TDT(j);
1646                 /* Disable Tx Head Writeback RO bit, since this hoses
1647                  * bookkeeping if things aren't delivered in order.
1648                  */
1649                 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
1650                 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
1651                 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
1652         }
1653         if (hw->mac.type == ixgbe_mac_82599EB) {
1654                 /* We enable 8 traffic classes, DCB only */
1655                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
1656                         IXGBE_WRITE_REG(hw, IXGBE_MTQC, (IXGBE_MTQC_RT_ENA |
1657                                         IXGBE_MTQC_8TC_8TQ));
1658         }
1659 }
1660
1661 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
1662
1663 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, int index)
1664 {
1665         struct ixgbe_ring *rx_ring;
1666         u32 srrctl;
1667         int queue0 = 0;
1668         unsigned long mask;
1669
1670         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1671                 queue0 = index;
1672         } else {
1673                 mask = (unsigned long) adapter->ring_feature[RING_F_RSS].mask;
1674                 queue0 = index & mask;
1675                 index = index & mask;
1676         }
1677
1678         rx_ring = &adapter->rx_ring[queue0];
1679
1680         srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
1681
1682         srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
1683         srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
1684
1685         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
1686                 u16 bufsz = IXGBE_RXBUFFER_2048;
1687                 /* grow the amount we can receive on large page machines */
1688                 if (bufsz < (PAGE_SIZE / 2))
1689                         bufsz = (PAGE_SIZE / 2);
1690                 /* cap the bufsz at our largest descriptor size */
1691                 bufsz = min((u16)IXGBE_MAX_RXBUFFER, bufsz);
1692
1693                 srrctl |= bufsz >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1694                 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1695                 srrctl |= ((IXGBE_RX_HDR_SIZE <<
1696                             IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
1697                            IXGBE_SRRCTL_BSIZEHDR_MASK);
1698         } else {
1699                 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
1700
1701                 if (rx_ring->rx_buf_len == MAXIMUM_ETHERNET_VLAN_SIZE)
1702                         srrctl |= IXGBE_RXBUFFER_2048 >>
1703                                   IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1704                 else
1705                         srrctl |= rx_ring->rx_buf_len >>
1706                                   IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1707         }
1708
1709         IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
1710 }
1711
1712 /**
1713  * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
1714  * @adapter: board private structure
1715  *
1716  * Configure the Rx unit of the MAC after a reset.
1717  **/
1718 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
1719 {
1720         u64 rdba;
1721         struct ixgbe_hw *hw = &adapter->hw;
1722         struct net_device *netdev = adapter->netdev;
1723         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1724         int i, j;
1725         u32 rdlen, rxctrl, rxcsum;
1726         static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
1727                           0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
1728                           0x6A3E67EA, 0x14364D17, 0x3BED200D};
1729         u32 fctrl, hlreg0;
1730         u32 reta = 0, mrqc = 0;
1731         u32 rdrxctl;
1732         int rx_buf_len;
1733
1734         /* Decide whether to use packet split mode or not */
1735         adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
1736
1737         /* Set the RX buffer length according to the mode */
1738         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
1739                 rx_buf_len = IXGBE_RX_HDR_SIZE;
1740                 if (hw->mac.type == ixgbe_mac_82599EB) {
1741                         /* PSRTYPE must be initialized in 82599 */
1742                         u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
1743                                       IXGBE_PSRTYPE_UDPHDR |
1744                                       IXGBE_PSRTYPE_IPV4HDR |
1745                                       IXGBE_PSRTYPE_IPV6HDR;
1746                         IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(0), psrtype);
1747                 }
1748         } else {
1749                 if (netdev->mtu <= ETH_DATA_LEN)
1750                         rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
1751                 else
1752                         rx_buf_len = ALIGN(max_frame, 1024);
1753         }
1754
1755         fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
1756         fctrl |= IXGBE_FCTRL_BAM;
1757         fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
1758         fctrl |= IXGBE_FCTRL_PMCF;
1759         IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
1760
1761         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
1762         if (adapter->netdev->mtu <= ETH_DATA_LEN)
1763                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
1764         else
1765                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
1766         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
1767
1768         rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc);
1769         /* disable receives while setting up the descriptors */
1770         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1771         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
1772
1773         /* Setup the HW Rx Head and Tail Descriptor Pointers and
1774          * the Base and Length of the Rx Descriptor Ring */
1775         for (i = 0; i < adapter->num_rx_queues; i++) {
1776                 rdba = adapter->rx_ring[i].dma;
1777                 j = adapter->rx_ring[i].reg_idx;
1778                 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_BIT_MASK(32)));
1779                 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
1780                 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
1781                 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
1782                 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
1783                 adapter->rx_ring[i].head = IXGBE_RDH(j);
1784                 adapter->rx_ring[i].tail = IXGBE_RDT(j);
1785                 adapter->rx_ring[i].rx_buf_len = rx_buf_len;
1786
1787                 ixgbe_configure_srrctl(adapter, j);
1788         }
1789
1790         if (hw->mac.type == ixgbe_mac_82598EB) {
1791                 /*
1792                  * For VMDq support of different descriptor types or
1793                  * buffer sizes through the use of multiple SRRCTL
1794                  * registers, RDRXCTL.MVMEN must be set to 1
1795                  *
1796                  * also, the manual doesn't mention it clearly but DCA hints
1797                  * will only use queue 0's tags unless this bit is set.  Side
1798                  * effects of setting this bit are only that SRRCTL must be
1799                  * fully programmed [0..15]
1800                  */
1801                 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1802                 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
1803                 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
1804         }
1805
1806         /* Program MRQC for the distribution of queues */
1807         if (hw->mac.type == ixgbe_mac_82599EB) {
1808                 int mask = adapter->flags & (
1809                                 IXGBE_FLAG_RSS_ENABLED
1810                                 | IXGBE_FLAG_DCB_ENABLED
1811                                 );
1812
1813                 switch (mask) {
1814                 case (IXGBE_FLAG_RSS_ENABLED):
1815                         mrqc = IXGBE_MRQC_RSSEN;
1816                         break;
1817                 case (IXGBE_FLAG_DCB_ENABLED):
1818                         mrqc = IXGBE_MRQC_RT8TCEN;
1819                         break;
1820                 default:
1821                         break;
1822                 }
1823         }
1824         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
1825                 /* Fill out redirection table */
1826                 for (i = 0, j = 0; i < 128; i++, j++) {
1827                         if (j == adapter->ring_feature[RING_F_RSS].indices)
1828                                 j = 0;
1829                         /* reta = 4-byte sliding window of
1830                          * 0x00..(indices-1)(indices-1)00..etc. */
1831                         reta = (reta << 8) | (j * 0x11);
1832                         if ((i & 3) == 3)
1833                                 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
1834                 }
1835
1836                 /* Fill out hash function seeds */
1837                 for (i = 0; i < 10; i++)
1838                         IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
1839
1840                 if (hw->mac.type == ixgbe_mac_82598EB)
1841                         mrqc |= IXGBE_MRQC_RSSEN;
1842                     /* Perform hash on these packet types */
1843                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
1844                       | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
1845                       | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
1846                       | IXGBE_MRQC_RSS_FIELD_IPV6
1847                       | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
1848                       | IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
1849         }
1850         IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
1851
1852         rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
1853
1854         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
1855             adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
1856                 /* Disable indicating checksum in descriptor, enables
1857                  * RSS hash */
1858                 rxcsum |= IXGBE_RXCSUM_PCSD;
1859         }
1860         if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
1861                 /* Enable IPv4 payload checksum for UDP fragments
1862                  * if PCSD is not set */
1863                 rxcsum |= IXGBE_RXCSUM_IPPCSE;
1864         }
1865
1866         IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
1867
1868         if (hw->mac.type == ixgbe_mac_82599EB) {
1869                 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1870                 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
1871                 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
1872         }
1873 }
1874
1875 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
1876 {
1877         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1878         struct ixgbe_hw *hw = &adapter->hw;
1879
1880         /* add VID to filter table */
1881         hw->mac.ops.set_vfta(&adapter->hw, vid, 0, true);
1882 }
1883
1884 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
1885 {
1886         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1887         struct ixgbe_hw *hw = &adapter->hw;
1888
1889         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1890                 ixgbe_irq_disable(adapter);
1891
1892         vlan_group_set_device(adapter->vlgrp, vid, NULL);
1893
1894         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1895                 ixgbe_irq_enable(adapter);
1896
1897         /* remove VID from filter table */
1898         hw->mac.ops.set_vfta(&adapter->hw, vid, 0, false);
1899 }
1900
1901 static void ixgbe_vlan_rx_register(struct net_device *netdev,
1902                                    struct vlan_group *grp)
1903 {
1904         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1905         u32 ctrl;
1906         int i, j;
1907
1908         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1909                 ixgbe_irq_disable(adapter);
1910         adapter->vlgrp = grp;
1911
1912         /*
1913          * For a DCB driver, always enable VLAN tag stripping so we can
1914          * still receive traffic from a DCB-enabled host even if we're
1915          * not in DCB mode.
1916          */
1917         ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
1918         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1919                 ctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
1920                 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
1921                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
1922         } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1923                 ctrl |= IXGBE_VLNCTRL_VFE;
1924                 /* enable VLAN tag insert/strip */
1925                 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
1926                 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
1927                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
1928                 for (i = 0; i < adapter->num_rx_queues; i++) {
1929                         j = adapter->rx_ring[i].reg_idx;
1930                         ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(j));
1931                         ctrl |= IXGBE_RXDCTL_VME;
1932                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(j), ctrl);
1933                 }
1934         }
1935         ixgbe_vlan_rx_add_vid(netdev, 0);
1936
1937         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1938                 ixgbe_irq_enable(adapter);
1939 }
1940
1941 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
1942 {
1943         ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
1944
1945         if (adapter->vlgrp) {
1946                 u16 vid;
1947                 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
1948                         if (!vlan_group_get_device(adapter->vlgrp, vid))
1949                                 continue;
1950                         ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
1951                 }
1952         }
1953 }
1954
1955 static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq)
1956 {
1957         struct dev_mc_list *mc_ptr;
1958         u8 *addr = *mc_addr_ptr;
1959         *vmdq = 0;
1960
1961         mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]);
1962         if (mc_ptr->next)
1963                 *mc_addr_ptr = mc_ptr->next->dmi_addr;
1964         else
1965                 *mc_addr_ptr = NULL;
1966
1967         return addr;
1968 }
1969
1970 /**
1971  * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
1972  * @netdev: network interface device structure
1973  *
1974  * The set_rx_method entry point is called whenever the unicast/multicast
1975  * address list or the network interface flags are updated.  This routine is
1976  * responsible for configuring the hardware for proper unicast, multicast and
1977  * promiscuous mode.
1978  **/
1979 static void ixgbe_set_rx_mode(struct net_device *netdev)
1980 {
1981         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1982         struct ixgbe_hw *hw = &adapter->hw;
1983         u32 fctrl, vlnctrl;
1984         u8 *addr_list = NULL;
1985         int addr_count = 0;
1986
1987         /* Check for Promiscuous and All Multicast modes */
1988
1989         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1990         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1991
1992         if (netdev->flags & IFF_PROMISC) {
1993                 hw->addr_ctrl.user_set_promisc = 1;
1994                 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
1995                 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1996         } else {
1997                 if (netdev->flags & IFF_ALLMULTI) {
1998                         fctrl |= IXGBE_FCTRL_MPE;
1999                         fctrl &= ~IXGBE_FCTRL_UPE;
2000                 } else {
2001                         fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2002                 }
2003                 vlnctrl |= IXGBE_VLNCTRL_VFE;
2004                 hw->addr_ctrl.user_set_promisc = 0;
2005         }
2006
2007         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2008         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2009
2010         /* reprogram secondary unicast list */
2011         addr_count = netdev->uc_count;
2012         if (addr_count)
2013                 addr_list = netdev->uc_list->dmi_addr;
2014         hw->mac.ops.update_uc_addr_list(hw, addr_list, addr_count,
2015                                           ixgbe_addr_list_itr);
2016
2017         /* reprogram multicast list */
2018         addr_count = netdev->mc_count;
2019         if (addr_count)
2020                 addr_list = netdev->mc_list->dmi_addr;
2021         hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count,
2022                                         ixgbe_addr_list_itr);
2023 }
2024
2025 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
2026 {
2027         int q_idx;
2028         struct ixgbe_q_vector *q_vector;
2029         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2030
2031         /* legacy and MSI only use one vector */
2032         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2033                 q_vectors = 1;
2034
2035         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2036                 struct napi_struct *napi;
2037                 q_vector = &adapter->q_vector[q_idx];
2038                 if (!q_vector->rxr_count)
2039                         continue;
2040                 napi = &q_vector->napi;
2041                 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) &&
2042                     (q_vector->rxr_count > 1))
2043                         napi->poll = &ixgbe_clean_rxonly_many;
2044
2045                 napi_enable(napi);
2046         }
2047 }
2048
2049 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
2050 {
2051         int q_idx;
2052         struct ixgbe_q_vector *q_vector;
2053         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2054
2055         /* legacy and MSI only use one vector */
2056         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2057                 q_vectors = 1;
2058
2059         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2060                 q_vector = &adapter->q_vector[q_idx];
2061                 if (!q_vector->rxr_count)
2062                         continue;
2063                 napi_disable(&q_vector->napi);
2064         }
2065 }
2066
2067 #ifdef CONFIG_IXGBE_DCB
2068 /*
2069  * ixgbe_configure_dcb - Configure DCB hardware
2070  * @adapter: ixgbe adapter struct
2071  *
2072  * This is called by the driver on open to configure the DCB hardware.
2073  * This is also called by the gennetlink interface when reconfiguring
2074  * the DCB state.
2075  */
2076 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
2077 {
2078         struct ixgbe_hw *hw = &adapter->hw;
2079         u32 txdctl, vlnctrl;
2080         int i, j;
2081
2082         ixgbe_dcb_check_config(&adapter->dcb_cfg);
2083         ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
2084         ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
2085
2086         /* reconfigure the hardware */
2087         ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
2088
2089         for (i = 0; i < adapter->num_tx_queues; i++) {
2090                 j = adapter->tx_ring[i].reg_idx;
2091                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2092                 /* PThresh workaround for Tx hang with DFP enabled. */
2093                 txdctl |= 32;
2094                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2095         }
2096         /* Enable VLAN tag insert/strip */
2097         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2098         if (hw->mac.type == ixgbe_mac_82598EB) {
2099                 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2100                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2101                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2102         } else if (hw->mac.type == ixgbe_mac_82599EB) {
2103                 vlnctrl |= IXGBE_VLNCTRL_VFE;
2104                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2105                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2106                 for (i = 0; i < adapter->num_rx_queues; i++) {
2107                         j = adapter->rx_ring[i].reg_idx;
2108                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2109                         vlnctrl |= IXGBE_RXDCTL_VME;
2110                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2111                 }
2112         }
2113         hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
2114 }
2115
2116 #endif
2117 static void ixgbe_configure(struct ixgbe_adapter *adapter)
2118 {
2119         struct net_device *netdev = adapter->netdev;
2120         int i;
2121
2122         ixgbe_set_rx_mode(netdev);
2123
2124         ixgbe_restore_vlan(adapter);
2125 #ifdef CONFIG_IXGBE_DCB
2126         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2127                 netif_set_gso_max_size(netdev, 32768);
2128                 ixgbe_configure_dcb(adapter);
2129         } else {
2130                 netif_set_gso_max_size(netdev, 65536);
2131         }
2132 #else
2133         netif_set_gso_max_size(netdev, 65536);
2134 #endif
2135
2136         ixgbe_configure_tx(adapter);
2137         ixgbe_configure_rx(adapter);
2138         for (i = 0; i < adapter->num_rx_queues; i++)
2139                 ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i],
2140                                        (adapter->rx_ring[i].count - 1));
2141 }
2142
2143 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2144 {
2145         switch (hw->phy.type) {
2146         case ixgbe_phy_sfp_avago:
2147         case ixgbe_phy_sfp_ftl:
2148         case ixgbe_phy_sfp_intel:
2149         case ixgbe_phy_sfp_unknown:
2150         case ixgbe_phy_tw_tyco:
2151         case ixgbe_phy_tw_unknown:
2152                 return true;
2153         default:
2154                 return false;
2155         }
2156 }
2157
2158 /**
2159  * ixgbe_sfp_link_config - set up SFP+ link
2160  * @adapter: pointer to private adapter struct
2161  **/
2162 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
2163 {
2164         struct ixgbe_hw *hw = &adapter->hw;
2165
2166                 if (hw->phy.multispeed_fiber) {
2167                         /*
2168                          * In multispeed fiber setups, the device may not have
2169                          * had a physical connection when the driver loaded.
2170                          * If that's the case, the initial link configuration
2171                          * couldn't get the MAC into 10G or 1G mode, so we'll
2172                          * never have a link status change interrupt fire.
2173                          * We need to try and force an autonegotiation
2174                          * session, then bring up link.
2175                          */
2176                         hw->mac.ops.setup_sfp(hw);
2177                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
2178                                 schedule_work(&adapter->multispeed_fiber_task);
2179                 } else {
2180                         /*
2181                          * Direct Attach Cu and non-multispeed fiber modules
2182                          * still need to be configured properly prior to
2183                          * attempting link.
2184                          */
2185                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
2186                                 schedule_work(&adapter->sfp_config_module_task);
2187                 }
2188 }
2189
2190 /**
2191  * ixgbe_non_sfp_link_config - set up non-SFP+ link
2192  * @hw: pointer to private hardware struct
2193  *
2194  * Returns 0 on success, negative on failure
2195  **/
2196 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
2197 {
2198         u32 autoneg;
2199         bool link_up = false;
2200         u32 ret = IXGBE_ERR_LINK_SETUP;
2201
2202         if (hw->mac.ops.check_link)
2203                 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2204
2205         if (ret)
2206                 goto link_cfg_out;
2207
2208         if (hw->mac.ops.get_link_capabilities)
2209                 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
2210                                                         &hw->mac.autoneg);
2211         if (ret)
2212                 goto link_cfg_out;
2213
2214         if (hw->mac.ops.setup_link_speed)
2215                 ret = hw->mac.ops.setup_link_speed(hw, autoneg, true, link_up);
2216 link_cfg_out:
2217         return ret;
2218 }
2219
2220 #define IXGBE_MAX_RX_DESC_POLL 10
2221 static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2222                                               int rxr)
2223 {
2224         int j = adapter->rx_ring[rxr].reg_idx;
2225         int k;
2226
2227         for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
2228                 if (IXGBE_READ_REG(&adapter->hw,
2229                                    IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
2230                         break;
2231                 else
2232                         msleep(1);
2233         }
2234         if (k >= IXGBE_MAX_RX_DESC_POLL) {
2235                 DPRINTK(DRV, ERR, "RXDCTL.ENABLE on Rx queue %d "
2236                         "not set within the polling period\n", rxr);
2237         }
2238         ixgbe_release_rx_desc(&adapter->hw, &adapter->rx_ring[rxr],
2239                               (adapter->rx_ring[rxr].count - 1));
2240 }
2241
2242 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
2243 {
2244         struct net_device *netdev = adapter->netdev;
2245         struct ixgbe_hw *hw = &adapter->hw;
2246         int i, j = 0;
2247         int num_rx_rings = adapter->num_rx_queues;
2248         int err;
2249         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2250         u32 txdctl, rxdctl, mhadd;
2251         u32 dmatxctl;
2252         u32 gpie;
2253
2254         ixgbe_get_hw_control(adapter);
2255
2256         if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
2257             (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
2258                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2259                         gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
2260                                 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
2261                 } else {
2262                         /* MSI only */
2263                         gpie = 0;
2264                 }
2265                 /* XXX: to interrupt immediately for EICS writes, enable this */
2266                 /* gpie |= IXGBE_GPIE_EIMEN; */
2267                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2268         }
2269
2270         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2271                 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
2272                  * specifically only auto mask tx and rx interrupts */
2273                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
2274         }
2275
2276         /* Enable fan failure interrupt if media type is copper */
2277         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2278                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2279                 gpie |= IXGBE_SDP1_GPIEN;
2280                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2281         }
2282
2283         if (hw->mac.type == ixgbe_mac_82599EB) {
2284                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2285                 gpie |= IXGBE_SDP1_GPIEN;
2286                 gpie |= IXGBE_SDP2_GPIEN;
2287                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2288         }
2289
2290         mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
2291         if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2292                 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2293                 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2294
2295                 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2296         }
2297
2298         for (i = 0; i < adapter->num_tx_queues; i++) {
2299                 j = adapter->tx_ring[i].reg_idx;
2300                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2301                 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2302                 txdctl |= (8 << 16);
2303                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2304         }
2305
2306         if (hw->mac.type == ixgbe_mac_82599EB) {
2307                 /* DMATXCTL.EN must be set after all Tx queue config is done */
2308                 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2309                 dmatxctl |= IXGBE_DMATXCTL_TE;
2310                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2311         }
2312         for (i = 0; i < adapter->num_tx_queues; i++) {
2313                 j = adapter->tx_ring[i].reg_idx;
2314                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2315                 txdctl |= IXGBE_TXDCTL_ENABLE;
2316                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2317         }
2318
2319         for (i = 0; i < num_rx_rings; i++) {
2320                 j = adapter->rx_ring[i].reg_idx;
2321                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2322                 /* enable PTHRESH=32 descriptors (half the internal cache)
2323                  * and HTHRESH=0 descriptors (to minimize latency on fetch),
2324                  * this also removes a pesky rx_no_buffer_count increment */
2325                 rxdctl |= 0x0020;
2326                 rxdctl |= IXGBE_RXDCTL_ENABLE;
2327                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
2328                 if (hw->mac.type == ixgbe_mac_82599EB)
2329                         ixgbe_rx_desc_queue_enable(adapter, i);
2330         }
2331         /* enable all receives */
2332         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2333         if (hw->mac.type == ixgbe_mac_82598EB)
2334                 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
2335         else
2336                 rxdctl |= IXGBE_RXCTRL_RXEN;
2337         hw->mac.ops.enable_rx_dma(hw, rxdctl);
2338
2339         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2340                 ixgbe_configure_msix(adapter);
2341         else
2342                 ixgbe_configure_msi_and_legacy(adapter);
2343
2344         clear_bit(__IXGBE_DOWN, &adapter->state);
2345         ixgbe_napi_enable_all(adapter);
2346
2347         /* clear any pending interrupts, may auto mask */
2348         IXGBE_READ_REG(hw, IXGBE_EICR);
2349
2350         ixgbe_irq_enable(adapter);
2351
2352         /*
2353          * For hot-pluggable SFP+ devices, a new SFP+ module may have
2354          * arrived before interrupts were enabled.  We need to kick off
2355          * the SFP+ module setup first, then try to bring up link.
2356          * If we're not hot-pluggable SFP+, we just need to configure link
2357          * and bring it up.
2358          */
2359         err = hw->phy.ops.identify(hw);
2360         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
2361                 DPRINTK(PROBE, ERR, "PHY not supported on this NIC %d\n", err);
2362                 ixgbe_down(adapter);
2363                 return err;
2364         }
2365
2366         if (ixgbe_is_sfp(hw)) {
2367                 ixgbe_sfp_link_config(adapter);
2368         } else {
2369                 err = ixgbe_non_sfp_link_config(hw);
2370                 if (err)
2371                         DPRINTK(PROBE, ERR, "link_config FAILED %d\n", err);
2372         }
2373
2374         /* enable transmits */
2375         netif_tx_start_all_queues(netdev);
2376
2377         /* bring the link up in the watchdog, this could race with our first
2378          * link up interrupt but shouldn't be a problem */
2379         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2380         adapter->link_check_timeout = jiffies;
2381         mod_timer(&adapter->watchdog_timer, jiffies);
2382         return 0;
2383 }
2384
2385 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
2386 {
2387         WARN_ON(in_interrupt());
2388         while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
2389                 msleep(1);
2390         ixgbe_down(adapter);
2391         ixgbe_up(adapter);
2392         clear_bit(__IXGBE_RESETTING, &adapter->state);
2393 }
2394
2395 int ixgbe_up(struct ixgbe_adapter *adapter)
2396 {
2397         /* hardware has been reset, we need to reload some things */
2398         ixgbe_configure(adapter);
2399
2400         ixgbe_napi_add_all(adapter);
2401
2402         return ixgbe_up_complete(adapter);
2403 }
2404
2405 void ixgbe_reset(struct ixgbe_adapter *adapter)
2406 {
2407         struct ixgbe_hw *hw = &adapter->hw;
2408         if (hw->mac.ops.init_hw(hw))
2409                 dev_err(&adapter->pdev->dev, "Hardware Error\n");
2410
2411         /* reprogram the RAR[0] in case user changed it. */
2412         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2413
2414 }
2415
2416 /**
2417  * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
2418  * @adapter: board private structure
2419  * @rx_ring: ring to free buffers from
2420  **/
2421 static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
2422                                 struct ixgbe_ring *rx_ring)
2423 {
2424         struct pci_dev *pdev = adapter->pdev;
2425         unsigned long size;
2426         unsigned int i;
2427
2428         /* Free all the Rx ring sk_buffs */
2429
2430         for (i = 0; i < rx_ring->count; i++) {
2431                 struct ixgbe_rx_buffer *rx_buffer_info;
2432
2433                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
2434                 if (rx_buffer_info->dma) {
2435                         pci_unmap_single(pdev, rx_buffer_info->dma,
2436                                          rx_ring->rx_buf_len,
2437                                          PCI_DMA_FROMDEVICE);
2438                         rx_buffer_info->dma = 0;
2439                 }
2440                 if (rx_buffer_info->skb) {
2441                         dev_kfree_skb(rx_buffer_info->skb);
2442                         rx_buffer_info->skb = NULL;
2443                 }
2444                 if (!rx_buffer_info->page)
2445                         continue;
2446                 pci_unmap_page(pdev, rx_buffer_info->page_dma, PAGE_SIZE / 2,
2447                                PCI_DMA_FROMDEVICE);
2448                 rx_buffer_info->page_dma = 0;
2449                 put_page(rx_buffer_info->page);
2450                 rx_buffer_info->page = NULL;
2451                 rx_buffer_info->page_offset = 0;
2452         }
2453
2454         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
2455         memset(rx_ring->rx_buffer_info, 0, size);
2456
2457         /* Zero out the descriptor ring */
2458         memset(rx_ring->desc, 0, rx_ring->size);
2459
2460         rx_ring->next_to_clean = 0;
2461         rx_ring->next_to_use = 0;
2462
2463         if (rx_ring->head)
2464                 writel(0, adapter->hw.hw_addr + rx_ring->head);
2465         if (rx_ring->tail)
2466                 writel(0, adapter->hw.hw_addr + rx_ring->tail);
2467 }
2468
2469 /**
2470  * ixgbe_clean_tx_ring - Free Tx Buffers
2471  * @adapter: board private structure
2472  * @tx_ring: ring to be cleaned
2473  **/
2474 static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
2475                                 struct ixgbe_ring *tx_ring)
2476 {
2477         struct ixgbe_tx_buffer *tx_buffer_info;
2478         unsigned long size;
2479         unsigned int i;
2480
2481         /* Free all the Tx ring sk_buffs */
2482
2483         for (i = 0; i < tx_ring->count; i++) {
2484                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2485                 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
2486         }
2487
2488         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
2489         memset(tx_ring->tx_buffer_info, 0, size);
2490
2491         /* Zero out the descriptor ring */
2492         memset(tx_ring->desc, 0, tx_ring->size);
2493
2494         tx_ring->next_to_use = 0;
2495         tx_ring->next_to_clean = 0;
2496
2497         if (tx_ring->head)
2498                 writel(0, adapter->hw.hw_addr + tx_ring->head);
2499         if (tx_ring->tail)
2500                 writel(0, adapter->hw.hw_addr + tx_ring->tail);
2501 }
2502
2503 /**
2504  * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
2505  * @adapter: board private structure
2506  **/
2507 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
2508 {
2509         int i;
2510
2511         for (i = 0; i < adapter->num_rx_queues; i++)
2512                 ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]);
2513 }
2514
2515 /**
2516  * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
2517  * @adapter: board private structure
2518  **/
2519 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
2520 {
2521         int i;
2522
2523         for (i = 0; i < adapter->num_tx_queues; i++)
2524                 ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]);
2525 }
2526
2527 void ixgbe_down(struct ixgbe_adapter *adapter)
2528 {
2529         struct net_device *netdev = adapter->netdev;
2530         struct ixgbe_hw *hw = &adapter->hw;
2531         u32 rxctrl;
2532         u32 txdctl;
2533         int i, j;
2534
2535         /* signal that we are down to the interrupt handler */
2536         set_bit(__IXGBE_DOWN, &adapter->state);
2537
2538         /* disable receives */
2539         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2540         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2541
2542         netif_tx_disable(netdev);
2543
2544         IXGBE_WRITE_FLUSH(hw);
2545         msleep(10);
2546
2547         netif_tx_stop_all_queues(netdev);
2548
2549         ixgbe_irq_disable(adapter);
2550
2551         ixgbe_napi_disable_all(adapter);
2552
2553         del_timer_sync(&adapter->watchdog_timer);
2554         cancel_work_sync(&adapter->watchdog_task);
2555
2556         /* disable transmits in the hardware now that interrupts are off */
2557         for (i = 0; i < adapter->num_tx_queues; i++) {
2558                 j = adapter->tx_ring[i].reg_idx;
2559                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2560                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
2561                                 (txdctl & ~IXGBE_TXDCTL_ENABLE));
2562         }
2563         /* Disable the Tx DMA engine on 82599 */
2564         if (hw->mac.type == ixgbe_mac_82599EB)
2565                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
2566                                 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
2567                                  ~IXGBE_DMATXCTL_TE));
2568
2569         netif_carrier_off(netdev);
2570
2571 #ifdef CONFIG_IXGBE_DCA
2572         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
2573                 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
2574                 dca_remove_requester(&adapter->pdev->dev);
2575         }
2576
2577 #endif
2578         if (!pci_channel_offline(adapter->pdev))
2579                 ixgbe_reset(adapter);
2580         ixgbe_clean_all_tx_rings(adapter);
2581         ixgbe_clean_all_rx_rings(adapter);
2582
2583 #ifdef CONFIG_IXGBE_DCA
2584         /* since we reset the hardware DCA settings were cleared */
2585         if (dca_add_requester(&adapter->pdev->dev) == 0) {
2586                 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
2587                 /* always use CB2 mode, difference is masked
2588                  * in the CB driver */
2589                 IXGBE_WRITE_REG(hw, IXGBE_DCA_CTRL, 2);
2590                 ixgbe_setup_dca(adapter);
2591         }
2592 #endif
2593 }
2594
2595 /**
2596  * ixgbe_poll - NAPI Rx polling callback
2597  * @napi: structure for representing this polling device
2598  * @budget: how many packets driver is allowed to clean
2599  *
2600  * This function is used for legacy and MSI, NAPI mode
2601  **/
2602 static int ixgbe_poll(struct napi_struct *napi, int budget)
2603 {
2604         struct ixgbe_q_vector *q_vector =
2605                                 container_of(napi, struct ixgbe_q_vector, napi);
2606         struct ixgbe_adapter *adapter = q_vector->adapter;
2607         int tx_clean_complete, work_done = 0;
2608
2609 #ifdef CONFIG_IXGBE_DCA
2610         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
2611                 ixgbe_update_tx_dca(adapter, adapter->tx_ring);
2612                 ixgbe_update_rx_dca(adapter, adapter->rx_ring);
2613         }
2614 #endif
2615
2616         tx_clean_complete = ixgbe_clean_tx_irq(adapter, adapter->tx_ring);
2617         ixgbe_clean_rx_irq(q_vector, adapter->rx_ring, &work_done, budget);
2618
2619         if (!tx_clean_complete)
2620                 work_done = budget;
2621
2622         /* If budget not fully consumed, exit the polling mode */
2623         if (work_done < budget) {
2624                 napi_complete(napi);
2625                 if (adapter->itr_setting & 1)
2626                         ixgbe_set_itr(adapter);
2627                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2628                         ixgbe_irq_enable_queues(adapter);
2629         }
2630         return work_done;
2631 }
2632
2633 /**
2634  * ixgbe_tx_timeout - Respond to a Tx Hang
2635  * @netdev: network interface device structure
2636  **/
2637 static void ixgbe_tx_timeout(struct net_device *netdev)
2638 {
2639         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2640
2641         /* Do the reset outside of interrupt context */
2642         schedule_work(&adapter->reset_task);
2643 }
2644
2645 static void ixgbe_reset_task(struct work_struct *work)
2646 {
2647         struct ixgbe_adapter *adapter;
2648         adapter = container_of(work, struct ixgbe_adapter, reset_task);
2649
2650         /* If we're already down or resetting, just bail */
2651         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
2652             test_bit(__IXGBE_RESETTING, &adapter->state))
2653                 return;
2654
2655         adapter->tx_timeout_count++;
2656
2657         ixgbe_reinit_locked(adapter);
2658 }
2659
2660 #ifdef CONFIG_IXGBE_DCB
2661 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
2662 {
2663         bool ret = false;
2664
2665         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2666                 adapter->ring_feature[RING_F_DCB].mask = 0x7 << 3;
2667                 adapter->num_rx_queues =
2668                                       adapter->ring_feature[RING_F_DCB].indices;
2669                 adapter->num_tx_queues =
2670                                       adapter->ring_feature[RING_F_DCB].indices;
2671                 ret = true;
2672         } else {
2673                 ret = false;
2674         }
2675
2676         return ret;
2677 }
2678 #endif
2679
2680 /**
2681  * ixgbe_set_rss_queues: Allocate queues for RSS
2682  * @adapter: board private structure to initialize
2683  *
2684  * This is our "base" multiqueue mode.  RSS (Receive Side Scaling) will try
2685  * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
2686  *
2687  **/
2688 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
2689 {
2690         bool ret = false;
2691
2692         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
2693                 adapter->ring_feature[RING_F_RSS].mask = 0xF;
2694                 adapter->num_rx_queues =
2695                                       adapter->ring_feature[RING_F_RSS].indices;
2696                 adapter->num_tx_queues =
2697                                       adapter->ring_feature[RING_F_RSS].indices;
2698                 ret = true;
2699         } else {
2700                 ret = false;
2701         }
2702
2703         return ret;
2704 }
2705
2706 /*
2707  * ixgbe_set_num_queues: Allocate queues for device, feature dependant
2708  * @adapter: board private structure to initialize
2709  *
2710  * This is the top level queue allocation routine.  The order here is very
2711  * important, starting with the "most" number of features turned on at once,
2712  * and ending with the smallest set of features.  This way large combinations
2713  * can be allocated if they're turned on, and smaller combinations are the
2714  * fallthrough conditions.
2715  *
2716  **/
2717 static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
2718 {
2719 #ifdef CONFIG_IXGBE_DCB
2720         if (ixgbe_set_dcb_queues(adapter))
2721                 goto done;
2722
2723 #endif
2724         if (ixgbe_set_rss_queues(adapter))
2725                 goto done;
2726
2727         /* fallback to base case */
2728         adapter->num_rx_queues = 1;
2729         adapter->num_tx_queues = 1;
2730
2731 done:
2732         /* Notify the stack of the (possibly) reduced Tx Queue count. */
2733         adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
2734 }
2735
2736 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
2737                                        int vectors)
2738 {
2739         int err, vector_threshold;
2740
2741         /* We'll want at least 3 (vector_threshold):
2742          * 1) TxQ[0] Cleanup
2743          * 2) RxQ[0] Cleanup
2744          * 3) Other (Link Status Change, etc.)
2745          * 4) TCP Timer (optional)
2746          */
2747         vector_threshold = MIN_MSIX_COUNT;
2748
2749         /* The more we get, the more we will assign to Tx/Rx Cleanup
2750          * for the separate queues...where Rx Cleanup >= Tx Cleanup.
2751          * Right now, we simply care about how many we'll get; we'll
2752          * set them up later while requesting irq's.
2753          */
2754         while (vectors >= vector_threshold) {
2755                 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
2756                                       vectors);
2757                 if (!err) /* Success in acquiring all requested vectors. */
2758                         break;
2759                 else if (err < 0)
2760                         vectors = 0; /* Nasty failure, quit now */
2761                 else /* err == number of vectors we should try again with */
2762                         vectors = err;
2763         }
2764
2765         if (vectors < vector_threshold) {
2766                 /* Can't allocate enough MSI-X interrupts?  Oh well.
2767                  * This just means we'll go with either a single MSI
2768                  * vector or fall back to legacy interrupts.
2769                  */
2770                 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
2771                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2772                 kfree(adapter->msix_entries);
2773                 adapter->msix_entries = NULL;
2774                 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
2775                 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
2776                 ixgbe_set_num_queues(adapter);
2777         } else {
2778                 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
2779                 /*
2780                  * Adjust for only the vectors we'll use, which is minimum
2781                  * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
2782                  * vectors we were allocated.
2783                  */
2784                 adapter->num_msix_vectors = min(vectors,
2785                                    adapter->max_msix_q_vectors + NON_Q_VECTORS);
2786         }
2787 }
2788
2789 /**
2790  * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
2791  * @adapter: board private structure to initialize
2792  *
2793  * Cache the descriptor ring offsets for RSS to the assigned rings.
2794  *
2795  **/
2796 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
2797 {
2798         int i;
2799         bool ret = false;
2800
2801         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
2802                 for (i = 0; i < adapter->num_rx_queues; i++)
2803                         adapter->rx_ring[i].reg_idx = i;
2804                 for (i = 0; i < adapter->num_tx_queues; i++)
2805                         adapter->tx_ring[i].reg_idx = i;
2806                 ret = true;
2807         } else {
2808                 ret = false;
2809         }
2810
2811         return ret;
2812 }
2813
2814 #ifdef CONFIG_IXGBE_DCB
2815 /**
2816  * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
2817  * @adapter: board private structure to initialize
2818  *
2819  * Cache the descriptor ring offsets for DCB to the assigned rings.
2820  *
2821  **/
2822 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
2823 {
2824         int i;
2825         bool ret = false;
2826         int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
2827
2828         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2829                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2830                         /* the number of queues is assumed to be symmetric */
2831                         for (i = 0; i < dcb_i; i++) {
2832                                 adapter->rx_ring[i].reg_idx = i << 3;
2833                                 adapter->tx_ring[i].reg_idx = i << 2;
2834                         }
2835                         ret = true;
2836                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2837                         if (dcb_i == 8) {
2838                                 /*
2839                                  * Tx TC0 starts at: descriptor queue 0
2840                                  * Tx TC1 starts at: descriptor queue 32
2841                                  * Tx TC2 starts at: descriptor queue 64
2842                                  * Tx TC3 starts at: descriptor queue 80
2843                                  * Tx TC4 starts at: descriptor queue 96
2844                                  * Tx TC5 starts at: descriptor queue 104
2845                                  * Tx TC6 starts at: descriptor queue 112
2846                                  * Tx TC7 starts at: descriptor queue 120
2847                                  *
2848                                  * Rx TC0-TC7 are offset by 16 queues each
2849                                  */
2850                                 for (i = 0; i < 3; i++) {
2851                                         adapter->tx_ring[i].reg_idx = i << 5;
2852                                         adapter->rx_ring[i].reg_idx = i << 4;
2853                                 }
2854                                 for ( ; i < 5; i++) {
2855                                         adapter->tx_ring[i].reg_idx =
2856                                                                  ((i + 2) << 4);
2857                                         adapter->rx_ring[i].reg_idx = i << 4;
2858                                 }
2859                                 for ( ; i < dcb_i; i++) {
2860                                         adapter->tx_ring[i].reg_idx =
2861                                                                  ((i + 8) << 3);
2862                                         adapter->rx_ring[i].reg_idx = i << 4;
2863                                 }
2864
2865                                 ret = true;
2866                         } else if (dcb_i == 4) {
2867                                 /*
2868                                  * Tx TC0 starts at: descriptor queue 0
2869                                  * Tx TC1 starts at: descriptor queue 64
2870                                  * Tx TC2 starts at: descriptor queue 96
2871                                  * Tx TC3 starts at: descriptor queue 112
2872                                  *
2873                                  * Rx TC0-TC3 are offset by 32 queues each
2874                                  */
2875                                 adapter->tx_ring[0].reg_idx = 0;
2876                                 adapter->tx_ring[1].reg_idx = 64;
2877                                 adapter->tx_ring[2].reg_idx = 96;
2878                                 adapter->tx_ring[3].reg_idx = 112;
2879                                 for (i = 0 ; i < dcb_i; i++)
2880                                         adapter->rx_ring[i].reg_idx = i << 5;
2881
2882                                 ret = true;
2883                         } else {
2884                                 ret = false;
2885                         }
2886                 } else {
2887                         ret = false;
2888                 }
2889         } else {
2890                 ret = false;
2891         }
2892
2893         return ret;
2894 }
2895 #endif
2896
2897 /**
2898  * ixgbe_cache_ring_register - Descriptor ring to register mapping
2899  * @adapter: board private structure to initialize
2900  *
2901  * Once we know the feature-set enabled for the device, we'll cache
2902  * the register offset the descriptor ring is assigned to.
2903  *
2904  * Note, the order the various feature calls is important.  It must start with
2905  * the "most" features enabled at the same time, then trickle down to the
2906  * least amount of features turned on at once.
2907  **/
2908 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
2909 {
2910         /* start with default case */
2911         adapter->rx_ring[0].reg_idx = 0;
2912         adapter->tx_ring[0].reg_idx = 0;
2913
2914 #ifdef CONFIG_IXGBE_DCB
2915         if (ixgbe_cache_ring_dcb(adapter))
2916                 return;
2917
2918 #endif
2919         if (ixgbe_cache_ring_rss(adapter))
2920                 return;
2921 }
2922
2923 /**
2924  * ixgbe_alloc_queues - Allocate memory for all rings
2925  * @adapter: board private structure to initialize
2926  *
2927  * We allocate one ring per queue at run-time since we don't know the
2928  * number of queues at compile-time.  The polling_netdev array is
2929  * intended for Multiqueue, but should work fine with a single queue.
2930  **/
2931 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
2932 {
2933         int i;
2934
2935         adapter->tx_ring = kcalloc(adapter->num_tx_queues,
2936                                    sizeof(struct ixgbe_ring), GFP_KERNEL);
2937         if (!adapter->tx_ring)
2938                 goto err_tx_ring_allocation;
2939
2940         adapter->rx_ring = kcalloc(adapter->num_rx_queues,
2941                                    sizeof(struct ixgbe_ring), GFP_KERNEL);
2942         if (!adapter->rx_ring)
2943                 goto err_rx_ring_allocation;
2944
2945         for (i = 0; i < adapter->num_tx_queues; i++) {
2946                 adapter->tx_ring[i].count = adapter->tx_ring_count;
2947                 adapter->tx_ring[i].queue_index = i;
2948         }
2949
2950         for (i = 0; i < adapter->num_rx_queues; i++) {
2951                 adapter->rx_ring[i].count = adapter->rx_ring_count;
2952                 adapter->rx_ring[i].queue_index = i;
2953         }
2954
2955         ixgbe_cache_ring_register(adapter);
2956
2957         return 0;
2958
2959 err_rx_ring_allocation:
2960         kfree(adapter->tx_ring);
2961 err_tx_ring_allocation:
2962         return -ENOMEM;
2963 }
2964
2965 /**
2966  * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
2967  * @adapter: board private structure to initialize
2968  *
2969  * Attempt to configure the interrupts using the best available
2970  * capabilities of the hardware and the kernel.
2971  **/
2972 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
2973 {
2974         struct ixgbe_hw *hw = &adapter->hw;
2975         int err = 0;
2976         int vector, v_budget;
2977
2978         /*
2979          * It's easy to be greedy for MSI-X vectors, but it really
2980          * doesn't do us much good if we have a lot more vectors
2981          * than CPU's.  So let's be conservative and only ask for
2982          * (roughly) twice the number of vectors as there are CPU's.
2983          */
2984         v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
2985                        (int)(num_online_cpus() * 2)) + NON_Q_VECTORS;
2986
2987         /*
2988          * At the same time, hardware can only support a maximum of
2989          * hw.mac->max_msix_vectors vectors.  With features
2990          * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
2991          * descriptor queues supported by our device.  Thus, we cap it off in
2992          * those rare cases where the cpu count also exceeds our vector limit.
2993          */
2994         v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
2995
2996         /* A failure in MSI-X entry allocation isn't fatal, but it does
2997          * mean we disable MSI-X capabilities of the adapter. */
2998         adapter->msix_entries = kcalloc(v_budget,
2999                                         sizeof(struct msix_entry), GFP_KERNEL);
3000         if (!adapter->msix_entries) {
3001                 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
3002                 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
3003                 ixgbe_set_num_queues(adapter);
3004                 kfree(adapter->tx_ring);
3005                 kfree(adapter->rx_ring);
3006                 err = ixgbe_alloc_queues(adapter);
3007                 if (err) {
3008                         DPRINTK(PROBE, ERR, "Unable to allocate memory "
3009                                 "for queues\n");
3010                         goto out;
3011                 }
3012
3013                 goto try_msi;
3014         }
3015
3016         for (vector = 0; vector < v_budget; vector++)
3017                 adapter->msix_entries[vector].entry = vector;
3018
3019         ixgbe_acquire_msix_vectors(adapter, v_budget);
3020
3021         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3022                 goto out;
3023
3024 try_msi:
3025         err = pci_enable_msi(adapter->pdev);
3026         if (!err) {
3027                 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
3028         } else {
3029                 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
3030                         "falling back to legacy.  Error: %d\n", err);
3031                 /* reset err */
3032                 err = 0;
3033         }
3034
3035 out:
3036         return err;
3037 }
3038
3039 void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
3040 {
3041         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3042                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3043                 pci_disable_msix(adapter->pdev);
3044                 kfree(adapter->msix_entries);
3045                 adapter->msix_entries = NULL;
3046         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
3047                 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
3048                 pci_disable_msi(adapter->pdev);
3049         }
3050         return;
3051 }
3052
3053 /**
3054  * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
3055  * @adapter: board private structure to initialize
3056  *
3057  * We determine which interrupt scheme to use based on...
3058  * - Kernel support (MSI, MSI-X)
3059  *   - which can be user-defined (via MODULE_PARAM)
3060  * - Hardware queue count (num_*_queues)
3061  *   - defined by miscellaneous hardware support/features (RSS, etc.)
3062  **/
3063 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
3064 {
3065         int err;
3066
3067         /* Number of supported queues */
3068         ixgbe_set_num_queues(adapter);
3069
3070         err = ixgbe_alloc_queues(adapter);
3071         if (err) {
3072                 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
3073                 goto err_alloc_queues;
3074         }
3075
3076         err = ixgbe_set_interrupt_capability(adapter);
3077         if (err) {
3078                 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
3079                 goto err_set_interrupt;
3080         }
3081
3082         DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
3083                 "Tx Queue count = %u\n",
3084                 (adapter->num_rx_queues > 1) ? "Enabled" :
3085                 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
3086
3087         set_bit(__IXGBE_DOWN, &adapter->state);
3088
3089         return 0;
3090
3091 err_set_interrupt:
3092         kfree(adapter->tx_ring);
3093         kfree(adapter->rx_ring);
3094 err_alloc_queues:
3095         return err;
3096 }
3097
3098 /**
3099  * ixgbe_sfp_timer - worker thread to find a missing module
3100  * @data: pointer to our adapter struct
3101  **/
3102 static void ixgbe_sfp_timer(unsigned long data)
3103 {
3104         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
3105
3106         /*
3107          * Do the sfp_timer outside of interrupt context due to the
3108          * delays that sfp+ detection requires
3109          */
3110         schedule_work(&adapter->sfp_task);
3111 }
3112
3113 /**
3114  * ixgbe_sfp_task - worker thread to find a missing module
3115  * @work: pointer to work_struct containing our data
3116  **/
3117 static void ixgbe_sfp_task(struct work_struct *work)
3118 {
3119         struct ixgbe_adapter *adapter = container_of(work,
3120                                                      struct ixgbe_adapter,
3121                                                      sfp_task);
3122         struct ixgbe_hw *hw = &adapter->hw;
3123
3124         if ((hw->phy.type == ixgbe_phy_nl) &&
3125             (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
3126                 s32 ret = hw->phy.ops.identify_sfp(hw);
3127                 if (ret)
3128                         goto reschedule;
3129                 ret = hw->phy.ops.reset(hw);
3130                 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
3131                         DPRINTK(PROBE, ERR, "failed to initialize because an "
3132                                 "unsupported SFP+ module type was detected.\n"
3133                                 "Reload the driver after installing a "
3134                                 "supported module.\n");
3135                         unregister_netdev(adapter->netdev);
3136                 } else {
3137                         DPRINTK(PROBE, INFO, "detected SFP+: %d\n",
3138                                 hw->phy.sfp_type);
3139                 }
3140                 /* don't need this routine any more */
3141                 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3142         }
3143         return;
3144 reschedule:
3145         if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
3146                 mod_timer(&adapter->sfp_timer,
3147                           round_jiffies(jiffies + (2 * HZ)));
3148 }
3149
3150 /**
3151  * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
3152  * @adapter: board private structure to initialize
3153  *
3154  * ixgbe_sw_init initializes the Adapter private data structure.
3155  * Fields are initialized based on PCI device information and
3156  * OS network device settings (MTU size).
3157  **/
3158 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
3159 {
3160         struct ixgbe_hw *hw = &adapter->hw;
3161         struct pci_dev *pdev = adapter->pdev;
3162         unsigned int rss;
3163 #ifdef CONFIG_IXGBE_DCB
3164         int j;
3165         struct tc_configuration *tc;
3166 #endif
3167
3168         /* PCI config space info */
3169
3170         hw->vendor_id = pdev->vendor;
3171         hw->device_id = pdev->device;
3172         hw->revision_id = pdev->revision;
3173         hw->subsystem_vendor_id = pdev->subsystem_vendor;
3174         hw->subsystem_device_id = pdev->subsystem_device;
3175
3176         /* Set capability flags */
3177         rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
3178         adapter->ring_feature[RING_F_RSS].indices = rss;
3179         adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
3180         adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
3181         if (hw->mac.type == ixgbe_mac_82598EB)
3182                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
3183         else if (hw->mac.type == ixgbe_mac_82599EB)
3184                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
3185
3186 #ifdef CONFIG_IXGBE_DCB
3187         /* Configure DCB traffic classes */
3188         for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
3189                 tc = &adapter->dcb_cfg.tc_config[j];
3190                 tc->path[DCB_TX_CONFIG].bwg_id = 0;
3191                 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
3192                 tc->path[DCB_RX_CONFIG].bwg_id = 0;
3193                 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
3194                 tc->dcb_pfc = pfc_disabled;
3195         }
3196         adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
3197         adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
3198         adapter->dcb_cfg.rx_pba_cfg = pba_equal;
3199         adapter->dcb_cfg.round_robin_enable = false;
3200         adapter->dcb_set_bitmap = 0x00;
3201         ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
3202                            adapter->ring_feature[RING_F_DCB].indices);
3203
3204 #endif
3205
3206         /* default flow control settings */
3207         hw->fc.requested_mode = ixgbe_fc_full;
3208         hw->fc.current_mode = ixgbe_fc_full;    /* init for ethtool output */
3209         hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
3210         hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
3211         hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
3212         hw->fc.send_xon = true;
3213         hw->fc.disable_fc_autoneg = false;
3214
3215         /* enable itr by default in dynamic mode */
3216         adapter->itr_setting = 1;
3217         adapter->eitr_param = 20000;
3218
3219         /* set defaults for eitr in MegaBytes */
3220         adapter->eitr_low = 10;
3221         adapter->eitr_high = 20;
3222
3223         /* set default ring sizes */
3224         adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
3225         adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
3226
3227         /* initialize eeprom parameters */
3228         if (ixgbe_init_eeprom_params_generic(hw)) {
3229                 dev_err(&pdev->dev, "EEPROM initialization failed\n");
3230                 return -EIO;
3231         }
3232
3233         /* enable rx csum by default */
3234         adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
3235
3236         set_bit(__IXGBE_DOWN, &adapter->state);
3237
3238         return 0;
3239 }
3240
3241 /**
3242  * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3243  * @adapter: board private structure
3244  * @tx_ring:    tx descriptor ring (for a specific queue) to setup
3245  *
3246  * Return 0 on success, negative on failure
3247  **/
3248 int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
3249                              struct ixgbe_ring *tx_ring)
3250 {
3251         struct pci_dev *pdev = adapter->pdev;
3252         int size;
3253
3254         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3255         tx_ring->tx_buffer_info = vmalloc(size);
3256         if (!tx_ring->tx_buffer_info)
3257                 goto err;
3258         memset(tx_ring->tx_buffer_info, 0, size);
3259
3260         /* round up to nearest 4K */
3261         tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3262         tx_ring->size = ALIGN(tx_ring->size, 4096);
3263
3264         tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
3265                                              &tx_ring->dma);
3266         if (!tx_ring->desc)
3267                 goto err;
3268
3269         tx_ring->next_to_use = 0;
3270         tx_ring->next_to_clean = 0;
3271         tx_ring->work_limit = tx_ring->count;
3272         return 0;
3273
3274 err:
3275         vfree(tx_ring->tx_buffer_info);
3276         tx_ring->tx_buffer_info = NULL;
3277         DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit "
3278                             "descriptor ring\n");
3279         return -ENOMEM;
3280 }
3281
3282 /**
3283  * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
3284  * @adapter: board private structure
3285  *
3286  * If this function returns with an error, then it's possible one or
3287  * more of the rings is populated (while the rest are not).  It is the
3288  * callers duty to clean those orphaned rings.
3289  *
3290  * Return 0 on success, negative on failure
3291  **/
3292 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
3293 {
3294         int i, err = 0;
3295
3296         for (i = 0; i < adapter->num_tx_queues; i++) {
3297                 err = ixgbe_setup_tx_resources(adapter, &adapter->tx_ring[i]);
3298                 if (!err)
3299                         continue;
3300                 DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i);
3301                 break;
3302         }
3303
3304         return err;
3305 }
3306
3307 /**
3308  * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3309  * @adapter: board private structure
3310  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
3311  *
3312  * Returns 0 on success, negative on failure
3313  **/
3314 int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
3315                              struct ixgbe_ring *rx_ring)
3316 {
3317         struct pci_dev *pdev = adapter->pdev;
3318         int size;
3319
3320         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3321         rx_ring->rx_buffer_info = vmalloc(size);
3322         if (!rx_ring->rx_buffer_info) {
3323                 DPRINTK(PROBE, ERR,
3324                         "vmalloc allocation failed for the rx desc ring\n");
3325                 goto alloc_failed;
3326         }
3327         memset(rx_ring->rx_buffer_info, 0, size);
3328
3329         /* Round up to nearest 4K */
3330         rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
3331         rx_ring->size = ALIGN(rx_ring->size, 4096);
3332
3333         rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma);
3334
3335         if (!rx_ring->desc) {
3336                 DPRINTK(PROBE, ERR,
3337                         "Memory allocation failed for the rx desc ring\n");
3338                 vfree(rx_ring->rx_buffer_info);
3339                 goto alloc_failed;
3340         }
3341
3342         rx_ring->next_to_clean = 0;
3343         rx_ring->next_to_use = 0;
3344
3345         return 0;
3346
3347 alloc_failed:
3348         return -ENOMEM;
3349 }
3350
3351 /**
3352  * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
3353  * @adapter: board private structure
3354  *
3355  * If this function returns with an error, then it's possible one or
3356  * more of the rings is populated (while the rest are not).  It is the
3357  * callers duty to clean those orphaned rings.
3358  *
3359  * Return 0 on success, negative on failure
3360  **/
3361
3362 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
3363 {
3364         int i, err = 0;
3365
3366         for (i = 0; i < adapter->num_rx_queues; i++) {
3367                 err = ixgbe_setup_rx_resources(adapter, &adapter->rx_ring[i]);
3368                 if (!err)
3369                         continue;
3370                 DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i);
3371                 break;
3372         }
3373
3374         return err;
3375 }
3376
3377 /**
3378  * ixgbe_free_tx_resources - Free Tx Resources per Queue
3379  * @adapter: board private structure
3380  * @tx_ring: Tx descriptor ring for a specific queue
3381  *
3382  * Free all transmit software resources
3383  **/
3384 void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
3385                              struct ixgbe_ring *tx_ring)
3386 {
3387         struct pci_dev *pdev = adapter->pdev;
3388
3389         ixgbe_clean_tx_ring(adapter, tx_ring);
3390
3391         vfree(tx_ring->tx_buffer_info);
3392         tx_ring->tx_buffer_info = NULL;
3393
3394         pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
3395
3396         tx_ring->desc = NULL;
3397 }
3398
3399 /**
3400  * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
3401  * @adapter: board private structure
3402  *
3403  * Free all transmit software resources
3404  **/
3405 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
3406 {
3407         int i;
3408
3409         for (i = 0; i < adapter->num_tx_queues; i++)
3410                 if (adapter->tx_ring[i].desc)
3411                         ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]);
3412 }
3413
3414 /**
3415  * ixgbe_free_rx_resources - Free Rx Resources
3416  * @adapter: board private structure
3417  * @rx_ring: ring to clean the resources from
3418  *
3419  * Free all receive software resources
3420  **/
3421 void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
3422                              struct ixgbe_ring *rx_ring)
3423 {
3424         struct pci_dev *pdev = adapter->pdev;
3425
3426         ixgbe_clean_rx_ring(adapter, rx_ring);
3427
3428         vfree(rx_ring->rx_buffer_info);
3429         rx_ring->rx_buffer_info = NULL;
3430
3431         pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
3432
3433         rx_ring->desc = NULL;
3434 }
3435
3436 /**
3437  * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
3438  * @adapter: board private structure
3439  *
3440  * Free all receive software resources
3441  **/
3442 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
3443 {
3444         int i;
3445
3446         for (i = 0; i < adapter->num_rx_queues; i++)
3447                 if (adapter->rx_ring[i].desc)
3448                         ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]);
3449 }
3450
3451 /**
3452  * ixgbe_change_mtu - Change the Maximum Transfer Unit
3453  * @netdev: network interface device structure
3454  * @new_mtu: new value for maximum frame size
3455  *
3456  * Returns 0 on success, negative on failure
3457  **/
3458 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
3459 {
3460         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3461         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
3462
3463         /* MTU < 68 is an error and causes problems on some kernels */
3464         if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
3465                 return -EINVAL;
3466
3467         DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
3468                 netdev->mtu, new_mtu);
3469         /* must set new MTU before calling down or up */
3470         netdev->mtu = new_mtu;
3471
3472         if (netif_running(netdev))
3473                 ixgbe_reinit_locked(adapter);
3474
3475         return 0;
3476 }
3477
3478 /**
3479  * ixgbe_open - Called when a network interface is made active
3480  * @netdev: network interface device structure
3481  *
3482  * Returns 0 on success, negative value on failure
3483  *
3484  * The open entry point is called when a network interface is made
3485  * active by the system (IFF_UP).  At this point all resources needed
3486  * for transmit and receive operations are allocated, the interrupt
3487  * handler is registered with the OS, the watchdog timer is started,
3488  * and the stack is notified that the interface is ready.
3489  **/
3490 static int ixgbe_open(struct net_device *netdev)
3491 {
3492         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3493         int err;
3494
3495         /* disallow open during test */
3496         if (test_bit(__IXGBE_TESTING, &adapter->state))
3497                 return -EBUSY;
3498
3499         netif_carrier_off(netdev);
3500
3501         /* allocate transmit descriptors */
3502         err = ixgbe_setup_all_tx_resources(adapter);
3503         if (err)
3504                 goto err_setup_tx;
3505
3506         /* allocate receive descriptors */
3507         err = ixgbe_setup_all_rx_resources(adapter);
3508         if (err)
3509                 goto err_setup_rx;
3510
3511         ixgbe_configure(adapter);
3512
3513         ixgbe_napi_add_all(adapter);
3514
3515         err = ixgbe_request_irq(adapter);
3516         if (err)
3517                 goto err_req_irq;
3518
3519         err = ixgbe_up_complete(adapter);
3520         if (err)
3521                 goto err_up;
3522
3523         netif_tx_start_all_queues(netdev);
3524
3525         return 0;
3526
3527 err_up:
3528         ixgbe_release_hw_control(adapter);
3529         ixgbe_free_irq(adapter);
3530 err_req_irq:
3531 err_setup_rx:
3532         ixgbe_free_all_rx_resources(adapter);
3533 err_setup_tx:
3534         ixgbe_free_all_tx_resources(adapter);
3535         ixgbe_reset(adapter);
3536
3537         return err;
3538 }
3539
3540 /**
3541  * ixgbe_close - Disables a network interface
3542  * @netdev: network interface device structure
3543  *
3544  * Returns 0, this is not allowed to fail
3545  *
3546  * The close entry point is called when an interface is de-activated
3547  * by the OS.  The hardware is still under the drivers control, but
3548  * needs to be disabled.  A global MAC reset is issued to stop the
3549  * hardware, and all transmit and receive resources are freed.
3550  **/
3551 static int ixgbe_close(struct net_device *netdev)
3552 {
3553         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3554
3555         ixgbe_down(adapter);
3556         ixgbe_free_irq(adapter);
3557
3558         ixgbe_free_all_tx_resources(adapter);
3559         ixgbe_free_all_rx_resources(adapter);
3560
3561         ixgbe_release_hw_control(adapter);
3562
3563         return 0;
3564 }
3565
3566 /**
3567  * ixgbe_napi_add_all - prep napi structs for use
3568  * @adapter: private struct
3569  *
3570  * helper function to napi_add each possible q_vector->napi
3571  */
3572 void ixgbe_napi_add_all(struct ixgbe_adapter *adapter)
3573 {
3574         int q_idx, q_vectors;
3575         struct net_device *netdev = adapter->netdev;
3576         int (*poll)(struct napi_struct *, int);
3577
3578         /* check if we already have our netdev->napi_list populated */
3579         if (&netdev->napi_list != netdev->napi_list.next)
3580                 return;
3581
3582         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3583                 poll = &ixgbe_clean_rxonly;
3584                 /* Only enable as many vectors as we have rx queues. */
3585                 q_vectors = adapter->num_rx_queues;
3586         } else {
3587                 poll = &ixgbe_poll;
3588                 /* only one q_vector for legacy modes */
3589                 q_vectors = 1;
3590         }
3591
3592         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3593                 struct ixgbe_q_vector *q_vector = &adapter->q_vector[q_idx];
3594                 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
3595         }
3596 }
3597
3598 void ixgbe_napi_del_all(struct ixgbe_adapter *adapter)
3599 {
3600         int q_idx;
3601         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3602
3603         /* legacy and MSI only use one vector */
3604         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3605                 q_vectors = 1;
3606
3607         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3608                 struct ixgbe_q_vector *q_vector = &adapter->q_vector[q_idx];
3609                 if (!q_vector->rxr_count)
3610                         continue;
3611                 netif_napi_del(&q_vector->napi);
3612         }
3613 }
3614
3615 #ifdef CONFIG_PM
3616 static int ixgbe_resume(struct pci_dev *pdev)
3617 {
3618         struct net_device *netdev = pci_get_drvdata(pdev);
3619         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3620         u32 err;
3621
3622         pci_set_power_state(pdev, PCI_D0);
3623         pci_restore_state(pdev);
3624         err = pci_enable_device(pdev);
3625         if (err) {
3626                 printk(KERN_ERR "ixgbe: Cannot enable PCI device from "
3627                                 "suspend\n");
3628                 return err;
3629         }
3630         pci_set_master(pdev);
3631
3632         pci_enable_wake(pdev, PCI_D3hot, 0);
3633         pci_enable_wake(pdev, PCI_D3cold, 0);
3634
3635         err = ixgbe_init_interrupt_scheme(adapter);
3636         if (err) {
3637                 printk(KERN_ERR "ixgbe: Cannot initialize interrupts for "
3638                                 "device\n");
3639                 return err;
3640         }
3641
3642         ixgbe_reset(adapter);
3643
3644         if (netif_running(netdev)) {
3645                 err = ixgbe_open(adapter->netdev);
3646                 if (err)
3647                         return err;
3648         }
3649
3650         netif_device_attach(netdev);
3651
3652         return 0;
3653 }
3654 #endif /* CONFIG_PM */
3655
3656 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
3657 {
3658         struct net_device *netdev = pci_get_drvdata(pdev);
3659         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3660         struct ixgbe_hw *hw = &adapter->hw;
3661         u32 ctrl, fctrl;
3662         u32 wufc = adapter->wol;
3663 #ifdef CONFIG_PM
3664         int retval = 0;
3665 #endif
3666
3667         netif_device_detach(netdev);
3668
3669         if (netif_running(netdev)) {
3670                 ixgbe_down(adapter);
3671                 ixgbe_free_irq(adapter);
3672                 ixgbe_free_all_tx_resources(adapter);
3673                 ixgbe_free_all_rx_resources(adapter);
3674         }
3675         ixgbe_reset_interrupt_capability(adapter);
3676         ixgbe_napi_del_all(adapter);
3677         INIT_LIST_HEAD(&netdev->napi_list);
3678         kfree(adapter->tx_ring);
3679         kfree(adapter->rx_ring);
3680
3681 #ifdef CONFIG_PM
3682         retval = pci_save_state(pdev);
3683         if (retval)
3684                 return retval;
3685
3686 #endif
3687         if (wufc) {
3688                 ixgbe_set_rx_mode(netdev);
3689
3690                 /* turn on all-multi mode if wake on multicast is enabled */
3691                 if (wufc & IXGBE_WUFC_MC) {
3692                         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3693                         fctrl |= IXGBE_FCTRL_MPE;
3694                         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3695                 }
3696
3697                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
3698                 ctrl |= IXGBE_CTRL_GIO_DIS;
3699                 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
3700
3701                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
3702         } else {
3703                 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
3704                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
3705         }
3706
3707         if (wufc && hw->mac.type == ixgbe_mac_82599EB) {
3708                 pci_enable_wake(pdev, PCI_D3hot, 1);
3709                 pci_enable_wake(pdev, PCI_D3cold, 1);
3710         } else {
3711                 pci_enable_wake(pdev, PCI_D3hot, 0);
3712                 pci_enable_wake(pdev, PCI_D3cold, 0);
3713         }
3714
3715         *enable_wake = !!wufc;
3716
3717         ixgbe_release_hw_control(adapter);
3718
3719         pci_disable_device(pdev);
3720
3721         return 0;
3722 }
3723
3724 #ifdef CONFIG_PM
3725 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
3726 {
3727         int retval;
3728         bool wake;
3729
3730         retval = __ixgbe_shutdown(pdev, &wake);
3731         if (retval)
3732                 return retval;
3733
3734         if (wake) {
3735                 pci_prepare_to_sleep(pdev);
3736         } else {
3737                 pci_wake_from_d3(pdev, false);
3738                 pci_set_power_state(pdev, PCI_D3hot);
3739         }
3740
3741         return 0;
3742 }
3743 #endif /* CONFIG_PM */
3744
3745 static void ixgbe_shutdown(struct pci_dev *pdev)
3746 {
3747         bool wake;
3748
3749         __ixgbe_shutdown(pdev, &wake);
3750
3751         if (system_state == SYSTEM_POWER_OFF) {
3752                 pci_wake_from_d3(pdev, wake);
3753                 pci_set_power_state(pdev, PCI_D3hot);
3754         }
3755 }
3756
3757 /**
3758  * ixgbe_update_stats - Update the board statistics counters.
3759  * @adapter: board private structure
3760  **/
3761 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
3762 {
3763         struct ixgbe_hw *hw = &adapter->hw;
3764         u64 total_mpc = 0;
3765         u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
3766
3767         if (hw->mac.type == ixgbe_mac_82599EB) {
3768                 for (i = 0; i < 16; i++)
3769                         adapter->hw_rx_no_dma_resources +=
3770                                              IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
3771         }
3772
3773         adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
3774         for (i = 0; i < 8; i++) {
3775                 /* for packet buffers not used, the register should read 0 */
3776                 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
3777                 missed_rx += mpc;
3778                 adapter->stats.mpc[i] += mpc;
3779                 total_mpc += adapter->stats.mpc[i];
3780                 if (hw->mac.type == ixgbe_mac_82598EB)
3781                         adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
3782                 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
3783                 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
3784                 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
3785                 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
3786                 if (hw->mac.type == ixgbe_mac_82599EB) {
3787                         adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
3788                                                             IXGBE_PXONRXCNT(i));
3789                         adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
3790                                                            IXGBE_PXOFFRXCNT(i));
3791                         adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
3792                 } else {
3793                         adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
3794                                                               IXGBE_PXONRXC(i));
3795                         adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
3796                                                              IXGBE_PXOFFRXC(i));
3797                 }
3798                 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
3799                                                             IXGBE_PXONTXC(i));
3800                 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
3801                                                              IXGBE_PXOFFTXC(i));
3802         }
3803         adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
3804         /* work around hardware counting issue */
3805         adapter->stats.gprc -= missed_rx;
3806
3807         /* 82598 hardware only has a 32 bit counter in the high register */
3808         if (hw->mac.type == ixgbe_mac_82599EB) {
3809                 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
3810                 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
3811                 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
3812                 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
3813                 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL);
3814                 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
3815                 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
3816                 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
3817         } else {
3818                 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3819                 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3820                 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3821                 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3822                 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3823         }
3824         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3825         adapter->stats.bprc += bprc;
3826         adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3827         if (hw->mac.type == ixgbe_mac_82598EB)
3828                 adapter->stats.mprc -= bprc;
3829         adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3830         adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3831         adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3832         adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3833         adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3834         adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3835         adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3836         adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
3837         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3838         adapter->stats.lxontxc += lxon;
3839         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3840         adapter->stats.lxofftxc += lxoff;
3841         adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3842         adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
3843         adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3844         /*
3845          * 82598 errata - tx of flow control packets is included in tx counters
3846          */
3847         xon_off_tot = lxon + lxoff;
3848         adapter->stats.gptc -= xon_off_tot;
3849         adapter->stats.mptc -= xon_off_tot;
3850         adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
3851         adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3852         adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3853         adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3854         adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3855         adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3856         adapter->stats.ptc64 -= xon_off_tot;
3857         adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3858         adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3859         adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3860         adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3861         adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3862         adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3863
3864         /* Fill out the OS statistics structure */
3865         adapter->net_stats.multicast = adapter->stats.mprc;
3866
3867         /* Rx Errors */
3868         adapter->net_stats.rx_errors = adapter->stats.crcerrs +
3869                                        adapter->stats.rlec;
3870         adapter->net_stats.rx_dropped = 0;
3871         adapter->net_stats.rx_length_errors = adapter->stats.rlec;
3872         adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
3873         adapter->net_stats.rx_missed_errors = total_mpc;
3874 }
3875
3876 /**
3877  * ixgbe_watchdog - Timer Call-back
3878  * @data: pointer to adapter cast into an unsigned long
3879  **/
3880 static void ixgbe_watchdog(unsigned long data)
3881 {
3882         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
3883         struct ixgbe_hw *hw = &adapter->hw;
3884
3885         /* Do the watchdog outside of interrupt context due to the lovely
3886          * delays that some of the newer hardware requires */
3887         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
3888                 u64 eics = 0;
3889                 int i;
3890
3891                 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++)
3892                         eics |= (1 << i);
3893
3894                 /* Cause software interrupt to ensure rx rings are cleaned */
3895                 switch (hw->mac.type) {
3896                 case ixgbe_mac_82598EB:
3897                         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3898                                 IXGBE_WRITE_REG(hw, IXGBE_EICS, (u32)eics);
3899                         } else {
3900                                 /*
3901                                  * for legacy and MSI interrupts don't set any
3902                                  * bits that are enabled for EIAM, because this
3903                                  * operation would set *both* EIMS and EICS for
3904                                  * any bit in EIAM
3905                                  */
3906                                 IXGBE_WRITE_REG(hw, IXGBE_EICS,
3907                                      (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
3908                         }
3909                         break;
3910                 case ixgbe_mac_82599EB:
3911                         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3912                                 /*
3913                                  * EICS(0..15) first 0-15 q vectors
3914                                  * EICS[1] (16..31) q vectors 16-31
3915                                  * EICS[2] (0..31) q vectors 32-63
3916                                  */
3917                                 IXGBE_WRITE_REG(hw, IXGBE_EICS,
3918                                                 (u32)(eics & 0xFFFF));
3919                                 IXGBE_WRITE_REG(hw, IXGBE_EICS_EX(1),
3920                                                 (u32)(eics & 0xFFFF0000));
3921                                 IXGBE_WRITE_REG(hw, IXGBE_EICS_EX(2),
3922                                                 (u32)(eics >> 32));
3923                         } else {
3924                                 /*
3925                                  * for legacy and MSI interrupts don't set any
3926                                  * bits that are enabled for EIAM, because this
3927                                  * operation would set *both* EIMS and EICS for
3928                                  * any bit in EIAM
3929                                  */
3930                                 IXGBE_WRITE_REG(hw, IXGBE_EICS,
3931                                      (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
3932                         }
3933                         break;
3934                 default:
3935                         break;
3936                 }
3937                 /* Reset the timer */
3938                 mod_timer(&adapter->watchdog_timer,
3939                           round_jiffies(jiffies + 2 * HZ));
3940         }
3941
3942         schedule_work(&adapter->watchdog_task);
3943 }
3944
3945 /**
3946  * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
3947  * @work: pointer to work_struct containing our data
3948  **/
3949 static void ixgbe_multispeed_fiber_task(struct work_struct *work)
3950 {
3951         struct ixgbe_adapter *adapter = container_of(work,
3952                                                      struct ixgbe_adapter,
3953                                                      multispeed_fiber_task);
3954         struct ixgbe_hw *hw = &adapter->hw;
3955         u32 autoneg;
3956
3957         adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
3958         if (hw->mac.ops.get_link_capabilities)
3959                 hw->mac.ops.get_link_capabilities(hw, &autoneg,
3960                                                   &hw->mac.autoneg);
3961         if (hw->mac.ops.setup_link_speed)
3962                 hw->mac.ops.setup_link_speed(hw, autoneg, true, true);
3963         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3964         adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
3965 }
3966
3967 /**
3968  * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
3969  * @work: pointer to work_struct containing our data
3970  **/
3971 static void ixgbe_sfp_config_module_task(struct work_struct *work)
3972 {
3973         struct ixgbe_adapter *adapter = container_of(work,
3974                                                      struct ixgbe_adapter,
3975                                                      sfp_config_module_task);
3976         struct ixgbe_hw *hw = &adapter->hw;
3977         u32 err;
3978
3979         adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
3980         err = hw->phy.ops.identify_sfp(hw);
3981         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
3982                 DPRINTK(PROBE, ERR, "PHY not supported on this NIC %d\n", err);
3983                 ixgbe_down(adapter);
3984                 return;
3985         }
3986         hw->mac.ops.setup_sfp(hw);
3987
3988         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
3989                 /* This will also work for DA Twinax connections */
3990                 schedule_work(&adapter->multispeed_fiber_task);
3991         adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
3992 }
3993
3994 /**
3995  * ixgbe_watchdog_task - worker thread to bring link up
3996  * @work: pointer to work_struct containing our data
3997  **/
3998 static void ixgbe_watchdog_task(struct work_struct *work)
3999 {
4000         struct ixgbe_adapter *adapter = container_of(work,
4001                                                      struct ixgbe_adapter,
4002                                                      watchdog_task);
4003         struct net_device *netdev = adapter->netdev;
4004         struct ixgbe_hw *hw = &adapter->hw;
4005         u32 link_speed = adapter->link_speed;
4006         bool link_up = adapter->link_up;
4007
4008         adapter->flags |= IXGBE_FLAG_IN_WATCHDOG_TASK;
4009
4010         if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4011                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
4012                 if (link_up ||
4013                     time_after(jiffies, (adapter->link_check_timeout +
4014                                          IXGBE_TRY_LINK_TIMEOUT))) {
4015                         IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
4016                         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4017                 }
4018                 adapter->link_up = link_up;
4019                 adapter->link_speed = link_speed;
4020         }
4021
4022         if (link_up) {
4023                 if (!netif_carrier_ok(netdev)) {
4024                         bool flow_rx, flow_tx;
4025
4026                         if (hw->mac.type == ixgbe_mac_82599EB) {
4027                                 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4028                                 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4029                                 flow_rx = (mflcn & IXGBE_MFLCN_RFCE);
4030                                 flow_tx = (fccfg & IXGBE_FCCFG_TFCE_802_3X);
4031                         } else {
4032                                 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4033                                 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
4034                                 flow_rx = (frctl & IXGBE_FCTRL_RFCE);
4035                                 flow_tx = (rmcs & IXGBE_RMCS_TFCE_802_3X);
4036                         }
4037
4038                         printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, "
4039                                "Flow Control: %s\n",
4040                                netdev->name,
4041                                (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
4042                                 "10 Gbps" :
4043                                 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
4044                                  "1 Gbps" : "unknown speed")),
4045                                ((flow_rx && flow_tx) ? "RX/TX" :
4046                                 (flow_rx ? "RX" :
4047                                 (flow_tx ? "TX" : "None"))));
4048
4049                         netif_carrier_on(netdev);
4050                 } else {
4051                         /* Force detection of hung controller */
4052                         adapter->detect_tx_hung = true;
4053                 }
4054         } else {
4055                 adapter->link_up = false;
4056                 adapter->link_speed = 0;
4057                 if (netif_carrier_ok(netdev)) {
4058                         printk(KERN_INFO "ixgbe: %s NIC Link is Down\n",
4059                                netdev->name);
4060                         netif_carrier_off(netdev);
4061                 }
4062         }
4063
4064         ixgbe_update_stats(adapter);
4065         adapter->flags &= ~IXGBE_FLAG_IN_WATCHDOG_TASK;
4066 }
4067
4068 static int ixgbe_tso(struct ixgbe_adapter *adapter,
4069                      struct ixgbe_ring *tx_ring, struct sk_buff *skb,
4070                      u32 tx_flags, u8 *hdr_len)
4071 {
4072         struct ixgbe_adv_tx_context_desc *context_desc;
4073         unsigned int i;
4074         int err;
4075         struct ixgbe_tx_buffer *tx_buffer_info;
4076         u32 vlan_macip_lens = 0, type_tucmd_mlhl;
4077         u32 mss_l4len_idx, l4len;
4078
4079         if (skb_is_gso(skb)) {
4080                 if (skb_header_cloned(skb)) {
4081                         err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
4082                         if (err)
4083                                 return err;
4084                 }
4085                 l4len = tcp_hdrlen(skb);
4086                 *hdr_len += l4len;
4087
4088                 if (skb->protocol == htons(ETH_P_IP)) {
4089                         struct iphdr *iph = ip_hdr(skb);
4090                         iph->tot_len = 0;
4091                         iph->check = 0;
4092                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4093                                                                  iph->daddr, 0,
4094                                                                  IPPROTO_TCP,
4095                                                                  0);
4096                         adapter->hw_tso_ctxt++;
4097                 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
4098                         ipv6_hdr(skb)->payload_len = 0;
4099                         tcp_hdr(skb)->check =
4100                             ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4101                                              &ipv6_hdr(skb)->daddr,
4102                                              0, IPPROTO_TCP, 0);
4103                         adapter->hw_tso6_ctxt++;
4104                 }
4105
4106                 i = tx_ring->next_to_use;
4107
4108                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4109                 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4110
4111                 /* VLAN MACLEN IPLEN */
4112                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4113                         vlan_macip_lens |=
4114                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4115                 vlan_macip_lens |= ((skb_network_offset(skb)) <<
4116                                     IXGBE_ADVTXD_MACLEN_SHIFT);
4117                 *hdr_len += skb_network_offset(skb);
4118                 vlan_macip_lens |=
4119                     (skb_transport_header(skb) - skb_network_header(skb));
4120                 *hdr_len +=
4121                     (skb_transport_header(skb) - skb_network_header(skb));
4122                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4123                 context_desc->seqnum_seed = 0;
4124
4125                 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4126                 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
4127                                    IXGBE_ADVTXD_DTYP_CTXT);
4128
4129                 if (skb->protocol == htons(ETH_P_IP))
4130                         type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
4131                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
4132                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4133
4134                 /* MSS L4LEN IDX */
4135                 mss_l4len_idx =
4136                     (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
4137                 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4138                 /* use index 1 for TSO */
4139                 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
4140                 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4141
4142                 tx_buffer_info->time_stamp = jiffies;
4143                 tx_buffer_info->next_to_watch = i;
4144
4145                 i++;
4146                 if (i == tx_ring->count)
4147                         i = 0;
4148                 tx_ring->next_to_use = i;
4149
4150                 return true;
4151         }
4152         return false;
4153 }
4154
4155 static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
4156                           struct ixgbe_ring *tx_ring,
4157                           struct sk_buff *skb, u32 tx_flags)
4158 {
4159         struct ixgbe_adv_tx_context_desc *context_desc;
4160         unsigned int i;
4161         struct ixgbe_tx_buffer *tx_buffer_info;
4162         u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
4163
4164         if (skb->ip_summed == CHECKSUM_PARTIAL ||
4165             (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
4166                 i = tx_ring->next_to_use;
4167                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4168                 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4169
4170                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4171                         vlan_macip_lens |=
4172                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4173                 vlan_macip_lens |= (skb_network_offset(skb) <<
4174                                     IXGBE_ADVTXD_MACLEN_SHIFT);
4175                 if (skb->ip_summed == CHECKSUM_PARTIAL)
4176                         vlan_macip_lens |= (skb_transport_header(skb) -
4177                                             skb_network_header(skb));
4178
4179                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4180                 context_desc->seqnum_seed = 0;
4181
4182                 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
4183                                     IXGBE_ADVTXD_DTYP_CTXT);
4184
4185                 if (skb->ip_summed == CHECKSUM_PARTIAL) {
4186                         switch (skb->protocol) {
4187                         case cpu_to_be16(ETH_P_IP):
4188                                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
4189                                 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
4190                                         type_tucmd_mlhl |=
4191                                                 IXGBE_ADVTXD_TUCMD_L4T_TCP;
4192                                 break;
4193                         case cpu_to_be16(ETH_P_IPV6):
4194                                 /* XXX what about other V6 headers?? */
4195                                 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
4196                                         type_tucmd_mlhl |=
4197                                                 IXGBE_ADVTXD_TUCMD_L4T_TCP;
4198                                 break;
4199                         default:
4200                                 if (unlikely(net_ratelimit())) {
4201                                         DPRINTK(PROBE, WARNING,
4202                                          "partial checksum but proto=%x!\n",
4203                                          skb->protocol);
4204                                 }
4205                                 break;
4206                         }
4207                 }
4208
4209                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4210                 /* use index zero for tx checksum offload */
4211                 context_desc->mss_l4len_idx = 0;
4212
4213                 tx_buffer_info->time_stamp = jiffies;
4214                 tx_buffer_info->next_to_watch = i;
4215
4216                 adapter->hw_csum_tx_good++;
4217                 i++;
4218                 if (i == tx_ring->count)
4219                         i = 0;
4220                 tx_ring->next_to_use = i;
4221
4222                 return true;
4223         }
4224
4225         return false;
4226 }
4227
4228 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
4229                         struct ixgbe_ring *tx_ring,
4230                         struct sk_buff *skb, unsigned int first)
4231 {
4232         struct ixgbe_tx_buffer *tx_buffer_info;
4233         unsigned int len = skb_headlen(skb);
4234         unsigned int offset = 0, size, count = 0, i;
4235         unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
4236         unsigned int f;
4237         dma_addr_t *map;
4238
4239         i = tx_ring->next_to_use;
4240
4241         if (skb_dma_map(&adapter->pdev->dev, skb, DMA_TO_DEVICE)) {
4242                 dev_err(&adapter->pdev->dev, "TX DMA map failed\n");
4243                 return 0;
4244         }
4245
4246         map = skb_shinfo(skb)->dma_maps;
4247
4248         while (len) {
4249                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4250                 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
4251
4252                 tx_buffer_info->length = size;
4253                 tx_buffer_info->dma = map[0] + offset;
4254                 tx_buffer_info->time_stamp = jiffies;
4255                 tx_buffer_info->next_to_watch = i;
4256
4257                 len -= size;
4258                 offset += size;
4259                 count++;
4260
4261                 if (len) {
4262                         i++;
4263                         if (i == tx_ring->count)
4264                                 i = 0;
4265                 }
4266         }
4267
4268         for (f = 0; f < nr_frags; f++) {
4269                 struct skb_frag_struct *frag;
4270
4271                 frag = &skb_shinfo(skb)->frags[f];
4272                 len = frag->size;
4273                 offset = 0;
4274
4275                 while (len) {
4276                         i++;
4277                         if (i == tx_ring->count)
4278                                 i = 0;
4279
4280                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
4281                         size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
4282
4283                         tx_buffer_info->length = size;
4284                         tx_buffer_info->dma = map[f + 1] + offset;
4285                         tx_buffer_info->time_stamp = jiffies;
4286                         tx_buffer_info->next_to_watch = i;
4287
4288                         len -= size;
4289                         offset += size;
4290                         count++;
4291                 }
4292         }
4293
4294         tx_ring->tx_buffer_info[i].skb = skb;
4295         tx_ring->tx_buffer_info[first].next_to_watch = i;
4296
4297         return count;
4298 }
4299
4300 static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
4301                            struct ixgbe_ring *tx_ring,
4302                            int tx_flags, int count, u32 paylen, u8 hdr_len)
4303 {
4304         union ixgbe_adv_tx_desc *tx_desc = NULL;
4305         struct ixgbe_tx_buffer *tx_buffer_info;
4306         u32 olinfo_status = 0, cmd_type_len = 0;
4307         unsigned int i;
4308         u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
4309
4310         cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
4311
4312         cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
4313
4314         if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4315                 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
4316
4317         if (tx_flags & IXGBE_TX_FLAGS_TSO) {
4318                 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
4319
4320                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
4321                                  IXGBE_ADVTXD_POPTS_SHIFT;
4322
4323                 /* use index 1 context for tso */
4324                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
4325                 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
4326                         olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
4327                                          IXGBE_ADVTXD_POPTS_SHIFT;
4328
4329         } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
4330                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
4331                                  IXGBE_ADVTXD_POPTS_SHIFT;
4332
4333         olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
4334
4335         i = tx_ring->next_to_use;
4336         while (count--) {
4337                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4338                 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
4339                 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
4340                 tx_desc->read.cmd_type_len =
4341                         cpu_to_le32(cmd_type_len | tx_buffer_info->length);
4342                 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
4343                 i++;
4344                 if (i == tx_ring->count)
4345                         i = 0;
4346         }
4347
4348         tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
4349
4350         /*
4351          * Force memory writes to complete before letting h/w
4352          * know there are new descriptors to fetch.  (Only
4353          * applicable for weak-ordered memory model archs,
4354          * such as IA-64).
4355          */
4356         wmb();
4357
4358         tx_ring->next_to_use = i;
4359         writel(i, adapter->hw.hw_addr + tx_ring->tail);
4360 }
4361
4362 static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
4363                                  struct ixgbe_ring *tx_ring, int size)
4364 {
4365         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4366
4367         netif_stop_subqueue(netdev, tx_ring->queue_index);
4368         /* Herbert's original patch had:
4369          *  smp_mb__after_netif_stop_queue();
4370          * but since that doesn't exist yet, just open code it. */
4371         smp_mb();
4372
4373         /* We need to check again in a case another CPU has just
4374          * made room available. */
4375         if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
4376                 return -EBUSY;
4377
4378         /* A reprieve! - use start_queue because it doesn't call schedule */
4379         netif_start_subqueue(netdev, tx_ring->queue_index);
4380         ++adapter->restart_queue;
4381         return 0;
4382 }
4383
4384 static int ixgbe_maybe_stop_tx(struct net_device *netdev,
4385                               struct ixgbe_ring *tx_ring, int size)
4386 {
4387         if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
4388                 return 0;
4389         return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
4390 }
4391
4392 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
4393 {
4394         struct ixgbe_adapter *adapter = netdev_priv(dev);
4395
4396         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
4397                 return 0;  /* All traffic should default to class 0 */
4398
4399         return skb_tx_hash(dev, skb);
4400 }
4401
4402 static int ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
4403 {
4404         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4405         struct ixgbe_ring *tx_ring;
4406         unsigned int first;
4407         unsigned int tx_flags = 0;
4408         u8 hdr_len = 0;
4409         int r_idx = 0, tso;
4410         int count = 0;
4411         unsigned int f;
4412
4413         r_idx = skb->queue_mapping;
4414         tx_ring = &adapter->tx_ring[r_idx];
4415
4416         if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
4417                 tx_flags |= vlan_tx_tag_get(skb);
4418                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4419                         tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
4420                         tx_flags |= (skb->queue_mapping << 13);
4421                 }
4422                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
4423                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
4424         } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4425                 tx_flags |= (skb->queue_mapping << 13);
4426                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
4427                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
4428         }
4429         /* three things can cause us to need a context descriptor */
4430         if (skb_is_gso(skb) ||
4431             (skb->ip_summed == CHECKSUM_PARTIAL) ||
4432             (tx_flags & IXGBE_TX_FLAGS_VLAN))
4433                 count++;
4434
4435         count += TXD_USE_COUNT(skb_headlen(skb));
4436         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
4437                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
4438
4439         if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
4440                 adapter->tx_busy++;
4441                 return NETDEV_TX_BUSY;
4442         }
4443
4444         if (skb->protocol == htons(ETH_P_IP))
4445                 tx_flags |= IXGBE_TX_FLAGS_IPV4;
4446         first = tx_ring->next_to_use;
4447         tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
4448         if (tso < 0) {
4449                 dev_kfree_skb_any(skb);
4450                 return NETDEV_TX_OK;
4451         }
4452
4453         if (tso)
4454                 tx_flags |= IXGBE_TX_FLAGS_TSO;
4455         else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
4456                  (skb->ip_summed == CHECKSUM_PARTIAL))
4457                 tx_flags |= IXGBE_TX_FLAGS_CSUM;
4458
4459         count = ixgbe_tx_map(adapter, tx_ring, skb, first);
4460
4461         if (count) {
4462                 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
4463                                hdr_len);
4464                 netdev->trans_start = jiffies;
4465                 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
4466
4467         } else {
4468                 dev_kfree_skb_any(skb);
4469                 tx_ring->tx_buffer_info[first].time_stamp = 0;
4470                 tx_ring->next_to_use = first;
4471         }
4472
4473         return NETDEV_TX_OK;
4474 }
4475
4476 /**
4477  * ixgbe_get_stats - Get System Network Statistics
4478  * @netdev: network interface device structure
4479  *
4480  * Returns the address of the device statistics structure.
4481  * The statistics are actually updated from the timer callback.
4482  **/
4483 static struct net_device_stats *ixgbe_get_stats(struct net_device *netdev)
4484 {
4485         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4486
4487         /* only return the current stats */
4488         return &adapter->net_stats;
4489 }
4490
4491 /**
4492  * ixgbe_set_mac - Change the Ethernet Address of the NIC
4493  * @netdev: network interface device structure
4494  * @p: pointer to an address structure
4495  *
4496  * Returns 0 on success, negative on failure
4497  **/
4498 static int ixgbe_set_mac(struct net_device *netdev, void *p)
4499 {
4500         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4501         struct ixgbe_hw *hw = &adapter->hw;
4502         struct sockaddr *addr = p;
4503
4504         if (!is_valid_ether_addr(addr->sa_data))
4505                 return -EADDRNOTAVAIL;
4506
4507         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
4508         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
4509
4510         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
4511
4512         return 0;
4513 }
4514
4515 #ifdef CONFIG_NET_POLL_CONTROLLER
4516 /*
4517  * Polling 'interrupt' - used by things like netconsole to send skbs
4518  * without having to re-enable interrupts. It's not called while
4519  * the interrupt routine is executing.
4520  */
4521 static void ixgbe_netpoll(struct net_device *netdev)
4522 {
4523         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4524
4525         disable_irq(adapter->pdev->irq);
4526         adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
4527         ixgbe_intr(adapter->pdev->irq, netdev);
4528         adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
4529         enable_irq(adapter->pdev->irq);
4530 }
4531 #endif
4532
4533 static const struct net_device_ops ixgbe_netdev_ops = {
4534         .ndo_open               = ixgbe_open,
4535         .ndo_stop               = ixgbe_close,
4536         .ndo_start_xmit         = ixgbe_xmit_frame,
4537         .ndo_select_queue       = ixgbe_select_queue,
4538         .ndo_get_stats          = ixgbe_get_stats,
4539         .ndo_set_rx_mode        = ixgbe_set_rx_mode,
4540         .ndo_set_multicast_list = ixgbe_set_rx_mode,
4541         .ndo_validate_addr      = eth_validate_addr,
4542         .ndo_set_mac_address    = ixgbe_set_mac,
4543         .ndo_change_mtu         = ixgbe_change_mtu,
4544         .ndo_tx_timeout         = ixgbe_tx_timeout,
4545         .ndo_vlan_rx_register   = ixgbe_vlan_rx_register,
4546         .ndo_vlan_rx_add_vid    = ixgbe_vlan_rx_add_vid,
4547         .ndo_vlan_rx_kill_vid   = ixgbe_vlan_rx_kill_vid,
4548 #ifdef CONFIG_NET_POLL_CONTROLLER
4549         .ndo_poll_controller    = ixgbe_netpoll,
4550 #endif
4551 };
4552
4553 /**
4554  * ixgbe_probe - Device Initialization Routine
4555  * @pdev: PCI device information struct
4556  * @ent: entry in ixgbe_pci_tbl
4557  *
4558  * Returns 0 on success, negative on failure
4559  *
4560  * ixgbe_probe initializes an adapter identified by a pci_dev structure.
4561  * The OS initialization, configuring of the adapter private structure,
4562  * and a hardware reset occur.
4563  **/
4564 static int __devinit ixgbe_probe(struct pci_dev *pdev,
4565                                  const struct pci_device_id *ent)
4566 {
4567         struct net_device *netdev;
4568         struct ixgbe_adapter *adapter = NULL;
4569         struct ixgbe_hw *hw;
4570         const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
4571         static int cards_found;
4572         int i, err, pci_using_dac;
4573         u16 pm_value = 0;
4574         u32 part_num, eec;
4575
4576         err = pci_enable_device(pdev);
4577         if (err)
4578                 return err;
4579
4580         if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
4581             !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
4582                 pci_using_dac = 1;
4583         } else {
4584                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4585                 if (err) {
4586                         err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
4587                         if (err) {
4588                                 dev_err(&pdev->dev, "No usable DMA "
4589                                         "configuration, aborting\n");
4590                                 goto err_dma;
4591                         }
4592                 }
4593                 pci_using_dac = 0;
4594         }
4595
4596         err = pci_request_regions(pdev, ixgbe_driver_name);
4597         if (err) {
4598                 dev_err(&pdev->dev, "pci_request_regions failed 0x%x\n", err);
4599                 goto err_pci_reg;
4600         }
4601
4602         err = pci_enable_pcie_error_reporting(pdev);
4603         if (err) {
4604                 dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed "
4605                                     "0x%x\n", err);
4606                 /* non-fatal, continue */
4607         }
4608
4609         pci_set_master(pdev);
4610         pci_save_state(pdev);
4611
4612         netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES);
4613         if (!netdev) {
4614                 err = -ENOMEM;
4615                 goto err_alloc_etherdev;
4616         }
4617
4618         SET_NETDEV_DEV(netdev, &pdev->dev);
4619
4620         pci_set_drvdata(pdev, netdev);
4621         adapter = netdev_priv(netdev);
4622
4623         adapter->netdev = netdev;
4624         adapter->pdev = pdev;
4625         hw = &adapter->hw;
4626         hw->back = adapter;
4627         adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
4628
4629         hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
4630                               pci_resource_len(pdev, 0));
4631         if (!hw->hw_addr) {
4632                 err = -EIO;
4633                 goto err_ioremap;
4634         }
4635
4636         for (i = 1; i <= 5; i++) {
4637                 if (pci_resource_len(pdev, i) == 0)
4638                         continue;
4639         }
4640
4641         netdev->netdev_ops = &ixgbe_netdev_ops;
4642         ixgbe_set_ethtool_ops(netdev);
4643         netdev->watchdog_timeo = 5 * HZ;
4644         strcpy(netdev->name, pci_name(pdev));
4645
4646         adapter->bd_number = cards_found;
4647
4648         /* Setup hw api */
4649         memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
4650         hw->mac.type  = ii->mac;
4651
4652         /* EEPROM */
4653         memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
4654         eec = IXGBE_READ_REG(hw, IXGBE_EEC);
4655         /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
4656         if (!(eec & (1 << 8)))
4657                 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
4658
4659         /* PHY */
4660         memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
4661         hw->phy.sfp_type = ixgbe_sfp_type_unknown;
4662
4663         /* set up this timer and work struct before calling get_invariants
4664          * which might start the timer
4665          */
4666         init_timer(&adapter->sfp_timer);
4667         adapter->sfp_timer.function = &ixgbe_sfp_timer;
4668         adapter->sfp_timer.data = (unsigned long) adapter;
4669
4670         INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
4671
4672         /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
4673         INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
4674
4675         /* a new SFP+ module arrival, called from GPI SDP2 context */
4676         INIT_WORK(&adapter->sfp_config_module_task,
4677                   ixgbe_sfp_config_module_task);
4678
4679         err = ii->get_invariants(hw);
4680         if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
4681                 /* start a kernel thread to watch for a module to arrive */
4682                 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4683                 mod_timer(&adapter->sfp_timer,
4684                           round_jiffies(jiffies + (2 * HZ)));
4685                 err = 0;
4686         } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4687                 DPRINTK(PROBE, ERR, "failed to load because an "
4688                         "unsupported SFP+ module type was detected.\n");
4689                 goto err_hw_init;
4690         } else if (err) {
4691                 goto err_hw_init;
4692         }
4693
4694         /* setup the private structure */
4695         err = ixgbe_sw_init(adapter);
4696         if (err)
4697                 goto err_sw_init;
4698
4699         /* reset_hw fills in the perm_addr as well */
4700         err = hw->mac.ops.reset_hw(hw);
4701         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4702                 dev_err(&adapter->pdev->dev, "failed to load because an "
4703                         "unsupported SFP+ module type was detected.\n");
4704                 goto err_sw_init;
4705         } else if (err) {
4706                 dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err);
4707                 goto err_sw_init;
4708         }
4709
4710         netdev->features = NETIF_F_SG |
4711                            NETIF_F_IP_CSUM |
4712                            NETIF_F_HW_VLAN_TX |
4713                            NETIF_F_HW_VLAN_RX |
4714                            NETIF_F_HW_VLAN_FILTER;
4715
4716         netdev->features |= NETIF_F_IPV6_CSUM;
4717         netdev->features |= NETIF_F_TSO;
4718         netdev->features |= NETIF_F_TSO6;
4719         netdev->features |= NETIF_F_GRO;
4720
4721         netdev->vlan_features |= NETIF_F_TSO;
4722         netdev->vlan_features |= NETIF_F_TSO6;
4723         netdev->vlan_features |= NETIF_F_IP_CSUM;
4724         netdev->vlan_features |= NETIF_F_SG;
4725
4726         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
4727                 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
4728
4729 #ifdef CONFIG_IXGBE_DCB
4730         netdev->dcbnl_ops = &dcbnl_ops;
4731 #endif
4732
4733         if (pci_using_dac)
4734                 netdev->features |= NETIF_F_HIGHDMA;
4735
4736         /* make sure the EEPROM is good */
4737         if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
4738                 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
4739                 err = -EIO;
4740                 goto err_eeprom;
4741         }
4742
4743         memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
4744         memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
4745
4746         if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
4747                 dev_err(&pdev->dev, "invalid MAC address\n");
4748                 err = -EIO;
4749                 goto err_eeprom;
4750         }
4751
4752         init_timer(&adapter->watchdog_timer);
4753         adapter->watchdog_timer.function = &ixgbe_watchdog;
4754         adapter->watchdog_timer.data = (unsigned long)adapter;
4755
4756         INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
4757         INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
4758
4759         err = ixgbe_init_interrupt_scheme(adapter);
4760         if (err)
4761                 goto err_sw_init;
4762
4763         switch (pdev->device) {
4764         case IXGBE_DEV_ID_82599_KX4:
4765 #define IXGBE_PCIE_PMCSR 0x44
4766                 adapter->wol = IXGBE_WUFC_MAG;
4767                 pci_read_config_word(pdev, IXGBE_PCIE_PMCSR, &pm_value);
4768                 pci_write_config_word(pdev, IXGBE_PCIE_PMCSR,
4769                                       (pm_value | (1 << 8)));
4770                 break;
4771         default:
4772                 adapter->wol = 0;
4773                 break;
4774         }
4775         device_init_wakeup(&adapter->pdev->dev, true);
4776         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
4777
4778         /* pick up the PCI bus settings for reporting later */
4779         hw->mac.ops.get_bus_info(hw);
4780
4781         /* print bus type/speed/width info */
4782         dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n",
4783                 ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s":
4784                  (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"),
4785                 ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" :
4786                  (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" :
4787                  (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" :
4788                  "Unknown"),
4789                 netdev->dev_addr);
4790         ixgbe_read_pba_num_generic(hw, &part_num);
4791         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
4792                 dev_info(&pdev->dev, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n",
4793                          hw->mac.type, hw->phy.type, hw->phy.sfp_type,
4794                          (part_num >> 8), (part_num & 0xff));
4795         else
4796                 dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
4797                          hw->mac.type, hw->phy.type,
4798                          (part_num >> 8), (part_num & 0xff));
4799
4800         if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
4801                 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
4802                          "this card is not sufficient for optimal "
4803                          "performance.\n");
4804                 dev_warn(&pdev->dev, "For optimal performance a x8 "
4805                          "PCI-Express slot is required.\n");
4806         }
4807
4808         /* save off EEPROM version number */
4809         hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
4810
4811         /* reset the hardware with the new settings */
4812         hw->mac.ops.start_hw(hw);
4813
4814         strcpy(netdev->name, "eth%d");
4815         err = register_netdev(netdev);
4816         if (err)
4817                 goto err_register;
4818
4819         /* carrier off reporting is important to ethtool even BEFORE open */
4820         netif_carrier_off(netdev);
4821
4822 #ifdef CONFIG_IXGBE_DCA
4823         if (dca_add_requester(&pdev->dev) == 0) {
4824                 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
4825                 /* always use CB2 mode, difference is masked
4826                  * in the CB driver */
4827                 IXGBE_WRITE_REG(hw, IXGBE_DCA_CTRL, 2);
4828                 ixgbe_setup_dca(adapter);
4829         }
4830 #endif
4831
4832         dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
4833         cards_found++;
4834         return 0;
4835
4836 err_register:
4837         ixgbe_release_hw_control(adapter);
4838 err_hw_init:
4839 err_sw_init:
4840         ixgbe_reset_interrupt_capability(adapter);
4841 err_eeprom:
4842         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4843         del_timer_sync(&adapter->sfp_timer);
4844         cancel_work_sync(&adapter->sfp_task);
4845         cancel_work_sync(&adapter->multispeed_fiber_task);
4846         cancel_work_sync(&adapter->sfp_config_module_task);
4847         iounmap(hw->hw_addr);
4848 err_ioremap:
4849         free_netdev(netdev);
4850 err_alloc_etherdev:
4851         pci_release_regions(pdev);
4852 err_pci_reg:
4853 err_dma:
4854         pci_disable_device(pdev);
4855         return err;
4856 }
4857
4858 /**
4859  * ixgbe_remove - Device Removal Routine
4860  * @pdev: PCI device information struct
4861  *
4862  * ixgbe_remove is called by the PCI subsystem to alert the driver
4863  * that it should release a PCI device.  The could be caused by a
4864  * Hot-Plug event, or because the driver is going to be removed from
4865  * memory.
4866  **/
4867 static void __devexit ixgbe_remove(struct pci_dev *pdev)
4868 {
4869         struct net_device *netdev = pci_get_drvdata(pdev);
4870         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4871         int err;
4872
4873         set_bit(__IXGBE_DOWN, &adapter->state);
4874         /* clear the module not found bit to make sure the worker won't
4875          * reschedule
4876          */
4877         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4878         del_timer_sync(&adapter->watchdog_timer);
4879
4880         del_timer_sync(&adapter->sfp_timer);
4881         cancel_work_sync(&adapter->watchdog_task);
4882         cancel_work_sync(&adapter->sfp_task);
4883         cancel_work_sync(&adapter->multispeed_fiber_task);
4884         cancel_work_sync(&adapter->sfp_config_module_task);
4885         flush_scheduled_work();
4886
4887 #ifdef CONFIG_IXGBE_DCA
4888         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
4889                 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
4890                 dca_remove_requester(&pdev->dev);
4891                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
4892         }
4893
4894 #endif
4895         if (netdev->reg_state == NETREG_REGISTERED)
4896                 unregister_netdev(netdev);
4897
4898         ixgbe_reset_interrupt_capability(adapter);
4899
4900         ixgbe_release_hw_control(adapter);
4901
4902         iounmap(adapter->hw.hw_addr);
4903         pci_release_regions(pdev);
4904
4905         DPRINTK(PROBE, INFO, "complete\n");
4906         kfree(adapter->tx_ring);
4907         kfree(adapter->rx_ring);
4908
4909         free_netdev(netdev);
4910
4911         err = pci_disable_pcie_error_reporting(pdev);
4912         if (err)
4913                 dev_err(&pdev->dev,
4914                         "pci_disable_pcie_error_reporting failed 0x%x\n", err);
4915
4916         pci_disable_device(pdev);
4917 }
4918
4919 /**
4920  * ixgbe_io_error_detected - called when PCI error is detected
4921  * @pdev: Pointer to PCI device
4922  * @state: The current pci connection state
4923  *
4924  * This function is called after a PCI bus error affecting
4925  * this device has been detected.
4926  */
4927 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
4928                                                 pci_channel_state_t state)
4929 {
4930         struct net_device *netdev = pci_get_drvdata(pdev);
4931         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4932
4933         netif_device_detach(netdev);
4934
4935         if (netif_running(netdev))
4936                 ixgbe_down(adapter);
4937         pci_disable_device(pdev);
4938
4939         /* Request a slot reset. */
4940         return PCI_ERS_RESULT_NEED_RESET;
4941 }
4942
4943 /**
4944  * ixgbe_io_slot_reset - called after the pci bus has been reset.
4945  * @pdev: Pointer to PCI device
4946  *
4947  * Restart the card from scratch, as if from a cold-boot.
4948  */
4949 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
4950 {
4951         struct net_device *netdev = pci_get_drvdata(pdev);
4952         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4953         pci_ers_result_t result;
4954         int err;
4955
4956         if (pci_enable_device(pdev)) {
4957                 DPRINTK(PROBE, ERR,
4958                         "Cannot re-enable PCI device after reset.\n");
4959                 result = PCI_ERS_RESULT_DISCONNECT;
4960         } else {
4961                 pci_set_master(pdev);
4962                 pci_restore_state(pdev);
4963
4964                 pci_enable_wake(pdev, PCI_D3hot, 0);
4965                 pci_enable_wake(pdev, PCI_D3cold, 0);
4966
4967                 ixgbe_reset(adapter);
4968                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
4969                 result = PCI_ERS_RESULT_RECOVERED;
4970         }
4971
4972         err = pci_cleanup_aer_uncorrect_error_status(pdev);
4973         if (err) {
4974                 dev_err(&pdev->dev,
4975                   "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err);
4976                 /* non-fatal, continue */
4977         }
4978
4979         return result;
4980 }
4981
4982 /**
4983  * ixgbe_io_resume - called when traffic can start flowing again.
4984  * @pdev: Pointer to PCI device
4985  *
4986  * This callback is called when the error recovery driver tells us that
4987  * its OK to resume normal operation.
4988  */
4989 static void ixgbe_io_resume(struct pci_dev *pdev)
4990 {
4991         struct net_device *netdev = pci_get_drvdata(pdev);
4992         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4993
4994         if (netif_running(netdev)) {
4995                 if (ixgbe_up(adapter)) {
4996                         DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
4997                         return;
4998                 }
4999         }
5000
5001         netif_device_attach(netdev);
5002 }
5003
5004 static struct pci_error_handlers ixgbe_err_handler = {
5005         .error_detected = ixgbe_io_error_detected,
5006         .slot_reset = ixgbe_io_slot_reset,
5007         .resume = ixgbe_io_resume,
5008 };
5009
5010 static struct pci_driver ixgbe_driver = {
5011         .name     = ixgbe_driver_name,
5012         .id_table = ixgbe_pci_tbl,
5013         .probe    = ixgbe_probe,
5014         .remove   = __devexit_p(ixgbe_remove),
5015 #ifdef CONFIG_PM
5016         .suspend  = ixgbe_suspend,
5017         .resume   = ixgbe_resume,
5018 #endif
5019         .shutdown = ixgbe_shutdown,
5020         .err_handler = &ixgbe_err_handler
5021 };
5022
5023 /**
5024  * ixgbe_init_module - Driver Registration Routine
5025  *
5026  * ixgbe_init_module is the first routine called when the driver is
5027  * loaded. All it does is register with the PCI subsystem.
5028  **/
5029 static int __init ixgbe_init_module(void)
5030 {
5031         int ret;
5032         printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
5033                ixgbe_driver_string, ixgbe_driver_version);
5034
5035         printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
5036
5037 #ifdef CONFIG_IXGBE_DCA
5038         dca_register_notify(&dca_notifier);
5039 #endif
5040
5041         ret = pci_register_driver(&ixgbe_driver);
5042         return ret;
5043 }
5044
5045 module_init(ixgbe_init_module);
5046
5047 /**
5048  * ixgbe_exit_module - Driver Exit Cleanup Routine
5049  *
5050  * ixgbe_exit_module is called just before the driver is removed
5051  * from memory.
5052  **/
5053 static void __exit ixgbe_exit_module(void)
5054 {
5055 #ifdef CONFIG_IXGBE_DCA
5056         dca_unregister_notify(&dca_notifier);
5057 #endif
5058         pci_unregister_driver(&ixgbe_driver);
5059 }
5060
5061 #ifdef CONFIG_IXGBE_DCA
5062 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
5063                             void *p)
5064 {
5065         int ret_val;
5066
5067         ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
5068                                          __ixgbe_notify_dca);
5069
5070         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
5071 }
5072
5073 #endif /* CONFIG_IXGBE_DCA */
5074 #ifdef DEBUG
5075 /**
5076  * ixgbe_get_hw_dev_name - return device name string
5077  * used by hardware layer to print debugging information
5078  **/
5079 char *ixgbe_get_hw_dev_name(struct ixgbe_hw *hw)
5080 {
5081         struct ixgbe_adapter *adapter = hw->back;
5082         return adapter->netdev->name;
5083 }
5084
5085 #endif
5086 module_exit(ixgbe_exit_module);
5087
5088 /* ixgbe_main.c */