Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
[linux-2.6] / drivers / video / nvidia / nv_setup.c
1  /***************************************************************************\
2 |*                                                                           *|
3 |*       Copyright 2003 NVIDIA, Corporation.  All rights reserved.           *|
4 |*                                                                           *|
5 |*     NOTICE TO USER:   The source code  is copyrighted under  U.S. and     *|
6 |*     international laws.  Users and possessors of this source code are     *|
7 |*     hereby granted a nonexclusive,  royalty-free copyright license to     *|
8 |*     use this code in individual and commercial software.                  *|
9 |*                                                                           *|
10 |*     Any use of this source code must include,  in the user documenta-     *|
11 |*     tion and  internal comments to the code,  notices to the end user     *|
12 |*     as follows:                                                           *|
13 |*                                                                           *|
14 |*       Copyright 2003 NVIDIA, Corporation.  All rights reserved.           *|
15 |*                                                                           *|
16 |*     NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY     *|
17 |*     OF  THIS SOURCE  CODE  FOR ANY PURPOSE.  IT IS  PROVIDED  "AS IS"     *|
18 |*     WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND.  NVIDIA, CORPOR-     *|
19 |*     ATION DISCLAIMS ALL WARRANTIES  WITH REGARD  TO THIS SOURCE CODE,     *|
20 |*     INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE-     *|
21 |*     MENT,  AND FITNESS  FOR A PARTICULAR PURPOSE.   IN NO EVENT SHALL     *|
22 |*     NVIDIA, CORPORATION  BE LIABLE FOR ANY SPECIAL,  INDIRECT,  INCI-     *|
23 |*     DENTAL, OR CONSEQUENTIAL DAMAGES,  OR ANY DAMAGES  WHATSOEVER RE-     *|
24 |*     SULTING FROM LOSS OF USE,  DATA OR PROFITS,  WHETHER IN AN ACTION     *|
25 |*     OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION,  ARISING OUT OF     *|
26 |*     OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE.     *|
27 |*                                                                           *|
28 |*     U.S. Government  End  Users.   This source code  is a "commercial     *|
29 |*     item,"  as that  term is  defined at  48 C.F.R. 2.101 (OCT 1995),     *|
30 |*     consisting  of "commercial  computer  software"  and  "commercial     *|
31 |*     computer  software  documentation,"  as such  terms  are  used in     *|
32 |*     48 C.F.R. 12.212 (SEPT 1995)  and is provided to the U.S. Govern-     *|
33 |*     ment only as  a commercial end item.   Consistent with  48 C.F.R.     *|
34 |*     12.212 and  48 C.F.R. 227.7202-1 through  227.7202-4 (JUNE 1995),     *|
35 |*     all U.S. Government End Users  acquire the source code  with only     *|
36 |*     those rights set forth herein.                                        *|
37 |*                                                                           *|
38  \***************************************************************************/
39
40 /*
41  * GPL Licensing Note - According to Mark Vojkovich, author of the Xorg/
42  * XFree86 'nv' driver, this source code is provided under MIT-style licensing
43  * where the source code is provided "as is" without warranty of any kind.
44  * The only usage restriction is for the copyright notices to be retained
45  * whenever code is used.
46  *
47  * Antonino Daplas <adaplas@pol.net> 2005-03-11
48  */
49
50 #include <video/vga.h>
51 #include <linux/delay.h>
52 #include <linux/pci.h>
53 #include "nv_type.h"
54 #include "nv_local.h"
55 #include "nv_proto.h"
56 /*
57  * Override VGA I/O routines.
58  */
59 void NVWriteCrtc(struct nvidia_par *par, u8 index, u8 value)
60 {
61         VGA_WR08(par->PCIO, par->IOBase + 0x04, index);
62         VGA_WR08(par->PCIO, par->IOBase + 0x05, value);
63 }
64 u8 NVReadCrtc(struct nvidia_par *par, u8 index)
65 {
66         VGA_WR08(par->PCIO, par->IOBase + 0x04, index);
67         return (VGA_RD08(par->PCIO, par->IOBase + 0x05));
68 }
69 void NVWriteGr(struct nvidia_par *par, u8 index, u8 value)
70 {
71         VGA_WR08(par->PVIO, VGA_GFX_I, index);
72         VGA_WR08(par->PVIO, VGA_GFX_D, value);
73 }
74 u8 NVReadGr(struct nvidia_par *par, u8 index)
75 {
76         VGA_WR08(par->PVIO, VGA_GFX_I, index);
77         return (VGA_RD08(par->PVIO, VGA_GFX_D));
78 }
79 void NVWriteSeq(struct nvidia_par *par, u8 index, u8 value)
80 {
81         VGA_WR08(par->PVIO, VGA_SEQ_I, index);
82         VGA_WR08(par->PVIO, VGA_SEQ_D, value);
83 }
84 u8 NVReadSeq(struct nvidia_par *par, u8 index)
85 {
86         VGA_WR08(par->PVIO, VGA_SEQ_I, index);
87         return (VGA_RD08(par->PVIO, VGA_SEQ_D));
88 }
89 void NVWriteAttr(struct nvidia_par *par, u8 index, u8 value)
90 {
91         volatile u8 tmp;
92
93         tmp = VGA_RD08(par->PCIO, par->IOBase + 0x0a);
94         if (par->paletteEnabled)
95                 index &= ~0x20;
96         else
97                 index |= 0x20;
98         VGA_WR08(par->PCIO, VGA_ATT_IW, index);
99         VGA_WR08(par->PCIO, VGA_ATT_W, value);
100 }
101 u8 NVReadAttr(struct nvidia_par *par, u8 index)
102 {
103         volatile u8 tmp;
104
105         tmp = VGA_RD08(par->PCIO, par->IOBase + 0x0a);
106         if (par->paletteEnabled)
107                 index &= ~0x20;
108         else
109                 index |= 0x20;
110         VGA_WR08(par->PCIO, VGA_ATT_IW, index);
111         return (VGA_RD08(par->PCIO, VGA_ATT_R));
112 }
113 void NVWriteMiscOut(struct nvidia_par *par, u8 value)
114 {
115         VGA_WR08(par->PVIO, VGA_MIS_W, value);
116 }
117 u8 NVReadMiscOut(struct nvidia_par *par)
118 {
119         return (VGA_RD08(par->PVIO, VGA_MIS_R));
120 }
121 #if 0
122 void NVEnablePalette(struct nvidia_par *par)
123 {
124         volatile u8 tmp;
125
126         tmp = VGA_RD08(par->PCIO, par->IOBase + 0x0a);
127         VGA_WR08(par->PCIO, VGA_ATT_IW, 0x00);
128         par->paletteEnabled = 1;
129 }
130 void NVDisablePalette(struct nvidia_par *par)
131 {
132         volatile u8 tmp;
133
134         tmp = VGA_RD08(par->PCIO, par->IOBase + 0x0a);
135         VGA_WR08(par->PCIO, VGA_ATT_IW, 0x20);
136         par->paletteEnabled = 0;
137 }
138 #endif  /*  0  */
139 void NVWriteDacMask(struct nvidia_par *par, u8 value)
140 {
141         VGA_WR08(par->PDIO, VGA_PEL_MSK, value);
142 }
143 #if 0
144 u8 NVReadDacMask(struct nvidia_par *par)
145 {
146         return (VGA_RD08(par->PDIO, VGA_PEL_MSK));
147 }
148 #endif  /*  0  */
149 void NVWriteDacReadAddr(struct nvidia_par *par, u8 value)
150 {
151         VGA_WR08(par->PDIO, VGA_PEL_IR, value);
152 }
153 void NVWriteDacWriteAddr(struct nvidia_par *par, u8 value)
154 {
155         VGA_WR08(par->PDIO, VGA_PEL_IW, value);
156 }
157 void NVWriteDacData(struct nvidia_par *par, u8 value)
158 {
159         VGA_WR08(par->PDIO, VGA_PEL_D, value);
160 }
161 u8 NVReadDacData(struct nvidia_par *par)
162 {
163         return (VGA_RD08(par->PDIO, VGA_PEL_D));
164 }
165
166 static int NVIsConnected(struct nvidia_par *par, int output)
167 {
168         volatile u32 __iomem *PRAMDAC = par->PRAMDAC0;
169         u32 reg52C, reg608;
170         int present;
171
172         if (output)
173                 PRAMDAC += 0x800;
174
175         reg52C = NV_RD32(PRAMDAC, 0x052C);
176         reg608 = NV_RD32(PRAMDAC, 0x0608);
177
178         NV_WR32(PRAMDAC, 0x0608, reg608 & ~0x00010000);
179
180         NV_WR32(PRAMDAC, 0x052C, reg52C & 0x0000FEEE);
181         msleep(1);
182         NV_WR32(PRAMDAC, 0x052C, NV_RD32(PRAMDAC, 0x052C) | 1);
183
184         NV_WR32(par->PRAMDAC0, 0x0610, 0x94050140);
185         NV_WR32(par->PRAMDAC0, 0x0608, NV_RD32(par->PRAMDAC0, 0x0608) |
186                 0x00001000);
187
188         msleep(1);
189
190         present = (NV_RD32(PRAMDAC, 0x0608) & (1 << 28)) ? 1 : 0;
191
192         if (present)
193                 printk("nvidiafb: CRTC%i analog found\n", output);
194         else
195                 printk("nvidiafb: CRTC%i analog not found\n", output);
196
197         NV_WR32(par->PRAMDAC0, 0x0608, NV_RD32(par->PRAMDAC0, 0x0608) &
198                 0x0000EFFF);
199
200         NV_WR32(PRAMDAC, 0x052C, reg52C);
201         NV_WR32(PRAMDAC, 0x0608, reg608);
202
203         return present;
204 }
205
206 static void NVSelectHeadRegisters(struct nvidia_par *par, int head)
207 {
208         if (head) {
209                 par->PCIO = par->PCIO0 + 0x2000;
210                 par->PCRTC = par->PCRTC0 + 0x800;
211                 par->PRAMDAC = par->PRAMDAC0 + 0x800;
212                 par->PDIO = par->PDIO0 + 0x2000;
213         } else {
214                 par->PCIO = par->PCIO0;
215                 par->PCRTC = par->PCRTC0;
216                 par->PRAMDAC = par->PRAMDAC0;
217                 par->PDIO = par->PDIO0;
218         }
219 }
220
221 static void nv4GetConfig(struct nvidia_par *par)
222 {
223         if (NV_RD32(par->PFB, 0x0000) & 0x00000100) {
224                 par->RamAmountKBytes =
225                     ((NV_RD32(par->PFB, 0x0000) >> 12) & 0x0F) * 1024 * 2 +
226                     1024 * 2;
227         } else {
228                 switch (NV_RD32(par->PFB, 0x0000) & 0x00000003) {
229                 case 0:
230                         par->RamAmountKBytes = 1024 * 32;
231                         break;
232                 case 1:
233                         par->RamAmountKBytes = 1024 * 4;
234                         break;
235                 case 2:
236                         par->RamAmountKBytes = 1024 * 8;
237                         break;
238                 case 3:
239                 default:
240                         par->RamAmountKBytes = 1024 * 16;
241                         break;
242                 }
243         }
244         par->CrystalFreqKHz = (NV_RD32(par->PEXTDEV, 0x0000) & 0x00000040) ?
245             14318 : 13500;
246         par->CURSOR = &par->PRAMIN[0x1E00];
247         par->MinVClockFreqKHz = 12000;
248         par->MaxVClockFreqKHz = 350000;
249 }
250
251 static void nv10GetConfig(struct nvidia_par *par)
252 {
253         struct pci_dev *dev;
254         u32 implementation = par->Chipset & 0x0ff0;
255
256 #ifdef __BIG_ENDIAN
257         /* turn on big endian register access */
258         if (!(NV_RD32(par->PMC, 0x0004) & 0x01000001)) {
259                 NV_WR32(par->PMC, 0x0004, 0x01000001);
260                 mb();
261         }
262 #endif
263
264         dev = pci_find_slot(0, 1);
265         if ((par->Chipset & 0xffff) == 0x01a0) {
266                 int amt = 0;
267
268                 pci_read_config_dword(dev, 0x7c, &amt);
269                 par->RamAmountKBytes = (((amt >> 6) & 31) + 1) * 1024;
270         } else if ((par->Chipset & 0xffff) == 0x01f0) {
271                 int amt = 0;
272
273                 pci_read_config_dword(dev, 0x84, &amt);
274                 par->RamAmountKBytes = (((amt >> 4) & 127) + 1) * 1024;
275         } else {
276                 par->RamAmountKBytes =
277                     (NV_RD32(par->PFB, 0x020C) & 0xFFF00000) >> 10;
278         }
279
280         par->CrystalFreqKHz = (NV_RD32(par->PEXTDEV, 0x0000) & (1 << 6)) ?
281             14318 : 13500;
282
283         if (par->twoHeads && (implementation != 0x0110)) {
284                 if (NV_RD32(par->PEXTDEV, 0x0000) & (1 << 22))
285                         par->CrystalFreqKHz = 27000;
286         }
287
288         par->CURSOR = NULL;     /* can't set this here */
289         par->MinVClockFreqKHz = 12000;
290         par->MaxVClockFreqKHz = par->twoStagePLL ? 400000 : 350000;
291 }
292
293 int NVCommonSetup(struct fb_info *info)
294 {
295         struct nvidia_par *par = info->par;
296         struct fb_var_screeninfo *var;
297         u16 implementation = par->Chipset & 0x0ff0;
298         u8 *edidA = NULL, *edidB = NULL;
299         struct fb_monspecs *monitorA, *monitorB;
300         struct fb_monspecs *monA = NULL, *monB = NULL;
301         int mobile = 0;
302         int tvA = 0;
303         int tvB = 0;
304         int FlatPanel = -1;     /* really means the CRTC is slaved */
305         int Television = 0;
306         int err = 0;
307
308         var = kzalloc(sizeof(struct fb_var_screeninfo), GFP_KERNEL);
309         monitorA = kzalloc(sizeof(struct fb_monspecs), GFP_KERNEL);
310         monitorB = kzalloc(sizeof(struct fb_monspecs), GFP_KERNEL);
311
312         if (!var || !monitorA || !monitorB) {
313                 err = -ENOMEM;
314                 goto done;
315         }
316
317         par->PRAMIN = par->REGS + (0x00710000 / 4);
318         par->PCRTC0 = par->REGS + (0x00600000 / 4);
319         par->PRAMDAC0 = par->REGS + (0x00680000 / 4);
320         par->PFB = par->REGS + (0x00100000 / 4);
321         par->PFIFO = par->REGS + (0x00002000 / 4);
322         par->PGRAPH = par->REGS + (0x00400000 / 4);
323         par->PEXTDEV = par->REGS + (0x00101000 / 4);
324         par->PTIMER = par->REGS + (0x00009000 / 4);
325         par->PMC = par->REGS + (0x00000000 / 4);
326         par->FIFO = par->REGS + (0x00800000 / 4);
327
328         /* 8 bit registers */
329         par->PCIO0 = (u8 __iomem *) par->REGS + 0x00601000;
330         par->PDIO0 = (u8 __iomem *) par->REGS + 0x00681000;
331         par->PVIO = (u8 __iomem *) par->REGS + 0x000C0000;
332
333         par->twoHeads = (par->Architecture >= NV_ARCH_10) &&
334             (implementation != 0x0100) &&
335             (implementation != 0x0150) &&
336             (implementation != 0x01A0) && (implementation != 0x0200);
337
338         par->fpScaler = (par->FpScale && par->twoHeads &&
339                          (implementation != 0x0110));
340
341         par->twoStagePLL = (implementation == 0x0310) ||
342             (implementation == 0x0340) || (par->Architecture >= NV_ARCH_40);
343
344         par->WaitVSyncPossible = (par->Architecture >= NV_ARCH_10) &&
345             (implementation != 0x0100);
346
347         par->BlendingPossible = ((par->Chipset & 0xffff) != 0x0020);
348
349         /* look for known laptop chips */
350         switch (par->Chipset & 0xffff) {
351         case 0x0112:
352         case 0x0174:
353         case 0x0175:
354         case 0x0176:
355         case 0x0177:
356         case 0x0179:
357         case 0x017C:
358         case 0x017D:
359         case 0x0186:
360         case 0x0187:
361         case 0x018D:
362         case 0x0228:
363         case 0x0286:
364         case 0x028C:
365         case 0x0316:
366         case 0x0317:
367         case 0x031A:
368         case 0x031B:
369         case 0x031C:
370         case 0x031D:
371         case 0x031E:
372         case 0x031F:
373         case 0x0324:
374         case 0x0325:
375         case 0x0328:
376         case 0x0329:
377         case 0x032C:
378         case 0x032D:
379         case 0x0347:
380         case 0x0348:
381         case 0x0349:
382         case 0x034B:
383         case 0x034C:
384         case 0x0160:
385         case 0x0166:
386         case 0x0169:
387         case 0x016B:
388         case 0x016C:
389         case 0x016D:
390         case 0x00C8:
391         case 0x00CC:
392         case 0x0144:
393         case 0x0146:
394         case 0x0147:
395         case 0x0148:
396         case 0x0098:
397         case 0x0099:
398                 mobile = 1;
399                 break;
400         default:
401                 break;
402         }
403
404         if (par->Architecture == NV_ARCH_04)
405                 nv4GetConfig(par);
406         else
407                 nv10GetConfig(par);
408
409         NVSelectHeadRegisters(par, 0);
410
411         NVLockUnlock(par, 0);
412
413         par->IOBase = (NVReadMiscOut(par) & 0x01) ? 0x3d0 : 0x3b0;
414
415         par->Television = 0;
416
417         nvidia_create_i2c_busses(par);
418         if (!par->twoHeads) {
419                 par->CRTCnumber = 0;
420                 if (nvidia_probe_i2c_connector(info, 1, &edidA))
421                         nvidia_probe_of_connector(info, 1, &edidA);
422                 if (edidA && !fb_parse_edid(edidA, var)) {
423                         printk("nvidiafb: EDID found from BUS1\n");
424                         monA = monitorA;
425                         fb_edid_to_monspecs(edidA, monA);
426                         FlatPanel = (monA->input & FB_DISP_DDI) ? 1 : 0;
427
428                         /* NV4 doesn't support FlatPanels */
429                         if ((par->Chipset & 0x0fff) <= 0x0020)
430                                 FlatPanel = 0;
431                 } else {
432                         VGA_WR08(par->PCIO, 0x03D4, 0x28);
433                         if (VGA_RD08(par->PCIO, 0x03D5) & 0x80) {
434                                 VGA_WR08(par->PCIO, 0x03D4, 0x33);
435                                 if (!(VGA_RD08(par->PCIO, 0x03D5) & 0x01))
436                                         Television = 1;
437                                 FlatPanel = 1;
438                         } else {
439                                 FlatPanel = 0;
440                         }
441                         printk("nvidiafb: HW is currently programmed for %s\n",
442                                FlatPanel ? (Television ? "TV" : "DFP") :
443                                "CRT");
444                 }
445
446                 if (par->FlatPanel == -1) {
447                         par->FlatPanel = FlatPanel;
448                         par->Television = Television;
449                 } else {
450                         printk("nvidiafb: Forcing display type to %s as "
451                                "specified\n", par->FlatPanel ? "DFP" : "CRT");
452                 }
453         } else {
454                 u8 outputAfromCRTC, outputBfromCRTC;
455                 int CRTCnumber = -1;
456                 u8 slaved_on_A, slaved_on_B;
457                 int analog_on_A, analog_on_B;
458                 u32 oldhead;
459                 u8 cr44;
460
461                 if (implementation != 0x0110) {
462                         if (NV_RD32(par->PRAMDAC0, 0x0000052C) & 0x100)
463                                 outputAfromCRTC = 1;
464                         else
465                                 outputAfromCRTC = 0;
466                         if (NV_RD32(par->PRAMDAC0, 0x0000252C) & 0x100)
467                                 outputBfromCRTC = 1;
468                         else
469                                 outputBfromCRTC = 0;
470                         analog_on_A = NVIsConnected(par, 0);
471                         analog_on_B = NVIsConnected(par, 1);
472                 } else {
473                         outputAfromCRTC = 0;
474                         outputBfromCRTC = 1;
475                         analog_on_A = 0;
476                         analog_on_B = 0;
477                 }
478
479                 VGA_WR08(par->PCIO, 0x03D4, 0x44);
480                 cr44 = VGA_RD08(par->PCIO, 0x03D5);
481
482                 VGA_WR08(par->PCIO, 0x03D5, 3);
483                 NVSelectHeadRegisters(par, 1);
484                 NVLockUnlock(par, 0);
485
486                 VGA_WR08(par->PCIO, 0x03D4, 0x28);
487                 slaved_on_B = VGA_RD08(par->PCIO, 0x03D5) & 0x80;
488                 if (slaved_on_B) {
489                         VGA_WR08(par->PCIO, 0x03D4, 0x33);
490                         tvB = !(VGA_RD08(par->PCIO, 0x03D5) & 0x01);
491                 }
492
493                 VGA_WR08(par->PCIO, 0x03D4, 0x44);
494                 VGA_WR08(par->PCIO, 0x03D5, 0);
495                 NVSelectHeadRegisters(par, 0);
496                 NVLockUnlock(par, 0);
497
498                 VGA_WR08(par->PCIO, 0x03D4, 0x28);
499                 slaved_on_A = VGA_RD08(par->PCIO, 0x03D5) & 0x80;
500                 if (slaved_on_A) {
501                         VGA_WR08(par->PCIO, 0x03D4, 0x33);
502                         tvA = !(VGA_RD08(par->PCIO, 0x03D5) & 0x01);
503                 }
504
505                 oldhead = NV_RD32(par->PCRTC0, 0x00000860);
506                 NV_WR32(par->PCRTC0, 0x00000860, oldhead | 0x00000010);
507
508                 if (nvidia_probe_i2c_connector(info, 1, &edidA))
509                         nvidia_probe_of_connector(info, 1, &edidA);
510                 if (edidA && !fb_parse_edid(edidA, var)) {
511                         printk("nvidiafb: EDID found from BUS1\n");
512                         monA = monitorA;
513                         fb_edid_to_monspecs(edidA, monA);
514                 }
515
516                 if (nvidia_probe_i2c_connector(info, 2, &edidB))
517                         nvidia_probe_of_connector(info, 2, &edidB);
518                 if (edidB && !fb_parse_edid(edidB, var)) {
519                         printk("nvidiafb: EDID found from BUS2\n");
520                         monB = monitorB;
521                         fb_edid_to_monspecs(edidB, monB);
522                 }
523
524                 if (slaved_on_A && !tvA) {
525                         CRTCnumber = 0;
526                         FlatPanel = 1;
527                         printk("nvidiafb: CRTC 0 is currently programmed for "
528                                "DFP\n");
529                 } else if (slaved_on_B && !tvB) {
530                         CRTCnumber = 1;
531                         FlatPanel = 1;
532                         printk("nvidiafb: CRTC 1 is currently programmed "
533                                "for DFP\n");
534                 } else if (analog_on_A) {
535                         CRTCnumber = outputAfromCRTC;
536                         FlatPanel = 0;
537                         printk("nvidiafb: CRTC %i appears to have a "
538                                "CRT attached\n", CRTCnumber);
539                 } else if (analog_on_B) {
540                         CRTCnumber = outputBfromCRTC;
541                         FlatPanel = 0;
542                         printk("nvidiafb: CRTC %i"
543                                "appears to have a "
544                                "CRT attached\n", CRTCnumber);
545                 } else if (slaved_on_A) {
546                         CRTCnumber = 0;
547                         FlatPanel = 1;
548                         Television = 1;
549                         printk("nvidiafb: CRTC 0 is currently programmed "
550                                "for TV\n");
551                 } else if (slaved_on_B) {
552                         CRTCnumber = 1;
553                         FlatPanel = 1;
554                         Television = 1;
555                         printk("nvidiafb: CRTC 1 is currently programmed for "
556                                "TV\n");
557                 } else if (monA) {
558                         FlatPanel = (monA->input & FB_DISP_DDI) ? 1 : 0;
559                 } else if (monB) {
560                         FlatPanel = (monB->input & FB_DISP_DDI) ? 1 : 0;
561                 }
562
563                 if (par->FlatPanel == -1) {
564                         if (FlatPanel != -1) {
565                                 par->FlatPanel = FlatPanel;
566                                 par->Television = Television;
567                         } else {
568                                 printk("nvidiafb: Unable to detect display "
569                                        "type...\n");
570                                 if (mobile) {
571                                         printk("...On a laptop, assuming "
572                                                "DFP\n");
573                                         par->FlatPanel = 1;
574                                 } else {
575                                         printk("...Using default of CRT\n");
576                                         par->FlatPanel = 0;
577                                 }
578                         }
579                 } else {
580                         printk("nvidiafb: Forcing display type to %s as "
581                                "specified\n", par->FlatPanel ? "DFP" : "CRT");
582                 }
583
584                 if (par->CRTCnumber == -1) {
585                         if (CRTCnumber != -1)
586                                 par->CRTCnumber = CRTCnumber;
587                         else {
588                                 printk("nvidiafb: Unable to detect which "
589                                        "CRTCNumber...\n");
590                                 if (par->FlatPanel)
591                                         par->CRTCnumber = 1;
592                                 else
593                                         par->CRTCnumber = 0;
594                                 printk("...Defaulting to CRTCNumber %i\n",
595                                        par->CRTCnumber);
596                         }
597                 } else {
598                         printk("nvidiafb: Forcing CRTCNumber %i as "
599                                "specified\n", par->CRTCnumber);
600                 }
601
602                 if (monA) {
603                         if (((monA->input & FB_DISP_DDI) &&
604                              par->FlatPanel) ||
605                             ((!(monA->input & FB_DISP_DDI)) &&
606                              !par->FlatPanel)) {
607                                 if (monB) {
608                                         fb_destroy_modedb(monB->modedb);
609                                         monB = NULL;
610                                 }
611                         } else {
612                                 fb_destroy_modedb(monA->modedb);
613                                 monA = NULL;
614                         }
615                 }
616
617                 if (monB) {
618                         if (((monB->input & FB_DISP_DDI) &&
619                              !par->FlatPanel) ||
620                             ((!(monB->input & FB_DISP_DDI)) &&
621                              par->FlatPanel)) {
622                                 fb_destroy_modedb(monB->modedb);
623                                 monB = NULL;
624                         } else
625                                 monA = monB;
626                 }
627
628                 if (implementation == 0x0110)
629                         cr44 = par->CRTCnumber * 0x3;
630
631                 NV_WR32(par->PCRTC0, 0x00000860, oldhead);
632
633                 VGA_WR08(par->PCIO, 0x03D4, 0x44);
634                 VGA_WR08(par->PCIO, 0x03D5, cr44);
635                 NVSelectHeadRegisters(par, par->CRTCnumber);
636         }
637
638         printk("nvidiafb: Using %s on CRTC %i\n",
639                par->FlatPanel ? (par->Television ? "TV" : "DFP") : "CRT",
640                par->CRTCnumber);
641
642         if (par->FlatPanel && !par->Television) {
643                 par->fpWidth = NV_RD32(par->PRAMDAC, 0x0820) + 1;
644                 par->fpHeight = NV_RD32(par->PRAMDAC, 0x0800) + 1;
645                 par->fpSyncs = NV_RD32(par->PRAMDAC, 0x0848) & 0x30000033;
646
647                 printk("nvidiafb: Panel size is %i x %i\n", par->fpWidth, par->fpHeight);
648         }
649
650         if (monA)
651                 info->monspecs = *monA;
652
653         if (!par->FlatPanel || !par->twoHeads)
654                 par->FPDither = 0;
655
656         par->LVDS = 0;
657         if (par->FlatPanel && par->twoHeads) {
658                 NV_WR32(par->PRAMDAC0, 0x08B0, 0x00010004);
659                 if (par->PRAMDAC0[0x08b4] & 1)
660                         par->LVDS = 1;
661                 printk("nvidiafb: Panel is %s\n", par->LVDS ? "LVDS" : "TMDS");
662         }
663
664         kfree(edidA);
665         kfree(edidB);
666 done:
667         kfree(var);
668         kfree(monitorA);
669         kfree(monitorB);
670         return err;
671 }