git.oblomov.eu Git - linux-2.6/blob - arch/powerpc/boot/dts/mpc8610_hpcd.dts

   1 /*
   2  * MPC8610 HPCD Device Tree Source
   3  *
   4  * Copyright 2007-2008 Freescale Semiconductor Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under the terms of the GNU General Public License Version 2 as published
   8  * by the Free Software Foundation.
   9  */
  10
  11 /dts-v1/;
  12
  13 / {
  14         model = "MPC8610HPCD";
  15         compatible = "fsl,MPC8610HPCD";
  16         #address-cells = <1>;
  17         #size-cells = <1>;
  18
  19         aliases {
  20                 serial0 = &serial0;
  21                 serial1 = &serial1;
  22                 pci0 = &pci0;
  23                 pci1 = &pci1;
  24                 pci2 = &pci2;
  25         };
  26
  27         cpus {
  28                 #address-cells = <1>;
  29                 #size-cells = <0>;
  30
  31                 PowerPC,8610@0 {
  32                         device_type = "cpu";
  33                         reg = <0>;
  34                         d-cache-line-size = <32>;
  35                         i-cache-line-size = <32>;
  36                         d-cache-size = <32768>;         // L1
  37                         i-cache-size = <32768>;         // L1
  38                         timebase-frequency = <0>;       // From uboot
  39                         bus-frequency = <0>;            // From uboot
  40                         clock-frequency = <0>;          // From uboot
  41                 };
  42         };
  43
  44         memory {
  45                 device_type = "memory";
  46                 reg = <0x00000000 0x20000000>;  // 512M at 0x0
  47         };
  48
  49         localbus@e0005000 {
  50                 #address-cells = <2>;
  51                 #size-cells = <1>;
  52                 compatible = "fsl,mpc8610-elbc", "fsl,elbc", "simple-bus";
  53                 reg = <0xe0005000 0x1000>;
  54                 interrupts = <19 2>;
  55                 interrupt-parent = <&mpic>;
  56                 ranges = <0 0 0xf8000000 0x08000000
  57                           1 0 0xf0000000 0x08000000
  58                           2 0 0xe8400000 0x00008000
  59                           4 0 0xe8440000 0x00008000
  60                           5 0 0xe8480000 0x00008000
  61                           6 0 0xe84c0000 0x00008000
  62                           3 0 0xe8000000 0x00000020>;
  63
  64                 flash@0,0 {
  65                         compatible = "cfi-flash";
  66                         reg = <0 0 0x8000000>;
  67                         bank-width = <2>;
  68                         device-width = <1>;
  69                 };
  70
  71                 flash@1,0 {
  72                         compatible = "cfi-flash";
  73                         reg = <1 0 0x8000000>;
  74                         bank-width = <2>;
  75                         device-width = <1>;
  76                 };
  77
  78                 flash@2,0 {
  79                         compatible = "fsl,mpc8610-fcm-nand",
  80                                      "fsl,elbc-fcm-nand";
  81                         reg = <2 0 0x8000>;
  82                 };
  83
  84                 flash@4,0 {
  85                         compatible = "fsl,mpc8610-fcm-nand",
  86                                      "fsl,elbc-fcm-nand";
  87                         reg = <4 0 0x8000>;
  88                 };
  89
  90                 flash@5,0 {
  91                         compatible = "fsl,mpc8610-fcm-nand",
  92                                      "fsl,elbc-fcm-nand";
  93                         reg = <5 0 0x8000>;
  94                 };
  95
  96                 flash@6,0 {
  97                         compatible = "fsl,mpc8610-fcm-nand",
  98                                      "fsl,elbc-fcm-nand";
  99                         reg = <6 0 0x8000>;
 100                 };
 101
 102                 board-control@3,0 {
 103                         compatible = "fsl,fpga-pixis";
 104                         reg = <3 0 0x20>;
 105                 };
 106         };
 107
 108         soc@e0000000 {
 109                 #address-cells = <1>;
 110                 #size-cells = <1>;
 111                 #interrupt-cells = <2>;
 112                 device_type = "soc";
 113                 compatible = "fsl,mpc8610-immr", "simple-bus";
 114                 ranges = <0x0 0xe0000000 0x00100000>;
 115                 bus-frequency = <0>;
 116
 117                 mcm-law@0 {
 118                         compatible = "fsl,mcm-law";
 119                         reg = <0x0 0x1000>;
 120                         fsl,num-laws = <10>;
 121                 };
 122
 123                 mcm@1000 {
 124                         compatible = "fsl,mpc8610-mcm", "fsl,mcm";
 125                         reg = <0x1000 0x1000>;
 126                         interrupts = <17 2>;
 127                         interrupt-parent = <&mpic>;
 128                 };
 129
 130                 i2c@3000 {
 131                         #address-cells = <1>;
 132                         #size-cells = <0>;
 133                         cell-index = <0>;
 134                         compatible = "fsl-i2c";
 135                         reg = <0x3000 0x100>;
 136                         interrupts = <43 2>;
 137                         interrupt-parent = <&mpic>;
 138                         dfsrr;
 139
 140                         cs4270:codec@4f {
 141                                 compatible = "cirrus,cs4270";
 142                                 reg = <0x4f>;
 143                                 /* MCLK source is a stand-alone oscillator */
 144                                 clock-frequency = <12288000>;
 145                         };
 146                 };
 147
 148                 i2c@3100 {
 149                         #address-cells = <1>;
 150                         #size-cells = <0>;
 151                         cell-index = <1>;
 152                         compatible = "fsl-i2c";
 153                         reg = <0x3100 0x100>;
 154                         interrupts = <43 2>;
 155                         interrupt-parent = <&mpic>;
 156                         dfsrr;
 157                 };
 158
 159                 serial0: serial@4500 {
 160                         cell-index = <0>;
 161                         device_type = "serial";
 162                         compatible = "ns16550";
 163                         reg = <0x4500 0x100>;
 164                         clock-frequency = <0>;
 165                         interrupts = <42 2>;
 166                         interrupt-parent = <&mpic>;
 167                 };
 168
 169                 serial1: serial@4600 {
 170                         cell-index = <1>;
 171                         device_type = "serial";
 172                         compatible = "ns16550";
 173                         reg = <0x4600 0x100>;
 174                         clock-frequency = <0>;
 175                         interrupts = <42 2>;
 176                         interrupt-parent = <&mpic>;
 177                 };
 178
 179                 display@2c000 {
 180                         compatible = "fsl,diu";
 181                         reg = <0x2c000 100>;
 182                         interrupts = <72 2>;
 183                         interrupt-parent = <&mpic>;
 184                 };
 185
 186                 mpic: interrupt-controller@40000 {
 187                         interrupt-controller;
 188                         #address-cells = <0>;
 189                         #interrupt-cells = <2>;
 190                         reg = <0x40000 0x40000>;
 191                         compatible = "chrp,open-pic";
 192                         device_type = "open-pic";
 193                 };
 194
 195                 msi@41600 {
 196                         compatible = "fsl,mpc8610-msi", "fsl,mpic-msi";
 197                         reg = <0x41600 0x80>;
 198                         msi-available-ranges = <0 0x100>;
 199                         interrupts = <
 200                                 0xe0 0
 201                                 0xe1 0
 202                                 0xe2 0
 203                                 0xe3 0
 204                                 0xe4 0
 205                                 0xe5 0
 206                                 0xe6 0
 207                                 0xe7 0>;
 208                         interrupt-parent = <&mpic>;
 209                 };
 210
 211                 global-utilities@e0000 {
 212                         compatible = "fsl,mpc8610-guts";
 213                         reg = <0xe0000 0x1000>;
 214                         fsl,has-rstcr;
 215                 };
 216
 217                 wdt@e4000 {
 218                         compatible = "fsl,mpc8610-wdt";
 219                         reg = <0xe4000 0x100>;
 220                 };
 221
 222                 ssi@16000 {
 223                         compatible = "fsl,mpc8610-ssi";
 224                         cell-index = <0>;
 225                         reg = <0x16000 0x100>;
 226                         interrupt-parent = <&mpic>;
 227                         interrupts = <62 2>;
 228                         fsl,mode = "i2s-slave";
 229                         codec-handle = <&cs4270>;
 230                         fsl,playback-dma = <&dma00>;
 231                         fsl,capture-dma = <&dma01>;
 232                         fsl,fifo-depth = <8>;
 233                 };
 234
 235                 ssi@16100 {
 236                         compatible = "fsl,mpc8610-ssi";
 237                         cell-index = <1>;
 238                         reg = <0x16100 0x100>;
 239                         interrupt-parent = <&mpic>;
 240                         interrupts = <63 2>;
 241                         fsl,fifo-depth = <8>;
 242                 };
 243
 244                 dma@21300 {
 245                         #address-cells = <1>;
 246                         #size-cells = <1>;
 247                         compatible = "fsl,mpc8610-dma", "fsl,eloplus-dma";
 248                         cell-index = <0>;
 249                         reg = <0x21300 0x4>; /* DMA general status register */
 250                         ranges = <0x0 0x21100 0x200>;
 251
 252                         dma00: dma-channel@0 {
 253                                 compatible = "fsl,mpc8610-dma-channel",
 254                                         "fsl,ssi-dma-channel";
 255                                 cell-index = <0>;
 256                                 reg = <0x0 0x80>;
 257                                 interrupt-parent = <&mpic>;
 258                                 interrupts = <20 2>;
 259                         };
 260                         dma01: dma-channel@1 {
 261                                 compatible = "fsl,mpc8610-dma-channel",
 262                                         "fsl,ssi-dma-channel";
 263                                 cell-index = <1>;
 264                                 reg = <0x80 0x80>;
 265                                 interrupt-parent = <&mpic>;
 266                                 interrupts = <21 2>;
 267                         };
 268                         dma-channel@2 {
 269                                 compatible = "fsl,mpc8610-dma-channel",
 270                                         "fsl,eloplus-dma-channel";
 271                                 cell-index = <2>;
 272                                 reg = <0x100 0x80>;
 273                                 interrupt-parent = <&mpic>;
 274                                 interrupts = <22 2>;
 275                         };
 276                         dma-channel@3 {
 277                                 compatible = "fsl,mpc8610-dma-channel",
 278                                         "fsl,eloplus-dma-channel";
 279                                 cell-index = <3>;
 280                                 reg = <0x180 0x80>;
 281                                 interrupt-parent = <&mpic>;
 282                                 interrupts = <23 2>;
 283                         };
 284                 };
 285
 286                 dma@c300 {
 287                         #address-cells = <1>;
 288                         #size-cells = <1>;
 289                         compatible = "fsl,mpc8610-dma", "fsl,eloplus-dma";
 290                         cell-index = <1>;
 291                         reg = <0xc300 0x4>; /* DMA general status register */
 292                         ranges = <0x0 0xc100 0x200>;
 293
 294                         dma-channel@0 {
 295                                 compatible = "fsl,mpc8610-dma-channel",
 296                                         "fsl,eloplus-dma-channel";
 297                                 cell-index = <0>;
 298                                 reg = <0x0 0x80>;
 299                                 interrupt-parent = <&mpic>;
 300                                 interrupts = <76 2>;
 301                         };
 302                         dma-channel@1 {
 303                                 compatible = "fsl,mpc8610-dma-channel",
 304                                         "fsl,eloplus-dma-channel";
 305                                 cell-index = <1>;
 306                                 reg = <0x80 0x80>;
 307                                 interrupt-parent = <&mpic>;
 308                                 interrupts = <77 2>;
 309                         };
 310                         dma-channel@2 {
 311                                 compatible = "fsl,mpc8610-dma-channel",
 312                                         "fsl,eloplus-dma-channel";
 313                                 cell-index = <2>;
 314                                 reg = <0x100 0x80>;
 315                                 interrupt-parent = <&mpic>;
 316                                 interrupts = <78 2>;
 317                         };
 318                         dma-channel@3 {
 319                                 compatible = "fsl,mpc8610-dma-channel",
 320                                         "fsl,eloplus-dma-channel";
 321                                 cell-index = <3>;
 322                                 reg = <0x180 0x80>;
 323                                 interrupt-parent = <&mpic>;
 324                                 interrupts = <79 2>;
 325                         };
 326                 };
 327
 328         };
 329
 330         pci0: pci@e0008000 {
 331                 compatible = "fsl,mpc8610-pci";
 332                 device_type = "pci";
 333                 #interrupt-cells = <1>;
 334                 #size-cells = <2>;
 335                 #address-cells = <3>;
 336                 reg = <0xe0008000 0x1000>;
 337                 bus-range = <0 0>;
 338                 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x10000000
 339                           0x01000000 0x0 0x00000000 0xe1000000 0x0 0x00100000>;
 340                 clock-frequency = <33333333>;
 341                 interrupt-parent = <&mpic>;
 342                 interrupts = <24 2>;
 343                 interrupt-map-mask = <0xf800 0 0 7>;
 344                 interrupt-map = <
 345                         /* IDSEL 0x11 */
 346                         0x8800 0 0 1 &mpic 4 1
 347                         0x8800 0 0 2 &mpic 5 1
 348                         0x8800 0 0 3 &mpic 6 1
 349                         0x8800 0 0 4 &mpic 7 1
 350
 351                         /* IDSEL 0x12 */
 352                         0x9000 0 0 1 &mpic 5 1
 353                         0x9000 0 0 2 &mpic 6 1
 354                         0x9000 0 0 3 &mpic 7 1
 355                         0x9000 0 0 4 &mpic 4 1
 356                         >;
 357         };
 358
 359         pci1: pcie@e000a000 {
 360                 compatible = "fsl,mpc8641-pcie";
 361                 device_type = "pci";
 362                 #interrupt-cells = <1>;
 363                 #size-cells = <2>;
 364                 #address-cells = <3>;
 365                 reg = <0xe000a000 0x1000>;
 366                 bus-range = <1 3>;
 367                 ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
 368                           0x01000000 0x0 0x00000000 0xe3000000 0x0 0x00100000>;
 369                 clock-frequency = <33333333>;
 370                 interrupt-parent = <&mpic>;
 371                 interrupts = <26 2>;
 372                 interrupt-map-mask = <0xf800 0 0 7>;
 373
 374                 interrupt-map = <
 375                         /* IDSEL 0x1b */
 376                         0xd800 0 0 1 &mpic 2 1
 377
 378                         /* IDSEL 0x1c*/
 379                         0xe000 0 0 1 &mpic 1 1
 380                         0xe000 0 0 2 &mpic 1 1
 381                         0xe000 0 0 3 &mpic 1 1
 382                         0xe000 0 0 4 &mpic 1 1
 383
 384                         /* IDSEL 0x1f */
 385                         0xf800 0 0 1 &mpic 3 2
 386                         0xf800 0 0 2 &mpic 0 1
 387                 >;
 388
 389                 pcie@0 {
 390                         reg = <0 0 0 0 0>;
 391                         #size-cells = <2>;
 392                         #address-cells = <3>;
 393                         device_type = "pci";
 394                         ranges = <0x02000000 0x0 0xa0000000
 395                                   0x02000000 0x0 0xa0000000
 396                                   0x0 0x10000000
 397                                   0x01000000 0x0 0x00000000
 398                                   0x01000000 0x0 0x00000000
 399                                   0x0 0x00100000>;
 400                         uli1575@0 {
 401                                 reg = <0 0 0 0 0>;
 402                                 #size-cells = <2>;
 403                                 #address-cells = <3>;
 404                                 ranges = <0x02000000 0x0 0xa0000000
 405                                           0x02000000 0x0 0xa0000000
 406                                           0x0 0x10000000
 407                                           0x01000000 0x0 0x00000000
 408                                           0x01000000 0x0 0x00000000
 409                                           0x0 0x00100000>;
 410
 411                                 isa@1e {
 412                                         device_type = "isa";
 413                                         #size-cells = <1>;
 414                                         #address-cells = <2>;
 415                                         reg = <0xf000 0 0 0 0>;
 416                                         ranges = <1 0 0x01000000 0 0
 417                                                   0x00001000>;
 418
 419                                         rtc@70 {
 420                                                 compatible = "pnpPNP,b00";
 421                                                 reg = <1 0x70 2>;
 422                                         };
 423                                 };
 424                         };
 425                 };
 426         };
 427
 428         pci2: pcie@e0009000 {
 429                 #address-cells = <3>;
 430                 #size-cells = <2>;
 431                 #interrupt-cells = <1>;
 432                 device_type = "pci";
 433                 compatible = "fsl,mpc8641-pcie";
 434                 reg = <0xe0009000 0x00001000>;
 435                 ranges = <0x02000000 0 0x90000000 0x90000000 0 0x10000000
 436                           0x01000000 0 0x00000000 0xe2000000 0 0x00100000>;
 437                 bus-range = <0 255>;
 438                 interrupt-map-mask = <0xf800 0 0 7>;
 439                 interrupt-map = <0x0000 0 0 1 &mpic 4 1
 440                                  0x0000 0 0 2 &mpic 5 1
 441                                  0x0000 0 0 3 &mpic 6 1
 442                                  0x0000 0 0 4 &mpic 7 1>;
 443                 interrupt-parent = <&mpic>;
 444                 interrupts = <25 2>;
 445                 clock-frequency = <33333333>;
 446         };
 447 };